Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 1/1 assign mubi_int = mubi;
Tests: T1 T2 T3
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
56 1/1 unused_logic <= MuBi4False;
Tests: T1 T2 T3
57 end else begin
58 1/1 unused_logic <= mubi_i;
Tests: T1 T2 T3
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T1 T2 T3
Branch Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
55 if (!rst_ni) begin
-1-
56 unused_logic <= MuBi4False;
==>
57 end else begin
58 unused_logic <= mubi_i;
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
611077083 |
610944181 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611077083 |
610944181 |
0 |
0 |
T1 |
7403 |
7342 |
0 |
0 |
T2 |
7263 |
7183 |
0 |
0 |
T3 |
16596 |
16499 |
0 |
0 |
T4 |
2551 |
2410 |
0 |
0 |
T5 |
3161 |
2979 |
0 |
0 |
T12 |
2541 |
2464 |
0 |
0 |
T13 |
117325 |
117237 |
0 |
0 |
T14 |
5817 |
5728 |
0 |
0 |
T15 |
46769 |
46681 |
0 |
0 |
T19 |
1332 |
1240 |
0 |
0 |