Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	612492333	10366	0	0
entropy_period_rd_A	612492333	2088	0	0
intr_enable_rd_A	612492333	2921	0	0
prefix_0_rd_A	612492333	2238	0	0
prefix_10_rd_A	612492333	2154	0	0
prefix_1_rd_A	612492333	2068	0	0
prefix_2_rd_A	612492333	2120	0	0
prefix_3_rd_A	612492333	2174	0	0
prefix_4_rd_A	612492333	2196	0	0
prefix_5_rd_A	612492333	2116	0	0
prefix_6_rd_A	612492333	2092	0	0
prefix_7_rd_A	612492333	2140	0	0
prefix_8_rd_A	612492333	2083	0	0
prefix_9_rd_A	612492333	2084	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	10366	0	0
T9	271765	0	0	0
T23	16443	0	0	0
T30	98498	294	0	0
T40	0	1244	0	0
T57	0	3900	0	0
T61	0	378	0	0
T62	183875	0	0	0
T81	167872	0	0	0
T82	44740	0	0	0
T83	73950	0	0	0
T84	39512	0	0	0
T85	224814	0	0	0
T86	57728	0	0	0
T121	0	7	0	0
T122	0	1	0	0
T124	0	822	0	0
T129	0	419	0	0
T130	0	20	0	0
T131	0	5	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2088	0	0
T103	3124	11	0	0
T105	5267	16	0	0
T123	22920	109	0	0
T146	2694	3	0	0
T147	1492	12	0	0
T148	1768	9	0	0
T149	5727	10	0	0
T150	2761	7	0	0
T151	4276	5	0	0
T152	9875	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2921	0	0
T103	3124	2	0	0
T105	5267	24	0	0
T123	22920	145	0	0
T127	1317	17	0	0
T146	2694	15	0	0
T147	1492	9	0	0
T148	1768	7	0	0
T149	5727	31	0	0
T150	2761	12	0	0
T151	4276	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2238	0	0
T103	3124	5	0	0
T105	5267	18	0	0
T123	22920	84	0	0
T146	2694	8	0	0
T147	1492	9	0	0
T148	1768	6	0	0
T149	5727	13	0	0
T150	2761	13	0	0
T151	4276	10	0	0
T152	9875	63	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2154	0	0
T103	3124	2	0	0
T105	5267	16	0	0
T123	22920	89	0	0
T147	1492	4	0	0
T149	5727	15	0	0
T150	2761	10	0	0
T151	4276	9	0	0
T152	9875	78	0	0
T153	24474	240	0	0
T154	3048	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2068	0	0
T103	3124	7	0	0
T105	5267	10	0	0
T123	22920	108	0	0
T147	1492	8	0	0
T149	5727	23	0	0
T150	2761	5	0	0
T152	9875	35	0	0
T153	24474	198	0	0
T154	3048	4	0	0
T155	7798	18	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2120	0	0
T103	3124	1	0	0
T105	5267	14	0	0
T123	22920	78	0	0
T146	2694	10	0	0
T147	1492	6	0	0
T148	1768	7	0	0
T149	5727	8	0	0
T150	2761	14	0	0
T151	4276	3	0	0
T152	9875	19	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2174	0	0
T103	3124	3	0	0
T105	5267	14	0	0
T123	22920	68	0	0
T148	1768	9	0	0
T149	5727	9	0	0
T150	2761	4	0	0
T151	4276	6	0	0
T152	9875	43	0	0
T153	24474	250	0	0
T154	3048	13	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2196	0	0
T103	3124	11	0	0
T105	5267	17	0	0
T123	22920	92	0	0
T146	2694	2	0	0
T147	1492	9	0	0
T148	1768	2	0	0
T149	5727	4	0	0
T150	2761	14	0	0
T151	4276	8	0	0
T152	9875	15	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2116	0	0
T103	3124	5	0	0
T105	5267	19	0	0
T123	22920	87	0	0
T146	2694	4	0	0
T147	1492	4	0	0
T148	1768	5	0	0
T149	5727	7	0	0
T150	2761	14	0	0
T151	4276	1	0	0
T152	9875	13	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2092	0	0
T105	5267	11	0	0
T123	22920	102	0	0
T146	2694	5	0	0
T147	1492	4	0	0
T148	1768	2	0	0
T149	5727	13	0	0
T150	2761	6	0	0
T151	4276	12	0	0
T152	9875	26	0	0
T153	24474	243	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2140	0	0
T103	3124	8	0	0
T105	5267	21	0	0
T123	22920	67	0	0
T146	2694	6	0	0
T148	1768	3	0	0
T149	5727	12	0	0
T150	2761	11	0	0
T151	4276	5	0	0
T152	9875	7	0	0
T153	24474	220	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2083	0	0
T103	3124	6	0	0
T105	5267	14	0	0
T123	22920	70	0	0
T146	2694	5	0	0
T147	1492	5	0	0
T148	1768	4	0	0
T149	5727	14	0	0
T150	2761	13	0	0
T151	4276	4	0	0
T152	9875	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612492333	2084	0	0
T105	5267	9	0	0
T123	22920	80	0	0
T146	2694	15	0	0
T147	1492	7	0	0
T148	1768	1	0	0
T149	5727	5	0	0
T152	9875	30	0	0
T153	24474	183	0	0
T154	3048	9	0	0
T155	7798	14	0	0