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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.25 95.87 92.34 100.00 68.60 94.08 98.87 96.01


Total test records in report: 869
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T762 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3503043454 Oct 03 10:28:59 AM UTC 24 Oct 03 10:29:02 AM UTC 24 31586369 ps
T763 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1235945075 Oct 03 10:29:00 AM UTC 24 Oct 03 10:29:03 AM UTC 24 53628665 ps
T764 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4147953313 Oct 03 10:28:59 AM UTC 24 Oct 03 10:29:03 AM UTC 24 147636324 ps
T765 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1027963450 Oct 03 10:28:59 AM UTC 24 Oct 03 10:29:03 AM UTC 24 323239643 ps
T766 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4072414615 Oct 03 10:28:59 AM UTC 24 Oct 03 10:29:03 AM UTC 24 356188141 ps
T767 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.2898994458 Oct 03 10:28:57 AM UTC 24 Oct 03 10:29:03 AM UTC 24 190916971 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4156961914 Oct 03 10:28:59 AM UTC 24 Oct 03 10:29:03 AM UTC 24 218066425 ps
T768 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3912234476 Oct 03 10:29:01 AM UTC 24 Oct 03 10:29:03 AM UTC 24 41826312 ps
T769 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.137604428 Oct 03 10:28:59 AM UTC 24 Oct 03 10:29:03 AM UTC 24 108067668 ps
T770 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2024208998 Oct 03 10:29:01 AM UTC 24 Oct 03 10:29:04 AM UTC 24 110127070 ps
T771 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3842163727 Oct 03 10:29:01 AM UTC 24 Oct 03 10:29:04 AM UTC 24 154887635 ps
T772 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3771626000 Oct 03 10:29:01 AM UTC 24 Oct 03 10:29:04 AM UTC 24 28605174 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.206473538 Oct 03 10:28:57 AM UTC 24 Oct 03 10:29:04 AM UTC 24 2324840938 ps
T773 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3897221563 Oct 03 10:28:58 AM UTC 24 Oct 03 10:29:04 AM UTC 24 219146128 ps
T774 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4256498702 Oct 03 10:29:00 AM UTC 24 Oct 03 10:29:04 AM UTC 24 180904234 ps
T775 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3730687893 Oct 03 10:29:01 AM UTC 24 Oct 03 10:29:04 AM UTC 24 84833541 ps
T776 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1323904942 Oct 03 10:29:00 AM UTC 24 Oct 03 10:29:04 AM UTC 24 200919051 ps
T777 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3457124368 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:04 AM UTC 24 21906626 ps
T778 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.776518282 Oct 03 10:29:00 AM UTC 24 Oct 03 10:29:05 AM UTC 24 46708278 ps
T779 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.4155773700 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:05 AM UTC 24 157022632 ps
T780 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2228375060 Oct 03 10:28:50 AM UTC 24 Oct 03 10:29:05 AM UTC 24 295178389 ps
T781 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1073000624 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:05 AM UTC 24 28741125 ps
T782 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1854100412 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:05 AM UTC 24 12919931 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4108923795 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:05 AM UTC 24 31204017 ps
T783 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2760082787 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:05 AM UTC 24 22494566 ps
T784 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2424051998 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:05 AM UTC 24 100417674 ps
T785 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2089814040 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:06 AM UTC 24 26431133 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3202684567 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:06 AM UTC 24 21520524 ps
T786 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3541628967 Oct 03 10:28:55 AM UTC 24 Oct 03 10:29:06 AM UTC 24 740142457 ps
T787 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1800114404 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:06 AM UTC 24 63934721 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.328872873 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:06 AM UTC 24 438193003 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1802309296 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:06 AM UTC 24 61339499 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2500748210 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:07 AM UTC 24 49442530 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1727906163 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:07 AM UTC 24 77189475 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1345845233 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:07 AM UTC 24 193772688 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2445747125 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:07 AM UTC 24 683409358 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1823434918 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:07 AM UTC 24 46314170 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.858338310 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:07 AM UTC 24 54196451 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.272931618 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:07 AM UTC 24 16069850 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2358184018 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:07 AM UTC 24 165810020 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3401538654 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:07 AM UTC 24 20737102 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.1485600945 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:08 AM UTC 24 105444558 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2757243113 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:08 AM UTC 24 219696649 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1204632819 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:08 AM UTC 24 63413573 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2656234994 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:08 AM UTC 24 83951765 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2962455645 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:08 AM UTC 24 27735045 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2350462975 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:08 AM UTC 24 67145386 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2724207156 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:12 AM UTC 24 16133212 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1581391377 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:08 AM UTC 24 87459824 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4182849309 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:08 AM UTC 24 158336746 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.343083096 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:08 AM UTC 24 233869608 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.168320014 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:08 AM UTC 24 378410246 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3343520504 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:08 AM UTC 24 122812474 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1869520958 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:09 AM UTC 24 161025485 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2003648912 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:09 AM UTC 24 255090437 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3480782513 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:09 AM UTC 24 68267068 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.82456065 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:09 AM UTC 24 29622947 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.765291857 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:09 AM UTC 24 48351928 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.553037495 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:09 AM UTC 24 101557657 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.485991891 Oct 03 10:29:04 AM UTC 24 Oct 03 10:29:09 AM UTC 24 398592254 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3232030104 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:09 AM UTC 24 203336492 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.788941064 Oct 03 10:29:02 AM UTC 24 Oct 03 10:29:10 AM UTC 24 395336300 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3030930501 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:10 AM UTC 24 127918168 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.396145568 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:10 AM UTC 24 42805201 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2615318871 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:10 AM UTC 24 13741361 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4225195606 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:10 AM UTC 24 463182341 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2915292961 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:10 AM UTC 24 12698692 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3693448928 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:11 AM UTC 24 59414800 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1378652751 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:11 AM UTC 24 36317825 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2936230243 Oct 03 10:29:05 AM UTC 24 Oct 03 10:29:11 AM UTC 24 366022854 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3045672402 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:11 AM UTC 24 28180296 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3774786919 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:11 AM UTC 24 83030840 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1477900188 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:11 AM UTC 24 33430266 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3820282095 Oct 03 10:29:09 AM UTC 24 Oct 03 10:29:11 AM UTC 24 55047243 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3866824309 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:11 AM UTC 24 61393553 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.76974098 Oct 03 10:28:53 AM UTC 24 Oct 03 10:29:12 AM UTC 24 1014010412 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1855548344 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:12 AM UTC 24 83277397 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2633051493 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:12 AM UTC 24 1107481759 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2738372373 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:12 AM UTC 24 28899745 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3726684706 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:12 AM UTC 24 167096834 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.861111399 Oct 03 10:29:07 AM UTC 24 Oct 03 10:29:12 AM UTC 24 514390489 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.1237325425 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:12 AM UTC 24 27129814 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3616206301 Oct 03 10:29:11 AM UTC 24 Oct 03 10:29:13 AM UTC 24 23121423 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.3914250709 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:13 AM UTC 24 12162957 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2855067893 Oct 03 10:29:11 AM UTC 24 Oct 03 10:29:13 AM UTC 24 18720715 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2364292498 Oct 03 10:29:11 AM UTC 24 Oct 03 10:29:13 AM UTC 24 79211715 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.244704845 Oct 03 10:29:11 AM UTC 24 Oct 03 10:29:13 AM UTC 24 166782606 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3179002099 Oct 03 10:29:11 AM UTC 24 Oct 03 10:29:13 AM UTC 24 53848656 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2074962096 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:13 AM UTC 24 123432510 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2717576674 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:13 AM UTC 24 62037449 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.622208025 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:13 AM UTC 24 367805588 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3477954041 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:13 AM UTC 24 248469048 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2655552604 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:13 AM UTC 24 64477865 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.4039489755 Oct 03 10:29:08 AM UTC 24 Oct 03 10:29:14 AM UTC 24 357915032 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3369084990 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:14 AM UTC 24 194793354 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1710602690 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:14 AM UTC 24 136350437 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.385994637 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:14 AM UTC 24 728297605 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3328816396 Oct 03 10:29:11 AM UTC 24 Oct 03 10:29:14 AM UTC 24 38130731 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1979230887 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:14 AM UTC 24 488104042 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4038421968 Oct 03 10:29:11 AM UTC 24 Oct 03 10:29:14 AM UTC 24 118365854 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.749996911 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:14 AM UTC 24 50782443 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1600793315 Oct 03 10:29:10 AM UTC 24 Oct 03 10:29:14 AM UTC 24 213203785 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2140635939 Oct 03 10:28:51 AM UTC 24 Oct 03 10:29:16 AM UTC 24 9058187721 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1303100006 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 31588111 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3477470464 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 14635052 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2030576976 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 84983424 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2596015182 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 48677460 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.4268032737 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 45942200 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.399439339 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 12533850 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3176363652 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 14764073 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1367267464 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 15807246 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.521411325 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 23423898 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1473608820 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 23219810 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.41449162 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:27 AM UTC 24 47567993 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2097095442 Oct 03 10:29:12 AM UTC 24 Oct 03 10:29:28 AM UTC 24 32604196 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.74358269 Oct 03 10:29:14 AM UTC 24 Oct 03 10:29:29 AM UTC 24 139539688 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1752912705 Oct 03 10:29:13 AM UTC 24 Oct 03 10:29:32 AM UTC 24 41523545 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1662973243 Oct 03 10:29:13 AM UTC 24 Oct 03 10:29:32 AM UTC 24 36999834 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3024379662 Oct 03 10:29:13 AM UTC 24 Oct 03 10:29:33 AM UTC 24 16838971 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.1214371110
Short name T3
Test name
Test status
Simulation time 204925807 ps
CPU time 3.37 seconds
Started Oct 03 10:29:17 AM UTC 24
Finished Oct 03 10:29:31 AM UTC 24
Peak memory 229488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214371110 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.1214371110 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.2361724378
Short name T18
Test name
Test status
Simulation time 3004621902 ps
CPU time 26.05 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:30:03 AM UTC 24
Peak memory 234120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361724378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2361724378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.593133514
Short name T121
Test name
Test status
Simulation time 201550587 ps
CPU time 4.29 seconds
Started Oct 03 10:28:46 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593133514 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.593133514 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.4057167459
Short name T9
Test name
Test status
Simulation time 10870640045 ps
CPU time 33.19 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:30:10 AM UTC 24
Peak memory 274572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057167459 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.4057167459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.3069496969
Short name T30
Test name
Test status
Simulation time 2052035735 ps
CPU time 32.82 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:30:10 AM UTC 24
Peak memory 250612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3069496969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_
with_rand_reset.3069496969 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.146857760
Short name T15
Test name
Test status
Simulation time 492309626 ps
CPU time 4.63 seconds
Started Oct 03 10:29:43 AM UTC 24
Finished Oct 03 10:29:55 AM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146857760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.146857760 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.3206553309
Short name T6
Test name
Test status
Simulation time 32706293 ps
CPU time 1.68 seconds
Started Oct 03 10:32:28 AM UTC 24
Finished Oct 03 10:32:31 AM UTC 24
Peak memory 226328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206553309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3206553309 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.3440561064
Short name T22
Test name
Test status
Simulation time 655981108 ps
CPU time 26.7 seconds
Started Oct 03 10:29:38 AM UTC 24
Finished Oct 03 10:30:09 AM UTC 24
Peak memory 236188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440561064 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.3440561064 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2370238226
Short name T103
Test name
Test status
Simulation time 32228049 ps
CPU time 1.5 seconds
Started Oct 03 10:28:46 AM UTC 24
Finished Oct 03 10:28:49 AM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370238226 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2370238226 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.564285810
Short name T27
Test name
Test status
Simulation time 16950109578 ps
CPU time 320.92 seconds
Started Oct 03 10:30:10 AM UTC 24
Finished Oct 03 10:35:36 AM UTC 24
Peak memory 375836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564285810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.564285810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.2900091755
Short name T8
Test name
Test status
Simulation time 42107001 ps
CPU time 2.04 seconds
Started Oct 03 10:42:45 AM UTC 24
Finished Oct 03 10:42:48 AM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900091755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2900091755 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.2535368886
Short name T67
Test name
Test status
Simulation time 1624624352 ps
CPU time 13.91 seconds
Started Oct 03 11:18:40 AM UTC 24
Finished Oct 03 11:18:55 AM UTC 24
Peak memory 244744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535368886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2535368886 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1537395389
Short name T125
Test name
Test status
Simulation time 42343515 ps
CPU time 0.91 seconds
Started Oct 03 10:28:47 AM UTC 24
Finished Oct 03 10:28:48 AM UTC 24
Peak memory 218684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537395389 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1537395389 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.297657191
Short name T63
Test name
Test status
Simulation time 24383713519 ps
CPU time 220.44 seconds
Started Oct 03 10:29:43 AM UTC 24
Finished Oct 03 10:33:31 AM UTC 24
Peak memory 390196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297657191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.297657191 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.3715298634
Short name T4
Test name
Test status
Simulation time 134347903 ps
CPU time 1.26 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:29:38 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715298634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3715298634 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.2102229842
Short name T57
Test name
Test status
Simulation time 3332226169 ps
CPU time 194.99 seconds
Started Oct 03 10:36:37 AM UTC 24
Finished Oct 03 10:39:55 AM UTC 24
Peak memory 277692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2102229842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_
with_rand_reset.2102229842 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.744683571
Short name T62
Test name
Test status
Simulation time 7994519564 ps
CPU time 44.46 seconds
Started Oct 03 10:29:14 AM UTC 24
Finished Oct 03 10:30:13 AM UTC 24
Peak memory 234224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744683571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.744683571 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.989000583
Short name T135
Test name
Test status
Simulation time 36629439 ps
CPU time 1.36 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:55 AM UTC 24
Peak memory 228684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989000583 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.989000583 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.1363750329
Short name T100
Test name
Test status
Simulation time 105280852 ps
CPU time 1.5 seconds
Started Oct 03 10:54:43 AM UTC 24
Finished Oct 03 10:54:45 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363750329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1363750329 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.3850634662
Short name T47
Test name
Test status
Simulation time 33378507 ps
CPU time 1.8 seconds
Started Oct 03 11:00:12 AM UTC 24
Finished Oct 03 11:00:15 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850634662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3850634662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.680112887
Short name T19
Test name
Test status
Simulation time 15699326 ps
CPU time 0.94 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:29:37 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680112887 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.680112887 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1494091252
Short name T109
Test name
Test status
Simulation time 30542114 ps
CPU time 1.29 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494091252 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1494091252 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.800431317
Short name T24
Test name
Test status
Simulation time 4654492496 ps
CPU time 53.7 seconds
Started Oct 03 10:29:43 AM UTC 24
Finished Oct 03 10:30:42 AM UTC 24
Peak memory 273236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800431317 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.800431317 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1725763716
Short name T105
Test name
Test status
Simulation time 219503238 ps
CPU time 1.43 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725763716 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1725763716 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.1492171757
Short name T52
Test name
Test status
Simulation time 4814603272 ps
CPU time 41.4 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:30:08 AM UTC 24
Peak memory 252568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492171757 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1492171757
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.622208025
Short name T128
Test name
Test status
Simulation time 367805588 ps
CPU time 3.7 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 229520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622208025 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.622208025 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.4281625164
Short name T143
Test name
Test status
Simulation time 13690203064 ps
CPU time 521.36 seconds
Started Oct 03 10:33:36 AM UTC 24
Finished Oct 03 10:42:24 AM UTC 24
Peak memory 250676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281625164 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.4281625164 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3950060139
Short name T127
Test name
Test status
Simulation time 26378328 ps
CPU time 0.86 seconds
Started Oct 03 10:28:58 AM UTC 24
Finished Oct 03 10:29:00 AM UTC 24
Peak memory 218684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950060139 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3950060139 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.4112922417
Short name T41
Test name
Test status
Simulation time 4143866258 ps
CPU time 68.52 seconds
Started Oct 03 10:29:44 AM UTC 24
Finished Oct 03 10:31:00 AM UTC 24
Peak memory 234296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112922417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.4112922417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.2996265211
Short name T174
Test name
Test status
Simulation time 250817117 ps
CPU time 2.57 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 229616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996265211 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.2996265211 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.4039489755
Short name T175
Test name
Test status
Simulation time 357915032 ps
CPU time 3.84 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 231484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039489755 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.4039489755 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.16331377
Short name T212
Test name
Test status
Simulation time 14637710142 ps
CPU time 290.82 seconds
Started Oct 03 10:29:14 AM UTC 24
Finished Oct 03 10:34:20 AM UTC 24
Peak memory 539704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16331377 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.16331377 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.168320014
Short name T808
Test name
Test status
Simulation time 378410246 ps
CPU time 2.51 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168320014 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.
168320014 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.2922685223
Short name T34
Test name
Test status
Simulation time 2597452248 ps
CPU time 185.34 seconds
Started Oct 03 10:29:43 AM UTC 24
Finished Oct 03 10:32:55 AM UTC 24
Peak memory 316468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922685223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2922685223 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.1583333892
Short name T754
Test name
Test status
Simulation time 1063344853 ps
CPU time 9.6 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:29:00 AM UTC 24
Peak memory 229124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583333892 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1583333892 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2228375060
Short name T780
Test name
Test status
Simulation time 295178389 ps
CPU time 13.9 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 218788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228375060 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2228375060 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1789677474
Short name T126
Test name
Test status
Simulation time 49940039 ps
CPU time 0.93 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:51 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789677474 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1789677474 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4275872323
Short name T130
Test name
Test status
Simulation time 35729000 ps
CPU time 2.61 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4275872323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_
mem_rw_with_rand_reset.4275872323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2537343736
Short name T146
Test name
Test status
Simulation time 449126530 ps
CPU time 1.26 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 227972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537343736 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2537343736 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.3835741052
Short name T722
Test name
Test status
Simulation time 27655465 ps
CPU time 1.38 seconds
Started Oct 03 10:28:46 AM UTC 24
Finished Oct 03 10:28:49 AM UTC 24
Peak memory 228680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835741052 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.3835741052 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.605830149
Short name T721
Test name
Test status
Simulation time 31504527 ps
CPU time 0.75 seconds
Started Oct 03 10:28:46 AM UTC 24
Finished Oct 03 10:28:48 AM UTC 24
Peak memory 218408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605830149 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.605830149 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2062413927
Short name T727
Test name
Test status
Simulation time 138717072 ps
CPU time 1.9 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 228756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062413927 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.2062413927 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3582767644
Short name T104
Test name
Test status
Simulation time 402455950 ps
CPU time 3.33 seconds
Started Oct 03 10:28:46 AM UTC 24
Finished Oct 03 10:28:51 AM UTC 24
Peak memory 236584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582767644 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.
3582767644 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.3384990644
Short name T129
Test name
Test status
Simulation time 509064791 ps
CPU time 3.32 seconds
Started Oct 03 10:28:46 AM UTC 24
Finished Oct 03 10:28:51 AM UTC 24
Peak memory 229568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384990644 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3384990644 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.4069916571
Short name T748
Test name
Test status
Simulation time 285354555 ps
CPU time 7.94 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:59 AM UTC 24
Peak memory 219144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069916571 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.4069916571 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.4001161569
Short name T744
Test name
Test status
Simulation time 160431740 ps
CPU time 7.05 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:58 AM UTC 24
Peak memory 219224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001161569 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.4001161569 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2200724769
Short name T148
Test name
Test status
Simulation time 177018000 ps
CPU time 1.03 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200724769 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2200724769 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3326534357
Short name T131
Test name
Test status
Simulation time 71038053 ps
CPU time 2.4 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:54 AM UTC 24
Peak memory 231636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326534357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_
mem_rw_with_rand_reset.3326534357 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2943609740
Short name T147
Test name
Test status
Simulation time 99594791 ps
CPU time 0.9 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943609740 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2943609740 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3192602900
Short name T166
Test name
Test status
Simulation time 19433797 ps
CPU time 0.86 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 218684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192602900 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3192602900 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2548415623
Short name T724
Test name
Test status
Simulation time 30312161 ps
CPU time 1.19 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 228680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548415623 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2548415623 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1717106717
Short name T723
Test name
Test status
Simulation time 10989543 ps
CPU time 0.76 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717106717 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1717106717 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1346289850
Short name T728
Test name
Test status
Simulation time 27196045 ps
CPU time 1.54 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 228756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346289850 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1346289850 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2296262534
Short name T116
Test name
Test status
Simulation time 36427847 ps
CPU time 1.71 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296262534 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.
2296262534 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.153345272
Short name T133
Test name
Test status
Simulation time 625287506 ps
CPU time 2.89 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:54 AM UTC 24
Peak memory 229840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153345272 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.153345272 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1530730998
Short name T122
Test name
Test status
Simulation time 199716596 ps
CPU time 2.37 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 229508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530730998 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.1530730998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2424051998
Short name T784
Test name
Test status
Simulation time 100417674 ps
CPU time 1.64 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 228624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2424051998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr
_mem_rw_with_rand_reset.2424051998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.4155773700
Short name T779
Test name
Test status
Simulation time 157022632 ps
CPU time 1.1 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 228728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155773700 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.4155773700 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3457124368
Short name T777
Test name
Test status
Simulation time 21906626 ps
CPU time 0.88 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457124368 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3457124368 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2760082787
Short name T783
Test name
Test status
Simulation time 22494566 ps
CPU time 1.46 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 228752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760082787 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.2760082787 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2024208998
Short name T770
Test name
Test status
Simulation time 110127070 ps
CPU time 1.58 seconds
Started Oct 03 10:29:01 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 228676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024208998 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.2024208998 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3771626000
Short name T772
Test name
Test status
Simulation time 28605174 ps
CPU time 1.76 seconds
Started Oct 03 10:29:01 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 228560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771626000 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw
.3771626000 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2358184018
Short name T797
Test name
Test status
Simulation time 165810020 ps
CPU time 4 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 229660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358184018 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2358184018 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2757243113
Short name T179
Test name
Test status
Simulation time 219696649 ps
CPU time 4.1 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757243113 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2757243113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1727906163
Short name T791
Test name
Test status
Simulation time 77189475 ps
CPU time 2.61 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1727906163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr
_mem_rw_with_rand_reset.1727906163 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1073000624
Short name T781
Test name
Test status
Simulation time 28741125 ps
CPU time 0.87 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073000624 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1073000624 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1854100412
Short name T782
Test name
Test status
Simulation time 12919931 ps
CPU time 0.89 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854100412 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1854100412 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.328872873
Short name T788
Test name
Test status
Simulation time 438193003 ps
CPU time 2.46 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:06 AM UTC 24
Peak memory 229448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328872873 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.328872873 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4108923795
Short name T112
Test name
Test status
Simulation time 31204017 ps
CPU time 1.32 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108923795 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.4108923795 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1800114404
Short name T787
Test name
Test status
Simulation time 63934721 ps
CPU time 2.61 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:06 AM UTC 24
Peak memory 236292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800114404 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw
.1800114404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2445747125
Short name T793
Test name
Test status
Simulation time 683409358 ps
CPU time 2.93 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 229624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445747125 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2445747125 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.788941064
Short name T177
Test name
Test status
Simulation time 395336300 ps
CPU time 5.63 seconds
Started Oct 03 10:29:02 AM UTC 24
Finished Oct 03 10:29:10 AM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788941064 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.788941064 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2656234994
Short name T801
Test name
Test status
Simulation time 83951765 ps
CPU time 2.3 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2656234994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr
_mem_rw_with_rand_reset.2656234994 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1802309296
Short name T789
Test name
Test status
Simulation time 61339499 ps
CPU time 1.2 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:06 AM UTC 24
Peak memory 218712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802309296 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1802309296 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2089814040
Short name T785
Test name
Test status
Simulation time 26431133 ps
CPU time 0.86 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:06 AM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089814040 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2089814040 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.858338310
Short name T795
Test name
Test status
Simulation time 54196451 ps
CPU time 1.58 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 228808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858338310 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.858338310 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3202684567
Short name T114
Test name
Test status
Simulation time 21520524 ps
CPU time 1.05 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:06 AM UTC 24
Peak memory 228676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202684567 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.3202684567 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1345845233
Short name T792
Test name
Test status
Simulation time 193772688 ps
CPU time 1.69 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345845233 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw
.1345845233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2500748210
Short name T790
Test name
Test status
Simulation time 49442530 ps
CPU time 1.61 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 228680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500748210 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2500748210 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.485991891
Short name T181
Test name
Test status
Simulation time 398592254 ps
CPU time 4.28 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 219276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485991891 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.485991891 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2003648912
Short name T811
Test name
Test status
Simulation time 255090437 ps
CPU time 2.28 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 236588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2003648912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr
_mem_rw_with_rand_reset.2003648912 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.1485600945
Short name T799
Test name
Test status
Simulation time 105444558 ps
CPU time 1.27 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 228648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485600945 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1485600945 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.272931618
Short name T796
Test name
Test status
Simulation time 16069850 ps
CPU time 0.86 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 218668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272931618 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.272931618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3343520504
Short name T809
Test name
Test status
Simulation time 122812474 ps
CPU time 1.77 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 228732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343520504 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3343520504 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1823434918
Short name T794
Test name
Test status
Simulation time 46314170 ps
CPU time 1.39 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823434918 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1823434918 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2350462975
Short name T803
Test name
Test status
Simulation time 67145386 ps
CPU time 2.22 seconds
Started Oct 03 10:29:04 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350462975 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2350462975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3480782513
Short name T812
Test name
Test status
Simulation time 68267068 ps
CPU time 2.44 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 231580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480782513 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3480782513 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.4182849309
Short name T806
Test name
Test status
Simulation time 158336746 ps
CPU time 1.3 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 228116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4182849309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr
_mem_rw_with_rand_reset.4182849309 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2962455645
Short name T802
Test name
Test status
Simulation time 27735045 ps
CPU time 1.1 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962455645 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2962455645 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3401538654
Short name T798
Test name
Test status
Simulation time 20737102 ps
CPU time 1.03 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:07 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401538654 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3401538654 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.553037495
Short name T815
Test name
Test status
Simulation time 101557657 ps
CPU time 2.6 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553037495 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.553037495 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1204632819
Short name T800
Test name
Test status
Simulation time 63413573 ps
CPU time 1.19 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 218376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204632819 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.1204632819 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1581391377
Short name T805
Test name
Test status
Simulation time 87459824 ps
CPU time 1.47 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 228872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581391377 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1581391377 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2936230243
Short name T178
Test name
Test status
Simulation time 366022854 ps
CPU time 4.1 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936230243 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2936230243 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.396145568
Short name T818
Test name
Test status
Simulation time 42805201 ps
CPU time 1.89 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:10 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=396145568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_
mem_rw_with_rand_reset.396145568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.82456065
Short name T813
Test name
Test status
Simulation time 29622947 ps
CPU time 1.1 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 218760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82456065 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.82456065 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1869520958
Short name T810
Test name
Test status
Simulation time 161025485 ps
CPU time 0.79 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869520958 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1869520958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3232030104
Short name T816
Test name
Test status
Simulation time 203336492 ps
CPU time 1.49 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232030104 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3232030104 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.343083096
Short name T807
Test name
Test status
Simulation time 233869608 ps
CPU time 1.33 seconds
Started Oct 03 10:29:05 AM UTC 24
Finished Oct 03 10:29:08 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343083096 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.343083096 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4225195606
Short name T820
Test name
Test status
Simulation time 463182341 ps
CPU time 2.79 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:10 AM UTC 24
Peak memory 236984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225195606 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw
.4225195606 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3030930501
Short name T817
Test name
Test status
Simulation time 127918168 ps
CPU time 1.87 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:10 AM UTC 24
Peak memory 228680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030930501 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3030930501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.861111399
Short name T176
Test name
Test status
Simulation time 514390489 ps
CPU time 4.79 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 229460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861111399 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.861111399 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2633051493
Short name T831
Test name
Test status
Simulation time 1107481759 ps
CPU time 2.57 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2633051493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr
_mem_rw_with_rand_reset.2633051493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3693448928
Short name T822
Test name
Test status
Simulation time 59414800 ps
CPU time 1.23 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 218712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693448928 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3693448928 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2615318871
Short name T819
Test name
Test status
Simulation time 13741361 ps
CPU time 0.75 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:10 AM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615318871 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2615318871 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3774786919
Short name T825
Test name
Test status
Simulation time 83030840 ps
CPU time 1.38 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774786919 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.3774786919 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.765291857
Short name T814
Test name
Test status
Simulation time 48351928 ps
CPU time 1.09 seconds
Started Oct 03 10:29:07 AM UTC 24
Finished Oct 03 10:29:09 AM UTC 24
Peak memory 218380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765291857 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.765291857 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3726684706
Short name T833
Test name
Test status
Simulation time 167096834 ps
CPU time 2.99 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 237076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726684706 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw
.3726684706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1477900188
Short name T826
Test name
Test status
Simulation time 33430266 ps
CPU time 2.05 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477900188 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1477900188 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3477954041
Short name T843
Test name
Test status
Simulation time 248469048 ps
CPU time 2.18 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 229016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3477954041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr
_mem_rw_with_rand_reset.3477954041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1378652751
Short name T823
Test name
Test status
Simulation time 36317825 ps
CPU time 0.97 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 218296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378652751 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1378652751 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2915292961
Short name T821
Test name
Test status
Simulation time 12698692 ps
CPU time 0.86 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:10 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915292961 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2915292961 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3820282095
Short name T827
Test name
Test status
Simulation time 55047243 ps
CPU time 1.59 seconds
Started Oct 03 10:29:09 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 228700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820282095 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.3820282095 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3045672402
Short name T824
Test name
Test status
Simulation time 28180296 ps
CPU time 1.23 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045672402 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.3045672402 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3866824309
Short name T828
Test name
Test status
Simulation time 61393553 ps
CPU time 1.87 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:11 AM UTC 24
Peak memory 228624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866824309 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw
.3866824309 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1855548344
Short name T830
Test name
Test status
Simulation time 83277397 ps
CPU time 2.34 seconds
Started Oct 03 10:29:08 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855548344 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1855548344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1710602690
Short name T846
Test name
Test status
Simulation time 136350437 ps
CPU time 2.47 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 236584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1710602690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr
_mem_rw_with_rand_reset.1710602690 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.1237325425
Short name T834
Test name
Test status
Simulation time 27129814 ps
CPU time 1.2 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237325425 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1237325425 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2724207156
Short name T804
Test name
Test status
Simulation time 16133212 ps
CPU time 0.98 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724207156 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2724207156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2717576674
Short name T842
Test name
Test status
Simulation time 62037449 ps
CPU time 1.72 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717576674 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.2717576674 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2738372373
Short name T832
Test name
Test status
Simulation time 28899745 ps
CPU time 1.28 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 227780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738372373 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.2738372373 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1979230887
Short name T849
Test name
Test status
Simulation time 488104042 ps
CPU time 2.73 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 229872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979230887 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw
.1979230887 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2655552604
Short name T844
Test name
Test status
Simulation time 64477865 ps
CPU time 2.17 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 229620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655552604 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2655552604 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1600793315
Short name T852
Test name
Test status
Simulation time 213203785 ps
CPU time 2.98 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600793315 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1600793315 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4038421968
Short name T850
Test name
Test status
Simulation time 118365854 ps
CPU time 2.27 seconds
Started Oct 03 10:29:11 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 231828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4038421968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr
_mem_rw_with_rand_reset.4038421968 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3616206301
Short name T835
Test name
Test status
Simulation time 23121423 ps
CPU time 1.02 seconds
Started Oct 03 10:29:11 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616206301 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3616206301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.3914250709
Short name T836
Test name
Test status
Simulation time 12162957 ps
CPU time 0.97 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914250709 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3914250709 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3328816396
Short name T848
Test name
Test status
Simulation time 38130731 ps
CPU time 2.18 seconds
Started Oct 03 10:29:11 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 229440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328816396 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.3328816396 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2074962096
Short name T841
Test name
Test status
Simulation time 123432510 ps
CPU time 1.67 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 228676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074962096 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2074962096 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.385994637
Short name T847
Test name
Test status
Simulation time 728297605 ps
CPU time 2.36 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 236464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385994637 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.
385994637 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.749996911
Short name T851
Test name
Test status
Simulation time 50782443 ps
CPU time 2.59 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 229840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749996911 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.749996911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3369084990
Short name T845
Test name
Test status
Simulation time 194793354 ps
CPU time 2.2 seconds
Started Oct 03 10:29:10 AM UTC 24
Finished Oct 03 10:29:14 AM UTC 24
Peak memory 229472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369084990 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3369084990 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3119725221
Short name T153
Test name
Test status
Simulation time 499479629 ps
CPU time 4.8 seconds
Started Oct 03 10:28:52 AM UTC 24
Finished Oct 03 10:28:58 AM UTC 24
Peak memory 219144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119725221 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3119725221 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2140635939
Short name T853
Test name
Test status
Simulation time 9058187721 ps
CPU time 23.58 seconds
Started Oct 03 10:28:51 AM UTC 24
Finished Oct 03 10:29:16 AM UTC 24
Peak memory 219468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140635939 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2140635939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.756915369
Short name T726
Test name
Test status
Simulation time 82610038 ps
CPU time 1.02 seconds
Started Oct 03 10:28:51 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756915369 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.756915369 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2345128188
Short name T736
Test name
Test status
Simulation time 398024742 ps
CPU time 2.75 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2345128188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_
mem_rw_with_rand_reset.2345128188 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1392300669
Short name T729
Test name
Test status
Simulation time 27094780 ps
CPU time 1.24 seconds
Started Oct 03 10:28:51 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 218708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392300669 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1392300669 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.570727994
Short name T169
Test name
Test status
Simulation time 45044326 ps
CPU time 0.78 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 218872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570727994 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.570727994 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.1514723331
Short name T134
Test name
Test status
Simulation time 53361540 ps
CPU time 1.62 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 228744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514723331 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.1514723331 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2478884142
Short name T725
Test name
Test status
Simulation time 21692244 ps
CPU time 0.93 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478884142 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2478884142 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2347406174
Short name T732
Test name
Test status
Simulation time 51148133 ps
CPU time 1.52 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:55 AM UTC 24
Peak memory 228756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347406174 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.2347406174 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4013810699
Short name T115
Test name
Test status
Simulation time 77838170 ps
CPU time 1.02 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:52 AM UTC 24
Peak memory 218444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013810699 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.4013810699 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.238295381
Short name T149
Test name
Test status
Simulation time 119329108 ps
CPU time 1.9 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:53 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238295381 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.2
38295381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.1311313195
Short name T132
Test name
Test status
Simulation time 95768035 ps
CPU time 2.43 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:54 AM UTC 24
Peak memory 229584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311313195 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1311313195 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.3601401469
Short name T123
Test name
Test status
Simulation time 229226728 ps
CPU time 4.44 seconds
Started Oct 03 10:28:50 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601401469 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.3601401469 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2364292498
Short name T838
Test name
Test status
Simulation time 79211715 ps
CPU time 0.89 seconds
Started Oct 03 10:29:11 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364292498 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2364292498 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3179002099
Short name T840
Test name
Test status
Simulation time 53848656 ps
CPU time 0.89 seconds
Started Oct 03 10:29:11 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179002099 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3179002099 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2855067893
Short name T837
Test name
Test status
Simulation time 18720715 ps
CPU time 0.93 seconds
Started Oct 03 10:29:11 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855067893 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2855067893 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.244704845
Short name T839
Test name
Test status
Simulation time 166782606 ps
CPU time 0.8 seconds
Started Oct 03 10:29:11 AM UTC 24
Finished Oct 03 10:29:13 AM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244704845 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.244704845 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2030576976
Short name T856
Test name
Test status
Simulation time 84983424 ps
CPU time 0.96 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030576976 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2030576976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3477470464
Short name T855
Test name
Test status
Simulation time 14635052 ps
CPU time 0.87 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477470464 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3477470464 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1303100006
Short name T854
Test name
Test status
Simulation time 31588111 ps
CPU time 0.88 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303100006 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1303100006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2596015182
Short name T857
Test name
Test status
Simulation time 48677460 ps
CPU time 0.91 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596015182 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2596015182 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.521411325
Short name T862
Test name
Test status
Simulation time 23423898 ps
CPU time 0.91 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521411325 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.521411325 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.4268032737
Short name T858
Test name
Test status
Simulation time 45942200 ps
CPU time 0.86 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268032737 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4268032737 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.907999708
Short name T750
Test name
Test status
Simulation time 203113944 ps
CPU time 5.39 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:59 AM UTC 24
Peak memory 218928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907999708 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.907999708 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.76974098
Short name T829
Test name
Test status
Simulation time 1014010412 ps
CPU time 17.78 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:29:12 AM UTC 24
Peak memory 219412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76974098 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.76974098 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2640341824
Short name T731
Test name
Test status
Simulation time 29287116 ps
CPU time 1.05 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:55 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640341824 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2640341824 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2343290162
Short name T151
Test name
Test status
Simulation time 171102196 ps
CPU time 1.72 seconds
Started Oct 03 10:28:54 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2343290162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_
mem_rw_with_rand_reset.2343290162 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.3067408975
Short name T150
Test name
Test status
Simulation time 110489171 ps
CPU time 1.21 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:55 AM UTC 24
Peak memory 218716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067408975 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3067408975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2483593072
Short name T167
Test name
Test status
Simulation time 16203537 ps
CPU time 1.06 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:55 AM UTC 24
Peak memory 218684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483593072 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2483593072 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.4238234908
Short name T730
Test name
Test status
Simulation time 65006130 ps
CPU time 0.88 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:55 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238234908 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.4238234908 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4030317432
Short name T733
Test name
Test status
Simulation time 44712190 ps
CPU time 1.61 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 228740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030317432 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.4030317432 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.67140605
Short name T107
Test name
Test status
Simulation time 110914813 ps
CPU time 1.11 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:55 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67140605 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.67140605 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4214354824
Short name T110
Test name
Test status
Simulation time 345813858 ps
CPU time 2.72 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 236336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214354824 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.
4214354824 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.4132040616
Short name T740
Test name
Test status
Simulation time 1679876604 ps
CPU time 3.3 seconds
Started Oct 03 10:28:53 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 229584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132040616 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.4132040616 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.399439339
Short name T859
Test name
Test status
Simulation time 12533850 ps
CPU time 0.8 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399439339 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.399439339 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1367267464
Short name T861
Test name
Test status
Simulation time 15807246 ps
CPU time 0.82 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367267464 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1367267464 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1473608820
Short name T863
Test name
Test status
Simulation time 23219810 ps
CPU time 0.79 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473608820 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1473608820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.41449162
Short name T864
Test name
Test status
Simulation time 47567993 ps
CPU time 0.85 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41449162 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.41449162 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.3176363652
Short name T860
Test name
Test status
Simulation time 14764073 ps
CPU time 0.81 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:27 AM UTC 24
Peak memory 218784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176363652 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3176363652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2097095442
Short name T865
Test name
Test status
Simulation time 32604196 ps
CPU time 0.94 seconds
Started Oct 03 10:29:12 AM UTC 24
Finished Oct 03 10:29:28 AM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097095442 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2097095442 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1752912705
Short name T867
Test name
Test status
Simulation time 41523545 ps
CPU time 0.69 seconds
Started Oct 03 10:29:13 AM UTC 24
Finished Oct 03 10:29:32 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752912705 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1752912705 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3024379662
Short name T869
Test name
Test status
Simulation time 16838971 ps
CPU time 0.81 seconds
Started Oct 03 10:29:13 AM UTC 24
Finished Oct 03 10:29:33 AM UTC 24
Peak memory 218596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024379662 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3024379662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1662973243
Short name T868
Test name
Test status
Simulation time 36999834 ps
CPU time 0.76 seconds
Started Oct 03 10:29:13 AM UTC 24
Finished Oct 03 10:29:32 AM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662973243 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1662973243 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1958700251
Short name T743
Test name
Test status
Simulation time 96508238 ps
CPU time 4.43 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:29:00 AM UTC 24
Peak memory 219204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958700251 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1958700251 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3541628967
Short name T786
Test name
Test status
Simulation time 740142457 ps
CPU time 10.2 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:29:06 AM UTC 24
Peak memory 219208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541628967 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3541628967 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.3820682345
Short name T737
Test name
Test status
Simulation time 46376606 ps
CPU time 1.35 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 228752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820682345 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3820682345 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3825719438
Short name T155
Test name
Test status
Simulation time 159161129 ps
CPU time 2.84 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:28:59 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3825719438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_
mem_rw_with_rand_reset.3825719438 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2296546851
Short name T738
Test name
Test status
Simulation time 54826824 ps
CPU time 1.26 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296546851 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2296546851 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.384060199
Short name T168
Test name
Test status
Simulation time 28602300 ps
CPU time 0.94 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 218872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384060199 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.384060199 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.318606930
Short name T136
Test name
Test status
Simulation time 133089207 ps
CPU time 1.76 seconds
Started Oct 03 10:28:54 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 228748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318606930 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.318606930 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.1114347826
Short name T734
Test name
Test status
Simulation time 31772370 ps
CPU time 0.97 seconds
Started Oct 03 10:28:54 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114347826 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1114347826 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.685090470
Short name T152
Test name
Test status
Simulation time 411540799 ps
CPU time 2.28 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:28:58 AM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685090470 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.685090470 +enable_m
asking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.679756722
Short name T735
Test name
Test status
Simulation time 66986023 ps
CPU time 1.03 seconds
Started Oct 03 10:28:54 AM UTC 24
Finished Oct 03 10:28:56 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679756722 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.679756722 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1093673052
Short name T742
Test name
Test status
Simulation time 347473776 ps
CPU time 2.02 seconds
Started Oct 03 10:28:54 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093673052 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.
1093673052 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3786566655
Short name T741
Test name
Test status
Simulation time 104518732 ps
CPU time 1.68 seconds
Started Oct 03 10:28:54 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 228664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786566655 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3786566655 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.2897570843
Short name T172
Test name
Test status
Simulation time 109434735 ps
CPU time 2.43 seconds
Started Oct 03 10:28:54 AM UTC 24
Finished Oct 03 10:28:58 AM UTC 24
Peak memory 219332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897570843 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.2897570843 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.74358269
Short name T866
Test name
Test status
Simulation time 139539688 ps
CPU time 0.78 seconds
Started Oct 03 10:29:14 AM UTC 24
Finished Oct 03 10:29:29 AM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74358269 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.74358269 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1267516998
Short name T747
Test name
Test status
Simulation time 51013402 ps
CPU time 1.95 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:28:59 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1267516998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_
mem_rw_with_rand_reset.1267516998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.1091502353
Short name T154
Test name
Test status
Simulation time 127093712 ps
CPU time 1.29 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:28:58 AM UTC 24
Peak memory 228764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091502353 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1091502353 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2024006029
Short name T170
Test name
Test status
Simulation time 19945621 ps
CPU time 0.99 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:28:58 AM UTC 24
Peak memory 218684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024006029 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2024006029 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1194691393
Short name T746
Test name
Test status
Simulation time 219095312 ps
CPU time 1.75 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:28:59 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194691393 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1194691393 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3741256416
Short name T739
Test name
Test status
Simulation time 69084776 ps
CPU time 1.06 seconds
Started Oct 03 10:28:55 AM UTC 24
Finished Oct 03 10:28:57 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741256416 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.3741256416 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2851522519
Short name T745
Test name
Test status
Simulation time 60077687 ps
CPU time 1.83 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:28:59 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851522519 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.
2851522519 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.4029548153
Short name T751
Test name
Test status
Simulation time 161358480 ps
CPU time 3.12 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:29:00 AM UTC 24
Peak memory 229584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029548153 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4029548153 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.343670318
Short name T173
Test name
Test status
Simulation time 520557239 ps
CPU time 4.03 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343670318 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.343670318 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2229656142
Short name T761
Test name
Test status
Simulation time 271939005 ps
CPU time 2.43 seconds
Started Oct 03 10:28:58 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 231636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2229656142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_
mem_rw_with_rand_reset.2229656142 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.467985795
Short name T752
Test name
Test status
Simulation time 111248258 ps
CPU time 1.38 seconds
Started Oct 03 10:28:57 AM UTC 24
Finished Oct 03 10:29:00 AM UTC 24
Peak memory 218708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467985795 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.467985795 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.622408924
Short name T749
Test name
Test status
Simulation time 31210654 ps
CPU time 0.89 seconds
Started Oct 03 10:28:57 AM UTC 24
Finished Oct 03 10:29:00 AM UTC 24
Peak memory 218812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622408924 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.622408924 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1434891806
Short name T759
Test name
Test status
Simulation time 372820478 ps
CPU time 2.53 seconds
Started Oct 03 10:28:58 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434891806 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1434891806 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1846487897
Short name T108
Test name
Test status
Simulation time 172125877 ps
CPU time 1.65 seconds
Started Oct 03 10:28:56 AM UTC 24
Finished Oct 03 10:28:59 AM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846487897 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.1846487897 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.649332448
Short name T111
Test name
Test status
Simulation time 200311769 ps
CPU time 2.66 seconds
Started Oct 03 10:28:57 AM UTC 24
Finished Oct 03 10:29:02 AM UTC 24
Peak memory 236660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649332448 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.6
49332448 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.2898994458
Short name T767
Test name
Test status
Simulation time 190916971 ps
CPU time 4.04 seconds
Started Oct 03 10:28:57 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 229628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898994458 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2898994458 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.206473538
Short name T180
Test name
Test status
Simulation time 2324840938 ps
CPU time 4.81 seconds
Started Oct 03 10:28:57 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206473538 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.206473538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3503043454
Short name T762
Test name
Test status
Simulation time 31586369 ps
CPU time 2.04 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:02 AM UTC 24
Peak memory 236652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3503043454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_
mem_rw_with_rand_reset.3503043454 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3676662032
Short name T758
Test name
Test status
Simulation time 127602470 ps
CPU time 1.43 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 218716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676662032 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3676662032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3787483130
Short name T757
Test name
Test status
Simulation time 181036580 ps
CPU time 1.44 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 228800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787483130 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3787483130 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1382765964
Short name T106
Test name
Test status
Simulation time 53812001 ps
CPU time 1.04 seconds
Started Oct 03 10:28:58 AM UTC 24
Finished Oct 03 10:29:00 AM UTC 24
Peak memory 218444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382765964 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.1382765964 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1498933899
Short name T120
Test name
Test status
Simulation time 196208878 ps
CPU time 1.63 seconds
Started Oct 03 10:28:58 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 228628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498933899 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.
1498933899 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.534598079
Short name T756
Test name
Test status
Simulation time 301026154 ps
CPU time 2.47 seconds
Started Oct 03 10:28:58 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 229884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534598079 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.534598079 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3897221563
Short name T773
Test name
Test status
Simulation time 219146128 ps
CPU time 4.88 seconds
Started Oct 03 10:28:58 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 229508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897221563 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.3897221563 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4072414615
Short name T766
Test name
Test status
Simulation time 356188141 ps
CPU time 2.49 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4072414615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_
mem_rw_with_rand_reset.4072414615 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2449916741
Short name T753
Test name
Test status
Simulation time 71846244 ps
CPU time 1.27 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449916741 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2449916741 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1973495748
Short name T755
Test name
Test status
Simulation time 45763002 ps
CPU time 0.97 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:01 AM UTC 24
Peak memory 218684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973495748 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1973495748 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1027963450
Short name T765
Test name
Test status
Simulation time 323239643 ps
CPU time 2.42 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 229468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027963450 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.1027963450 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4156961914
Short name T113
Test name
Test status
Simulation time 218066425 ps
CPU time 2.89 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156961914 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.
4156961914 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.137604428
Short name T769
Test name
Test status
Simulation time 108067668 ps
CPU time 3.46 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 229648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137604428 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.137604428 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4147953313
Short name T764
Test name
Test status
Simulation time 147636324 ps
CPU time 2.52 seconds
Started Oct 03 10:28:59 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 229428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147953313 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.4147953313 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3842163727
Short name T771
Test name
Test status
Simulation time 154887635 ps
CPU time 1.71 seconds
Started Oct 03 10:29:01 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 235664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3842163727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_
mem_rw_with_rand_reset.3842163727 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3912234476
Short name T768
Test name
Test status
Simulation time 41826312 ps
CPU time 1.19 seconds
Started Oct 03 10:29:01 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912234476 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3912234476 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.2371211610
Short name T760
Test name
Test status
Simulation time 174036728 ps
CPU time 0.92 seconds
Started Oct 03 10:29:00 AM UTC 24
Finished Oct 03 10:29:02 AM UTC 24
Peak memory 218684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371211610 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2371211610 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3730687893
Short name T775
Test name
Test status
Simulation time 84833541 ps
CPU time 2.32 seconds
Started Oct 03 10:29:01 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 229472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730687893 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3730687893 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1235945075
Short name T763
Test name
Test status
Simulation time 53628665 ps
CPU time 1.14 seconds
Started Oct 03 10:29:00 AM UTC 24
Finished Oct 03 10:29:03 AM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235945075 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.1235945075 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4256498702
Short name T774
Test name
Test status
Simulation time 180904234 ps
CPU time 2.5 seconds
Started Oct 03 10:29:00 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256498702 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.
4256498702 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.776518282
Short name T778
Test name
Test status
Simulation time 46708278 ps
CPU time 3.13 seconds
Started Oct 03 10:29:00 AM UTC 24
Finished Oct 03 10:29:05 AM UTC 24
Peak memory 229628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776518282 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.776518282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1323904942
Short name T776
Test name
Test status
Simulation time 200919051 ps
CPU time 2.76 seconds
Started Oct 03 10:29:00 AM UTC 24
Finished Oct 03 10:29:04 AM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323904942 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1323904942 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.905086896
Short name T158
Test name
Test status
Simulation time 21188525516 ps
CPU time 250.44 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:33:40 AM UTC 24
Peak memory 435028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905086896 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.905086896 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.2734918886
Short name T25
Test name
Test status
Simulation time 29414217623 ps
CPU time 110.75 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:31:19 AM UTC 24
Peak memory 267096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734918886 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2734918886 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.163762320
Short name T310
Test name
Test status
Simulation time 53186127499 ps
CPU time 942.21 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:45:19 AM UTC 24
Peak memory 273708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163762320 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.163762320 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.3148972825
Short name T246
Test name
Test status
Simulation time 74136364813 ps
CPU time 575.29 seconds
Started Oct 03 10:29:14 AM UTC 24
Finished Oct 03 10:39:10 AM UTC 24
Peak memory 1027680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148972825 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.3148972825 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.1895864867
Short name T88
Test name
Test status
Simulation time 33133090059 ps
CPU time 333.24 seconds
Started Oct 03 10:29:17 AM UTC 24
Finished Oct 03 10:35:05 AM UTC 24
Peak memory 541820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895864867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1895864867 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.2226722488
Short name T341
Test name
Test status
Simulation time 30152843683 ps
CPU time 1111.15 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:48:21 AM UTC 24
Peak memory 1586064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226722488 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2226722488 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.3089359345
Short name T1
Test name
Test status
Simulation time 77145945 ps
CPU time 2.16 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:29:29 AM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089359345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.3089359345 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.2478987727
Short name T2
Test name
Test status
Simulation time 73382464 ps
CPU time 2.2 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:29:29 AM UTC 24
Peak memory 229492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478987727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2478987727 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.112271451
Short name T504
Test name
Test status
Simulation time 246523891052 ps
CPU time 2311.01 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 11:08:23 AM UTC 24
Peak memory 3183784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112271451 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.112271451 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.653307252
Short name T13
Test name
Test status
Simulation time 1209521693 ps
CPU time 26.13 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:29:53 AM UTC 24
Peak memory 238128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653307252 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.653307252 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.589633540
Short name T313
Test name
Test status
Simulation time 9095727210 ps
CPU time 962.28 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:45:40 AM UTC 24
Peak memory 711308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589633540 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.589633540 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.438440530
Short name T157
Test name
Test status
Simulation time 8439141952 ps
CPU time 165.17 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:32:13 AM UTC 24
Peak memory 238240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438440530 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.43844053
0 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.1897131503
Short name T188
Test name
Test status
Simulation time 22840190765 ps
CPU time 416.08 seconds
Started Oct 03 10:29:15 AM UTC 24
Finished Oct 03 10:36:28 AM UTC 24
Peak memory 357016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897131503 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1897131
503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.1865181692
Short name T48
Test name
Test status
Simulation time 130122578 ps
CPU time 1.02 seconds
Started Oct 03 10:29:54 AM UTC 24
Finished Oct 03 10:29:59 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865181692 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1865181692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.1091929618
Short name T32
Test name
Test status
Simulation time 7494978512 ps
CPU time 40.5 seconds
Started Oct 03 10:29:38 AM UTC 24
Finished Oct 03 10:30:33 AM UTC 24
Peak memory 258548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091929618 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1091929618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.1046689326
Short name T55
Test name
Test status
Simulation time 6228606868 ps
CPU time 518.06 seconds
Started Oct 03 10:29:30 AM UTC 24
Finished Oct 03 10:38:15 AM UTC 24
Peak memory 250744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046689326 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1046689326 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.108212689
Short name T50
Test name
Test status
Simulation time 1891661667 ps
CPU time 14.83 seconds
Started Oct 03 10:29:43 AM UTC 24
Finished Oct 03 10:30:06 AM UTC 24
Peak memory 233380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108212689 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.108212689 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.2931978711
Short name T31
Test name
Test status
Simulation time 1606292239 ps
CPU time 35.83 seconds
Started Oct 03 10:29:44 AM UTC 24
Finished Oct 03 10:30:27 AM UTC 24
Peak memory 233928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931978711 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2931978711 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.1870619196
Short name T5
Test name
Test status
Simulation time 316188904 ps
CPU time 1.9 seconds
Started Oct 03 10:29:44 AM UTC 24
Finished Oct 03 10:29:53 AM UTC 24
Peak memory 226304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870619196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1870619196 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.2698887870
Short name T303
Test name
Test status
Simulation time 19301985963 ps
CPU time 917.81 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:45:05 AM UTC 24
Peak memory 820056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698887870 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.2698887870 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.4081213523
Short name T11
Test name
Test status
Simulation time 10436498794 ps
CPU time 84.82 seconds
Started Oct 03 10:29:54 AM UTC 24
Finished Oct 03 10:31:22 AM UTC 24
Peak memory 266420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081213523 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.4081213523 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.1002076492
Short name T35
Test name
Test status
Simulation time 28673334665 ps
CPU time 219.19 seconds
Started Oct 03 10:29:29 AM UTC 24
Finished Oct 03 10:33:29 AM UTC 24
Peak memory 420664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002076492 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1002076492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.130759231
Short name T16
Test name
Test status
Simulation time 1312626204 ps
CPU time 19.78 seconds
Started Oct 03 10:29:28 AM UTC 24
Finished Oct 03 10:29:57 AM UTC 24
Peak memory 233580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130759231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.130759231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.3484842493
Short name T308
Test name
Test status
Simulation time 45900058288 ps
CPU time 913.6 seconds
Started Oct 03 10:29:44 AM UTC 24
Finished Oct 03 10:45:15 AM UTC 24
Peak memory 726004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484842493 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3484842493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.122861543
Short name T12
Test name
Test status
Simulation time 115629853 ps
CPU time 1.57 seconds
Started Oct 03 10:29:35 AM UTC 24
Finished Oct 03 10:29:38 AM UTC 24
Peak memory 226296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122861543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.122861543 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.4183209375
Short name T14
Test name
Test status
Simulation time 61246415 ps
CPU time 2.13 seconds
Started Oct 03 10:29:38 AM UTC 24
Finished Oct 03 10:29:54 AM UTC 24
Peak memory 229312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183209375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.4183209375 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.3244004572
Short name T85
Test name
Test status
Simulation time 2270864880 ps
CPU time 51.36 seconds
Started Oct 03 10:29:30 AM UTC 24
Finished Oct 03 10:30:24 AM UTC 24
Peak memory 254704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244004572 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3244004572
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.569183131
Short name T81
Test name
Test status
Simulation time 1678753463 ps
CPU time 38.03 seconds
Started Oct 03 10:29:30 AM UTC 24
Finished Oct 03 10:30:10 AM UTC 24
Peak memory 252716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569183131 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.569183131 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.1698766249
Short name T87
Test name
Test status
Simulation time 2172524210 ps
CPU time 30.05 seconds
Started Oct 03 10:29:32 AM UTC 24
Finished Oct 03 10:30:26 AM UTC 24
Peak memory 233692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698766249 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1698766249
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.1626616530
Short name T17
Test name
Test status
Simulation time 274341138 ps
CPU time 12.73 seconds
Started Oct 03 10:29:33 AM UTC 24
Finished Oct 03 10:30:00 AM UTC 24
Peak memory 229420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626616530 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1626616530
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.916463128
Short name T184
Test name
Test status
Simulation time 14969950080 ps
CPU time 204.31 seconds
Started Oct 03 10:29:33 AM UTC 24
Finished Oct 03 10:33:14 AM UTC 24
Peak memory 436896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916463128 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.91646312
8 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.2372337800
Short name T94
Test name
Test status
Simulation time 7049504186 ps
CPU time 107.4 seconds
Started Oct 03 10:29:34 AM UTC 24
Finished Oct 03 10:31:31 AM UTC 24
Peak memory 263184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372337800 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2372337
800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.1101975781
Short name T245
Test name
Test status
Simulation time 47117216 ps
CPU time 1.16 seconds
Started Oct 03 10:39:05 AM UTC 24
Finished Oct 03 10:39:07 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101975781 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1101975781 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.1565137990
Short name T255
Test name
Test status
Simulation time 1991043397 ps
CPU time 61.92 seconds
Started Oct 03 10:38:44 AM UTC 24
Finished Oct 03 10:39:47 AM UTC 24
Peak memory 269012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565137990 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1565137990 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.972405182
Short name T407
Test name
Test status
Simulation time 33833112666 ps
CPU time 1042.97 seconds
Started Oct 03 10:38:41 AM UTC 24
Finished Oct 03 10:56:17 AM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972405182 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.972405182 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1145661156
Short name T247
Test name
Test status
Simulation time 613909050 ps
CPU time 13.54 seconds
Started Oct 03 10:38:57 AM UTC 24
Finished Oct 03 10:39:12 AM UTC 24
Peak memory 233276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145661156 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1145661156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.1109302100
Short name T242
Test name
Test status
Simulation time 119707492 ps
CPU time 1.58 seconds
Started Oct 03 10:38:58 AM UTC 24
Finished Oct 03 10:39:01 AM UTC 24
Peak memory 226380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109302100 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1109302100 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.2333651854
Short name T265
Test name
Test status
Simulation time 5939048380 ps
CPU time 108.22 seconds
Started Oct 03 10:38:49 AM UTC 24
Finished Oct 03 10:40:39 AM UTC 24
Peak memory 324404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333651854 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2333651854 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.3580918041
Short name T272
Test name
Test status
Simulation time 1956230714 ps
CPU time 130.01 seconds
Started Oct 03 10:38:51 AM UTC 24
Finished Oct 03 10:41:03 AM UTC 24
Peak memory 309936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580918041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3580918041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.3514570681
Short name T78
Test name
Test status
Simulation time 1278896618 ps
CPU time 10.93 seconds
Started Oct 03 10:38:52 AM UTC 24
Finished Oct 03 10:39:04 AM UTC 24
Peak memory 227168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514570681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3514570681 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.4279357362
Short name T244
Test name
Test status
Simulation time 46297986 ps
CPU time 2.11 seconds
Started Oct 03 10:39:01 AM UTC 24
Finished Oct 03 10:39:05 AM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279357362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.4279357362 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.3041218055
Short name T675
Test name
Test status
Simulation time 138062674803 ps
CPU time 2860.24 seconds
Started Oct 03 10:38:34 AM UTC 24
Finished Oct 03 11:26:48 AM UTC 24
Peak memory 3392484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041218055 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.3041218055 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.1571216978
Short name T298
Test name
Test status
Simulation time 4107701408 ps
CPU time 350.1 seconds
Started Oct 03 10:38:36 AM UTC 24
Finished Oct 03 10:44:31 AM UTC 24
Peak memory 371508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571216978 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1571216978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.3175525948
Short name T237
Test name
Test status
Simulation time 927998155 ps
CPU time 7.32 seconds
Started Oct 03 10:38:31 AM UTC 24
Finished Oct 03 10:38:40 AM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175525948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3175525948 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.720545979
Short name T391
Test name
Test status
Simulation time 49200917660 ps
CPU time 921.68 seconds
Started Oct 03 10:39:03 AM UTC 24
Finished Oct 03 10:54:37 AM UTC 24
Peak memory 721944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720545979 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.720545979 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.4056029696
Short name T253
Test name
Test status
Simulation time 41289055 ps
CPU time 1.23 seconds
Started Oct 03 10:39:43 AM UTC 24
Finished Oct 03 10:39:45 AM UTC 24
Peak memory 216372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056029696 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.4056029696 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.3507102624
Short name T273
Test name
Test status
Simulation time 2627317746 ps
CPU time 121.05 seconds
Started Oct 03 10:39:13 AM UTC 24
Finished Oct 03 10:41:17 AM UTC 24
Peak memory 269232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507102624 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3507102624 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.3964299417
Short name T343
Test name
Test status
Simulation time 40036462933 ps
CPU time 567.21 seconds
Started Oct 03 10:39:11 AM UTC 24
Finished Oct 03 10:48:46 AM UTC 24
Peak memory 248672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964299417 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3964299417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.791049487
Short name T259
Test name
Test status
Simulation time 5420822992 ps
CPU time 31.64 seconds
Started Oct 03 10:39:37 AM UTC 24
Finished Oct 03 10:40:09 AM UTC 24
Peak memory 234060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791049487 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.791049487 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.1663526990
Short name T254
Test name
Test status
Simulation time 651903602 ps
CPU time 6.99 seconds
Started Oct 03 10:39:39 AM UTC 24
Finished Oct 03 10:39:47 AM UTC 24
Peak memory 227200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663526990 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1663526990 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.897520926
Short name T294
Test name
Test status
Simulation time 6048405451 ps
CPU time 289.69 seconds
Started Oct 03 10:39:17 AM UTC 24
Finished Oct 03 10:44:11 AM UTC 24
Peak memory 341044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897520926 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.897520926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.3496690968
Short name T263
Test name
Test status
Simulation time 6109671296 ps
CPU time 55.39 seconds
Started Oct 03 10:39:31 AM UTC 24
Finished Oct 03 10:40:28 AM UTC 24
Peak memory 267100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496690968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3496690968 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.105602935
Short name T252
Test name
Test status
Simulation time 406275777 ps
CPU time 4.63 seconds
Started Oct 03 10:39:36 AM UTC 24
Finished Oct 03 10:39:42 AM UTC 24
Peak memory 227528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105602935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.105602935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.2925045233
Short name T45
Test name
Test status
Simulation time 36525928 ps
CPU time 1.9 seconds
Started Oct 03 10:39:39 AM UTC 24
Finished Oct 03 10:39:42 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925045233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2925045233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.3409055733
Short name T677
Test name
Test status
Simulation time 138213062778 ps
CPU time 2843.04 seconds
Started Oct 03 10:39:06 AM UTC 24
Finished Oct 03 11:27:00 AM UTC 24
Peak memory 3441688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409055733 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.3409055733 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.3472036610
Short name T287
Test name
Test status
Simulation time 2930178530 ps
CPU time 259.17 seconds
Started Oct 03 10:39:08 AM UTC 24
Finished Oct 03 10:43:31 AM UTC 24
Peak memory 332592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472036610 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3472036610 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.106978744
Short name T249
Test name
Test status
Simulation time 3143480130 ps
CPU time 29.24 seconds
Started Oct 03 10:39:05 AM UTC 24
Finished Oct 03 10:39:35 AM UTC 24
Peak memory 233768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106978744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.106978744 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.2114316733
Short name T469
Test name
Test status
Simulation time 129515356412 ps
CPU time 1440.49 seconds
Started Oct 03 10:39:43 AM UTC 24
Finished Oct 03 11:04:03 AM UTC 24
Peak memory 1180652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114316733 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2114316733 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.2427188306
Short name T266
Test name
Test status
Simulation time 74898413 ps
CPU time 1.3 seconds
Started Oct 03 10:40:37 AM UTC 24
Finished Oct 03 10:40:39 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427188306 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2427188306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.2230448189
Short name T279
Test name
Test status
Simulation time 1852652926 ps
CPU time 120.67 seconds
Started Oct 03 10:39:55 AM UTC 24
Finished Oct 03 10:41:59 AM UTC 24
Peak memory 265140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230448189 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2230448189 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.2332886705
Short name T301
Test name
Test status
Simulation time 6122136973 ps
CPU time 307.1 seconds
Started Oct 03 10:39:48 AM UTC 24
Finished Oct 03 10:45:00 AM UTC 24
Peak memory 240380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332886705 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2332886705 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.3945159945
Short name T270
Test name
Test status
Simulation time 1733298444 ps
CPU time 41.57 seconds
Started Oct 03 10:40:14 AM UTC 24
Finished Oct 03 10:40:57 AM UTC 24
Peak memory 233896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945159945 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3945159945 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3933541118
Short name T271
Test name
Test status
Simulation time 2878531143 ps
CPU time 39.8 seconds
Started Oct 03 10:40:19 AM UTC 24
Finished Oct 03 10:41:00 AM UTC 24
Peak memory 234088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933541118 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3933541118 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.464264735
Short name T305
Test name
Test status
Simulation time 81384771455 ps
CPU time 298.29 seconds
Started Oct 03 10:40:05 AM UTC 24
Finished Oct 03 10:45:07 AM UTC 24
Peak memory 363284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464264735 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.464264735 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.4050295701
Short name T44
Test name
Test status
Simulation time 42379714163 ps
CPU time 534.71 seconds
Started Oct 03 10:40:09 AM UTC 24
Finished Oct 03 10:49:11 AM UTC 24
Peak memory 648024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050295701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.4050295701 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.1896834081
Short name T261
Test name
Test status
Simulation time 1833538286 ps
CPU time 5.88 seconds
Started Oct 03 10:40:11 AM UTC 24
Finished Oct 03 10:40:18 AM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896834081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.1896834081 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.1141731769
Short name T267
Test name
Test status
Simulation time 1966070266 ps
CPU time 20.73 seconds
Started Oct 03 10:40:28 AM UTC 24
Finished Oct 03 10:40:50 AM UTC 24
Peak memory 234364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141731769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1141731769 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2272649395
Short name T388
Test name
Test status
Simulation time 42798106473 ps
CPU time 857.45 seconds
Started Oct 03 10:39:48 AM UTC 24
Finished Oct 03 10:54:18 AM UTC 24
Peak memory 1178000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272649395 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2272649395 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.3081598492
Short name T300
Test name
Test status
Simulation time 44631114981 ps
CPU time 305.47 seconds
Started Oct 03 10:39:48 AM UTC 24
Finished Oct 03 10:44:59 AM UTC 24
Peak memory 355064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081598492 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3081598492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.3981397004
Short name T260
Test name
Test status
Simulation time 932702055 ps
CPU time 25.91 seconds
Started Oct 03 10:39:46 AM UTC 24
Finished Oct 03 10:40:13 AM UTC 24
Peak memory 231612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981397004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3981397004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.2181500202
Short name T306
Test name
Test status
Simulation time 11355418259 ps
CPU time 273.79 seconds
Started Oct 03 10:40:29 AM UTC 24
Finished Oct 03 10:45:07 AM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181500202 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2181500202 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.809687283
Short name T278
Test name
Test status
Simulation time 35043938 ps
CPU time 1.21 seconds
Started Oct 03 10:41:33 AM UTC 24
Finished Oct 03 10:41:36 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809687283 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.809687283 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.1051271405
Short name T290
Test name
Test status
Simulation time 15367366129 ps
CPU time 185.05 seconds
Started Oct 03 10:40:52 AM UTC 24
Finished Oct 03 10:44:00 AM UTC 24
Peak memory 373664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051271405 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1051271405 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.35700651
Short name T404
Test name
Test status
Simulation time 184464547051 ps
CPU time 906.39 seconds
Started Oct 03 10:40:52 AM UTC 24
Finished Oct 03 10:56:09 AM UTC 24
Peak memory 259064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35700651 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.35700651 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.57007598
Short name T277
Test name
Test status
Simulation time 1983778930 ps
CPU time 14.7 seconds
Started Oct 03 10:41:17 AM UTC 24
Finished Oct 03 10:41:33 AM UTC 24
Peak memory 231276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57007598 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.57007598 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.2370330370
Short name T275
Test name
Test status
Simulation time 616019617 ps
CPU time 6.7 seconds
Started Oct 03 10:41:21 AM UTC 24
Finished Oct 03 10:41:30 AM UTC 24
Peak memory 229576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370330370 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2370330370 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.4050369153
Short name T288
Test name
Test status
Simulation time 14654970737 ps
CPU time 166.71 seconds
Started Oct 03 10:40:58 AM UTC 24
Finished Oct 03 10:43:48 AM UTC 24
Peak memory 346924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050369153 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.4050369153 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.3748472173
Short name T332
Test name
Test status
Simulation time 16496170542 ps
CPU time 379.75 seconds
Started Oct 03 10:41:01 AM UTC 24
Finished Oct 03 10:47:26 AM UTC 24
Peak memory 375596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748472173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3748472173 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.1576920819
Short name T274
Test name
Test status
Simulation time 2740724090 ps
CPU time 15.14 seconds
Started Oct 03 10:41:04 AM UTC 24
Finished Oct 03 10:41:20 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576920819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1576920819 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.4169668617
Short name T7
Test name
Test status
Simulation time 217984528 ps
CPU time 3.07 seconds
Started Oct 03 10:41:31 AM UTC 24
Finished Oct 03 10:41:36 AM UTC 24
Peak memory 227364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169668617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.4169668617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.479689661
Short name T534
Test name
Test status
Simulation time 123666850388 ps
CPU time 1818.31 seconds
Started Oct 03 10:40:40 AM UTC 24
Finished Oct 03 11:11:20 AM UTC 24
Peak memory 2444060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479689661 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.479689661 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.1150829730
Short name T334
Test name
Test status
Simulation time 37776376401 ps
CPU time 390.88 seconds
Started Oct 03 10:40:50 AM UTC 24
Finished Oct 03 10:47:28 AM UTC 24
Peak memory 529240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150829730 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1150829730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.1854722856
Short name T269
Test name
Test status
Simulation time 643487300 ps
CPU time 9.52 seconds
Started Oct 03 10:40:40 AM UTC 24
Finished Oct 03 10:40:51 AM UTC 24
Peak memory 229544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854722856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.1854722856 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.620858708
Short name T638
Test name
Test status
Simulation time 47117538388 ps
CPU time 2400.84 seconds
Started Oct 03 10:41:32 AM UTC 24
Finished Oct 03 11:22:04 AM UTC 24
Peak memory 839036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620858708 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.620858708 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.2808082892
Short name T285
Test name
Test status
Simulation time 43973088 ps
CPU time 1.21 seconds
Started Oct 03 10:42:53 AM UTC 24
Finished Oct 03 10:42:55 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808082892 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2808082892 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.3551796063
Short name T161
Test name
Test status
Simulation time 3276055505 ps
CPU time 114.26 seconds
Started Oct 03 10:42:06 AM UTC 24
Finished Oct 03 10:44:03 AM UTC 24
Peak memory 265180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551796063 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3551796063 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.1976272640
Short name T289
Test name
Test status
Simulation time 2698374137 ps
CPU time 109.4 seconds
Started Oct 03 10:42:00 AM UTC 24
Finished Oct 03 10:43:51 AM UTC 24
Peak memory 234236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976272640 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1976272640 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2380163311
Short name T284
Test name
Test status
Simulation time 249489933 ps
CPU time 9.67 seconds
Started Oct 03 10:42:42 AM UTC 24
Finished Oct 03 10:42:52 AM UTC 24
Peak memory 229320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380163311 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2380163311 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.1621672579
Short name T286
Test name
Test status
Simulation time 3176627131 ps
CPU time 33.67 seconds
Started Oct 03 10:42:44 AM UTC 24
Finished Oct 03 10:43:19 AM UTC 24
Peak memory 233996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621672579 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1621672579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.401715872
Short name T320
Test name
Test status
Simulation time 19291508592 ps
CPU time 248.58 seconds
Started Oct 03 10:42:09 AM UTC 24
Finished Oct 03 10:46:22 AM UTC 24
Peak memory 306008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401715872 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.401715872 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.3109336950
Short name T165
Test name
Test status
Simulation time 6393107061 ps
CPU time 206.97 seconds
Started Oct 03 10:42:25 AM UTC 24
Finished Oct 03 10:45:56 AM UTC 24
Peak memory 416820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109336950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3109336950 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.660794069
Short name T282
Test name
Test status
Simulation time 255060256 ps
CPU time 3.17 seconds
Started Oct 03 10:42:39 AM UTC 24
Finished Oct 03 10:42:44 AM UTC 24
Peak memory 227208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660794069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.660794069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.2166293677
Short name T460
Test name
Test status
Simulation time 33354852914 ps
CPU time 1235.4 seconds
Started Oct 03 10:41:37 AM UTC 24
Finished Oct 03 11:02:27 AM UTC 24
Peak memory 1713124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166293677 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.2166293677 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.1871795935
Short name T291
Test name
Test status
Simulation time 3847568176 ps
CPU time 125.75 seconds
Started Oct 03 10:41:55 AM UTC 24
Finished Oct 03 10:44:03 AM UTC 24
Peak memory 305972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871795935 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1871795935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.419541068
Short name T280
Test name
Test status
Simulation time 482818886 ps
CPU time 29.98 seconds
Started Oct 03 10:41:36 AM UTC 24
Finished Oct 03 10:42:08 AM UTC 24
Peak memory 231596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419541068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.419541068 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.2148123835
Short name T686
Test name
Test status
Simulation time 143695864279 ps
CPU time 2867.21 seconds
Started Oct 03 10:42:49 AM UTC 24
Finished Oct 03 11:31:09 AM UTC 24
Peak memory 820208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148123835 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2148123835 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.3551892084
Short name T295
Test name
Test status
Simulation time 93438304 ps
CPU time 1.35 seconds
Started Oct 03 10:44:09 AM UTC 24
Finished Oct 03 10:44:11 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551892084 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3551892084 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.1148107320
Short name T311
Test name
Test status
Simulation time 7755432849 ps
CPU time 106.27 seconds
Started Oct 03 10:43:32 AM UTC 24
Finished Oct 03 10:45:21 AM UTC 24
Peak memory 263196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148107320 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1148107320 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.2989887698
Short name T355
Test name
Test status
Simulation time 33638153879 ps
CPU time 415.15 seconds
Started Oct 03 10:43:32 AM UTC 24
Finished Oct 03 10:50:34 AM UTC 24
Peak memory 242484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989887698 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2989887698 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.87192071
Short name T297
Test name
Test status
Simulation time 748541563 ps
CPU time 19.68 seconds
Started Oct 03 10:44:04 AM UTC 24
Finished Oct 03 10:44:25 AM UTC 24
Peak memory 233644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87192071 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.87192071 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.1400518926
Short name T296
Test name
Test status
Simulation time 92727525 ps
CPU time 8.09 seconds
Started Oct 03 10:44:04 AM UTC 24
Finished Oct 03 10:44:13 AM UTC 24
Peak memory 231392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400518926 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1400518926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.3779669000
Short name T367
Test name
Test status
Simulation time 77945611477 ps
CPU time 450.83 seconds
Started Oct 03 10:43:48 AM UTC 24
Finished Oct 03 10:51:26 AM UTC 24
Peak memory 470012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779669000 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3779669000 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.3572173544
Short name T302
Test name
Test status
Simulation time 807052326 ps
CPU time 66.91 seconds
Started Oct 03 10:43:53 AM UTC 24
Finished Oct 03 10:45:01 AM UTC 24
Peak memory 267124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572173544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3572173544 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.2677593058
Short name T292
Test name
Test status
Simulation time 1027983732 ps
CPU time 3.4 seconds
Started Oct 03 10:44:01 AM UTC 24
Finished Oct 03 10:44:05 AM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677593058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2677593058 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.3043582149
Short name T46
Test name
Test status
Simulation time 33978636 ps
CPU time 1.44 seconds
Started Oct 03 10:44:06 AM UTC 24
Finished Oct 03 10:44:08 AM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043582149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3043582149 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.3887826463
Short name T349
Test name
Test status
Simulation time 15991894089 ps
CPU time 429.32 seconds
Started Oct 03 10:42:56 AM UTC 24
Finished Oct 03 10:50:12 AM UTC 24
Peak memory 474128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887826463 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.3887826463 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.3535083927
Short name T347
Test name
Test status
Simulation time 22185763696 ps
CPU time 372.34 seconds
Started Oct 03 10:43:20 AM UTC 24
Finished Oct 03 10:49:38 AM UTC 24
Peak memory 373556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535083927 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3535083927 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.2833370852
Short name T293
Test name
Test status
Simulation time 16609825244 ps
CPU time 71.84 seconds
Started Oct 03 10:42:53 AM UTC 24
Finished Oct 03 10:44:07 AM UTC 24
Peak memory 234260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833370852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2833370852 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.1439633305
Short name T439
Test name
Test status
Simulation time 11421174687 ps
CPU time 912.65 seconds
Started Oct 03 10:44:07 AM UTC 24
Finished Oct 03 10:59:32 AM UTC 24
Peak memory 529500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439633305 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1439633305 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.2348022936
Short name T307
Test name
Test status
Simulation time 25613456 ps
CPU time 1.17 seconds
Started Oct 03 10:45:08 AM UTC 24
Finished Oct 03 10:45:10 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348022936 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2348022936 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.2355841512
Short name T322
Test name
Test status
Simulation time 38008754289 ps
CPU time 118.82 seconds
Started Oct 03 10:44:32 AM UTC 24
Finished Oct 03 10:46:33 AM UTC 24
Peak memory 332592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355841512 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2355841512 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.798107038
Short name T431
Test name
Test status
Simulation time 51764396318 ps
CPU time 846.77 seconds
Started Oct 03 10:44:25 AM UTC 24
Finished Oct 03 10:58:43 AM UTC 24
Peak memory 262960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798107038 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.798107038 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2392092026
Short name T312
Test name
Test status
Simulation time 4693342535 ps
CPU time 18.71 seconds
Started Oct 03 10:45:02 AM UTC 24
Finished Oct 03 10:45:22 AM UTC 24
Peak memory 234316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392092026 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2392092026 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.392884227
Short name T309
Test name
Test status
Simulation time 106401816 ps
CPU time 8.33 seconds
Started Oct 03 10:45:06 AM UTC 24
Finished Oct 03 10:45:16 AM UTC 24
Peak memory 231324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392884227 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.392884227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.2854598591
Short name T328
Test name
Test status
Simulation time 2323308075 ps
CPU time 142.5 seconds
Started Oct 03 10:44:47 AM UTC 24
Finished Oct 03 10:47:12 AM UTC 24
Peak memory 287544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854598591 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2854598591 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.4263681789
Short name T369
Test name
Test status
Simulation time 30505757527 ps
CPU time 393.09 seconds
Started Oct 03 10:45:00 AM UTC 24
Finished Oct 03 10:51:38 AM UTC 24
Peak memory 584788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263681789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.4263681789 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.815231109
Short name T304
Test name
Test status
Simulation time 1269234880 ps
CPU time 4.13 seconds
Started Oct 03 10:45:01 AM UTC 24
Finished Oct 03 10:45:06 AM UTC 24
Peak memory 227232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815231109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.815231109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.1288536858
Short name T71
Test name
Test status
Simulation time 52050332 ps
CPU time 2.01 seconds
Started Oct 03 10:45:07 AM UTC 24
Finished Oct 03 10:45:10 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288536858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1288536858 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.3117983234
Short name T444
Test name
Test status
Simulation time 111147775456 ps
CPU time 945.99 seconds
Started Oct 03 10:44:12 AM UTC 24
Finished Oct 03 11:00:11 AM UTC 24
Peak memory 832336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117983234 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.3117983234 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.774079545
Short name T314
Test name
Test status
Simulation time 3046502757 ps
CPU time 84.44 seconds
Started Oct 03 10:44:14 AM UTC 24
Finished Oct 03 10:45:41 AM UTC 24
Peak memory 308020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774079545 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.774079545 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.3193943245
Short name T299
Test name
Test status
Simulation time 1547310511 ps
CPU time 32.55 seconds
Started Oct 03 10:44:12 AM UTC 24
Finished Oct 03 10:44:46 AM UTC 24
Peak memory 233612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193943245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3193943245 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.2560026095
Short name T672
Test name
Test status
Simulation time 341266266124 ps
CPU time 2443.37 seconds
Started Oct 03 10:45:08 AM UTC 24
Finished Oct 03 11:26:20 AM UTC 24
Peak memory 1572028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560026095 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2560026095 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.136087986
Short name T318
Test name
Test status
Simulation time 20708636 ps
CPU time 1.32 seconds
Started Oct 03 10:45:56 AM UTC 24
Finished Oct 03 10:45:59 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136087986 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.136087986 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.234948552
Short name T329
Test name
Test status
Simulation time 6787428860 ps
CPU time 114.83 seconds
Started Oct 03 10:45:20 AM UTC 24
Finished Oct 03 10:47:17 AM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234948552 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.234948552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.1667542202
Short name T325
Test name
Test status
Simulation time 3758814304 ps
CPU time 87.73 seconds
Started Oct 03 10:45:17 AM UTC 24
Finished Oct 03 10:46:47 AM UTC 24
Peak memory 234356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667542202 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1667542202 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3828293043
Short name T323
Test name
Test status
Simulation time 5346626295 ps
CPU time 55.01 seconds
Started Oct 03 10:45:42 AM UTC 24
Finished Oct 03 10:46:39 AM UTC 24
Peak memory 234024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828293043 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3828293043 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.2832683728
Short name T321
Test name
Test status
Simulation time 767482025 ps
CPU time 33.15 seconds
Started Oct 03 10:45:51 AM UTC 24
Finished Oct 03 10:46:26 AM UTC 24
Peak memory 234000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832683728 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2832683728 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.4080361224
Short name T319
Test name
Test status
Simulation time 5804518937 ps
CPU time 48.59 seconds
Started Oct 03 10:45:22 AM UTC 24
Finished Oct 03 10:46:12 AM UTC 24
Peak memory 244504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080361224 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.4080361224 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.2077015776
Short name T398
Test name
Test status
Simulation time 21667221498 ps
CPU time 605.74 seconds
Started Oct 03 10:45:23 AM UTC 24
Finished Oct 03 10:55:37 AM UTC 24
Peak memory 689012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077015776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2077015776 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.2461355548
Short name T316
Test name
Test status
Simulation time 698433185 ps
CPU time 8.41 seconds
Started Oct 03 10:45:41 AM UTC 24
Finished Oct 03 10:45:51 AM UTC 24
Peak memory 227164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461355548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2461355548 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.229653608
Short name T317
Test name
Test status
Simulation time 78659217 ps
CPU time 1.95 seconds
Started Oct 03 10:45:52 AM UTC 24
Finished Oct 03 10:45:55 AM UTC 24
Peak memory 226328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229653608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.229653608 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.4065856252
Short name T705
Test name
Test status
Simulation time 167193861710 ps
CPU time 3594.29 seconds
Started Oct 03 10:45:11 AM UTC 24
Finished Oct 03 11:45:46 AM UTC 24
Peak memory 3973928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065856252 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.4065856252 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.1482563921
Short name T365
Test name
Test status
Simulation time 4517706548 ps
CPU time 357.51 seconds
Started Oct 03 10:45:16 AM UTC 24
Finished Oct 03 10:51:18 AM UTC 24
Peak memory 387820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482563921 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1482563921 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.377199720
Short name T315
Test name
Test status
Simulation time 3349889887 ps
CPU time 37.44 seconds
Started Oct 03 10:45:11 AM UTC 24
Finished Oct 03 10:45:50 AM UTC 24
Peak memory 233860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377199720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.377199720 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.119884092
Short name T410
Test name
Test status
Simulation time 78333499600 ps
CPU time 637.49 seconds
Started Oct 03 10:45:56 AM UTC 24
Finished Oct 03 10:56:43 AM UTC 24
Peak memory 449796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119884092 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.119884092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.3331075654
Short name T331
Test name
Test status
Simulation time 42578315 ps
CPU time 1.08 seconds
Started Oct 03 10:47:18 AM UTC 24
Finished Oct 03 10:47:20 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331075654 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3331075654 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.841042589
Short name T333
Test name
Test status
Simulation time 1901224002 ps
CPU time 50.89 seconds
Started Oct 03 10:46:34 AM UTC 24
Finished Oct 03 10:47:26 AM UTC 24
Peak memory 254836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841042589 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.841042589 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.867761680
Short name T450
Test name
Test status
Simulation time 184625031299 ps
CPU time 855.32 seconds
Started Oct 03 10:46:27 AM UTC 24
Finished Oct 03 11:00:54 AM UTC 24
Peak memory 254768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867761680 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.867761680 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.648060727
Short name T335
Test name
Test status
Simulation time 1037590872 ps
CPU time 36.34 seconds
Started Oct 03 10:46:54 AM UTC 24
Finished Oct 03 10:47:32 AM UTC 24
Peak memory 233896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648060727 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.648060727 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.3230797606
Short name T336
Test name
Test status
Simulation time 3657113700 ps
CPU time 60.78 seconds
Started Oct 03 10:47:01 AM UTC 24
Finished Oct 03 10:48:04 AM UTC 24
Peak memory 234024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230797606 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3230797606 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.61438815
Short name T324
Test name
Test status
Simulation time 131784947 ps
CPU time 2.67 seconds
Started Oct 03 10:46:40 AM UTC 24
Finished Oct 03 10:46:44 AM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61438815 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.61438815 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.1699338348
Short name T380
Test name
Test status
Simulation time 35828835564 ps
CPU time 411.89 seconds
Started Oct 03 10:46:44 AM UTC 24
Finished Oct 03 10:53:42 AM UTC 24
Peak memory 660272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699338348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1699338348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.3508131577
Short name T326
Test name
Test status
Simulation time 864905722 ps
CPU time 5.16 seconds
Started Oct 03 10:46:47 AM UTC 24
Finished Oct 03 10:46:53 AM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508131577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3508131577 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.1001549899
Short name T330
Test name
Test status
Simulation time 97474316 ps
CPU time 1.8 seconds
Started Oct 03 10:47:14 AM UTC 24
Finished Oct 03 10:47:17 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001549899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1001549899 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1234268549
Short name T706
Test name
Test status
Simulation time 414244951819 ps
CPU time 3691.05 seconds
Started Oct 03 10:46:13 AM UTC 24
Finished Oct 03 11:48:26 AM UTC 24
Peak memory 3984148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234268549 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1234268549 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.189605666
Short name T359
Test name
Test status
Simulation time 39292422733 ps
CPU time 266.53 seconds
Started Oct 03 10:46:23 AM UTC 24
Finished Oct 03 10:50:53 AM UTC 24
Peak memory 434936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189605666 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.189605666 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2373602386
Short name T327
Test name
Test status
Simulation time 8433823163 ps
CPU time 58.77 seconds
Started Oct 03 10:46:00 AM UTC 24
Finished Oct 03 10:47:00 AM UTC 24
Peak memory 234328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373602386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2373602386 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.194713081
Short name T337
Test name
Test status
Simulation time 5647382819 ps
CPU time 45.52 seconds
Started Oct 03 10:47:18 AM UTC 24
Finished Oct 03 10:48:05 AM UTC 24
Peak memory 261168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194713081 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.194713081 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.4284979731
Short name T344
Test name
Test status
Simulation time 67552293 ps
CPU time 1 seconds
Started Oct 03 10:48:45 AM UTC 24
Finished Oct 03 10:48:47 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284979731 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4284979731 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.3851588030
Short name T339
Test name
Test status
Simulation time 1491829856 ps
CPU time 35.56 seconds
Started Oct 03 10:47:33 AM UTC 24
Finished Oct 03 10:48:10 AM UTC 24
Peak memory 254676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851588030 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3851588030 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.783056010
Short name T371
Test name
Test status
Simulation time 11066008523 ps
CPU time 274.58 seconds
Started Oct 03 10:47:28 AM UTC 24
Finished Oct 03 10:52:07 AM UTC 24
Peak memory 240432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783056010 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.783056010 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.2375591845
Short name T342
Test name
Test status
Simulation time 2223020965 ps
CPU time 30.83 seconds
Started Oct 03 10:48:12 AM UTC 24
Finished Oct 03 10:48:44 AM UTC 24
Peak memory 234064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375591845 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2375591845 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2802809247
Short name T346
Test name
Test status
Simulation time 3185940979 ps
CPU time 54.01 seconds
Started Oct 03 10:48:18 AM UTC 24
Finished Oct 03 10:49:13 AM UTC 24
Peak memory 233960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802809247 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2802809247 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.3706981228
Short name T366
Test name
Test status
Simulation time 27434143188 ps
CPU time 196.3 seconds
Started Oct 03 10:48:05 AM UTC 24
Finished Oct 03 10:51:25 AM UTC 24
Peak memory 312116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706981228 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3706981228 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.3233013534
Short name T377
Test name
Test status
Simulation time 7041154602 ps
CPU time 268.48 seconds
Started Oct 03 10:48:05 AM UTC 24
Finished Oct 03 10:52:38 AM UTC 24
Peak memory 416500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233013534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3233013534 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.4206798738
Short name T340
Test name
Test status
Simulation time 1842969849 ps
CPU time 6.05 seconds
Started Oct 03 10:48:10 AM UTC 24
Finished Oct 03 10:48:17 AM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206798738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.4206798738 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.3918564637
Short name T101
Test name
Test status
Simulation time 62972208 ps
CPU time 2.14 seconds
Started Oct 03 10:48:22 AM UTC 24
Finished Oct 03 10:48:25 AM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918564637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3918564637 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.263433017
Short name T692
Test name
Test status
Simulation time 446916366130 ps
CPU time 2843.73 seconds
Started Oct 03 10:47:27 AM UTC 24
Finished Oct 03 11:35:23 AM UTC 24
Peak memory 3095420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263433017 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.263433017 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.860464881
Short name T363
Test name
Test status
Simulation time 9280844771 ps
CPU time 217.4 seconds
Started Oct 03 10:47:27 AM UTC 24
Finished Oct 03 10:51:08 AM UTC 24
Peak memory 453372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860464881 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.860464881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.3174532649
Short name T338
Test name
Test status
Simulation time 2624548191 ps
CPU time 46.27 seconds
Started Oct 03 10:47:21 AM UTC 24
Finished Oct 03 10:48:09 AM UTC 24
Peak memory 234288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174532649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3174532649 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.2474456359
Short name T406
Test name
Test status
Simulation time 59352676042 ps
CPU time 463.48 seconds
Started Oct 03 10:48:26 AM UTC 24
Finished Oct 03 10:56:16 AM UTC 24
Peak memory 435312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474456359 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2474456359 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.77733584
Short name T60
Test name
Test status
Simulation time 14732103 ps
CPU time 1.23 seconds
Started Oct 03 10:30:25 AM UTC 24
Finished Oct 03 10:30:28 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77733584 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.77733584 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.3420060824
Short name T119
Test name
Test status
Simulation time 2037211521 ps
CPU time 77.39 seconds
Started Oct 03 10:30:05 AM UTC 24
Finished Oct 03 10:31:24 AM UTC 24
Peak memory 261016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420060824 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3420060824 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.2917432480
Short name T220
Test name
Test status
Simulation time 32956566375 ps
CPU time 336.76 seconds
Started Oct 03 10:30:07 AM UTC 24
Finished Oct 03 10:35:49 AM UTC 24
Peak memory 494388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917432480 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2917432480 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.547034874
Short name T54
Test name
Test status
Simulation time 5442067098 ps
CPU time 443.77 seconds
Started Oct 03 10:29:56 AM UTC 24
Finished Oct 03 10:37:26 AM UTC 24
Peak memory 244528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547034874 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.547034874 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2474490215
Short name T33
Test name
Test status
Simulation time 603782786 ps
CPU time 25.42 seconds
Started Oct 03 10:30:11 AM UTC 24
Finished Oct 03 10:30:38 AM UTC 24
Peak memory 233900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474490215 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2474490215 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.1935251367
Short name T86
Test name
Test status
Simulation time 2309174053 ps
CPU time 13.9 seconds
Started Oct 03 10:30:11 AM UTC 24
Finished Oct 03 10:30:26 AM UTC 24
Peak memory 233440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935251367 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1935251367 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.309756012
Short name T42
Test name
Test status
Simulation time 4513513037 ps
CPU time 46.78 seconds
Started Oct 03 10:30:14 AM UTC 24
Finished Oct 03 10:31:02 AM UTC 24
Peak memory 234328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309756012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.309756012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1854383211
Short name T26
Test name
Test status
Simulation time 14253594257 ps
CPU time 101.83 seconds
Started Oct 03 10:30:09 AM UTC 24
Finished Oct 03 10:31:53 AM UTC 24
Peak memory 269408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854383211 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1854383211 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.3998411558
Short name T20
Test name
Test status
Simulation time 1961256452 ps
CPU time 15.93 seconds
Started Oct 03 10:30:11 AM UTC 24
Finished Oct 03 10:30:28 AM UTC 24
Peak memory 227196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998411558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3998411558 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.2609212322
Short name T23
Test name
Test status
Simulation time 164464818 ps
CPU time 6.64 seconds
Started Oct 03 10:30:17 AM UTC 24
Finished Oct 03 10:30:24 AM UTC 24
Peak memory 231856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609212322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2609212322 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.3550292031
Short name T182
Test name
Test status
Simulation time 2403973865 ps
CPU time 200.98 seconds
Started Oct 03 10:29:56 AM UTC 24
Finished Oct 03 10:33:20 AM UTC 24
Peak memory 361464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550292031 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.3550292031 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.754965087
Short name T38
Test name
Test status
Simulation time 1093473180 ps
CPU time 73.59 seconds
Started Oct 03 10:30:09 AM UTC 24
Finished Oct 03 10:31:24 AM UTC 24
Peak memory 252940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754965087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.754965087 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.2989009593
Short name T10
Test name
Test status
Simulation time 10804492732 ps
CPU time 35.93 seconds
Started Oct 03 10:30:25 AM UTC 24
Finished Oct 03 10:31:03 AM UTC 24
Peak memory 276724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989009593 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2989009593 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.1616518199
Short name T213
Test name
Test status
Simulation time 2736017783 ps
CPU time 268.73 seconds
Started Oct 03 10:29:56 AM UTC 24
Finished Oct 03 10:34:29 AM UTC 24
Peak memory 320344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616518199 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1616518199 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.4100769468
Short name T82
Test name
Test status
Simulation time 447426896 ps
CPU time 23.18 seconds
Started Oct 03 10:29:55 AM UTC 24
Finished Oct 03 10:30:19 AM UTC 24
Peak memory 231788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100769468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.4100769468 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.1625611755
Short name T117
Test name
Test status
Simulation time 6455518013 ps
CPU time 120.37 seconds
Started Oct 03 10:30:21 AM UTC 24
Finished Oct 03 10:32:23 AM UTC 24
Peak memory 300084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625611755 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1625611755 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.2900479539
Short name T40
Test name
Test status
Simulation time 8411147329 ps
CPU time 137.39 seconds
Started Oct 03 10:30:22 AM UTC 24
Finished Oct 03 10:32:42 AM UTC 24
Peak memory 312540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2900479539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_
with_rand_reset.2900479539 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.935167070
Short name T49
Test name
Test status
Simulation time 55534401 ps
CPU time 2.61 seconds
Started Oct 03 10:30:00 AM UTC 24
Finished Oct 03 10:30:04 AM UTC 24
Peak memory 227736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935167070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.935167070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.609020173
Short name T51
Test name
Test status
Simulation time 116579232 ps
CPU time 3.43 seconds
Started Oct 03 10:30:04 AM UTC 24
Finished Oct 03 10:30:08 AM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609020173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.609020173 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.2866648328
Short name T183
Test name
Test status
Simulation time 2407979481 ps
CPU time 39.9 seconds
Started Oct 03 10:29:57 AM UTC 24
Finished Oct 03 10:30:39 AM UTC 24
Peak memory 234164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866648328 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2866648328
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3881918046
Short name T156
Test name
Test status
Simulation time 2457617678 ps
CPU time 40.85 seconds
Started Oct 03 10:29:59 AM UTC 24
Finished Oct 03 10:30:41 AM UTC 24
Peak memory 250608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881918046 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3881918046
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3888481566
Short name T189
Test name
Test status
Simulation time 7859870666 ps
CPU time 42.72 seconds
Started Oct 03 10:30:00 AM UTC 24
Finished Oct 03 10:30:45 AM UTC 24
Peak memory 238656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888481566 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3888481566
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.2357585996
Short name T83
Test name
Test status
Simulation time 762366701 ps
CPU time 19.09 seconds
Started Oct 03 10:30:00 AM UTC 24
Finished Oct 03 10:30:21 AM UTC 24
Peak memory 234072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357585996 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2357585996
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1148380619
Short name T206
Test name
Test status
Simulation time 13225285763 ps
CPU time 230.28 seconds
Started Oct 03 10:30:00 AM UTC 24
Finished Oct 03 10:33:54 AM UTC 24
Peak memory 277192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148380619 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1148380
619 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.3640888100
Short name T418
Test name
Test status
Simulation time 17399614670 ps
CPU time 1632.33 seconds
Started Oct 03 10:30:00 AM UTC 24
Finished Oct 03 10:57:33 AM UTC 24
Peak memory 1133764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640888100 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3640888
100 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.4233544054
Short name T353
Test name
Test status
Simulation time 19934605 ps
CPU time 1.07 seconds
Started Oct 03 10:50:15 AM UTC 24
Finished Oct 03 10:50:17 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233544054 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4233544054 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.3214608659
Short name T361
Test name
Test status
Simulation time 4227467600 ps
CPU time 105.43 seconds
Started Oct 03 10:49:15 AM UTC 24
Finished Oct 03 10:51:03 AM UTC 24
Peak memory 291560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214608659 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3214608659 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.1188951672
Short name T477
Test name
Test status
Simulation time 23828553779 ps
CPU time 916.47 seconds
Started Oct 03 10:49:11 AM UTC 24
Finished Oct 03 11:04:39 AM UTC 24
Peak memory 267040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188951672 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1188951672 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.1112505449
Short name T375
Test name
Test status
Simulation time 11419592057 ps
CPU time 164.02 seconds
Started Oct 03 10:49:39 AM UTC 24
Finished Oct 03 10:52:26 AM UTC 24
Peak memory 328512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112505449 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1112505449 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.3767943175
Short name T350
Test name
Test status
Simulation time 1187103645 ps
CPU time 25.77 seconds
Started Oct 03 10:49:46 AM UTC 24
Finished Oct 03 10:50:13 AM UTC 24
Peak memory 266932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767943175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3767943175 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.1887120750
Short name T354
Test name
Test status
Simulation time 1721154772 ps
CPU time 15.11 seconds
Started Oct 03 10:50:02 AM UTC 24
Finished Oct 03 10:50:18 AM UTC 24
Peak memory 227200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887120750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1887120750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.1562470220
Short name T352
Test name
Test status
Simulation time 47646357 ps
CPU time 1.7 seconds
Started Oct 03 10:50:12 AM UTC 24
Finished Oct 03 10:50:15 AM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562470220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1562470220 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2861658409
Short name T711
Test name
Test status
Simulation time 326744771175 ps
CPU time 3687.74 seconds
Started Oct 03 10:48:48 AM UTC 24
Finished Oct 03 11:51:01 AM UTC 24
Peak memory 4062232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861658409 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2861658409 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.428435904
Short name T351
Test name
Test status
Simulation time 9250710339 ps
CPU time 80.34 seconds
Started Oct 03 10:48:50 AM UTC 24
Finished Oct 03 10:50:13 AM UTC 24
Peak memory 291632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428435904 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.428435904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.330944278
Short name T348
Test name
Test status
Simulation time 2727452785 ps
CPU time 71.97 seconds
Started Oct 03 10:48:47 AM UTC 24
Finished Oct 03 10:50:01 AM UTC 24
Peak memory 234256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330944278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.330944278 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.2085048368
Short name T482
Test name
Test status
Simulation time 35553167322 ps
CPU time 918.65 seconds
Started Oct 03 10:50:13 AM UTC 24
Finished Oct 03 11:05:44 AM UTC 24
Peak memory 1348568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085048368 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2085048368 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.2824423584
Short name T364
Test name
Test status
Simulation time 18071582 ps
CPU time 1.29 seconds
Started Oct 03 10:51:07 AM UTC 24
Finished Oct 03 10:51:09 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824423584 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2824423584 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.1061927664
Short name T357
Test name
Test status
Simulation time 26898269 ps
CPU time 2.01 seconds
Started Oct 03 10:50:44 AM UTC 24
Finished Oct 03 10:50:47 AM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061927664 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1061927664 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.3629275484
Short name T443
Test name
Test status
Simulation time 75287832606 ps
CPU time 564.36 seconds
Started Oct 03 10:50:35 AM UTC 24
Finished Oct 03 11:00:06 AM UTC 24
Peak memory 252668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629275484 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3629275484 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.136489501
Short name T409
Test name
Test status
Simulation time 40765580464 ps
CPU time 346.71 seconds
Started Oct 03 10:50:48 AM UTC 24
Finished Oct 03 10:56:40 AM UTC 24
Peak memory 465972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136489501 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.136489501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.3406661461
Short name T370
Test name
Test status
Simulation time 3756476845 ps
CPU time 62.18 seconds
Started Oct 03 10:50:51 AM UTC 24
Finished Oct 03 10:51:55 AM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406661461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3406661461 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.3463811249
Short name T360
Test name
Test status
Simulation time 2300005051 ps
CPU time 6.33 seconds
Started Oct 03 10:50:54 AM UTC 24
Finished Oct 03 10:51:02 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463811249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3463811249 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.2306561443
Short name T362
Test name
Test status
Simulation time 125975046 ps
CPU time 1.86 seconds
Started Oct 03 10:51:02 AM UTC 24
Finished Oct 03 10:51:05 AM UTC 24
Peak memory 226360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306561443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2306561443 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.149612433
Short name T491
Test name
Test status
Simulation time 99966920830 ps
CPU time 955.93 seconds
Started Oct 03 10:50:18 AM UTC 24
Finished Oct 03 11:06:26 AM UTC 24
Peak memory 1286960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149612433 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.149612433 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.36690748
Short name T390
Test name
Test status
Simulation time 12173072899 ps
CPU time 245.6 seconds
Started Oct 03 10:50:19 AM UTC 24
Finished Oct 03 10:54:28 AM UTC 24
Peak memory 336688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36690748 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.36690748 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.3135354205
Short name T356
Test name
Test status
Simulation time 1449641034 ps
CPU time 25.92 seconds
Started Oct 03 10:50:16 AM UTC 24
Finished Oct 03 10:50:43 AM UTC 24
Peak memory 231508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135354205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3135354205 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.3914998394
Short name T483
Test name
Test status
Simulation time 49311742873 ps
CPU time 871.51 seconds
Started Oct 03 10:51:03 AM UTC 24
Finished Oct 03 11:05:46 AM UTC 24
Peak memory 677016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914998394 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3914998394 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.878186843
Short name T374
Test name
Test status
Simulation time 23303975 ps
CPU time 1.29 seconds
Started Oct 03 10:52:12 AM UTC 24
Finished Oct 03 10:52:14 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878186843 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.878186843 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.1985732268
Short name T396
Test name
Test status
Simulation time 8582145916 ps
CPU time 228.37 seconds
Started Oct 03 10:51:27 AM UTC 24
Finished Oct 03 10:55:19 AM UTC 24
Peak memory 398124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985732268 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1985732268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.3741782093
Short name T426
Test name
Test status
Simulation time 32508546798 ps
CPU time 397.17 seconds
Started Oct 03 10:51:26 AM UTC 24
Finished Oct 03 10:58:09 AM UTC 24
Peak memory 250676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741782093 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.3741782093 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.668359024
Short name T419
Test name
Test status
Simulation time 16464628465 ps
CPU time 359.5 seconds
Started Oct 03 10:51:33 AM UTC 24
Finished Oct 03 10:57:38 AM UTC 24
Peak memory 510812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668359024 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.668359024 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.269815895
Short name T415
Test name
Test status
Simulation time 27825637757 ps
CPU time 327.39 seconds
Started Oct 03 10:51:39 AM UTC 24
Finished Oct 03 10:57:12 AM UTC 24
Peak memory 533304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269815895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.269815895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.3866058212
Short name T373
Test name
Test status
Simulation time 1689086704 ps
CPU time 13.2 seconds
Started Oct 03 10:51:56 AM UTC 24
Finished Oct 03 10:52:11 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866058212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3866058212 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.299447673
Short name T372
Test name
Test status
Simulation time 30011453 ps
CPU time 2.02 seconds
Started Oct 03 10:52:08 AM UTC 24
Finished Oct 03 10:52:11 AM UTC 24
Peak memory 227616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299447673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.299447673 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2575070328
Short name T670
Test name
Test status
Simulation time 49384827895 ps
CPU time 2050.9 seconds
Started Oct 03 10:51:10 AM UTC 24
Finished Oct 03 11:25:46 AM UTC 24
Peak memory 2452268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575070328 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2575070328 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.30796435
Short name T389
Test name
Test status
Simulation time 33919754585 ps
CPU time 182.28 seconds
Started Oct 03 10:51:19 AM UTC 24
Finished Oct 03 10:54:24 AM UTC 24
Peak memory 379636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30796435 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.30796435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.1571048499
Short name T376
Test name
Test status
Simulation time 7406615592 ps
CPU time 75.37 seconds
Started Oct 03 10:51:09 AM UTC 24
Finished Oct 03 10:52:26 AM UTC 24
Peak memory 234392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571048499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1571048499 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.2637716620
Short name T400
Test name
Test status
Simulation time 11484658014 ps
CPU time 223.82 seconds
Started Oct 03 10:52:12 AM UTC 24
Finished Oct 03 10:55:59 AM UTC 24
Peak memory 267420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637716620 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2637716620 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.2911825639
Short name T386
Test name
Test status
Simulation time 78629516 ps
CPU time 1.32 seconds
Started Oct 03 10:53:48 AM UTC 24
Finished Oct 03 10:53:50 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911825639 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2911825639 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.4151039419
Short name T382
Test name
Test status
Simulation time 922476349 ps
CPU time 59.49 seconds
Started Oct 03 10:52:45 AM UTC 24
Finished Oct 03 10:53:46 AM UTC 24
Peak memory 244660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151039419 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.4151039419 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.183931145
Short name T421
Test name
Test status
Simulation time 15521156997 ps
CPU time 295.94 seconds
Started Oct 03 10:52:39 AM UTC 24
Finished Oct 03 10:57:39 AM UTC 24
Peak memory 240372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183931145 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.183931145 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.1408491162
Short name T384
Test name
Test status
Simulation time 9393184679 ps
CPU time 59.28 seconds
Started Oct 03 10:52:47 AM UTC 24
Finished Oct 03 10:53:49 AM UTC 24
Peak memory 242424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408491162 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1408491162 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.4121034079
Short name T458
Test name
Test status
Simulation time 17465301371 ps
CPU time 539.27 seconds
Started Oct 03 10:53:12 AM UTC 24
Finished Oct 03 11:02:18 AM UTC 24
Peak memory 576340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121034079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.4121034079 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.1643631010
Short name T383
Test name
Test status
Simulation time 196042438 ps
CPU time 2.99 seconds
Started Oct 03 10:53:43 AM UTC 24
Finished Oct 03 10:53:47 AM UTC 24
Peak memory 227464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643631010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1643631010 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.900707618
Short name T385
Test name
Test status
Simulation time 215403622 ps
CPU time 1.75 seconds
Started Oct 03 10:53:46 AM UTC 24
Finished Oct 03 10:53:49 AM UTC 24
Peak memory 226316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900707618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.900707618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.895123671
Short name T712
Test name
Test status
Simulation time 302333506704 ps
CPU time 3515.15 seconds
Started Oct 03 10:52:27 AM UTC 24
Finished Oct 03 11:51:42 AM UTC 24
Peak memory 3777348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895123671 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.895123671 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.2850250245
Short name T433
Test name
Test status
Simulation time 24778445269 ps
CPU time 383.19 seconds
Started Oct 03 10:52:27 AM UTC 24
Finished Oct 03 10:58:56 AM UTC 24
Peak memory 482292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850250245 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2850250245 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.2776644459
Short name T381
Test name
Test status
Simulation time 10552259306 ps
CPU time 88.1 seconds
Started Oct 03 10:52:15 AM UTC 24
Finished Oct 03 10:53:45 AM UTC 24
Peak memory 234464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776644459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2776644459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.862492291
Short name T634
Test name
Test status
Simulation time 84531675074 ps
CPU time 1653.84 seconds
Started Oct 03 10:53:47 AM UTC 24
Finished Oct 03 11:21:44 AM UTC 24
Peak memory 591008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862492291 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.862492291 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.3406773123
Short name T394
Test name
Test status
Simulation time 14677593 ps
CPU time 1.22 seconds
Started Oct 03 10:55:08 AM UTC 24
Finished Oct 03 10:55:10 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406773123 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3406773123 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.3269640214
Short name T416
Test name
Test status
Simulation time 13092073926 ps
CPU time 169.53 seconds
Started Oct 03 10:54:19 AM UTC 24
Finished Oct 03 10:57:12 AM UTC 24
Peak memory 302192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269640214 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3269640214 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.1397697577
Short name T481
Test name
Test status
Simulation time 71297226782 ps
CPU time 670.73 seconds
Started Oct 03 10:54:10 AM UTC 24
Finished Oct 03 11:05:30 AM UTC 24
Peak memory 252724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397697577 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1397697577 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.3882083844
Short name T397
Test name
Test status
Simulation time 8794836479 ps
CPU time 69.54 seconds
Started Oct 03 10:54:26 AM UTC 24
Finished Oct 03 10:55:37 AM UTC 24
Peak memory 248572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882083844 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3882083844 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.3154322802
Short name T395
Test name
Test status
Simulation time 1995439505 ps
CPU time 48.03 seconds
Started Oct 03 10:54:29 AM UTC 24
Finished Oct 03 10:55:18 AM UTC 24
Peak memory 260828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154322802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3154322802 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.4160754778
Short name T392
Test name
Test status
Simulation time 460737839 ps
CPU time 3.34 seconds
Started Oct 03 10:54:38 AM UTC 24
Finished Oct 03 10:54:42 AM UTC 24
Peak memory 227164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160754778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.4160754778 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3294713380
Short name T667
Test name
Test status
Simulation time 69568808448 ps
CPU time 1881.72 seconds
Started Oct 03 10:53:49 AM UTC 24
Finished Oct 03 11:25:31 AM UTC 24
Peak memory 2702120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294713380 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3294713380 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.1705634431
Short name T387
Test name
Test status
Simulation time 167734968 ps
CPU time 17.28 seconds
Started Oct 03 10:53:51 AM UTC 24
Finished Oct 03 10:54:10 AM UTC 24
Peak memory 234524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705634431 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1705634431 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.3859255596
Short name T393
Test name
Test status
Simulation time 19730713141 ps
CPU time 76.4 seconds
Started Oct 03 10:53:49 AM UTC 24
Finished Oct 03 10:55:07 AM UTC 24
Peak memory 234544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859255596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3859255596 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.445724856
Short name T503
Test name
Test status
Simulation time 10070882522 ps
CPU time 798.37 seconds
Started Oct 03 10:54:46 AM UTC 24
Finished Oct 03 11:08:14 AM UTC 24
Peak memory 588892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445724856 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.445724856 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.2547011414
Short name T405
Test name
Test status
Simulation time 30895931 ps
CPU time 1.19 seconds
Started Oct 03 10:56:10 AM UTC 24
Finished Oct 03 10:56:12 AM UTC 24
Peak memory 215708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547011414 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2547011414 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.3316001622
Short name T424
Test name
Test status
Simulation time 9614809872 ps
CPU time 144.15 seconds
Started Oct 03 10:55:38 AM UTC 24
Finished Oct 03 10:58:05 AM UTC 24
Peak memory 299736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316001622 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3316001622 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.1139486945
Short name T463
Test name
Test status
Simulation time 4985825967 ps
CPU time 449.64 seconds
Started Oct 03 10:55:38 AM UTC 24
Finished Oct 03 11:03:14 AM UTC 24
Peak memory 244472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139486945 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1139486945 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.3130145591
Short name T401
Test name
Test status
Simulation time 349310821 ps
CPU time 7.03 seconds
Started Oct 03 10:55:56 AM UTC 24
Finished Oct 03 10:56:04 AM UTC 24
Peak memory 231540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130145591 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3130145591 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.2030345527
Short name T429
Test name
Test status
Simulation time 6113628258 ps
CPU time 131.86 seconds
Started Oct 03 10:55:57 AM UTC 24
Finished Oct 03 10:58:12 AM UTC 24
Peak memory 281716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030345527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2030345527 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.4162903358
Short name T402
Test name
Test status
Simulation time 424200054 ps
CPU time 5.08 seconds
Started Oct 03 10:56:00 AM UTC 24
Finished Oct 03 10:56:07 AM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162903358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.4162903358 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.279939467
Short name T403
Test name
Test status
Simulation time 55386644 ps
CPU time 2.28 seconds
Started Oct 03 10:56:05 AM UTC 24
Finished Oct 03 10:56:09 AM UTC 24
Peak memory 227292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279939467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.279939467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.4048903988
Short name T704
Test name
Test status
Simulation time 288538204111 ps
CPU time 2975.8 seconds
Started Oct 03 10:55:19 AM UTC 24
Finished Oct 03 11:45:31 AM UTC 24
Peak memory 3453728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048903988 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.4048903988 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.2084606579
Short name T435
Test name
Test status
Simulation time 5641345236 ps
CPU time 225.02 seconds
Started Oct 03 10:55:20 AM UTC 24
Finished Oct 03 10:59:09 AM UTC 24
Peak memory 328540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084606579 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2084606579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.3876570398
Short name T399
Test name
Test status
Simulation time 3897617241 ps
CPU time 43.34 seconds
Started Oct 03 10:55:11 AM UTC 24
Finished Oct 03 10:55:56 AM UTC 24
Peak memory 234320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876570398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3876570398 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.2612559013
Short name T553
Test name
Test status
Simulation time 70674346682 ps
CPU time 1016.36 seconds
Started Oct 03 10:56:07 AM UTC 24
Finished Oct 03 11:13:16 AM UTC 24
Peak memory 955456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612559013 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2612559013 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.4195706573
Short name T417
Test name
Test status
Simulation time 38899273 ps
CPU time 1.03 seconds
Started Oct 03 10:57:12 AM UTC 24
Finished Oct 03 10:57:14 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195706573 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.4195706573 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.3086963052
Short name T438
Test name
Test status
Simulation time 33424632597 ps
CPU time 171.69 seconds
Started Oct 03 10:56:26 AM UTC 24
Finished Oct 03 10:59:21 AM UTC 24
Peak memory 392160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086963052 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3086963052 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.2748979054
Short name T171
Test name
Test status
Simulation time 7596786758 ps
CPU time 659.78 seconds
Started Oct 03 10:56:18 AM UTC 24
Finished Oct 03 11:07:26 AM UTC 24
Peak memory 250620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748979054 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2748979054 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.3253578775
Short name T436
Test name
Test status
Simulation time 89557751543 ps
CPU time 148.92 seconds
Started Oct 03 10:56:41 AM UTC 24
Finished Oct 03 10:59:13 AM UTC 24
Peak memory 303964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253578775 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3253578775 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.3611073184
Short name T441
Test name
Test status
Simulation time 26097519801 ps
CPU time 186.55 seconds
Started Oct 03 10:56:44 AM UTC 24
Finished Oct 03 10:59:54 AM UTC 24
Peak memory 400180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611073184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3611073184 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.3503133574
Short name T413
Test name
Test status
Simulation time 11774014253 ps
CPU time 20.11 seconds
Started Oct 03 10:56:49 AM UTC 24
Finished Oct 03 10:57:11 AM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503133574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3503133574 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.2579024266
Short name T414
Test name
Test status
Simulation time 106648582 ps
CPU time 1.39 seconds
Started Oct 03 10:57:09 AM UTC 24
Finished Oct 03 10:57:11 AM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579024266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2579024266 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.1682487105
Short name T679
Test name
Test status
Simulation time 74694919050 ps
CPU time 1827.01 seconds
Started Oct 03 10:56:13 AM UTC 24
Finished Oct 03 11:27:01 AM UTC 24
Peak memory 1319660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682487105 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.1682487105 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.2075907409
Short name T408
Test name
Test status
Simulation time 127624183 ps
CPU time 7.23 seconds
Started Oct 03 10:56:17 AM UTC 24
Finished Oct 03 10:56:25 AM UTC 24
Peak memory 231632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075907409 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2075907409 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.2974623614
Short name T411
Test name
Test status
Simulation time 1973716189 ps
CPU time 37.11 seconds
Started Oct 03 10:56:10 AM UTC 24
Finished Oct 03 10:56:48 AM UTC 24
Peak memory 233460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974623614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2974623614 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.635055067
Short name T684
Test name
Test status
Simulation time 94678650165 ps
CPU time 1935.31 seconds
Started Oct 03 10:57:12 AM UTC 24
Finished Oct 03 11:29:52 AM UTC 24
Peak memory 813900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635055067 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.635055067 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.3240288960
Short name T427
Test name
Test status
Simulation time 16813484 ps
CPU time 1.31 seconds
Started Oct 03 10:58:07 AM UTC 24
Finished Oct 03 10:58:09 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240288960 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3240288960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.1126246874
Short name T428
Test name
Test status
Simulation time 3677792180 ps
CPU time 29.17 seconds
Started Oct 03 10:57:39 AM UTC 24
Finished Oct 03 10:58:10 AM UTC 24
Peak memory 250604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126246874 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1126246874 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.1014825962
Short name T512
Test name
Test status
Simulation time 18312710505 ps
CPU time 692.29 seconds
Started Oct 03 10:57:33 AM UTC 24
Finished Oct 03 11:09:15 AM UTC 24
Peak memory 248632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014825962 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1014825962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3239114520
Short name T466
Test name
Test status
Simulation time 34541272668 ps
CPU time 362.36 seconds
Started Oct 03 10:57:39 AM UTC 24
Finished Oct 03 11:03:47 AM UTC 24
Peak memory 527172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239114520 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3239114520 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.757080503
Short name T452
Test name
Test status
Simulation time 19268013140 ps
CPU time 194.46 seconds
Started Oct 03 10:57:40 AM UTC 24
Finished Oct 03 11:00:58 AM UTC 24
Peak memory 414448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757080503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.757080503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.1404558190
Short name T430
Test name
Test status
Simulation time 2139531524 ps
CPU time 12.9 seconds
Started Oct 03 10:58:02 AM UTC 24
Finished Oct 03 10:58:16 AM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404558190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1404558190 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.1494732415
Short name T425
Test name
Test status
Simulation time 75052537 ps
CPU time 1.66 seconds
Started Oct 03 10:58:04 AM UTC 24
Finished Oct 03 10:58:06 AM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494732415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1494732415 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1673275169
Short name T597
Test name
Test status
Simulation time 47057788815 ps
CPU time 1220.55 seconds
Started Oct 03 10:57:13 AM UTC 24
Finished Oct 03 11:17:49 AM UTC 24
Peak memory 1796848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673275169 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1673275169 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.954021919
Short name T470
Test name
Test status
Simulation time 7709616638 ps
CPU time 403.8 seconds
Started Oct 03 10:57:15 AM UTC 24
Finished Oct 03 11:04:05 AM UTC 24
Peak memory 365560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954021919 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.954021919 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.2705016460
Short name T420
Test name
Test status
Simulation time 1267501829 ps
CPU time 24.27 seconds
Started Oct 03 10:57:13 AM UTC 24
Finished Oct 03 10:57:38 AM UTC 24
Peak memory 233684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705016460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2705016460 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.2601681686
Short name T524
Test name
Test status
Simulation time 36630854266 ps
CPU time 744.44 seconds
Started Oct 03 10:58:06 AM UTC 24
Finished Oct 03 11:10:40 AM UTC 24
Peak memory 375972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601681686 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2601681686 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.1651598745
Short name T437
Test name
Test status
Simulation time 21039615 ps
CPU time 1.22 seconds
Started Oct 03 10:59:14 AM UTC 24
Finished Oct 03 10:59:16 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651598745 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1651598745 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.1594721727
Short name T478
Test name
Test status
Simulation time 13408992150 ps
CPU time 393.28 seconds
Started Oct 03 10:58:16 AM UTC 24
Finished Oct 03 11:04:55 AM UTC 24
Peak memory 496436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594721727 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1594721727 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.2459298933
Short name T490
Test name
Test status
Simulation time 44268097595 ps
CPU time 481.97 seconds
Started Oct 03 10:58:13 AM UTC 24
Finished Oct 03 11:06:22 AM UTC 24
Peak memory 244532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459298933 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2459298933 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.294942181
Short name T446
Test name
Test status
Simulation time 4279013620 ps
CPU time 101.28 seconds
Started Oct 03 10:58:43 AM UTC 24
Finished Oct 03 11:00:27 AM UTC 24
Peak memory 303924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294942181 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.294942181 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.4275340441
Short name T451
Test name
Test status
Simulation time 12875461351 ps
CPU time 124.29 seconds
Started Oct 03 10:58:52 AM UTC 24
Finished Oct 03 11:00:58 AM UTC 24
Peak memory 353108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275340441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.4275340441 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.3319955931
Short name T434
Test name
Test status
Simulation time 687380256 ps
CPU time 7.77 seconds
Started Oct 03 10:58:57 AM UTC 24
Finished Oct 03 10:59:05 AM UTC 24
Peak memory 227228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319955931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3319955931 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.861024816
Short name T65
Test name
Test status
Simulation time 202332515 ps
CPU time 7.18 seconds
Started Oct 03 10:59:07 AM UTC 24
Finished Oct 03 10:59:15 AM UTC 24
Peak memory 231696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861024816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.861024816 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.397905447
Short name T546
Test name
Test status
Simulation time 34081736402 ps
CPU time 863.25 seconds
Started Oct 03 10:58:10 AM UTC 24
Finished Oct 03 11:12:44 AM UTC 24
Peak memory 819960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397905447 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.397905447 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.818322052
Short name T440
Test name
Test status
Simulation time 5412510648 ps
CPU time 95.78 seconds
Started Oct 03 10:58:11 AM UTC 24
Finished Oct 03 10:59:49 AM UTC 24
Peak memory 277308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818322052 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.818322052 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.298356580
Short name T432
Test name
Test status
Simulation time 3879292933 ps
CPU time 39.04 seconds
Started Oct 03 10:58:10 AM UTC 24
Finished Oct 03 10:58:50 AM UTC 24
Peak memory 233744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298356580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.298356580 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.1017102314
Short name T532
Test name
Test status
Simulation time 87479014134 ps
CPU time 706.57 seconds
Started Oct 03 10:59:10 AM UTC 24
Finished Oct 03 11:11:06 AM UTC 24
Peak memory 453784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017102314 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1017102314 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.1433141299
Short name T447
Test name
Test status
Simulation time 170377710 ps
CPU time 1.28 seconds
Started Oct 03 11:00:28 AM UTC 24
Finished Oct 03 11:00:30 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433141299 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1433141299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.4055259775
Short name T448
Test name
Test status
Simulation time 9994110152 ps
CPU time 48.54 seconds
Started Oct 03 10:59:49 AM UTC 24
Finished Oct 03 11:00:40 AM UTC 24
Peak memory 240628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055259775 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.4055259775 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.152211875
Short name T465
Test name
Test status
Simulation time 70216120301 ps
CPU time 249.06 seconds
Started Oct 03 10:59:33 AM UTC 24
Finished Oct 03 11:03:46 AM UTC 24
Peak memory 240424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152211875 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.152211875 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.570781352
Short name T472
Test name
Test status
Simulation time 39408652372 ps
CPU time 251.57 seconds
Started Oct 03 10:59:56 AM UTC 24
Finished Oct 03 11:04:11 AM UTC 24
Peak memory 404280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570781352 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.570781352 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.1528431233
Short name T453
Test name
Test status
Simulation time 4877441360 ps
CPU time 89.78 seconds
Started Oct 03 11:00:06 AM UTC 24
Finished Oct 03 11:01:38 AM UTC 24
Peak memory 299824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528431233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1528431233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.3213331302
Short name T445
Test name
Test status
Simulation time 3613665125 ps
CPU time 18.56 seconds
Started Oct 03 11:00:07 AM UTC 24
Finished Oct 03 11:00:27 AM UTC 24
Peak memory 227392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213331302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3213331302 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.1742153708
Short name T703
Test name
Test status
Simulation time 109779881352 ps
CPU time 2717.8 seconds
Started Oct 03 10:59:17 AM UTC 24
Finished Oct 03 11:45:07 AM UTC 24
Peak memory 3244844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742153708 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.1742153708 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.649696829
Short name T455
Test name
Test status
Simulation time 11648189709 ps
CPU time 153.92 seconds
Started Oct 03 10:59:21 AM UTC 24
Finished Oct 03 11:01:58 AM UTC 24
Peak memory 357172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649696829 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.649696829 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.942735074
Short name T442
Test name
Test status
Simulation time 5560033585 ps
CPU time 44.68 seconds
Started Oct 03 10:59:16 AM UTC 24
Finished Oct 03 11:00:02 AM UTC 24
Peak memory 233872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942735074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.942735074 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.499506952
Short name T601
Test name
Test status
Simulation time 30599780355 ps
CPU time 1084.93 seconds
Started Oct 03 11:00:16 AM UTC 24
Finished Oct 03 11:18:36 AM UTC 24
Peak memory 572140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499506952 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.499506952 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.1498004105
Short name T93
Test name
Test status
Simulation time 13106731 ps
CPU time 1.19 seconds
Started Oct 03 10:31:23 AM UTC 24
Finished Oct 03 10:31:25 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498004105 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1498004105 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.2582156220
Short name T194
Test name
Test status
Simulation time 18722398376 ps
CPU time 115.71 seconds
Started Oct 03 10:30:43 AM UTC 24
Finished Oct 03 10:32:41 AM UTC 24
Peak memory 316208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582156220 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2582156220 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.620701353
Short name T202
Test name
Test status
Simulation time 31202681656 ps
CPU time 175.38 seconds
Started Oct 03 10:30:45 AM UTC 24
Finished Oct 03 10:33:44 AM UTC 24
Peak memory 369496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620701353 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.620701353 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.3030195633
Short name T56
Test name
Test status
Simulation time 18127594681 ps
CPU time 509.07 seconds
Started Oct 03 10:30:28 AM UTC 24
Finished Oct 03 10:39:04 AM UTC 24
Peak memory 242524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030195633 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3030195633 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.979074926
Short name T97
Test name
Test status
Simulation time 1276742018 ps
CPU time 38.29 seconds
Started Oct 03 10:31:02 AM UTC 24
Finished Oct 03 10:31:42 AM UTC 24
Peak memory 233876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979074926 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.979074926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.938638432
Short name T95
Test name
Test status
Simulation time 1543402017 ps
CPU time 28.04 seconds
Started Oct 03 10:31:03 AM UTC 24
Finished Oct 03 10:31:33 AM UTC 24
Peak memory 233840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938638432 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.938638432 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2683544480
Short name T96
Test name
Test status
Simulation time 2640605844 ps
CPU time 35.03 seconds
Started Oct 03 10:31:03 AM UTC 24
Finished Oct 03 10:31:40 AM UTC 24
Peak memory 234336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683544480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2683544480 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3017793381
Short name T159
Test name
Test status
Simulation time 90452335643 ps
CPU time 339.74 seconds
Started Oct 03 10:30:47 AM UTC 24
Finished Oct 03 10:36:32 AM UTC 24
Peak memory 484144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017793381 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3017793381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.3746153383
Short name T59
Test name
Test status
Simulation time 7685101283 ps
CPU time 212.28 seconds
Started Oct 03 10:30:50 AM UTC 24
Finished Oct 03 10:34:25 AM UTC 24
Peak memory 433120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746153383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3746153383 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.1384572535
Short name T21
Test name
Test status
Simulation time 1145575132 ps
CPU time 9.28 seconds
Started Oct 03 10:31:01 AM UTC 24
Finished Oct 03 10:31:11 AM UTC 24
Peak memory 227160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384572535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1384572535 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.3420616778
Short name T70
Test name
Test status
Simulation time 37655896 ps
CPU time 2 seconds
Started Oct 03 10:31:12 AM UTC 24
Finished Oct 03 10:31:15 AM UTC 24
Peak memory 226304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420616778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3420616778 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.700002307
Short name T276
Test name
Test status
Simulation time 23595119907 ps
CPU time 656.07 seconds
Started Oct 03 10:30:27 AM UTC 24
Finished Oct 03 10:41:32 AM UTC 24
Peak memory 1117276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700002307 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.700002307 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.1957165217
Short name T39
Test name
Test status
Simulation time 6469039900 ps
CPU time 46.04 seconds
Started Oct 03 10:30:48 AM UTC 24
Finished Oct 03 10:31:36 AM UTC 24
Peak memory 271420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957165217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1957165217 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.1115821741
Short name T79
Test name
Test status
Simulation time 47890907301 ps
CPU time 48.54 seconds
Started Oct 03 10:31:23 AM UTC 24
Finished Oct 03 10:32:13 AM UTC 24
Peak memory 276564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115821741 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1115821741 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.878782807
Short name T36
Test name
Test status
Simulation time 13567968268 ps
CPU time 363.31 seconds
Started Oct 03 10:30:28 AM UTC 24
Finished Oct 03 10:36:36 AM UTC 24
Peak memory 524968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878782807 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.878782807 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.3165506658
Short name T186
Test name
Test status
Simulation time 198333485 ps
CPU time 13.2 seconds
Started Oct 03 10:30:25 AM UTC 24
Finished Oct 03 10:30:40 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165506658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3165506658 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.378167069
Short name T423
Test name
Test status
Simulation time 20906834372 ps
CPU time 1586.72 seconds
Started Oct 03 10:31:16 AM UTC 24
Finished Oct 03 10:58:02 AM UTC 24
Peak memory 807772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378167069 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.378167069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all_with_rand_reset.494138761
Short name T61
Test name
Test status
Simulation time 781825761 ps
CPU time 34.86 seconds
Started Oct 03 10:31:19 AM UTC 24
Finished Oct 03 10:31:56 AM UTC 24
Peak memory 250824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=494138761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_w
ith_rand_reset.494138761 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.2155767055
Short name T190
Test name
Test status
Simulation time 303518265 ps
CPU time 3.39 seconds
Started Oct 03 10:30:41 AM UTC 24
Finished Oct 03 10:30:46 AM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155767055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.2155767055 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2778398793
Short name T191
Test name
Test status
Simulation time 36878728 ps
CPU time 3.66 seconds
Started Oct 03 10:30:42 AM UTC 24
Finished Oct 03 10:30:48 AM UTC 24
Peak memory 229488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778398793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2778398793 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1393037021
Short name T422
Test name
Test status
Simulation time 72054532107 ps
CPU time 1631.92 seconds
Started Oct 03 10:30:29 AM UTC 24
Finished Oct 03 10:58:01 AM UTC 24
Peak memory 1159860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393037021 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1393037021
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.4568216
Short name T518
Test name
Test status
Simulation time 113505710471 ps
CPU time 2344.67 seconds
Started Oct 03 10:30:29 AM UTC 24
Finished Oct 03 11:10:00 AM UTC 24
Peak memory 2947828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4568216 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.4568216 +enab
le_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2141047962
Short name T412
Test name
Test status
Simulation time 48814805074 ps
CPU time 1574.16 seconds
Started Oct 03 10:30:34 AM UTC 24
Finished Oct 03 10:57:08 AM UTC 24
Peak memory 2302616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141047962 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2141047962
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3323351911
Short name T192
Test name
Test status
Simulation time 926846202 ps
CPU time 24.19 seconds
Started Oct 03 10:30:36 AM UTC 24
Finished Oct 03 10:31:01 AM UTC 24
Peak memory 234040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323351911 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3323351911
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3555577499
Short name T646
Test name
Test status
Simulation time 157476586813 ps
CPU time 3126.04 seconds
Started Oct 03 10:30:39 AM UTC 24
Finished Oct 03 11:23:19 AM UTC 24
Peak memory 3597044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555577499 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3555577
499 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.1365734145
Short name T241
Test name
Test status
Simulation time 67834013349 ps
CPU time 490.42 seconds
Started Oct 03 10:30:40 AM UTC 24
Finished Oct 03 10:38:57 AM UTC 24
Peak memory 359056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365734145 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1365734
145 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.1275704126
Short name T457
Test name
Test status
Simulation time 16666148 ps
CPU time 1.19 seconds
Started Oct 03 11:01:59 AM UTC 24
Finished Oct 03 11:02:01 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275704126 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1275704126 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.1935636948
Short name T461
Test name
Test status
Simulation time 3182089079 ps
CPU time 111.73 seconds
Started Oct 03 11:00:55 AM UTC 24
Finished Oct 03 11:02:49 AM UTC 24
Peak memory 300056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935636948 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1935636948 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.1514965664
Short name T520
Test name
Test status
Simulation time 24461800352 ps
CPU time 545.29 seconds
Started Oct 03 11:00:50 AM UTC 24
Finished Oct 03 11:10:03 AM UTC 24
Peak memory 244476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514965664 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1514965664 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.159919501
Short name T471
Test name
Test status
Simulation time 88899251687 ps
CPU time 183.72 seconds
Started Oct 03 11:00:59 AM UTC 24
Finished Oct 03 11:04:06 AM UTC 24
Peak memory 328540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159919501 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.159919501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.4149408774
Short name T485
Test name
Test status
Simulation time 3635306820 ps
CPU time 296.37 seconds
Started Oct 03 11:00:59 AM UTC 24
Finished Oct 03 11:06:00 AM UTC 24
Peak memory 365624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149408774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.4149408774 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.2636722485
Short name T454
Test name
Test status
Simulation time 1753829467 ps
CPU time 5.06 seconds
Started Oct 03 11:01:39 AM UTC 24
Finished Oct 03 11:01:45 AM UTC 24
Peak memory 227264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636722485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2636722485 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.1811046431
Short name T66
Test name
Test status
Simulation time 719452831 ps
CPU time 4.18 seconds
Started Oct 03 11:01:46 AM UTC 24
Finished Oct 03 11:01:51 AM UTC 24
Peak memory 229548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811046431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1811046431 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.1047349266
Short name T695
Test name
Test status
Simulation time 19300874719 ps
CPU time 2154.74 seconds
Started Oct 03 11:00:31 AM UTC 24
Finished Oct 03 11:36:52 AM UTC 24
Peak memory 1485592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047349266 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.1047349266 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.3269713809
Short name T456
Test name
Test status
Simulation time 4582913828 ps
CPU time 78.01 seconds
Started Oct 03 11:00:40 AM UTC 24
Finished Oct 03 11:02:00 AM UTC 24
Peak memory 289524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269713809 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3269713809 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.2101384813
Short name T449
Test name
Test status
Simulation time 594137698 ps
CPU time 19.81 seconds
Started Oct 03 11:00:28 AM UTC 24
Finished Oct 03 11:00:49 AM UTC 24
Peak memory 231532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101384813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2101384813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.2479323979
Short name T609
Test name
Test status
Simulation time 25022117747 ps
CPU time 1047.15 seconds
Started Oct 03 11:01:52 AM UTC 24
Finished Oct 03 11:19:33 AM UTC 24
Peak memory 1235668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479323979 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2479323979 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.256442422
Short name T467
Test name
Test status
Simulation time 53263749 ps
CPU time 1.03 seconds
Started Oct 03 11:03:47 AM UTC 24
Finished Oct 03 11:03:50 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256442422 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.256442422 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.1888709530
Short name T501
Test name
Test status
Simulation time 10784386730 ps
CPU time 300 seconds
Started Oct 03 11:02:28 AM UTC 24
Finished Oct 03 11:07:32 AM UTC 24
Peak memory 500532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888709530 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1888709530 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.2224264240
Short name T573
Test name
Test status
Simulation time 8889716305 ps
CPU time 812.38 seconds
Started Oct 03 11:02:22 AM UTC 24
Finished Oct 03 11:16:05 AM UTC 24
Peak memory 250620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224264240 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2224264240 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.1126774936
Short name T462
Test name
Test status
Simulation time 65137455 ps
CPU time 7.16 seconds
Started Oct 03 11:02:50 AM UTC 24
Finished Oct 03 11:02:58 AM UTC 24
Peak memory 233580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126774936 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1126774936 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.2820923310
Short name T497
Test name
Test status
Simulation time 64162395492 ps
CPU time 249.71 seconds
Started Oct 03 11:02:59 AM UTC 24
Finished Oct 03 11:07:13 AM UTC 24
Peak memory 394132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820923310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2820923310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.266642668
Short name T464
Test name
Test status
Simulation time 897104830 ps
CPU time 10.21 seconds
Started Oct 03 11:03:15 AM UTC 24
Finished Oct 03 11:03:26 AM UTC 24
Peak memory 227528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266642668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.266642668 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.903470408
Short name T68
Test name
Test status
Simulation time 103741482 ps
CPU time 1.59 seconds
Started Oct 03 11:03:27 AM UTC 24
Finished Oct 03 11:03:30 AM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903470408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.903470408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.1908035480
Short name T528
Test name
Test status
Simulation time 78345517301 ps
CPU time 520.4 seconds
Started Oct 03 11:02:02 AM UTC 24
Finished Oct 03 11:10:50 AM UTC 24
Peak memory 889580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908035480 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.1908035480 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.3347244918
Short name T515
Test name
Test status
Simulation time 4558397346 ps
CPU time 451.84 seconds
Started Oct 03 11:02:20 AM UTC 24
Finished Oct 03 11:09:58 AM UTC 24
Peak memory 383796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347244918 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3347244918 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.2429120596
Short name T459
Test name
Test status
Simulation time 337241694 ps
CPU time 17.35 seconds
Started Oct 03 11:02:01 AM UTC 24
Finished Oct 03 11:02:21 AM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429120596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2429120596 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.2460427068
Short name T600
Test name
Test status
Simulation time 11277556179 ps
CPU time 861.51 seconds
Started Oct 03 11:03:30 AM UTC 24
Finished Oct 03 11:18:04 AM UTC 24
Peak memory 375540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460427068 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2460427068 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.3361267538
Short name T476
Test name
Test status
Simulation time 30320739 ps
CPU time 1.2 seconds
Started Oct 03 11:04:37 AM UTC 24
Finished Oct 03 11:04:39 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361267538 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3361267538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.2730193083
Short name T494
Test name
Test status
Simulation time 6828253946 ps
CPU time 168.11 seconds
Started Oct 03 11:04:06 AM UTC 24
Finished Oct 03 11:06:57 AM UTC 24
Peak memory 369420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730193083 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2730193083 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.2405480459
Short name T500
Test name
Test status
Simulation time 25132412861 ps
CPU time 203.42 seconds
Started Oct 03 11:04:04 AM UTC 24
Finished Oct 03 11:07:30 AM UTC 24
Peak memory 238308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405480459 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2405480459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2310804692
Short name T475
Test name
Test status
Simulation time 3508058915 ps
CPU time 28.93 seconds
Started Oct 03 11:04:06 AM UTC 24
Finished Oct 03 11:04:36 AM UTC 24
Peak memory 236284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310804692 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2310804692 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.2324877079
Short name T511
Test name
Test status
Simulation time 16439125927 ps
CPU time 290.53 seconds
Started Oct 03 11:04:12 AM UTC 24
Finished Oct 03 11:09:07 AM UTC 24
Peak memory 375540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324877079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2324877079 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.368918521
Short name T473
Test name
Test status
Simulation time 797445591 ps
CPU time 3.69 seconds
Started Oct 03 11:04:14 AM UTC 24
Finished Oct 03 11:04:19 AM UTC 24
Peak memory 227272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368918521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.368918521 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.1065370783
Short name T474
Test name
Test status
Simulation time 112116141 ps
CPU time 2.06 seconds
Started Oct 03 11:04:19 AM UTC 24
Finished Oct 03 11:04:23 AM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065370783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1065370783 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.1293513072
Short name T716
Test name
Test status
Simulation time 211607167329 ps
CPU time 3644.21 seconds
Started Oct 03 11:03:51 AM UTC 24
Finished Oct 03 12:05:15 PM UTC 24
Peak memory 4125528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293513072 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.1293513072 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.1778376388
Short name T493
Test name
Test status
Simulation time 1759764222 ps
CPU time 169.63 seconds
Started Oct 03 11:04:03 AM UTC 24
Finished Oct 03 11:06:55 AM UTC 24
Peak memory 287380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778376388 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1778376388 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.2302237282
Short name T468
Test name
Test status
Simulation time 3868772367 ps
CPU time 12.7 seconds
Started Oct 03 11:03:48 AM UTC 24
Finished Oct 03 11:04:01 AM UTC 24
Peak memory 232020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302237282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2302237282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.2437342317
Short name T612
Test name
Test status
Simulation time 51508661794 ps
CPU time 924.15 seconds
Started Oct 03 11:04:24 AM UTC 24
Finished Oct 03 11:20:00 AM UTC 24
Peak memory 748600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437342317 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2437342317 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.4060112442
Short name T488
Test name
Test status
Simulation time 50396802 ps
CPU time 1.22 seconds
Started Oct 03 11:06:01 AM UTC 24
Finished Oct 03 11:06:03 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060112442 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.4060112442 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.3925143466
Short name T489
Test name
Test status
Simulation time 2308815780 ps
CPU time 44.59 seconds
Started Oct 03 11:05:29 AM UTC 24
Finished Oct 03 11:06:16 AM UTC 24
Peak memory 271072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925143466 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3925143466 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.1278182440
Short name T486
Test name
Test status
Simulation time 7285427444 ps
CPU time 33.89 seconds
Started Oct 03 11:05:25 AM UTC 24
Finished Oct 03 11:06:00 AM UTC 24
Peak memory 234328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278182440 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1278182440 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3208897048
Short name T530
Test name
Test status
Simulation time 32761574572 ps
CPU time 322.09 seconds
Started Oct 03 11:05:30 AM UTC 24
Finished Oct 03 11:10:58 AM UTC 24
Peak memory 475956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208897048 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3208897048 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.494413987
Short name T523
Test name
Test status
Simulation time 59334311920 ps
CPU time 267.58 seconds
Started Oct 03 11:05:45 AM UTC 24
Finished Oct 03 11:10:16 AM UTC 24
Peak memory 463792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494413987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.494413987 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.1365056431
Short name T484
Test name
Test status
Simulation time 3156054799 ps
CPU time 9.82 seconds
Started Oct 03 11:05:47 AM UTC 24
Finished Oct 03 11:05:58 AM UTC 24
Peak memory 227292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365056431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1365056431 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.2141023173
Short name T487
Test name
Test status
Simulation time 123038840 ps
CPU time 1.79 seconds
Started Oct 03 11:05:59 AM UTC 24
Finished Oct 03 11:06:02 AM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141023173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2141023173 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.4052739531
Short name T585
Test name
Test status
Simulation time 74566702504 ps
CPU time 726.46 seconds
Started Oct 03 11:04:41 AM UTC 24
Finished Oct 03 11:16:57 AM UTC 24
Peak memory 1098468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052739531 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.4052739531 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.762382448
Short name T510
Test name
Test status
Simulation time 3097430528 ps
CPU time 243.48 seconds
Started Oct 03 11:04:56 AM UTC 24
Finished Oct 03 11:09:03 AM UTC 24
Peak memory 336692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762382448 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.762382448 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.501378014
Short name T480
Test name
Test status
Simulation time 2022968722 ps
CPU time 46.78 seconds
Started Oct 03 11:04:40 AM UTC 24
Finished Oct 03 11:05:28 AM UTC 24
Peak memory 233680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501378014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.501378014 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.2951463123
Short name T517
Test name
Test status
Simulation time 9207089345 ps
CPU time 235.08 seconds
Started Oct 03 11:06:01 AM UTC 24
Finished Oct 03 11:10:00 AM UTC 24
Peak memory 342832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951463123 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2951463123 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.635720021
Short name T499
Test name
Test status
Simulation time 22208444 ps
CPU time 1.19 seconds
Started Oct 03 11:07:14 AM UTC 24
Finished Oct 03 11:07:16 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635720021 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.635720021 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.1385608006
Short name T543
Test name
Test status
Simulation time 46071269081 ps
CPU time 361.6 seconds
Started Oct 03 11:06:26 AM UTC 24
Finished Oct 03 11:12:33 AM UTC 24
Peak memory 478004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385608006 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1385608006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.3711993008
Short name T589
Test name
Test status
Simulation time 59850608944 ps
CPU time 633.28 seconds
Started Oct 03 11:06:23 AM UTC 24
Finished Oct 03 11:17:05 AM UTC 24
Peak memory 257144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711993008 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3711993008 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2400798572
Short name T547
Test name
Test status
Simulation time 67289229300 ps
CPU time 365.39 seconds
Started Oct 03 11:06:37 AM UTC 24
Finished Oct 03 11:12:48 AM UTC 24
Peak memory 463928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400798572 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2400798572 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.4113954127
Short name T513
Test name
Test status
Simulation time 28281491749 ps
CPU time 159.13 seconds
Started Oct 03 11:06:57 AM UTC 24
Finished Oct 03 11:09:39 AM UTC 24
Peak memory 371448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113954127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.4113954127 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.4083374200
Short name T498
Test name
Test status
Simulation time 1540255788 ps
CPU time 14.39 seconds
Started Oct 03 11:06:58 AM UTC 24
Finished Oct 03 11:07:14 AM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083374200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.4083374200 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.2596211344
Short name T496
Test name
Test status
Simulation time 137762986 ps
CPU time 1.95 seconds
Started Oct 03 11:07:01 AM UTC 24
Finished Oct 03 11:07:04 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596211344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2596211344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3970262555
Short name T702
Test name
Test status
Simulation time 92188464920 ps
CPU time 2227.34 seconds
Started Oct 03 11:06:04 AM UTC 24
Finished Oct 03 11:43:38 AM UTC 24
Peak memory 1622760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970262555 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3970262555 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.2374043196
Short name T492
Test name
Test status
Simulation time 2877575919 ps
CPU time 18.08 seconds
Started Oct 03 11:06:16 AM UTC 24
Finished Oct 03 11:06:36 AM UTC 24
Peak memory 244780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374043196 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2374043196 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.3146529551
Short name T495
Test name
Test status
Simulation time 867047392 ps
CPU time 55.86 seconds
Started Oct 03 11:06:02 AM UTC 24
Finished Oct 03 11:07:00 AM UTC 24
Peak memory 233576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146529551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3146529551 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.783487935
Short name T588
Test name
Test status
Simulation time 13215699681 ps
CPU time 591.38 seconds
Started Oct 03 11:07:05 AM UTC 24
Finished Oct 03 11:17:04 AM UTC 24
Peak memory 300152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783487935 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.783487935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.3337088103
Short name T508
Test name
Test status
Simulation time 80866225 ps
CPU time 1.17 seconds
Started Oct 03 11:08:38 AM UTC 24
Finished Oct 03 11:08:40 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337088103 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3337088103 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.413430100
Short name T541
Test name
Test status
Simulation time 29066084382 ps
CPU time 277.9 seconds
Started Oct 03 11:07:34 AM UTC 24
Finished Oct 03 11:12:16 AM UTC 24
Peak memory 330580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413430100 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.413430100 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.728078170
Short name T590
Test name
Test status
Simulation time 18322699814 ps
CPU time 572.48 seconds
Started Oct 03 11:07:31 AM UTC 24
Finished Oct 03 11:17:12 AM UTC 24
Peak memory 254700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728078170 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.728078170 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.1543893086
Short name T509
Test name
Test status
Simulation time 9209823285 ps
CPU time 71.44 seconds
Started Oct 03 11:07:35 AM UTC 24
Finished Oct 03 11:08:48 AM UTC 24
Peak memory 279608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543893086 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1543893086 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.307633955
Short name T571
Test name
Test status
Simulation time 46813958950 ps
CPU time 452.34 seconds
Started Oct 03 11:08:15 AM UTC 24
Finished Oct 03 11:15:55 AM UTC 24
Peak memory 543536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307633955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.307633955 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.3084081665
Short name T506
Test name
Test status
Simulation time 1277964587 ps
CPU time 10.46 seconds
Started Oct 03 11:08:24 AM UTC 24
Finished Oct 03 11:08:36 AM UTC 24
Peak memory 227488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084081665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3084081665 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.3878043074
Short name T507
Test name
Test status
Simulation time 65837964 ps
CPU time 1.72 seconds
Started Oct 03 11:08:34 AM UTC 24
Finished Oct 03 11:08:37 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878043074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3878043074 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.2912156199
Short name T544
Test name
Test status
Simulation time 11060095014 ps
CPU time 312.24 seconds
Started Oct 03 11:07:17 AM UTC 24
Finished Oct 03 11:12:34 AM UTC 24
Peak memory 604904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912156199 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.2912156199 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.2162660778
Short name T542
Test name
Test status
Simulation time 16472013303 ps
CPU time 298.91 seconds
Started Oct 03 11:07:27 AM UTC 24
Finished Oct 03 11:12:30 AM UTC 24
Peak memory 353372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162660778 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2162660778 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.3962243964
Short name T502
Test name
Test status
Simulation time 3060580578 ps
CPU time 18.24 seconds
Started Oct 03 11:07:14 AM UTC 24
Finished Oct 03 11:07:34 AM UTC 24
Peak memory 233788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962243964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3962243964 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.1266182908
Short name T668
Test name
Test status
Simulation time 9748368622 ps
CPU time 1007.42 seconds
Started Oct 03 11:08:38 AM UTC 24
Finished Oct 03 11:25:38 AM UTC 24
Peak memory 640116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266182908 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1266182908 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.2332437063
Short name T521
Test name
Test status
Simulation time 14618885 ps
CPU time 1.25 seconds
Started Oct 03 11:10:01 AM UTC 24
Finished Oct 03 11:10:04 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332437063 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2332437063 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.1351272746
Short name T563
Test name
Test status
Simulation time 45653660235 ps
CPU time 326.36 seconds
Started Oct 03 11:09:08 AM UTC 24
Finished Oct 03 11:14:39 AM UTC 24
Peak memory 506740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351272746 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1351272746 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.3660058989
Short name T525
Test name
Test status
Simulation time 8627007377 ps
CPU time 97.43 seconds
Started Oct 03 11:09:04 AM UTC 24
Finished Oct 03 11:10:44 AM UTC 24
Peak memory 250672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660058989 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3660058989 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.57282982
Short name T537
Test name
Test status
Simulation time 2833994331 ps
CPU time 142.05 seconds
Started Oct 03 11:09:16 AM UTC 24
Finished Oct 03 11:11:40 AM UTC 24
Peak memory 287740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57282982 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.57282982 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.1262273092
Short name T527
Test name
Test status
Simulation time 1136198145 ps
CPU time 66.98 seconds
Started Oct 03 11:09:40 AM UTC 24
Finished Oct 03 11:10:49 AM UTC 24
Peak memory 281300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262273092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1262273092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.3337175173
Short name T516
Test name
Test status
Simulation time 5025831135 ps
CPU time 16.09 seconds
Started Oct 03 11:09:41 AM UTC 24
Finished Oct 03 11:09:58 AM UTC 24
Peak memory 227296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337175173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3337175173 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.1017134537
Short name T519
Test name
Test status
Simulation time 179878055 ps
CPU time 2.14 seconds
Started Oct 03 11:09:59 AM UTC 24
Finished Oct 03 11:10:03 AM UTC 24
Peak memory 227300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017134537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1017134537 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.2694245601
Short name T714
Test name
Test status
Simulation time 77090733007 ps
CPU time 3340.19 seconds
Started Oct 03 11:08:48 AM UTC 24
Finished Oct 03 12:05:06 PM UTC 24
Peak memory 3707684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694245601 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.2694245601 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.3485427948
Short name T522
Test name
Test status
Simulation time 13347116505 ps
CPU time 76.76 seconds
Started Oct 03 11:08:49 AM UTC 24
Finished Oct 03 11:10:08 AM UTC 24
Peak memory 295668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485427948 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3485427948 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.3332031030
Short name T514
Test name
Test status
Simulation time 2209258757 ps
CPU time 55.98 seconds
Started Oct 03 11:08:42 AM UTC 24
Finished Oct 03 11:09:40 AM UTC 24
Peak memory 234264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332031030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3332031030 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.1234926056
Short name T664
Test name
Test status
Simulation time 304136194011 ps
CPU time 886.11 seconds
Started Oct 03 11:09:59 AM UTC 24
Finished Oct 03 11:24:57 AM UTC 24
Peak memory 1315556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234926056 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1234926056 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.323331775
Short name T529
Test name
Test status
Simulation time 14921257 ps
CPU time 1.22 seconds
Started Oct 03 11:10:51 AM UTC 24
Finished Oct 03 11:10:53 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323331775 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.323331775 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.4088309102
Short name T567
Test name
Test status
Simulation time 10348766359 ps
CPU time 309.35 seconds
Started Oct 03 11:10:09 AM UTC 24
Finished Oct 03 11:15:23 AM UTC 24
Peak memory 478236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088309102 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.4088309102 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.153403719
Short name T574
Test name
Test status
Simulation time 3995580375 ps
CPU time 362.96 seconds
Started Oct 03 11:10:05 AM UTC 24
Finished Oct 03 11:16:13 AM UTC 24
Peak memory 242472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153403719 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.153403719 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.811196280
Short name T555
Test name
Test status
Simulation time 11341337538 ps
CPU time 207.44 seconds
Started Oct 03 11:10:17 AM UTC 24
Finished Oct 03 11:13:48 AM UTC 24
Peak memory 427052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811196280 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.811196280 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.1418822910
Short name T558
Test name
Test status
Simulation time 22783920698 ps
CPU time 212.24 seconds
Started Oct 03 11:10:41 AM UTC 24
Finished Oct 03 11:14:17 AM UTC 24
Peak memory 443220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418822910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1418822910 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.2907512269
Short name T526
Test name
Test status
Simulation time 202708016 ps
CPU time 2.1 seconds
Started Oct 03 11:10:44 AM UTC 24
Finished Oct 03 11:10:48 AM UTC 24
Peak memory 226948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907512269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2907512269 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.4093609652
Short name T531
Test name
Test status
Simulation time 3023304468 ps
CPU time 13.4 seconds
Started Oct 03 11:10:48 AM UTC 24
Finished Oct 03 11:11:03 AM UTC 24
Peak memory 250660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093609652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.4093609652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.4095488727
Short name T715
Test name
Test status
Simulation time 102887508548 ps
CPU time 3267.29 seconds
Started Oct 03 11:10:04 AM UTC 24
Finished Oct 03 12:05:07 PM UTC 24
Peak memory 3740420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095488727 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.4095488727 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.2601796969
Short name T545
Test name
Test status
Simulation time 19134070119 ps
CPU time 150.01 seconds
Started Oct 03 11:10:04 AM UTC 24
Finished Oct 03 11:12:37 AM UTC 24
Peak memory 320308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601796969 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2601796969 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.4294944582
Short name T533
Test name
Test status
Simulation time 4487147906 ps
CPU time 69.12 seconds
Started Oct 03 11:10:01 AM UTC 24
Finished Oct 03 11:11:12 AM UTC 24
Peak memory 234292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294944582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.4294944582 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.1942087740
Short name T568
Test name
Test status
Simulation time 8848735527 ps
CPU time 290.37 seconds
Started Oct 03 11:10:50 AM UTC 24
Finished Oct 03 11:15:44 AM UTC 24
Peak memory 635732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942087740 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1942087740 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.428677568
Short name T540
Test name
Test status
Simulation time 21952913 ps
CPU time 1.33 seconds
Started Oct 03 11:11:47 AM UTC 24
Finished Oct 03 11:11:49 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428677568 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.428677568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.1792060633
Short name T581
Test name
Test status
Simulation time 9200715148 ps
CPU time 333.42 seconds
Started Oct 03 11:11:13 AM UTC 24
Finished Oct 03 11:16:52 AM UTC 24
Peak memory 342772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792060633 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1792060633 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.1360765652
Short name T602
Test name
Test status
Simulation time 23211425745 ps
CPU time 445.49 seconds
Started Oct 03 11:11:07 AM UTC 24
Finished Oct 03 11:18:39 AM UTC 24
Peak memory 250652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360765652 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1360765652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.897752567
Short name T564
Test name
Test status
Simulation time 10162762901 ps
CPU time 196.19 seconds
Started Oct 03 11:11:20 AM UTC 24
Finished Oct 03 11:14:40 AM UTC 24
Peak memory 387832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897752567 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.897752567 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.984456484
Short name T566
Test name
Test status
Simulation time 22196261448 ps
CPU time 226.45 seconds
Started Oct 03 11:11:22 AM UTC 24
Finished Oct 03 11:15:12 AM UTC 24
Peak memory 437240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984456484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.984456484 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.3699843678
Short name T539
Test name
Test status
Simulation time 1490827401 ps
CPU time 4.35 seconds
Started Oct 03 11:11:41 AM UTC 24
Finished Oct 03 11:11:46 AM UTC 24
Peak memory 227264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699843678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3699843678 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.3007903018
Short name T538
Test name
Test status
Simulation time 74337045 ps
CPU time 1.91 seconds
Started Oct 03 11:11:42 AM UTC 24
Finished Oct 03 11:11:45 AM UTC 24
Peak memory 226300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007903018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3007903018 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.4103436570
Short name T693
Test name
Test status
Simulation time 106282360890 ps
CPU time 1477.99 seconds
Started Oct 03 11:10:59 AM UTC 24
Finished Oct 03 11:35:55 AM UTC 24
Peak memory 2024172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103436570 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.4103436570 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.4083565640
Short name T596
Test name
Test status
Simulation time 4768727229 ps
CPU time 397.88 seconds
Started Oct 03 11:11:04 AM UTC 24
Finished Oct 03 11:17:48 AM UTC 24
Peak memory 392288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083565640 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.4083565640 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.275280978
Short name T535
Test name
Test status
Simulation time 832184115 ps
CPU time 25.57 seconds
Started Oct 03 11:10:54 AM UTC 24
Finished Oct 03 11:11:21 AM UTC 24
Peak memory 231532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275280978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.275280978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.291431858
Short name T710
Test name
Test status
Simulation time 89112953989 ps
CPU time 2276.6 seconds
Started Oct 03 11:11:46 AM UTC 24
Finished Oct 03 11:50:11 AM UTC 24
Peak memory 1561700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291431858 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.291431858 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.3329294021
Short name T551
Test name
Test status
Simulation time 16567203 ps
CPU time 1.32 seconds
Started Oct 03 11:13:02 AM UTC 24
Finished Oct 03 11:13:04 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329294021 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3329294021 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.2441135007
Short name T595
Test name
Test status
Simulation time 10864695012 ps
CPU time 300.97 seconds
Started Oct 03 11:12:35 AM UTC 24
Finished Oct 03 11:17:40 AM UTC 24
Peak memory 475892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441135007 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2441135007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.3719271683
Short name T554
Test name
Test status
Simulation time 6912931261 ps
CPU time 68.77 seconds
Started Oct 03 11:12:34 AM UTC 24
Finished Oct 03 11:13:44 AM UTC 24
Peak memory 234232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719271683 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3719271683 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.3759415536
Short name T606
Test name
Test status
Simulation time 30263165701 ps
CPU time 389.65 seconds
Started Oct 03 11:12:37 AM UTC 24
Finished Oct 03 11:19:12 AM UTC 24
Peak memory 500832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759415536 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3759415536 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.1497138257
Short name T562
Test name
Test status
Simulation time 6756730076 ps
CPU time 108.04 seconds
Started Oct 03 11:12:45 AM UTC 24
Finished Oct 03 11:14:36 AM UTC 24
Peak memory 299892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497138257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1497138257 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.3874146978
Short name T549
Test name
Test status
Simulation time 792924455 ps
CPU time 7.65 seconds
Started Oct 03 11:12:49 AM UTC 24
Finished Oct 03 11:12:58 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874146978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3874146978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.564587970
Short name T550
Test name
Test status
Simulation time 147111579 ps
CPU time 2.02 seconds
Started Oct 03 11:12:57 AM UTC 24
Finished Oct 03 11:13:00 AM UTC 24
Peak memory 227564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564587970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.564587970 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.1288412051
Short name T618
Test name
Test status
Simulation time 45625531515 ps
CPU time 481.07 seconds
Started Oct 03 11:12:16 AM UTC 24
Finished Oct 03 11:20:25 AM UTC 24
Peak memory 764652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288412051 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.1288412051 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.3742622001
Short name T607
Test name
Test status
Simulation time 4701892978 ps
CPU time 408.5 seconds
Started Oct 03 11:12:32 AM UTC 24
Finished Oct 03 11:19:26 AM UTC 24
Peak memory 400480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742622001 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3742622001 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.3656581579
Short name T548
Test name
Test status
Simulation time 12439607029 ps
CPU time 64.24 seconds
Started Oct 03 11:11:50 AM UTC 24
Finished Oct 03 11:12:56 AM UTC 24
Peak memory 234228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656581579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3656581579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.2369620414
Short name T700
Test name
Test status
Simulation time 440788563525 ps
CPU time 1537.92 seconds
Started Oct 03 11:12:58 AM UTC 24
Finished Oct 03 11:38:55 AM UTC 24
Peak memory 840856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369620414 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2369620414 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.2762975568
Short name T140
Test name
Test status
Simulation time 14719801 ps
CPU time 1.23 seconds
Started Oct 03 10:32:34 AM UTC 24
Finished Oct 03 10:32:36 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762975568 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2762975568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.655428322
Short name T227
Test name
Test status
Simulation time 26430062243 ps
CPU time 285.29 seconds
Started Oct 03 10:31:57 AM UTC 24
Finished Oct 03 10:36:46 AM UTC 24
Peak memory 471988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655428322 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.655428322 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.3918975263
Short name T196
Test name
Test status
Simulation time 27826744200 ps
CPU time 55.05 seconds
Started Oct 03 10:31:57 AM UTC 24
Finished Oct 03 10:32:53 AM UTC 24
Peak memory 246832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918975263 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3918975263 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.3008168407
Short name T53
Test name
Test status
Simulation time 505716583 ps
CPU time 54.02 seconds
Started Oct 03 10:31:32 AM UTC 24
Finished Oct 03 10:32:27 AM UTC 24
Peak memory 234420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008168407 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3008168407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.2951361268
Short name T195
Test name
Test status
Simulation time 3007876881 ps
CPU time 22.58 seconds
Started Oct 03 10:32:21 AM UTC 24
Finished Oct 03 10:32:45 AM UTC 24
Peak memory 234048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951361268 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2951361268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2302070745
Short name T84
Test name
Test status
Simulation time 411631445 ps
CPU time 8.42 seconds
Started Oct 03 10:32:21 AM UTC 24
Finished Oct 03 10:32:30 AM UTC 24
Peak memory 231256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302070745 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2302070745 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.3940839479
Short name T118
Test name
Test status
Simulation time 2762027286 ps
CPU time 12.51 seconds
Started Oct 03 10:32:25 AM UTC 24
Finished Oct 03 10:32:39 AM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940839479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3940839479 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3036537291
Short name T203
Test name
Test status
Simulation time 4332492735 ps
CPU time 104.15 seconds
Started Oct 03 10:31:59 AM UTC 24
Finished Oct 03 10:33:45 AM UTC 24
Peak memory 281396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036537291 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3036537291 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.3412870828
Short name T58
Test name
Test status
Simulation time 185411986 ps
CPU time 17.75 seconds
Started Oct 03 10:32:14 AM UTC 24
Finished Oct 03 10:32:33 AM UTC 24
Peak memory 244760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412870828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3412870828 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.160118170
Short name T72
Test name
Test status
Simulation time 303040621 ps
CPU time 4.38 seconds
Started Oct 03 10:32:15 AM UTC 24
Finished Oct 03 10:32:20 AM UTC 24
Peak memory 227272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160118170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.160118170 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1455308631
Short name T505
Test name
Test status
Simulation time 335873871721 ps
CPU time 2201.43 seconds
Started Oct 03 10:31:25 AM UTC 24
Finished Oct 03 11:08:33 AM UTC 24
Peak memory 2812728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455308631 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1455308631 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.2482962538
Short name T89
Test name
Test status
Simulation time 27579106363 ps
CPU time 192.76 seconds
Started Oct 03 10:32:03 AM UTC 24
Finished Oct 03 10:35:19 AM UTC 24
Peak memory 384120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482962538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2482962538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.1788309615
Short name T80
Test name
Test status
Simulation time 9269144890 ps
CPU time 46.48 seconds
Started Oct 03 10:32:34 AM UTC 24
Finished Oct 03 10:33:22 AM UTC 24
Peak memory 276616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788309615 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1788309615 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.571999206
Short name T138
Test name
Test status
Simulation time 2431474053 ps
CPU time 64.54 seconds
Started Oct 03 10:31:26 AM UTC 24
Finished Oct 03 10:32:33 AM UTC 24
Peak memory 273384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571999206 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.571999206 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.1195878462
Short name T98
Test name
Test status
Simulation time 5940480048 ps
CPU time 22.29 seconds
Started Oct 03 10:31:24 AM UTC 24
Finished Oct 03 10:31:48 AM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195878462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1195878462 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.2502084783
Short name T358
Test name
Test status
Simulation time 272001565552 ps
CPU time 1084.57 seconds
Started Oct 03 10:32:31 AM UTC 24
Finished Oct 03 10:50:50 AM UTC 24
Peak memory 1018992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502084783 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2502084783 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1053078582
Short name T99
Test name
Test status
Simulation time 34441482 ps
CPU time 3.34 seconds
Started Oct 03 10:31:51 AM UTC 24
Finished Oct 03 10:31:56 AM UTC 24
Peak memory 229584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053078582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1053078582 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.4232933047
Short name T193
Test name
Test status
Simulation time 29741374 ps
CPU time 2.94 seconds
Started Oct 03 10:31:53 AM UTC 24
Finished Oct 03 10:31:57 AM UTC 24
Peak memory 229488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232933047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.4232933047 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.1567675210
Short name T556
Test name
Test status
Simulation time 89967880778 ps
CPU time 2519.86 seconds
Started Oct 03 10:31:34 AM UTC 24
Finished Oct 03 11:14:03 AM UTC 24
Peak memory 3103388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567675210 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1567675210
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.3839751568
Short name T139
Test name
Test status
Simulation time 3410947140 ps
CPU time 55.63 seconds
Started Oct 03 10:31:37 AM UTC 24
Finished Oct 03 10:32:34 AM UTC 24
Peak memory 253016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839751568 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3839751568
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.894004297
Short name T137
Test name
Test status
Simulation time 4784879290 ps
CPU time 38.09 seconds
Started Oct 03 10:31:40 AM UTC 24
Finished Oct 03 10:32:20 AM UTC 24
Peak memory 236260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894004297 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.894004297 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.4120957550
Short name T378
Test name
Test status
Simulation time 160831489772 ps
CPU time 1249.18 seconds
Started Oct 03 10:31:40 AM UTC 24
Finished Oct 03 10:52:44 AM UTC 24
Peak memory 1708956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120957550 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4120957550
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.985494411
Short name T625
Test name
Test status
Simulation time 244022381523 ps
CPU time 2922.32 seconds
Started Oct 03 10:31:43 AM UTC 24
Finished Oct 03 11:21:00 AM UTC 24
Peak memory 3617432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985494411 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.98549441
1 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2774120020
Short name T205
Test name
Test status
Simulation time 12127753492 ps
CPU time 120.81 seconds
Started Oct 03 10:31:49 AM UTC 24
Finished Oct 03 10:33:53 AM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774120020 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2774120
020 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.1009587098
Short name T561
Test name
Test status
Simulation time 19950905 ps
CPU time 1.22 seconds
Started Oct 03 11:14:29 AM UTC 24
Finished Oct 03 11:14:31 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009587098 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1009587098 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.2683587348
Short name T586
Test name
Test status
Simulation time 7543493219 ps
CPU time 186.36 seconds
Started Oct 03 11:13:49 AM UTC 24
Finished Oct 03 11:16:59 AM UTC 24
Peak memory 293792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683587348 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2683587348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.142243456
Short name T673
Test name
Test status
Simulation time 48690279825 ps
CPU time 751.17 seconds
Started Oct 03 11:13:45 AM UTC 24
Finished Oct 03 11:26:26 AM UTC 24
Peak memory 258836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142243456 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.142243456 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.2479734109
Short name T560
Test name
Test status
Simulation time 1264576354 ps
CPU time 22.63 seconds
Started Oct 03 11:14:04 AM UTC 24
Finished Oct 03 11:14:28 AM UTC 24
Peak memory 248536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479734109 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2479734109 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.2339351835
Short name T579
Test name
Test status
Simulation time 5181386427 ps
CPU time 140 seconds
Started Oct 03 11:14:13 AM UTC 24
Finished Oct 03 11:16:35 AM UTC 24
Peak memory 381744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339351835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2339351835 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.1919487437
Short name T559
Test name
Test status
Simulation time 429458394 ps
CPU time 4.98 seconds
Started Oct 03 11:14:18 AM UTC 24
Finished Oct 03 11:14:24 AM UTC 24
Peak memory 227168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919487437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1919487437 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.2420545117
Short name T102
Test name
Test status
Simulation time 45068157 ps
CPU time 1.97 seconds
Started Oct 03 11:14:25 AM UTC 24
Finished Oct 03 11:14:28 AM UTC 24
Peak memory 226300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420545117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2420545117 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.853305790
Short name T694
Test name
Test status
Simulation time 24586379738 ps
CPU time 1360.18 seconds
Started Oct 03 11:13:17 AM UTC 24
Finished Oct 03 11:36:15 AM UTC 24
Peak memory 942896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853305790 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.853305790 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.3691948482
Short name T631
Test name
Test status
Simulation time 97551597865 ps
CPU time 491.86 seconds
Started Oct 03 11:13:17 AM UTC 24
Finished Oct 03 11:21:36 AM UTC 24
Peak memory 633656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691948482 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3691948482 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.2645185282
Short name T552
Test name
Test status
Simulation time 535539490 ps
CPU time 8.13 seconds
Started Oct 03 11:13:05 AM UTC 24
Finished Oct 03 11:13:15 AM UTC 24
Peak memory 229520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645185282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2645185282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.1205689976
Short name T698
Test name
Test status
Simulation time 56231520718 ps
CPU time 1416.78 seconds
Started Oct 03 11:14:29 AM UTC 24
Finished Oct 03 11:38:23 AM UTC 24
Peak memory 1510184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205689976 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1205689976 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.569589834
Short name T572
Test name
Test status
Simulation time 30206063 ps
CPU time 1.25 seconds
Started Oct 03 11:15:56 AM UTC 24
Finished Oct 03 11:15:58 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569589834 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.569589834 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.2441429069
Short name T577
Test name
Test status
Simulation time 8049042120 ps
CPU time 87.18 seconds
Started Oct 03 11:14:53 AM UTC 24
Finished Oct 03 11:16:22 AM UTC 24
Peak memory 291608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441429069 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2441429069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.299796552
Short name T663
Test name
Test status
Simulation time 16616791888 ps
CPU time 607.94 seconds
Started Oct 03 11:14:41 AM UTC 24
Finished Oct 03 11:24:56 AM UTC 24
Peak memory 254768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299796552 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.299796552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.2641897301
Short name T598
Test name
Test status
Simulation time 10793103679 ps
CPU time 161.53 seconds
Started Oct 03 11:15:13 AM UTC 24
Finished Oct 03 11:17:58 AM UTC 24
Peak memory 271200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641897301 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2641897301 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.352145054
Short name T575
Test name
Test status
Simulation time 1629481659 ps
CPU time 51.47 seconds
Started Oct 03 11:15:24 AM UTC 24
Finished Oct 03 11:16:17 AM UTC 24
Peak memory 277204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352145054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.352145054 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.2777031484
Short name T569
Test name
Test status
Simulation time 914719251 ps
CPU time 3.05 seconds
Started Oct 03 11:15:45 AM UTC 24
Finished Oct 03 11:15:49 AM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777031484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2777031484 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.2276992412
Short name T570
Test name
Test status
Simulation time 153574205 ps
CPU time 2.08 seconds
Started Oct 03 11:15:50 AM UTC 24
Finished Oct 03 11:15:53 AM UTC 24
Peak memory 227304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276992412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2276992412 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.3084986359
Short name T699
Test name
Test status
Simulation time 179102459631 ps
CPU time 1428.41 seconds
Started Oct 03 11:14:36 AM UTC 24
Finished Oct 03 11:38:42 AM UTC 24
Peak memory 1901584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084986359 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.3084986359 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.3108005057
Short name T629
Test name
Test status
Simulation time 17772895091 ps
CPU time 401.14 seconds
Started Oct 03 11:14:39 AM UTC 24
Finished Oct 03 11:21:26 AM UTC 24
Peak memory 611156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108005057 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3108005057 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.2985521244
Short name T565
Test name
Test status
Simulation time 1092655233 ps
CPU time 17.96 seconds
Started Oct 03 11:14:32 AM UTC 24
Finished Oct 03 11:14:51 AM UTC 24
Peak memory 231636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985521244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2985521244 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.128860186
Short name T662
Test name
Test status
Simulation time 5942558462 ps
CPU time 527.69 seconds
Started Oct 03 11:15:54 AM UTC 24
Finished Oct 03 11:24:50 AM UTC 24
Peak memory 328436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128860186 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.128860186 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.424493319
Short name T584
Test name
Test status
Simulation time 17519243 ps
CPU time 1.26 seconds
Started Oct 03 11:16:54 AM UTC 24
Finished Oct 03 11:16:56 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424493319 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.424493319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.2996219493
Short name T632
Test name
Test status
Simulation time 11205075720 ps
CPU time 314.31 seconds
Started Oct 03 11:16:20 AM UTC 24
Finished Oct 03 11:21:39 AM UTC 24
Peak memory 451692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996219493 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2996219493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.2748710591
Short name T657
Test name
Test status
Simulation time 24102478609 ps
CPU time 492.95 seconds
Started Oct 03 11:16:18 AM UTC 24
Finished Oct 03 11:24:38 AM UTC 24
Peak memory 244576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748710591 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2748710591 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.190447027
Short name T583
Test name
Test status
Simulation time 2373230257 ps
CPU time 28.93 seconds
Started Oct 03 11:16:23 AM UTC 24
Finished Oct 03 11:16:54 AM UTC 24
Peak memory 250808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190447027 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.190447027 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.1130900590
Short name T633
Test name
Test status
Simulation time 22312194703 ps
CPU time 308.69 seconds
Started Oct 03 11:16:26 AM UTC 24
Finished Oct 03 11:21:40 AM UTC 24
Peak memory 517172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130900590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1130900590 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.3582311941
Short name T580
Test name
Test status
Simulation time 1187734055 ps
CPU time 12.34 seconds
Started Oct 03 11:16:36 AM UTC 24
Finished Oct 03 11:16:49 AM UTC 24
Peak memory 227164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582311941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3582311941 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.45082826
Short name T582
Test name
Test status
Simulation time 433567729 ps
CPU time 2.13 seconds
Started Oct 03 11:16:50 AM UTC 24
Finished Oct 03 11:16:53 AM UTC 24
Peak memory 229640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45082826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.45082826 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1352909549
Short name T623
Test name
Test status
Simulation time 10731131642 ps
CPU time 287.38 seconds
Started Oct 03 11:16:06 AM UTC 24
Finished Oct 03 11:20:58 AM UTC 24
Peak memory 394020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352909549 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1352909549 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.115630161
Short name T576
Test name
Test status
Simulation time 155966102 ps
CPU time 3.98 seconds
Started Oct 03 11:16:14 AM UTC 24
Finished Oct 03 11:16:19 AM UTC 24
Peak memory 231600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115630161 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.115630161 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.141550017
Short name T578
Test name
Test status
Simulation time 1009012220 ps
CPU time 25.07 seconds
Started Oct 03 11:15:59 AM UTC 24
Finished Oct 03 11:16:25 AM UTC 24
Peak memory 231632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141550017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.141550017 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.2940834279
Short name T587
Test name
Test status
Simulation time 701025198 ps
CPU time 5.93 seconds
Started Oct 03 11:16:53 AM UTC 24
Finished Oct 03 11:17:00 AM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940834279 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2940834279 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.1611521911
Short name T594
Test name
Test status
Simulation time 24431028 ps
CPU time 1.21 seconds
Started Oct 03 11:17:34 AM UTC 24
Finished Oct 03 11:17:37 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611521911 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1611521911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.1055581381
Short name T599
Test name
Test status
Simulation time 1044249615 ps
CPU time 61.38 seconds
Started Oct 03 11:17:00 AM UTC 24
Finished Oct 03 11:18:04 AM UTC 24
Peak memory 246440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055581381 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1055581381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.1398271467
Short name T622
Test name
Test status
Simulation time 2730693961 ps
CPU time 231.53 seconds
Started Oct 03 11:16:59 AM UTC 24
Finished Oct 03 11:20:54 AM UTC 24
Peak memory 244536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398271467 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1398271467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.1697978605
Short name T621
Test name
Test status
Simulation time 6010250638 ps
CPU time 216.25 seconds
Started Oct 03 11:17:06 AM UTC 24
Finished Oct 03 11:20:45 AM UTC 24
Peak memory 328444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697978605 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1697978605 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.700314796
Short name T647
Test name
Test status
Simulation time 18666001335 ps
CPU time 382.68 seconds
Started Oct 03 11:17:06 AM UTC 24
Finished Oct 03 11:23:34 AM UTC 24
Peak memory 484140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700314796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.700314796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.2832637711
Short name T591
Test name
Test status
Simulation time 1144220390 ps
CPU time 11.15 seconds
Started Oct 03 11:17:13 AM UTC 24
Finished Oct 03 11:17:25 AM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832637711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2832637711 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.1141048682
Short name T592
Test name
Test status
Simulation time 91553255 ps
CPU time 1.98 seconds
Started Oct 03 11:17:26 AM UTC 24
Finished Oct 03 11:17:29 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141048682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1141048682 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.2635253031
Short name T708
Test name
Test status
Simulation time 74564641321 ps
CPU time 1873.69 seconds
Started Oct 03 11:16:57 AM UTC 24
Finished Oct 03 11:48:33 AM UTC 24
Peak memory 1336040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635253031 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.2635253031 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.1245034344
Short name T652
Test name
Test status
Simulation time 13875812151 ps
CPU time 419.89 seconds
Started Oct 03 11:16:58 AM UTC 24
Finished Oct 03 11:24:04 AM UTC 24
Peak memory 598844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245034344 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1245034344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.721134300
Short name T593
Test name
Test status
Simulation time 2425395634 ps
CPU time 36.87 seconds
Started Oct 03 11:16:55 AM UTC 24
Finished Oct 03 11:17:33 AM UTC 24
Peak memory 233848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721134300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.721134300 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.948334059
Short name T689
Test name
Test status
Simulation time 30026335830 ps
CPU time 902.19 seconds
Started Oct 03 11:17:30 AM UTC 24
Finished Oct 03 11:32:44 AM UTC 24
Peak memory 578264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948334059 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.948334059 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.2311701186
Short name T605
Test name
Test status
Simulation time 43065935 ps
CPU time 1.34 seconds
Started Oct 03 11:18:54 AM UTC 24
Finished Oct 03 11:18:56 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311701186 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2311701186 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.2303888885
Short name T640
Test name
Test status
Simulation time 22568965326 ps
CPU time 253.21 seconds
Started Oct 03 11:17:59 AM UTC 24
Finished Oct 03 11:22:16 AM UTC 24
Peak memory 330544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303888885 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.2303888885 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.1987884651
Short name T683
Test name
Test status
Simulation time 15790730701 ps
CPU time 628.39 seconds
Started Oct 03 11:17:50 AM UTC 24
Finished Oct 03 11:28:28 AM UTC 24
Peak memory 244508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987884651 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1987884651 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.3307996971
Short name T613
Test name
Test status
Simulation time 1701755401 ps
CPU time 114.51 seconds
Started Oct 03 11:18:04 AM UTC 24
Finished Oct 03 11:20:01 AM UTC 24
Peak memory 269016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307996971 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3307996971 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.4265835656
Short name T604
Test name
Test status
Simulation time 10318115037 ps
CPU time 15.57 seconds
Started Oct 03 11:18:36 AM UTC 24
Finished Oct 03 11:18:53 AM UTC 24
Peak memory 227352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265835656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.4265835656 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.2830552737
Short name T720
Test name
Test status
Simulation time 1287447878855 ps
CPU time 5802.34 seconds
Started Oct 03 11:17:42 AM UTC 24
Finished Oct 03 12:55:28 PM UTC 24
Peak memory 4447620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830552737 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.2830552737 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.4218165109
Short name T620
Test name
Test status
Simulation time 24931582124 ps
CPU time 163.5 seconds
Started Oct 03 11:17:49 AM UTC 24
Finished Oct 03 11:20:35 AM UTC 24
Peak memory 363636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218165109 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.4218165109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.1529033739
Short name T603
Test name
Test status
Simulation time 3678528303 ps
CPU time 61.55 seconds
Started Oct 03 11:17:37 AM UTC 24
Finished Oct 03 11:18:41 AM UTC 24
Peak memory 234324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529033739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1529033739 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.3150376734
Short name T691
Test name
Test status
Simulation time 15545393512 ps
CPU time 976.14 seconds
Started Oct 03 11:18:42 AM UTC 24
Finished Oct 03 11:35:10 AM UTC 24
Peak memory 689208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150376734 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3150376734 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.606491123
Short name T616
Test name
Test status
Simulation time 26331781 ps
CPU time 1.28 seconds
Started Oct 03 11:20:02 AM UTC 24
Finished Oct 03 11:20:05 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606491123 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.606491123 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.1182697863
Short name T619
Test name
Test status
Simulation time 2338726877 ps
CPU time 56.94 seconds
Started Oct 03 11:19:29 AM UTC 24
Finished Oct 03 11:20:28 AM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182697863 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1182697863 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.2659998587
Short name T696
Test name
Test status
Simulation time 56216389570 ps
CPU time 1064.36 seconds
Started Oct 03 11:19:26 AM UTC 24
Finished Oct 03 11:37:24 AM UTC 24
Peak memory 269384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659998587 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2659998587 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.3516330562
Short name T611
Test name
Test status
Simulation time 691734635 ps
CPU time 14.25 seconds
Started Oct 03 11:19:34 AM UTC 24
Finished Oct 03 11:19:49 AM UTC 24
Peak memory 234184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516330562 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3516330562 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.3944794201
Short name T644
Test name
Test status
Simulation time 16192569550 ps
CPU time 204.69 seconds
Started Oct 03 11:19:36 AM UTC 24
Finished Oct 03 11:23:04 AM UTC 24
Peak memory 330588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944794201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3944794201 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.3209047830
Short name T614
Test name
Test status
Simulation time 973892011 ps
CPU time 10.78 seconds
Started Oct 03 11:19:50 AM UTC 24
Finished Oct 03 11:20:02 AM UTC 24
Peak memory 227168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209047830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3209047830 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.3649074210
Short name T615
Test name
Test status
Simulation time 83035113 ps
CPU time 2.63 seconds
Started Oct 03 11:20:00 AM UTC 24
Finished Oct 03 11:20:04 AM UTC 24
Peak memory 227364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649074210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3649074210 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.2134122480
Short name T713
Test name
Test status
Simulation time 296640626307 ps
CPU time 2572.43 seconds
Started Oct 03 11:18:57 AM UTC 24
Finished Oct 03 12:02:19 PM UTC 24
Peak memory 3019560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134122480 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.2134122480 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.925988305
Short name T651
Test name
Test status
Simulation time 3091302943 ps
CPU time 267.64 seconds
Started Oct 03 11:19:13 AM UTC 24
Finished Oct 03 11:23:45 AM UTC 24
Peak memory 336724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925988305 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.925988305 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.2778834332
Short name T610
Test name
Test status
Simulation time 661556653 ps
CPU time 37.39 seconds
Started Oct 03 11:18:56 AM UTC 24
Finished Oct 03 11:19:35 AM UTC 24
Peak memory 231536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778834332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2778834332 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.3163378123
Short name T628
Test name
Test status
Simulation time 8503966359 ps
CPU time 65.04 seconds
Started Oct 03 11:20:02 AM UTC 24
Finished Oct 03 11:21:09 AM UTC 24
Peak memory 261176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163378123 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3163378123 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.1811752941
Short name T627
Test name
Test status
Simulation time 22512544 ps
CPU time 1.26 seconds
Started Oct 03 11:21:01 AM UTC 24
Finished Oct 03 11:21:03 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811752941 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1811752941 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.3312005213
Short name T653
Test name
Test status
Simulation time 7044638775 ps
CPU time 235.38 seconds
Started Oct 03 11:20:29 AM UTC 24
Finished Oct 03 11:24:29 AM UTC 24
Peak memory 387868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312005213 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3312005213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.1762008862
Short name T688
Test name
Test status
Simulation time 297510437967 ps
CPU time 725.03 seconds
Started Oct 03 11:20:26 AM UTC 24
Finished Oct 03 11:32:40 AM UTC 24
Peak memory 258868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762008862 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1762008862 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2789864617
Short name T643
Test name
Test status
Simulation time 14617553820 ps
CPU time 133.19 seconds
Started Oct 03 11:20:37 AM UTC 24
Finished Oct 03 11:22:53 AM UTC 24
Peak memory 287576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789864617 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2789864617 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.3801795616
Short name T661
Test name
Test status
Simulation time 16476102389 ps
CPU time 236.67 seconds
Started Oct 03 11:20:46 AM UTC 24
Finished Oct 03 11:24:47 AM UTC 24
Peak memory 414488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801795616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3801795616 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.4227981676
Short name T624
Test name
Test status
Simulation time 313377569 ps
CPU time 2.75 seconds
Started Oct 03 11:20:55 AM UTC 24
Finished Oct 03 11:20:59 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227981676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.4227981676 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.92749536
Short name T626
Test name
Test status
Simulation time 176470927 ps
CPU time 2.04 seconds
Started Oct 03 11:20:58 AM UTC 24
Finished Oct 03 11:21:02 AM UTC 24
Peak memory 227524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92749536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.92749536 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2262720877
Short name T656
Test name
Test status
Simulation time 11291940609 ps
CPU time 267.09 seconds
Started Oct 03 11:20:06 AM UTC 24
Finished Oct 03 11:24:37 AM UTC 24
Peak memory 388012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262720877 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2262720877 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.1342598246
Short name T669
Test name
Test status
Simulation time 52180660808 ps
CPU time 319.65 seconds
Started Oct 03 11:20:20 AM UTC 24
Finished Oct 03 11:25:44 AM UTC 24
Peak memory 510804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342598246 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1342598246 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.2409709434
Short name T617
Test name
Test status
Simulation time 777614762 ps
CPU time 12.78 seconds
Started Oct 03 11:20:04 AM UTC 24
Finished Oct 03 11:20:18 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409709434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2409709434 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.1716052224
Short name T701
Test name
Test status
Simulation time 62251739852 ps
CPU time 1168.35 seconds
Started Oct 03 11:21:00 AM UTC 24
Finished Oct 03 11:40:42 AM UTC 24
Peak memory 724156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716052224 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1716052224 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.2196512925
Short name T637
Test name
Test status
Simulation time 101799577 ps
CPU time 1.18 seconds
Started Oct 03 11:21:49 AM UTC 24
Finished Oct 03 11:21:51 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196512925 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2196512925 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.1945698387
Short name T681
Test name
Test status
Simulation time 64927631168 ps
CPU time 399.42 seconds
Started Oct 03 11:21:33 AM UTC 24
Finished Oct 03 11:28:19 AM UTC 24
Peak memory 547632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945698387 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1945698387 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.3769942915
Short name T685
Test name
Test status
Simulation time 61813312645 ps
CPU time 564.06 seconds
Started Oct 03 11:21:27 AM UTC 24
Finished Oct 03 11:30:59 AM UTC 24
Peak memory 248888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769942915 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3769942915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.3698759394
Short name T666
Test name
Test status
Simulation time 61148044615 ps
CPU time 209.76 seconds
Started Oct 03 11:21:37 AM UTC 24
Finished Oct 03 11:25:10 AM UTC 24
Peak memory 351024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698759394 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3698759394 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.3697101031
Short name T682
Test name
Test status
Simulation time 46095749744 ps
CPU time 398.17 seconds
Started Oct 03 11:21:40 AM UTC 24
Finished Oct 03 11:28:24 AM UTC 24
Peak memory 387860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697101031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3697101031 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.2575735092
Short name T635
Test name
Test status
Simulation time 1644451741 ps
CPU time 5.11 seconds
Started Oct 03 11:21:41 AM UTC 24
Finished Oct 03 11:21:47 AM UTC 24
Peak memory 227200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575735092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2575735092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.2219381569
Short name T636
Test name
Test status
Simulation time 235569541 ps
CPU time 1.84 seconds
Started Oct 03 11:21:45 AM UTC 24
Finished Oct 03 11:21:48 AM UTC 24
Peak memory 226324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219381569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2219381569 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.3847813395
Short name T718
Test name
Test status
Simulation time 179071649837 ps
CPU time 4053.15 seconds
Started Oct 03 11:21:04 AM UTC 24
Finished Oct 03 12:29:25 PM UTC 24
Peak memory 4358888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847813395 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.3847813395 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.2191210068
Short name T639
Test name
Test status
Simulation time 7444742089 ps
CPU time 58.98 seconds
Started Oct 03 11:21:10 AM UTC 24
Finished Oct 03 11:22:11 AM UTC 24
Peak memory 279284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191210068 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2191210068 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.941690951
Short name T630
Test name
Test status
Simulation time 571712901 ps
CPU time 27.93 seconds
Started Oct 03 11:21:03 AM UTC 24
Finished Oct 03 11:21:32 AM UTC 24
Peak memory 231584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941690951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.941690951 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.1924221873
Short name T697
Test name
Test status
Simulation time 66088624886 ps
CPU time 942.33 seconds
Started Oct 03 11:21:48 AM UTC 24
Finished Oct 03 11:37:42 AM UTC 24
Peak memory 453688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924221873 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1924221873 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.3095409935
Short name T648
Test name
Test status
Simulation time 47998267 ps
CPU time 1.22 seconds
Started Oct 03 11:23:36 AM UTC 24
Finished Oct 03 11:23:39 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095409935 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3095409935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.2927859389
Short name T649
Test name
Test status
Simulation time 8518888571 ps
CPU time 64.69 seconds
Started Oct 03 11:22:34 AM UTC 24
Finished Oct 03 11:23:40 AM UTC 24
Peak memory 265200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927859389 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2927859389 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.3229062562
Short name T671
Test name
Test status
Simulation time 24420272898 ps
CPU time 218.98 seconds
Started Oct 03 11:22:17 AM UTC 24
Finished Oct 03 11:26:00 AM UTC 24
Peak memory 244728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229062562 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3229062562 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.1130142690
Short name T655
Test name
Test status
Simulation time 7217599103 ps
CPU time 105.88 seconds
Started Oct 03 11:22:47 AM UTC 24
Finished Oct 03 11:24:35 AM UTC 24
Peak memory 269472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130142690 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1130142690 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.1769183440
Short name T676
Test name
Test status
Simulation time 3236632401 ps
CPU time 240.69 seconds
Started Oct 03 11:22:53 AM UTC 24
Finished Oct 03 11:26:58 AM UTC 24
Peak memory 340820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769183440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1769183440 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.3555476588
Short name T645
Test name
Test status
Simulation time 2637002450 ps
CPU time 8.6 seconds
Started Oct 03 11:23:04 AM UTC 24
Finished Oct 03 11:23:14 AM UTC 24
Peak memory 227292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555476588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3555476588 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.2460904335
Short name T650
Test name
Test status
Simulation time 856399283 ps
CPU time 27.56 seconds
Started Oct 03 11:23:15 AM UTC 24
Finished Oct 03 11:23:43 AM UTC 24
Peak memory 248568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460904335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2460904335 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.81165569
Short name T719
Test name
Test status
Simulation time 503648902445 ps
CPU time 4713.13 seconds
Started Oct 03 11:22:05 AM UTC 24
Finished Oct 03 12:41:33 PM UTC 24
Peak memory 4635488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81165569 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.81165569 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.3135789736
Short name T641
Test name
Test status
Simulation time 181961232 ps
CPU time 19.73 seconds
Started Oct 03 11:22:12 AM UTC 24
Finished Oct 03 11:22:33 AM UTC 24
Peak memory 234360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135789736 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3135789736 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.1622206675
Short name T642
Test name
Test status
Simulation time 2282798491 ps
CPU time 52.41 seconds
Started Oct 03 11:21:52 AM UTC 24
Finished Oct 03 11:22:46 AM UTC 24
Peak memory 234480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622206675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1622206675 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.2581536542
Short name T717
Test name
Test status
Simulation time 112453064496 ps
CPU time 2599.53 seconds
Started Oct 03 11:23:20 AM UTC 24
Finished Oct 03 12:07:10 PM UTC 24
Peak memory 1006684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581536542 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2581536542 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.2387601181
Short name T660
Test name
Test status
Simulation time 14714656 ps
CPU time 1.04 seconds
Started Oct 03 11:24:39 AM UTC 24
Finished Oct 03 11:24:41 AM UTC 24
Peak memory 216384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387601181 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2387601181 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.796683762
Short name T665
Test name
Test status
Simulation time 10746127552 ps
CPU time 58.43 seconds
Started Oct 03 11:24:05 AM UTC 24
Finished Oct 03 11:25:05 AM UTC 24
Peak memory 283456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796683762 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.796683762 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.627588365
Short name T687
Test name
Test status
Simulation time 28803916090 ps
CPU time 517.4 seconds
Started Oct 03 11:23:46 AM UTC 24
Finished Oct 03 11:32:31 AM UTC 24
Peak memory 248984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627588365 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.627588365 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.2521696061
Short name T680
Test name
Test status
Simulation time 20267086303 ps
CPU time 208.66 seconds
Started Oct 03 11:24:20 AM UTC 24
Finished Oct 03 11:27:52 AM UTC 24
Peak memory 428896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521696061 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2521696061 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.4195366582
Short name T678
Test name
Test status
Simulation time 20539497269 ps
CPU time 148.53 seconds
Started Oct 03 11:24:29 AM UTC 24
Finished Oct 03 11:27:01 AM UTC 24
Peak memory 365596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195366582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4195366582 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.1760868090
Short name T659
Test name
Test status
Simulation time 944136564 ps
CPU time 9.62 seconds
Started Oct 03 11:24:30 AM UTC 24
Finished Oct 03 11:24:41 AM UTC 24
Peak memory 227168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760868090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1760868090 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.2513271060
Short name T658
Test name
Test status
Simulation time 53150152 ps
CPU time 2.05 seconds
Started Oct 03 11:24:36 AM UTC 24
Finished Oct 03 11:24:40 AM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513271060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2513271060 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3916327398
Short name T690
Test name
Test status
Simulation time 26282501641 ps
CPU time 605.02 seconds
Started Oct 03 11:23:41 AM UTC 24
Finished Oct 03 11:33:54 AM UTC 24
Peak memory 994088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916327398 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.3916327398 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.1771766558
Short name T674
Test name
Test status
Simulation time 12861571172 ps
CPU time 166.5 seconds
Started Oct 03 11:23:44 AM UTC 24
Finished Oct 03 11:26:35 AM UTC 24
Peak memory 389940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771766558 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1771766558 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.2796352833
Short name T654
Test name
Test status
Simulation time 3031886408 ps
CPU time 46.96 seconds
Started Oct 03 11:23:40 AM UTC 24
Finished Oct 03 11:24:29 AM UTC 24
Peak memory 233688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796352833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2796352833 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.2968267045
Short name T707
Test name
Test status
Simulation time 237305892784 ps
CPU time 1412.15 seconds
Started Oct 03 11:24:37 AM UTC 24
Finished Oct 03 11:48:28 AM UTC 24
Peak memory 1031312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968267045 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2968267045 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.2088125105
Short name T199
Test name
Test status
Simulation time 42378211 ps
CPU time 1.2 seconds
Started Oct 03 10:33:24 AM UTC 24
Finished Oct 03 10:33:26 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088125105 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2088125105 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.1191064414
Short name T231
Test name
Test status
Simulation time 61646355858 ps
CPU time 273.04 seconds
Started Oct 03 10:32:43 AM UTC 24
Finished Oct 03 10:37:20 AM UTC 24
Peak memory 443416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191064414 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1191064414 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.2042109172
Short name T200
Test name
Test status
Simulation time 12275720086 ps
CPU time 47.75 seconds
Started Oct 03 10:32:46 AM UTC 24
Finished Oct 03 10:33:35 AM UTC 24
Peak memory 252756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042109172 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2042109172 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.229815734
Short name T144
Test name
Test status
Simulation time 10292184495 ps
CPU time 589.98 seconds
Started Oct 03 10:32:43 AM UTC 24
Finished Oct 03 10:42:40 AM UTC 24
Peak memory 248620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229815734 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.229815734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.2447782451
Short name T198
Test name
Test status
Simulation time 149700087 ps
CPU time 3.7 seconds
Started Oct 03 10:33:13 AM UTC 24
Finished Oct 03 10:33:18 AM UTC 24
Peak memory 227168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447782451 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2447782451 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.2447213794
Short name T207
Test name
Test status
Simulation time 1861037152 ps
CPU time 42.62 seconds
Started Oct 03 10:33:14 AM UTC 24
Finished Oct 03 10:33:58 AM UTC 24
Peak memory 233888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447213794 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.2447213794 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.4039365589
Short name T204
Test name
Test status
Simulation time 2155521260 ps
CPU time 32.76 seconds
Started Oct 03 10:33:18 AM UTC 24
Finished Oct 03 10:33:52 AM UTC 24
Peak memory 233820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039365589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.4039365589 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.491296023
Short name T197
Test name
Test status
Simulation time 359020513 ps
CPU time 11.52 seconds
Started Oct 03 10:32:53 AM UTC 24
Finished Oct 03 10:33:05 AM UTC 24
Peak memory 234072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491296023 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.491296023 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.4270124811
Short name T29
Test name
Test status
Simulation time 32377755838 ps
CPU time 293.38 seconds
Started Oct 03 10:32:56 AM UTC 24
Finished Oct 03 10:37:54 AM UTC 24
Peak memory 332788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270124811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.4270124811 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.1963132477
Short name T73
Test name
Test status
Simulation time 1445311877 ps
CPU time 10.46 seconds
Started Oct 03 10:33:06 AM UTC 24
Finished Oct 03 10:33:18 AM UTC 24
Peak memory 227268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963132477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1963132477 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.595724383
Short name T69
Test name
Test status
Simulation time 98234944 ps
CPU time 2.18 seconds
Started Oct 03 10:33:18 AM UTC 24
Finished Oct 03 10:33:22 AM UTC 24
Peak memory 227304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595724383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.595724383 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.4211290568
Short name T479
Test name
Test status
Simulation time 118692394033 ps
CPU time 1944.28 seconds
Started Oct 03 10:32:37 AM UTC 24
Finished Oct 03 11:05:24 AM UTC 24
Peak memory 2360416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211290568 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.4211290568 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.375303973
Short name T90
Test name
Test status
Simulation time 35723614345 ps
CPU time 182.79 seconds
Started Oct 03 10:32:54 AM UTC 24
Finished Oct 03 10:35:59 AM UTC 24
Peak memory 312764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375303973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.375303973 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.3366091401
Short name T229
Test name
Test status
Simulation time 3728843319 ps
CPU time 253.99 seconds
Started Oct 03 10:32:39 AM UTC 24
Finished Oct 03 10:36:57 AM UTC 24
Peak memory 338772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366091401 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3366091401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.2951475
Short name T185
Test name
Test status
Simulation time 3104810616 ps
CPU time 35.53 seconds
Started Oct 03 10:32:35 AM UTC 24
Finished Oct 03 10:33:12 AM UTC 24
Peak memory 234288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2951475 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.380600662
Short name T536
Test name
Test status
Simulation time 165091694589 ps
CPU time 2269.95 seconds
Started Oct 03 10:33:21 AM UTC 24
Finished Oct 03 11:11:40 AM UTC 24
Peak memory 1014844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380600662 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.380600662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.3358247937
Short name T211
Test name
Test status
Simulation time 19369968 ps
CPU time 1.27 seconds
Started Oct 03 10:34:17 AM UTC 24
Finished Oct 03 10:34:20 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358247937 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3358247937 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.319875006
Short name T230
Test name
Test status
Simulation time 3924630940 ps
CPU time 198.08 seconds
Started Oct 03 10:33:40 AM UTC 24
Finished Oct 03 10:37:02 AM UTC 24
Peak memory 301844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319875006 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.319875006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.2174826685
Short name T222
Test name
Test status
Simulation time 7285325482 ps
CPU time 130.56 seconds
Started Oct 03 10:33:44 AM UTC 24
Finished Oct 03 10:35:57 AM UTC 24
Peak memory 342772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174826685 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2174826685 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.4293550485
Short name T208
Test name
Test status
Simulation time 770288000 ps
CPU time 9.2 seconds
Started Oct 03 10:33:55 AM UTC 24
Finished Oct 03 10:34:05 AM UTC 24
Peak memory 233576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293550485 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.4293550485 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.2958509333
Short name T209
Test name
Test status
Simulation time 370087106 ps
CPU time 8.25 seconds
Started Oct 03 10:33:59 AM UTC 24
Finished Oct 03 10:34:08 AM UTC 24
Peak memory 231648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958509333 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2958509333 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.101558100
Short name T162
Test name
Test status
Simulation time 10116239149 ps
CPU time 31.6 seconds
Started Oct 03 10:34:06 AM UTC 24
Finished Oct 03 10:34:39 AM UTC 24
Peak memory 234164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101558100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.101558100 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.2356672173
Short name T251
Test name
Test status
Simulation time 14014435402 ps
CPU time 347.27 seconds
Started Oct 03 10:33:45 AM UTC 24
Finished Oct 03 10:39:38 AM UTC 24
Peak memory 465724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356672173 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2356672173 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.443672852
Short name T164
Test name
Test status
Simulation time 18554518290 ps
CPU time 521.87 seconds
Started Oct 03 10:33:53 AM UTC 24
Finished Oct 03 10:42:42 AM UTC 24
Peak memory 619316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443672852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.443672852 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.2970922097
Short name T74
Test name
Test status
Simulation time 1779887833 ps
CPU time 9.97 seconds
Started Oct 03 10:33:54 AM UTC 24
Finished Oct 03 10:34:05 AM UTC 24
Peak memory 227168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970922097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2970922097 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.1436065689
Short name T210
Test name
Test status
Simulation time 36992514 ps
CPU time 2.76 seconds
Started Oct 03 10:34:06 AM UTC 24
Finished Oct 03 10:34:10 AM UTC 24
Peak memory 227364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436065689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1436065689 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.3369205810
Short name T709
Test name
Test status
Simulation time 497533305284 ps
CPU time 4460.9 seconds
Started Oct 03 10:33:30 AM UTC 24
Finished Oct 03 11:48:42 AM UTC 24
Peak memory 4561820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369205810 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.3369205810 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.1319382094
Short name T64
Test name
Test status
Simulation time 1157292472 ps
CPU time 57.78 seconds
Started Oct 03 10:33:46 AM UTC 24
Finished Oct 03 10:34:46 AM UTC 24
Peak memory 252932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319382094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1319382094 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.3213757083
Short name T221
Test name
Test status
Simulation time 6075509944 ps
CPU time 138.02 seconds
Started Oct 03 10:33:32 AM UTC 24
Finished Oct 03 10:35:53 AM UTC 24
Peak memory 283744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213757083 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3213757083 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.1020534881
Short name T201
Test name
Test status
Simulation time 2479245187 ps
CPU time 15.58 seconds
Started Oct 03 10:33:27 AM UTC 24
Finished Oct 03 10:33:43 AM UTC 24
Peak memory 229928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020534881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1020534881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.1523137092
Short name T243
Test name
Test status
Simulation time 28627403422 ps
CPU time 289.2 seconds
Started Oct 03 10:34:09 AM UTC 24
Finished Oct 03 10:39:02 AM UTC 24
Peak memory 404272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523137092 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1523137092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.4240386551
Short name T219
Test name
Test status
Simulation time 49744569 ps
CPU time 1.29 seconds
Started Oct 03 10:35:36 AM UTC 24
Finished Oct 03 10:35:38 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240386551 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.4240386551 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.595306319
Short name T214
Test name
Test status
Simulation time 57770762 ps
CPU time 5.67 seconds
Started Oct 03 10:34:40 AM UTC 24
Finished Oct 03 10:34:46 AM UTC 24
Peak memory 231716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595306319 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.595306319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.1704987381
Short name T37
Test name
Test status
Simulation time 9000960279 ps
CPU time 180.52 seconds
Started Oct 03 10:34:47 AM UTC 24
Finished Oct 03 10:37:50 AM UTC 24
Peak memory 361308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704987381 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1704987381 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.3038882995
Short name T142
Test name
Test status
Simulation time 20863242965 ps
CPU time 438.44 seconds
Started Oct 03 10:34:30 AM UTC 24
Finished Oct 03 10:41:54 AM UTC 24
Peak memory 244792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038882995 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3038882995 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2336146581
Short name T43
Test name
Test status
Simulation time 1474578570 ps
CPU time 33.79 seconds
Started Oct 03 10:35:06 AM UTC 24
Finished Oct 03 10:35:42 AM UTC 24
Peak memory 234036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336146581 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2336146581 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.1044232446
Short name T218
Test name
Test status
Simulation time 4308203088 ps
CPU time 23.3 seconds
Started Oct 03 10:35:11 AM UTC 24
Finished Oct 03 10:35:35 AM UTC 24
Peak memory 233964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044232446 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1044232446 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.558296657
Short name T163
Test name
Test status
Simulation time 23036440006 ps
CPU time 67.08 seconds
Started Oct 03 10:35:15 AM UTC 24
Finished Oct 03 10:36:24 AM UTC 24
Peak memory 234332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558296657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.558296657 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.1509053034
Short name T256
Test name
Test status
Simulation time 37463809116 ps
CPU time 296.51 seconds
Started Oct 03 10:34:47 AM UTC 24
Finished Oct 03 10:39:48 AM UTC 24
Peak memory 437012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509053034 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1509053034 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.222395537
Short name T28
Test name
Test status
Simulation time 3056602460 ps
CPU time 50.9 seconds
Started Oct 03 10:35:00 AM UTC 24
Finished Oct 03 10:35:53 AM UTC 24
Peak memory 264944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222395537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.222395537 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.380398798
Short name T75
Test name
Test status
Simulation time 785590058 ps
CPU time 9.28 seconds
Started Oct 03 10:35:06 AM UTC 24
Finished Oct 03 10:35:17 AM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380398798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.380398798 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.2489090627
Short name T217
Test name
Test status
Simulation time 129604875 ps
CPU time 2.14 seconds
Started Oct 03 10:35:18 AM UTC 24
Finished Oct 03 10:35:21 AM UTC 24
Peak memory 227600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489090627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2489090627 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.3651173367
Short name T379
Test name
Test status
Simulation time 160633272067 ps
CPU time 1091.34 seconds
Started Oct 03 10:34:21 AM UTC 24
Finished Oct 03 10:52:47 AM UTC 24
Peak memory 1414236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651173367 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.3651173367 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.4115374987
Short name T91
Test name
Test status
Simulation time 1359916347 ps
CPU time 112.42 seconds
Started Oct 03 10:34:48 AM UTC 24
Finished Oct 03 10:36:43 AM UTC 24
Peak memory 265152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115374987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.4115374987 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.3462132381
Short name T216
Test name
Test status
Simulation time 519455963 ps
CPU time 45.5 seconds
Started Oct 03 10:34:26 AM UTC 24
Finished Oct 03 10:35:14 AM UTC 24
Peak memory 242332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462132381 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3462132381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.2585502107
Short name T215
Test name
Test status
Simulation time 683042863 ps
CPU time 24.92 seconds
Started Oct 03 10:34:20 AM UTC 24
Finished Oct 03 10:34:47 AM UTC 24
Peak memory 231532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585502107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2585502107 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.4281314541
Short name T145
Test name
Test status
Simulation time 30304709913 ps
CPU time 484.96 seconds
Started Oct 03 10:35:20 AM UTC 24
Finished Oct 03 10:43:31 AM UTC 24
Peak memory 474464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281314541 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.4281314541 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.4089314162
Short name T124
Test name
Test status
Simulation time 5347982318 ps
CPU time 34.19 seconds
Started Oct 03 10:35:22 AM UTC 24
Finished Oct 03 10:35:58 AM UTC 24
Peak memory 244600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4089314162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_
with_rand_reset.4089314162 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.1191222080
Short name T225
Test name
Test status
Simulation time 17337797 ps
CPU time 1.26 seconds
Started Oct 03 10:36:38 AM UTC 24
Finished Oct 03 10:36:40 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191222080 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1191222080 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.3444089167
Short name T239
Test name
Test status
Simulation time 97805424194 ps
CPU time 173.87 seconds
Started Oct 03 10:35:54 AM UTC 24
Finished Oct 03 10:38:51 AM UTC 24
Peak memory 359216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444089167 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3444089167 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.3918972797
Short name T258
Test name
Test status
Simulation time 25755883386 ps
CPU time 250.44 seconds
Started Oct 03 10:35:54 AM UTC 24
Finished Oct 03 10:40:08 AM UTC 24
Peak memory 334660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918972797 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3918972797 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.4274093435
Short name T141
Test name
Test status
Simulation time 84815624575 ps
CPU time 170.7 seconds
Started Oct 03 10:35:49 AM UTC 24
Finished Oct 03 10:38:43 AM UTC 24
Peak memory 234292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274093435 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.4274093435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.869546470
Short name T226
Test name
Test status
Simulation time 1076066997 ps
CPU time 15.04 seconds
Started Oct 03 10:36:24 AM UTC 24
Finished Oct 03 10:36:40 AM UTC 24
Peak memory 233548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869546470 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.869546470 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.4252079299
Short name T223
Test name
Test status
Simulation time 195965261 ps
CPU time 4.62 seconds
Started Oct 03 10:36:27 AM UTC 24
Finished Oct 03 10:36:33 AM UTC 24
Peak memory 229220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252079299 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.4252079299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.2758409
Short name T160
Test name
Test status
Simulation time 8527494665 ps
CPU time 65.95 seconds
Started Oct 03 10:36:28 AM UTC 24
Finished Oct 03 10:37:36 AM UTC 24
Peak memory 234492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2758409 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.1891601737
Short name T268
Test name
Test status
Simulation time 14344104474 ps
CPU time 287.48 seconds
Started Oct 03 10:35:59 AM UTC 24
Finished Oct 03 10:40:51 AM UTC 24
Peak memory 482392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891601737 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1891601737 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.3885250710
Short name T257
Test name
Test status
Simulation time 42273787908 ps
CPU time 238.88 seconds
Started Oct 03 10:36:01 AM UTC 24
Finished Oct 03 10:40:04 AM UTC 24
Peak memory 492340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885250710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3885250710 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.3641424482
Short name T76
Test name
Test status
Simulation time 1766989034 ps
CPU time 9.18 seconds
Started Oct 03 10:36:16 AM UTC 24
Finished Oct 03 10:36:26 AM UTC 24
Peak memory 227524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641424482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3641424482 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.2380558482
Short name T224
Test name
Test status
Simulation time 115157954 ps
CPU time 2.49 seconds
Started Oct 03 10:36:33 AM UTC 24
Finished Oct 03 10:36:37 AM UTC 24
Peak memory 229540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380558482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2380558482 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.3669655962
Short name T608
Test name
Test status
Simulation time 243013745050 ps
CPU time 2597.18 seconds
Started Oct 03 10:35:39 AM UTC 24
Finished Oct 03 11:19:27 AM UTC 24
Peak memory 3050288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669655962 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.3669655962 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.3078484234
Short name T250
Test name
Test status
Simulation time 7069821265 ps
CPU time 212.78 seconds
Started Oct 03 10:35:59 AM UTC 24
Finished Oct 03 10:39:35 AM UTC 24
Peak memory 379968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078484234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3078484234 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.3489712007
Short name T283
Test name
Test status
Simulation time 4258165119 ps
CPU time 422.78 seconds
Started Oct 03 10:35:42 AM UTC 24
Finished Oct 03 10:42:52 AM UTC 24
Peak memory 386208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489712007 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3489712007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.2815743721
Short name T187
Test name
Test status
Simulation time 1594530999 ps
CPU time 37.06 seconds
Started Oct 03 10:35:36 AM UTC 24
Finished Oct 03 10:36:15 AM UTC 24
Peak memory 234064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815743721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2815743721 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.2557616871
Short name T557
Test name
Test status
Simulation time 353144731285 ps
CPU time 2232.45 seconds
Started Oct 03 10:36:34 AM UTC 24
Finished Oct 03 11:14:11 AM UTC 24
Peak memory 1696828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557616871 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2557616871 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.1739214773
Short name T234
Test name
Test status
Simulation time 114434049 ps
CPU time 1.32 seconds
Started Oct 03 10:38:28 AM UTC 24
Finished Oct 03 10:38:31 AM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739214773 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1739214773 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.936547603
Short name T262
Test name
Test status
Simulation time 4397292799 ps
CPU time 211.61 seconds
Started Oct 03 10:36:52 AM UTC 24
Finished Oct 03 10:40:27 AM UTC 24
Peak memory 312108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936547603 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.936547603 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.2179573763
Short name T248
Test name
Test status
Simulation time 25255740982 ps
CPU time 148.98 seconds
Started Oct 03 10:36:58 AM UTC 24
Finished Oct 03 10:39:30 AM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179573763 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2179573763 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.1487218434
Short name T345
Test name
Test status
Simulation time 124084918561 ps
CPU time 712.3 seconds
Started Oct 03 10:36:47 AM UTC 24
Finished Oct 03 10:48:49 AM UTC 24
Peak memory 254708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487218434 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1487218434 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.418875879
Short name T232
Test name
Test status
Simulation time 38757939 ps
CPU time 3.13 seconds
Started Oct 03 10:37:51 AM UTC 24
Finished Oct 03 10:37:55 AM UTC 24
Peak memory 229284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418875879 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.418875879 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.470629962
Short name T235
Test name
Test status
Simulation time 8914714037 ps
CPU time 40.19 seconds
Started Oct 03 10:37:51 AM UTC 24
Finished Oct 03 10:38:33 AM UTC 24
Peak memory 234004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470629962 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.470629962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2708220235
Short name T238
Test name
Test status
Simulation time 39046902961 ps
CPU time 53.51 seconds
Started Oct 03 10:37:55 AM UTC 24
Finished Oct 03 10:38:50 AM UTC 24
Peak memory 234236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708220235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2708220235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.518827177
Short name T240
Test name
Test status
Simulation time 15248189136 ps
CPU time 111.26 seconds
Started Oct 03 10:37:02 AM UTC 24
Finished Oct 03 10:38:56 AM UTC 24
Peak memory 297752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518827177 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.518827177 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.563640583
Short name T236
Test name
Test status
Simulation time 2151427899 ps
CPU time 65.28 seconds
Started Oct 03 10:37:28 AM UTC 24
Finished Oct 03 10:38:35 AM UTC 24
Peak memory 295724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563640583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.563640583 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.1319904958
Short name T77
Test name
Test status
Simulation time 3825825422 ps
CPU time 10.31 seconds
Started Oct 03 10:37:38 AM UTC 24
Finished Oct 03 10:37:50 AM UTC 24
Peak memory 227596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319904958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1319904958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.69394250
Short name T233
Test name
Test status
Simulation time 56013177 ps
CPU time 2.63 seconds
Started Oct 03 10:37:56 AM UTC 24
Finished Oct 03 10:38:00 AM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69394250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.69394250 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.2173226859
Short name T264
Test name
Test status
Simulation time 4822204684 ps
CPU time 231.83 seconds
Started Oct 03 10:36:41 AM UTC 24
Finished Oct 03 10:40:37 AM UTC 24
Peak memory 371448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173226859 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.2173226859 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.2520755027
Short name T92
Test name
Test status
Simulation time 4839077705 ps
CPU time 63.64 seconds
Started Oct 03 10:37:21 AM UTC 24
Finished Oct 03 10:38:27 AM UTC 24
Peak memory 257384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520755027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2520755027 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.609955139
Short name T281
Test name
Test status
Simulation time 12231865758 ps
CPU time 349.43 seconds
Started Oct 03 10:36:44 AM UTC 24
Finished Oct 03 10:42:39 AM UTC 24
Peak memory 468076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609955139 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.609955139 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.942907559
Short name T228
Test name
Test status
Simulation time 568518939 ps
CPU time 9.27 seconds
Started Oct 03 10:36:41 AM UTC 24
Finished Oct 03 10:36:51 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942907559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.942907559 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.2000500057
Short name T368
Test name
Test status
Simulation time 71027330246 ps
CPU time 801.69 seconds
Started Oct 03 10:38:00 AM UTC 24
Finished Oct 03 10:51:32 AM UTC 24
Peak memory 480348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000500057 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2000500057 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest
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