Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43513152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

50549329

1

T1

542

T2

435

T3

129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51146036	1			T1	501		T2	309		T3	58
values[0x0]	20775942	1			T1	215		T2	155		T3	46
values[0x1]	22140503	1			T1	243		T2	131		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33793021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60269460

1

T1

647

T2

477

T3

131

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	599217	1			T4	3		T11	25		T12	58
valid_sources[0x01]	329018	1			T4	2		T12	61		T13	3
valid_sources[0x02]	277645	1			T3	1		T4	3		T11	8
valid_sources[0x03]	349260	1			T4	1		T11	32		T12	68
valid_sources[0x04]	488369	1			T1	20		T11	14		T12	71
valid_sources[0x05]	273837	1			T4	5		T11	3		T12	72
valid_sources[0x06]	280315	1			T4	1		T11	31		T12	69
valid_sources[0x07]	420807	1			T3	11		T4	1		T12	52
valid_sources[0x08]	295484	1			T1	1		T4	7		T11	21
valid_sources[0x09]	275366	1			T11	12		T12	72		T13	50
valid_sources[0x0a]	275865	1			T4	1		T11	14		T12	64
valid_sources[0x0b]	273914	1			T4	3		T11	8		T12	62
valid_sources[0x0c]	278964	1			T4	2		T11	9		T12	72
valid_sources[0x0d]	282111	1			T4	3		T11	12		T12	53
valid_sources[0x0e]	851637	1			T1	13		T4	3		T11	9
valid_sources[0x0f]	1476481	1			T3	3		T11	6		T12	65
valid_sources[0x10]	273336	1			T4	7		T11	6		T12	65
valid_sources[0x11]	355468	1			T4	9		T11	24		T12	60
valid_sources[0x12]	276824	1			T1	3		T4	4		T11	35
valid_sources[0x13]	296140	1			T4	2		T11	42		T12	66
valid_sources[0x14]	275394	1			T11	6		T12	84		T14	77
valid_sources[0x15]	271912	1			T4	2		T11	12		T12	66
valid_sources[0x16]	273056	1			T12	81		T13	4		T14	72
valid_sources[0x17]	335240	1			T3	1		T4	1		T12	50
valid_sources[0x18]	1142511	1			T4	3		T11	15		T12	66
valid_sources[0x19]	273413	1			T1	8		T3	3		T4	2
valid_sources[0x1a]	274332	1			T4	2		T11	2		T12	59
valid_sources[0x1b]	269338	1			T11	19		T12	55		T13	21
valid_sources[0x1c]	727136	1			T4	5		T11	10		T12	70
valid_sources[0x1d]	279354	1			T4	4		T12	85		T13	1
valid_sources[0x1e]	359296	1			T4	2		T11	4		T12	68
valid_sources[0x1f]	389420	1			T1	11		T12	72		T13	85
valid_sources[0x20]	274031	1			T4	3		T12	67		T14	113
valid_sources[0x21]	273861	1			T4	4		T12	61		T13	16
valid_sources[0x22]	307891	1			T11	5		T12	56		T13	6
valid_sources[0x23]	887677	1			T4	4		T11	34		T12	68
valid_sources[0x24]	273935	1			T4	4		T11	6		T12	50
valid_sources[0x25]	303056	1			T1	17		T3	6		T4	4
valid_sources[0x26]	278845	1			T4	2		T11	4		T12	70
valid_sources[0x27]	275346	1			T4	3		T11	24		T12	62
valid_sources[0x28]	280509	1			T11	34		T12	66		T13	2
valid_sources[0x29]	275284	1			T4	6		T11	17		T12	72
valid_sources[0x2a]	274654	1			T4	4		T11	8		T12	49
valid_sources[0x2b]	327881	1			T4	2		T11	2		T12	48
valid_sources[0x2c]	273877	1			T1	6		T4	1		T11	12
valid_sources[0x2d]	284648	1			T11	11		T12	69		T13	2
valid_sources[0x2e]	1147646	1			T4	3		T12	58		T13	57
valid_sources[0x2f]	274934	1			T4	1		T11	29		T12	68
valid_sources[0x30]	323520	1			T1	33		T3	3		T4	7
valid_sources[0x31]	273539	1			T4	5		T11	10		T12	92
valid_sources[0x32]	275501	1			T4	6		T11	35		T12	54
valid_sources[0x33]	273316	1			T4	3		T11	26		T12	52
valid_sources[0x34]	272962	1			T4	5		T11	32		T12	70
valid_sources[0x35]	275570	1			T11	11		T12	80		T14	95
valid_sources[0x36]	398878	1			T4	1		T12	56		T13	1
valid_sources[0x37]	273914	1			T4	1		T11	8		T12	66
valid_sources[0x38]	277116	1			T4	3		T11	2		T12	67
valid_sources[0x39]	275539	1			T4	5		T11	1		T12	63
valid_sources[0x3a]	289442	1			T4	3		T12	60		T13	11
valid_sources[0x3b]	273309	1			T4	1		T11	16		T12	84
valid_sources[0x3c]	274303	1			T2	595		T3	2		T11	13
valid_sources[0x3d]	278044	1			T4	1		T12	57		T13	1
valid_sources[0x3e]	276041	1			T1	19		T12	64		T13	45
valid_sources[0x3f]	312172	1			T4	1		T11	24		T12	69
valid_sources[0x40]	294219	1			T4	7		T11	3		T12	55
valid_sources[0x41]	303485	1			T4	5		T12	66		T13	1
valid_sources[0x42]	275226	1			T4	1		T11	2		T12	67
valid_sources[0x43]	275268	1			T1	12		T4	3		T12	56
valid_sources[0x44]	274142	1			T1	21		T4	3		T11	19
valid_sources[0x45]	279058	1			T4	1		T11	7		T12	64
valid_sources[0x46]	279939	1			T4	3		T11	20		T12	87
valid_sources[0x47]	275672	1			T11	14		T12	51		T13	2
valid_sources[0x48]	282527	1			T4	4		T11	7		T12	80
valid_sources[0x49]	274902	1			T4	4		T11	28		T12	61
valid_sources[0x4a]	273244	1			T11	26		T12	70		T13	3
valid_sources[0x4b]	274540	1			T11	21		T12	55		T14	100
valid_sources[0x4c]	356064	1			T11	14		T12	72		T13	1
valid_sources[0x4d]	272417	1			T1	2		T4	1		T11	4
valid_sources[0x4e]	291382	1			T4	2		T11	1		T12	60
valid_sources[0x4f]	274726	1			T4	1		T11	5		T12	74
valid_sources[0x50]	344168	1			T11	1		T12	61		T13	31
valid_sources[0x51]	306912	1			T1	13		T3	4		T4	3
valid_sources[0x52]	274745	1			T4	2		T11	18		T12	68
valid_sources[0x53]	283078	1			T1	10		T4	4		T11	4
valid_sources[0x54]	275736	1			T4	4		T11	27		T12	54
valid_sources[0x55]	274843	1			T1	2		T3	9		T4	1
valid_sources[0x56]	271204	1			T3	2		T4	2		T11	7
valid_sources[0x57]	276172	1			T4	2		T11	7		T12	66
valid_sources[0x58]	274850	1			T12	85		T13	13		T14	111
valid_sources[0x59]	275989	1			T1	14		T4	4		T11	40
valid_sources[0x5a]	272814	1			T4	3		T11	4		T12	71
valid_sources[0x5b]	277926	1			T1	89		T4	1		T12	56
valid_sources[0x5c]	276009	1			T4	1		T11	5		T12	61
valid_sources[0x5d]	641422	1			T4	5		T11	21		T12	75
valid_sources[0x5e]	270913	1			T4	4		T11	33		T12	86
valid_sources[0x5f]	873645	1			T3	2		T4	1		T11	22
valid_sources[0x60]	275878	1			T11	11		T12	49		T13	21
valid_sources[0x61]	292968	1			T4	8		T12	59		T13	3
valid_sources[0x62]	714618	1			T11	25		T12	53		T13	86
valid_sources[0x63]	1011602	1			T1	19		T3	8		T4	1
valid_sources[0x64]	350941	1			T11	2		T12	57		T13	108
valid_sources[0x65]	276905	1			T12	68		T13	27		T14	99
valid_sources[0x66]	432252	1			T4	3		T11	1		T12	83
valid_sources[0x67]	276676	1			T11	11		T12	63		T13	164
valid_sources[0x68]	338075	1			T1	13		T4	3		T11	5
valid_sources[0x69]	440385	1			T4	3		T11	5		T12	56
valid_sources[0x6a]	273802	1			T1	7		T11	23		T12	63
valid_sources[0x6b]	378177	1			T4	1		T11	59		T12	72
valid_sources[0x6c]	286279	1			T4	2		T12	50		T13	5
valid_sources[0x6d]	2013130	1			T3	3		T4	1		T12	53
valid_sources[0x6e]	274178	1			T4	1		T11	32		T12	68
valid_sources[0x6f]	275752	1			T4	2		T11	10		T12	60
valid_sources[0x70]	274729	1			T4	1		T11	13		T12	76
valid_sources[0x71]	280880	1			T3	1		T4	2		T12	66
valid_sources[0x72]	270943	1			T1	74		T11	10		T12	43
valid_sources[0x73]	279732	1			T11	16		T12	59		T13	26
valid_sources[0x74]	345867	1			T4	2		T12	60		T13	2
valid_sources[0x75]	275370	1			T4	2		T12	71		T13	68
valid_sources[0x76]	297852	1			T1	6		T3	2		T4	1
valid_sources[0x77]	278236	1			T11	20		T12	45		T13	1
valid_sources[0x78]	276341	1			T3	3		T4	2		T11	11
valid_sources[0x79]	277117	1			T4	1		T11	39		T12	81
valid_sources[0x7a]	372389	1			T1	6		T4	4		T11	17
valid_sources[0x7b]	526543	1			T3	1		T4	1		T11	11
valid_sources[0x7c]	275070	1			T4	2		T11	12		T12	60
valid_sources[0x7d]	273411	1			T11	3		T12	84		T13	40
valid_sources[0x7e]	414691	1			T1	29		T4	1		T11	18
valid_sources[0x7f]	1491988	1			T4	3		T11	7		T12	71
valid_sources[0x80]	456253	1			T1	9		T4	2		T11	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24470696

1

T1

286

T2

212

T3

54

values[0x0]

all_enables

biggest_size

13751161

1

T1

129

T2

130

T3

44

values[0x1]

all_enables

biggest_size

12327472

1

T1

127

T2

93

T3

31