Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43563021

1

T1

417

T2

160

T3

8

full_word

50552410

1

T1

542

T2

435

T3

129

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	94115141	1			T1	959		T2	595		T3	137
auto[TlIntgErrCmd]	98	1			T112	2		T113	3		T114	1
auto[TlIntgErrData]	96	1			T112	5		T113	4		T114	6
auto[TlIntgErrBoth]	96	1			T112	3		T113	3		T114	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51156991

1

T1

501

T2

309

T3

58

auto[1]

42958440

1

T1

458

T2

286

T3

79

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26685300	1			T1	215		T2	97		T3	4
auto[TlIntgErrNone]	partial	auto[1]	16877454	1			T1	202		T2	63		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	24471555	1			T1	286		T2	212		T3	54
auto[TlIntgErrNone]	full_word	auto[1]	26080832	1			T1	256		T2	223		T3	75
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T172	1		T173	1		T174	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T112	2		T113	2		T114	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T113	1		T175	1		T176	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T172	1		T177	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T112	4		T113	2		T114	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T112	1		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T113	1		T174	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T114	2		T172	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T112	2		T113	1		T114	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T112	1		T113	2		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T174	1		T180	1		T175	1