Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588263242	54205423	0	0
DataKnown_AKnownEnable	588263242	588068879	0	0
DepthKnown_A	588263242	588068879	0	0
RvalidKnown_A	588263242	588068879	0	0
WreadyKnown_A	588263242	588068879	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	54205423	0	0
T1	3191	619	0	0
T2	2553	363	0	0
T3	3118	84	0	0
T4	75687	575	0	0
T11	95001	554	0	0
T12	47249	7006	0	0
T13	95132	4080	0	0
T14	61890	11873	0	0
T15	138198	6082	0	0
T18	1056	7	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	884	884	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588263242	110095065	0	0
DataKnown_AKnownEnable	588263242	588068879	0	0
DepthKnown_A	588263242	588068879	0	0
RvalidKnown_A	588263242	588068879	0	0
WreadyKnown_A	588263242	588068879	0	0
gen_passthru_fifo.paramCheckPass	884	884	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	110095065	0	0
T1	3191	619	0	0
T2	2553	363	0	0
T3	3118	412	0	0
T4	75687	575	0	0
T11	95001	554	0	0
T12	47249	7006	0	0
T13	95132	18875	0	0
T14	61890	11873	0	0
T15	138198	27849	0	0
T18	1056	7	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	588068879	0	0
T1	3191	3109	0	0
T2	2553	2484	0	0
T3	3118	2970	0	0
T4	75687	75626	0	0
T11	95001	94910	0	0
T12	47249	47176	0	0
T13	95132	95061	0	0
T14	61890	61794	0	0
T15	138198	138099	0	0
T18	1056	979	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	884	884	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0