Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	588263242	8603	0	0
entropy_period_rd_A	588263242	1248	0	0
intr_enable_rd_A	588263242	1889	0	0
prefix_0_rd_A	588263242	1338	0	0
prefix_10_rd_A	588263242	1537	0	0
prefix_1_rd_A	588263242	1273	0	0
prefix_2_rd_A	588263242	1250	0	0
prefix_3_rd_A	588263242	1304	0	0
prefix_4_rd_A	588263242	1355	0	0
prefix_5_rd_A	588263242	1182	0	0
prefix_6_rd_A	588263242	1340	0	0
prefix_7_rd_A	588263242	1285	0	0
prefix_8_rd_A	588263242	1304	0	0
prefix_9_rd_A	588263242	1295	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	8603	0	0
T24	826729	0	0	0
T35	83463	920	0	0
T36	717801	0	0	0
T41	43321	0	0	0
T58	0	2306	0	0
T59	0	831	0	0
T66	35549	0	0	0
T93	0	1802	0	0
T114	0	2	0	0
T118	0	131	0	0
T119	0	2	0	0
T120	0	139	0	0
T121	0	5	0	0
T122	0	218	0	0
T124	168653	0	0	0
T125	63436	0	0	0
T126	10431	0	0	0
T127	209047	0	0	0
T128	137546	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1248	0	0
T72	77755	0	0	0
T93	442293	17	0	0
T119	0	7	0	0
T121	0	16	0	0
T123	0	24	0	0
T143	0	21	0	0
T144	0	7	0	0
T145	0	9	0	0
T146	0	35	0	0
T147	0	115	0	0
T148	0	18	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1889	0	0
T72	77755	0	0	0
T93	442293	17	0	0
T115	0	19	0	0
T119	0	10	0	0
T121	0	17	0	0
T123	0	45	0	0
T143	0	25	0	0
T144	0	17	0	0
T145	0	4	0	0
T146	0	7	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0
T157	0	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1338	0	0
T72	77755	0	0	0
T93	442293	10	0	0
T118	0	2	0	0
T119	0	11	0	0
T121	0	19	0	0
T123	0	19	0	0
T143	0	23	0	0
T144	0	3	0	0
T146	0	17	0	0
T147	0	105	0	0
T148	0	19	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1537	0	0
T72	77755	0	0	0
T93	442293	19	0	0
T119	0	8	0	0
T121	0	18	0	0
T123	0	17	0	0
T143	0	77	0	0
T144	0	9	0	0
T145	0	6	0	0
T146	0	24	0	0
T147	0	203	0	0
T148	0	12	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1273	0	0
T72	77755	0	0	0
T93	442293	11	0	0
T119	0	11	0	0
T121	0	23	0	0
T123	0	7	0	0
T143	0	19	0	0
T144	0	7	0	0
T145	0	4	0	0
T146	0	17	0	0
T147	0	141	0	0
T148	0	17	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1250	0	0
T72	77755	0	0	0
T93	442293	20	0	0
T118	0	2	0	0
T121	0	15	0	0
T123	0	15	0	0
T143	0	17	0	0
T144	0	2	0	0
T145	0	7	0	0
T146	0	29	0	0
T147	0	129	0	0
T148	0	12	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1304	0	0
T72	77755	0	0	0
T93	442293	14	0	0
T119	0	13	0	0
T121	0	23	0	0
T123	0	23	0	0
T143	0	16	0	0
T144	0	7	0	0
T145	0	1	0	0
T146	0	39	0	0
T147	0	105	0	0
T148	0	15	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1355	0	0
T72	77755	0	0	0
T93	442293	11	0	0
T119	0	7	0	0
T121	0	17	0	0
T123	0	18	0	0
T143	0	66	0	0
T144	0	5	0	0
T145	0	9	0	0
T146	0	9	0	0
T147	0	106	0	0
T148	0	16	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1182	0	0
T72	77755	0	0	0
T93	442293	12	0	0
T101	0	11	0	0
T121	0	21	0	0
T123	0	21	0	0
T143	0	26	0	0
T144	0	3	0	0
T145	0	8	0	0
T146	0	21	0	0
T147	0	128	0	0
T148	0	3	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1340	0	0
T72	77755	0	0	0
T93	442293	30	0	0
T119	0	4	0	0
T121	0	9	0	0
T123	0	4	0	0
T143	0	13	0	0
T144	0	5	0	0
T145	0	2	0	0
T146	0	40	0	0
T147	0	77	0	0
T148	0	13	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1285	0	0
T72	77755	0	0	0
T93	442293	30	0	0
T119	0	12	0	0
T121	0	16	0	0
T123	0	19	0	0
T143	0	24	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	15	0	0
T147	0	102	0	0
T148	0	22	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1304	0	0
T72	77755	0	0	0
T93	442293	17	0	0
T119	0	7	0	0
T121	0	12	0	0
T123	0	13	0	0
T143	0	25	0	0
T144	0	5	0	0
T145	0	3	0	0
T146	0	52	0	0
T147	0	133	0	0
T148	0	10	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588263242	1295	0	0
T72	77755	0	0	0
T93	442293	12	0	0
T119	0	10	0	0
T121	0	17	0	0
T123	0	14	0	0
T143	0	42	0	0
T144	0	1	0	0
T145	0	6	0	0
T146	0	22	0	0
T147	0	101	0	0
T148	0	14	0	0
T149	93933	0	0	0
T150	55096	0	0	0
T151	232255	0	0	0
T152	402515	0	0	0
T153	600110	0	0	0
T154	1600	0	0	0
T155	145468	0	0	0
T156	1362	0	0	0