Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15111589	1			T1	1		T2	87		T3	88
all_values[1]	15111589	1			T1	1		T2	87		T3	88
all_values[2]	15111589	1			T1	1		T2	87		T3	88

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

573197

1

T2

16

T3

12

T14

195

auto[1]

44761570

1

T1

3

T2

245

T3

252

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45119451

1

T1

3

T2

249

T3

249

auto[1]

215316

1

T2

12

T3

15

T14

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	173997	1			T3	8		T16	9		T17	9
all_values[0]	auto[0]	auto[1]	1329	1			T3	4		T16	10		T17	4
all_values[0]	auto[1]	auto[0]	14865820	1			T1	1		T2	83		T3	75
all_values[0]	auto[1]	auto[1]	70443	1			T2	4		T3	1		T14	6
all_values[1]	auto[0]	auto[0]	196092	1			T2	7		T14	194		T18	437
all_values[1]	auto[0]	auto[1]	1060	1			T2	1		T14	1		T18	2
all_values[1]	auto[1]	auto[0]	14843725	1			T1	1		T2	76		T3	83
all_values[1]	auto[1]	auto[1]	70712	1			T2	3		T3	5		T14	5
all_values[2]	auto[0]	auto[0]	199674	1			T2	7		T17	9		T18	85
all_values[2]	auto[0]	auto[1]	1045	1			T2	1		T17	4		T77	2
all_values[2]	auto[1]	auto[0]	14840143	1			T1	1		T2	76		T3	83
all_values[2]	auto[1]	auto[1]	70727	1			T2	3		T3	5		T14	6