Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53376 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
57238 |
1 |
|
|
T1 |
10 |
|
T3 |
4 |
|
T15 |
36 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27857 |
1 |
|
|
T2 |
4 |
|
T15 |
13 |
|
T16 |
62 |
lower_val |
27123 |
1 |
|
|
T1 |
7 |
|
T3 |
2 |
|
T4 |
1 |
zero_val |
924 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
55064 |
1 |
|
|
T1 |
6 |
|
T2 |
6 |
|
T3 |
6 |
lower_val |
55548 |
1 |
|
|
T1 |
6 |
|
T4 |
2 |
|
T14 |
6 |
zero_val |
2 |
1 |
|
|
T156 |
2 |
|
- |
- |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6748 |
1 |
|
|
T2 |
4 |
|
T16 |
33 |
|
T17 |
2 |
higher_val |
higher_val |
auto[1] |
7200 |
1 |
|
|
T15 |
6 |
|
T64 |
28 |
|
T92 |
37 |
higher_val |
lower_val |
auto[0] |
6651 |
1 |
|
|
T16 |
29 |
|
T17 |
1 |
|
T18 |
1 |
higher_val |
lower_val |
auto[1] |
7258 |
1 |
|
|
T15 |
7 |
|
T18 |
3 |
|
T64 |
14 |
lower_val |
higher_val |
auto[0] |
6475 |
1 |
|
|
T16 |
26 |
|
T17 |
1 |
|
T65 |
40 |
lower_val |
higher_val |
auto[1] |
7036 |
1 |
|
|
T1 |
3 |
|
T3 |
2 |
|
T15 |
6 |
lower_val |
lower_val |
auto[0] |
6523 |
1 |
|
|
T4 |
1 |
|
T14 |
2 |
|
T16 |
33 |
lower_val |
lower_val |
auto[1] |
7087 |
1 |
|
|
T1 |
4 |
|
T15 |
2 |
|
T64 |
17 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T156 |
2 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
361 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
86 |
1 |
|
|
T50 |
1 |
|
T87 |
1 |
|
T135 |
2 |
zero_val |
lower_val |
auto[0] |
388 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T18 |
2 |
zero_val |
lower_val |
auto[1] |
89 |
1 |
|
|
T18 |
1 |
|
T44 |
3 |
|
T50 |
4 |