Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	292	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	2840	1			T80	4		T44	1		T50	3
len_5001_7500	6451	1			T80	12		T50	7		T51	36
len_2501_5000	1550	1			T80	1		T50	2		T51	4
len_1025_2500	951	1			T50	1		T51	1		T52	7
len_769_1024	5098	1			T14	1		T18	1		T23	6
len_513_768	5711	1			T14	2		T23	7		T24	1
len_257_512	5858	1			T14	1		T18	1		T23	7
len_0_256	19082	1			T2	3		T3	3		T16	105
len_keccak_block_sizes[72]	40	1			T16	1		T92	1		T93	1
len_keccak_block_sizes[104]	37	1			T16	1		T92	1		T93	1
len_keccak_block_sizes[136]	32	1			T92	1		T93	1		T94	1
len_keccak_block_sizes[144]	35	1			T92	1		T142	1		T85	1
len_keccak_block_sizes[168]	25	1			T85	1		T181	1		T182	1
len_1	66	1			T16	1		T64	1		T92	1
len_0	487	1			T16	1		T64	3		T65	4