Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
| | | | | | | | | | | | |
auto[0] |
6216444 |
1 |
|
|
T1 |
228 |
|
T2 |
24 |
|
T3 |
24 |
auto[1] |
9517085 |
1 |
|
|
T1 |
228 |
|
T2 |
150 |
|
T3 |
150 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
| | | | | | | | | | | | |
word_access |
15701666 |
1 |
|
|
T1 |
456 |
|
T2 |
174 |
|
T3 |
174 |
triple_byte_access |
10642 |
1 |
|
|
T14 |
2 |
|
T18 |
1 |
|
T64 |
30 |
halfword_access |
10495 |
1 |
|
|
T64 |
17 |
|
T65 |
39 |
|
T80 |
4 |
byte_access |
10726 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T64 |
20 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
| | | | | | | | | | | | | |
auto[0] |
word_access |
6184581 |
1 |
|
|
T1 |
228 |
|
T2 |
24 |
|
T3 |
24 |
auto[0] |
triple_byte_access |
10642 |
1 |
|
|
T14 |
2 |
|
T18 |
1 |
|
T64 |
30 |
auto[0] |
halfword_access |
10495 |
1 |
|
|
T64 |
17 |
|
T65 |
39 |
|
T80 |
4 |
auto[0] |
byte_access |
10726 |
1 |
|
|
T14 |
1 |
|
T18 |
1 |
|
T64 |
20 |
auto[1] |
word_access |
9517085 |
1 |
|
|
T1 |
228 |
|
T2 |
150 |
|
T3 |
150 |