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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.05 96.19 92.52 100.00 72.73 94.61 99.03 96.29


Total test records in report: 921
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T779 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2132928169 Oct 12 02:32:42 AM UTC 24 Oct 12 02:32:47 AM UTC 24 148164642 ps
T780 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.3688568899 Oct 12 02:32:42 AM UTC 24 Oct 12 02:32:47 AM UTC 24 1095626761 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.310359071 Oct 12 02:32:46 AM UTC 24 Oct 12 02:32:49 AM UTC 24 217708999 ps
T781 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.2877188147 Oct 12 02:32:47 AM UTC 24 Oct 12 02:32:49 AM UTC 24 31812590 ps
T782 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2712243810 Oct 12 02:32:39 AM UTC 24 Oct 12 02:32:49 AM UTC 24 509967735 ps
T783 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.33517455 Oct 12 02:32:46 AM UTC 24 Oct 12 02:32:50 AM UTC 24 146669223 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.768523120 Oct 12 02:32:47 AM UTC 24 Oct 12 02:32:50 AM UTC 24 23313860 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2245280313 Oct 12 02:32:46 AM UTC 24 Oct 12 02:32:50 AM UTC 24 1259871456 ps
T784 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.931539645 Oct 12 02:32:47 AM UTC 24 Oct 12 02:32:50 AM UTC 24 75588674 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.3199313919 Oct 12 02:32:48 AM UTC 24 Oct 12 02:32:50 AM UTC 24 11705568 ps
T785 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1785070522 Oct 12 02:32:46 AM UTC 24 Oct 12 02:32:51 AM UTC 24 760984294 ps
T786 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2885531607 Oct 12 02:32:48 AM UTC 24 Oct 12 02:32:51 AM UTC 24 87956461 ps
T787 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2014173309 Oct 12 02:32:49 AM UTC 24 Oct 12 02:32:51 AM UTC 24 13084670 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.183487779 Oct 12 02:32:47 AM UTC 24 Oct 12 02:32:52 AM UTC 24 81464396 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3396544522 Oct 12 02:32:40 AM UTC 24 Oct 12 02:32:53 AM UTC 24 2548761233 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2154350590 Oct 12 02:32:45 AM UTC 24 Oct 12 02:32:53 AM UTC 24 3220350865 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1764633583 Oct 12 02:32:51 AM UTC 24 Oct 12 02:32:54 AM UTC 24 164288422 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4160984169 Oct 12 02:32:52 AM UTC 24 Oct 12 02:32:54 AM UTC 24 16533000 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.116977867 Oct 12 02:32:52 AM UTC 24 Oct 12 02:32:54 AM UTC 24 18674335 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.118594835 Oct 12 02:32:52 AM UTC 24 Oct 12 02:32:54 AM UTC 24 89881275 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3090696199 Oct 12 02:32:51 AM UTC 24 Oct 12 02:32:55 AM UTC 24 158968953 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1715243300 Oct 12 02:32:52 AM UTC 24 Oct 12 02:32:55 AM UTC 24 106797742 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3956435688 Oct 12 02:32:53 AM UTC 24 Oct 12 02:32:56 AM UTC 24 95349027 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.4194731200 Oct 12 02:32:52 AM UTC 24 Oct 12 02:32:56 AM UTC 24 420053356 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1979445361 Oct 12 02:32:52 AM UTC 24 Oct 12 02:32:57 AM UTC 24 452561505 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3240194978 Oct 12 02:32:53 AM UTC 24 Oct 12 02:32:57 AM UTC 24 72213039 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3751739051 Oct 12 02:32:52 AM UTC 24 Oct 12 02:32:57 AM UTC 24 111036121 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.495258863 Oct 12 02:32:54 AM UTC 24 Oct 12 02:32:58 AM UTC 24 80132149 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3770621345 Oct 12 02:32:56 AM UTC 24 Oct 12 02:32:58 AM UTC 24 33827021 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.732671675 Oct 12 02:32:56 AM UTC 24 Oct 12 02:32:58 AM UTC 24 22241194 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.9684730 Oct 12 02:32:56 AM UTC 24 Oct 12 02:32:59 AM UTC 24 59743636 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1086873140 Oct 12 02:32:56 AM UTC 24 Oct 12 02:32:59 AM UTC 24 96579836 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2839325945 Oct 12 02:32:56 AM UTC 24 Oct 12 02:32:59 AM UTC 24 42580813 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2173813205 Oct 12 02:32:45 AM UTC 24 Oct 12 02:32:59 AM UTC 24 642496230 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.2737312096 Oct 12 02:32:57 AM UTC 24 Oct 12 02:32:59 AM UTC 24 16976146 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.4139614955 Oct 12 02:32:56 AM UTC 24 Oct 12 02:32:59 AM UTC 24 109365355 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1532030148 Oct 12 02:32:54 AM UTC 24 Oct 12 02:33:00 AM UTC 24 786085691 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3126230605 Oct 12 02:32:57 AM UTC 24 Oct 12 02:33:00 AM UTC 24 30269307 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.3632623013 Oct 12 02:32:56 AM UTC 24 Oct 12 02:33:00 AM UTC 24 132527370 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.2079742259 Oct 12 02:32:56 AM UTC 24 Oct 12 02:33:01 AM UTC 24 382085758 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1227198272 Oct 12 02:32:59 AM UTC 24 Oct 12 02:33:02 AM UTC 24 35129987 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.4056871282 Oct 12 02:32:58 AM UTC 24 Oct 12 02:33:02 AM UTC 24 119592535 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.255036355 Oct 12 02:33:14 AM UTC 24 Oct 12 02:33:17 AM UTC 24 31072109 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2963989099 Oct 12 02:32:57 AM UTC 24 Oct 12 02:33:02 AM UTC 24 592098510 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1048515868 Oct 12 02:32:50 AM UTC 24 Oct 12 02:33:02 AM UTC 24 401268751 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1515119552 Oct 12 02:33:00 AM UTC 24 Oct 12 02:33:02 AM UTC 24 70381686 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.107549027 Oct 12 02:32:58 AM UTC 24 Oct 12 02:33:02 AM UTC 24 325564154 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.4283883658 Oct 12 02:33:00 AM UTC 24 Oct 12 02:33:02 AM UTC 24 64276041 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.4182516300 Oct 12 02:32:59 AM UTC 24 Oct 12 02:33:02 AM UTC 24 101387620 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2912732974 Oct 12 02:33:00 AM UTC 24 Oct 12 02:33:03 AM UTC 24 54325883 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2861068386 Oct 12 02:33:00 AM UTC 24 Oct 12 02:33:03 AM UTC 24 77450326 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1756853892 Oct 12 02:33:00 AM UTC 24 Oct 12 02:33:03 AM UTC 24 48180550 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.79474866 Oct 12 02:33:00 AM UTC 24 Oct 12 02:33:03 AM UTC 24 36687284 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.268216630 Oct 12 02:33:01 AM UTC 24 Oct 12 02:33:03 AM UTC 24 57777322 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1848243634 Oct 12 02:33:01 AM UTC 24 Oct 12 02:33:03 AM UTC 24 15981956 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4110173675 Oct 12 02:32:59 AM UTC 24 Oct 12 02:33:04 AM UTC 24 207942849 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2789865046 Oct 12 02:33:01 AM UTC 24 Oct 12 02:33:05 AM UTC 24 244401871 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3918218712 Oct 12 02:32:50 AM UTC 24 Oct 12 02:33:05 AM UTC 24 293989032 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3580610241 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:05 AM UTC 24 13868393 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.23110880 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:05 AM UTC 24 33700967 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.729803076 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:05 AM UTC 24 40511999 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3144905962 Oct 12 02:33:01 AM UTC 24 Oct 12 02:33:05 AM UTC 24 151157583 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1438426815 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:06 AM UTC 24 47489426 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.529219759 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:06 AM UTC 24 44387163 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4024299621 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:06 AM UTC 24 65832044 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3292918627 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:06 AM UTC 24 220792420 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3983201783 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:06 AM UTC 24 235147768 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3260318739 Oct 12 02:33:04 AM UTC 24 Oct 12 02:33:06 AM UTC 24 24049481 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.710401558 Oct 12 02:33:00 AM UTC 24 Oct 12 02:33:07 AM UTC 24 2481280745 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3525363604 Oct 12 02:33:04 AM UTC 24 Oct 12 02:33:07 AM UTC 24 76436921 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.622026538 Oct 12 02:33:04 AM UTC 24 Oct 12 02:33:07 AM UTC 24 52204810 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3860037355 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:07 AM UTC 24 70752184 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3732728950 Oct 12 02:33:04 AM UTC 24 Oct 12 02:33:07 AM UTC 24 61325034 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.4240431885 Oct 12 02:33:03 AM UTC 24 Oct 12 02:33:08 AM UTC 24 52158563 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1688165495 Oct 12 02:33:06 AM UTC 24 Oct 12 02:33:08 AM UTC 24 47607321 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.275563232 Oct 12 02:33:05 AM UTC 24 Oct 12 02:33:08 AM UTC 24 72019451 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2726731830 Oct 12 02:33:06 AM UTC 24 Oct 12 02:33:08 AM UTC 24 60384210 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3817474263 Oct 12 02:33:05 AM UTC 24 Oct 12 02:33:08 AM UTC 24 66918032 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2331908655 Oct 12 02:33:06 AM UTC 24 Oct 12 02:33:08 AM UTC 24 45095056 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.4081241482 Oct 12 02:33:04 AM UTC 24 Oct 12 02:33:08 AM UTC 24 662153232 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.98364134 Oct 12 02:33:06 AM UTC 24 Oct 12 02:33:09 AM UTC 24 53368031 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.340021765 Oct 12 02:33:04 AM UTC 24 Oct 12 02:33:09 AM UTC 24 151602229 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2336273244 Oct 12 02:33:07 AM UTC 24 Oct 12 02:33:10 AM UTC 24 212839947 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1643701203 Oct 12 02:33:07 AM UTC 24 Oct 12 02:33:10 AM UTC 24 895374915 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2409440182 Oct 12 02:33:07 AM UTC 24 Oct 12 02:33:10 AM UTC 24 151074424 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2420963675 Oct 12 02:33:07 AM UTC 24 Oct 12 02:33:10 AM UTC 24 209485268 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2574952414 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:15 AM UTC 24 18163479 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2506966988 Oct 12 02:33:12 AM UTC 24 Oct 12 02:33:16 AM UTC 24 60901470 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.2410321662 Oct 12 02:33:14 AM UTC 24 Oct 12 02:33:16 AM UTC 24 23231588 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.872204622 Oct 12 02:33:08 AM UTC 24 Oct 12 02:33:10 AM UTC 24 92854806 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.894494509 Oct 12 02:33:09 AM UTC 24 Oct 12 02:33:11 AM UTC 24 16632628 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3433836670 Oct 12 02:33:08 AM UTC 24 Oct 12 02:33:11 AM UTC 24 56235375 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.4244975898 Oct 12 02:33:06 AM UTC 24 Oct 12 02:33:11 AM UTC 24 618276638 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3292557661 Oct 12 02:33:07 AM UTC 24 Oct 12 02:33:11 AM UTC 24 263688449 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.97223409 Oct 12 02:33:09 AM UTC 24 Oct 12 02:33:11 AM UTC 24 48521277 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2593858961 Oct 12 02:33:08 AM UTC 24 Oct 12 02:33:11 AM UTC 24 193218769 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.226410180 Oct 12 02:33:07 AM UTC 24 Oct 12 02:33:11 AM UTC 24 350020995 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.427855731 Oct 12 02:33:08 AM UTC 24 Oct 12 02:33:11 AM UTC 24 97793596 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.125922028 Oct 12 02:33:08 AM UTC 24 Oct 12 02:33:11 AM UTC 24 44853426 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2945278380 Oct 12 02:33:06 AM UTC 24 Oct 12 02:33:12 AM UTC 24 258441436 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.295776856 Oct 12 02:33:08 AM UTC 24 Oct 12 02:33:12 AM UTC 24 50000305 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1412070231 Oct 12 02:33:10 AM UTC 24 Oct 12 02:33:12 AM UTC 24 103088281 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1842398372 Oct 12 02:33:10 AM UTC 24 Oct 12 02:33:13 AM UTC 24 59635293 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1272216822 Oct 12 02:33:09 AM UTC 24 Oct 12 02:33:13 AM UTC 24 121819185 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.175973332 Oct 12 02:33:11 AM UTC 24 Oct 12 02:33:13 AM UTC 24 11180956 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2450553181 Oct 12 02:33:10 AM UTC 24 Oct 12 02:33:13 AM UTC 24 117464946 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4253508931 Oct 12 02:33:11 AM UTC 24 Oct 12 02:33:14 AM UTC 24 30891846 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3776466337 Oct 12 02:33:11 AM UTC 24 Oct 12 02:33:14 AM UTC 24 103515880 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1296953183 Oct 12 02:33:09 AM UTC 24 Oct 12 02:33:14 AM UTC 24 201128201 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.467715196 Oct 12 02:33:10 AM UTC 24 Oct 12 02:33:14 AM UTC 24 460718609 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1293127351 Oct 12 02:33:10 AM UTC 24 Oct 12 02:33:14 AM UTC 24 264277113 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3899347801 Oct 12 02:33:11 AM UTC 24 Oct 12 02:33:14 AM UTC 24 511558559 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1387698679 Oct 12 02:33:11 AM UTC 24 Oct 12 02:33:14 AM UTC 24 218285335 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2564725810 Oct 12 02:33:11 AM UTC 24 Oct 12 02:33:15 AM UTC 24 40441741 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1976676293 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:15 AM UTC 24 17050072 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.575032672 Oct 12 02:33:12 AM UTC 24 Oct 12 02:33:15 AM UTC 24 12384792 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1404672472 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:15 AM UTC 24 78752467 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2661918579 Oct 12 02:33:11 AM UTC 24 Oct 12 02:33:15 AM UTC 24 256321245 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.4007869311 Oct 12 02:33:10 AM UTC 24 Oct 12 02:33:15 AM UTC 24 677285107 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1462281176 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:16 AM UTC 24 80751930 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1358546548 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:16 AM UTC 24 122383841 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1448087150 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:16 AM UTC 24 73885222 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1882474577 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:16 AM UTC 24 940171721 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.825340293 Oct 12 02:33:13 AM UTC 24 Oct 12 02:33:17 AM UTC 24 403927040 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2075926077 Oct 12 02:33:15 AM UTC 24 Oct 12 02:33:17 AM UTC 24 61688287 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4225004161 Oct 12 02:33:14 AM UTC 24 Oct 12 02:33:17 AM UTC 24 335675856 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3245423407 Oct 12 02:33:15 AM UTC 24 Oct 12 02:33:18 AM UTC 24 17769738 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1177716388 Oct 12 02:33:14 AM UTC 24 Oct 12 02:33:18 AM UTC 24 279791687 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.33163653 Oct 12 02:33:16 AM UTC 24 Oct 12 02:33:18 AM UTC 24 111894880 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.5460649 Oct 12 02:33:15 AM UTC 24 Oct 12 02:33:18 AM UTC 24 46063897 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1365976780 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:19 AM UTC 24 92717744 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3342238282 Oct 12 02:33:15 AM UTC 24 Oct 12 02:33:19 AM UTC 24 102972490 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3789063450 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:19 AM UTC 24 12543994 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.494281089 Oct 12 02:33:16 AM UTC 24 Oct 12 02:33:19 AM UTC 24 80958396 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3594280608 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:19 AM UTC 24 22622457 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2850198415 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:19 AM UTC 24 15407830 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.188469476 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:19 AM UTC 24 55229082 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3691856666 Oct 12 02:33:16 AM UTC 24 Oct 12 02:33:19 AM UTC 24 168682671 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.4107880607 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:19 AM UTC 24 30633223 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2546243949 Oct 12 02:33:15 AM UTC 24 Oct 12 02:33:19 AM UTC 24 92291971 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1309744569 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:19 AM UTC 24 30891172 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4069822704 Oct 12 02:33:15 AM UTC 24 Oct 12 02:33:19 AM UTC 24 196499187 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3897066235 Oct 12 02:33:18 AM UTC 24 Oct 12 02:33:20 AM UTC 24 41508575 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2330551810 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:20 AM UTC 24 181302071 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3794757810 Oct 12 02:33:18 AM UTC 24 Oct 12 02:33:20 AM UTC 24 16790599 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2599868753 Oct 12 02:33:18 AM UTC 24 Oct 12 02:33:20 AM UTC 24 38958731 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1966136848 Oct 12 02:33:18 AM UTC 24 Oct 12 02:33:20 AM UTC 24 46681960 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3030676616 Oct 12 02:33:18 AM UTC 24 Oct 12 02:33:20 AM UTC 24 17838774 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1357878736 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:20 AM UTC 24 37928177 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2585719352 Oct 12 02:33:18 AM UTC 24 Oct 12 02:33:20 AM UTC 24 42265095 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1016520632 Oct 12 02:33:18 AM UTC 24 Oct 12 02:33:21 AM UTC 24 19797059 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.826448342 Oct 12 02:33:17 AM UTC 24 Oct 12 02:33:21 AM UTC 24 344168928 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3920787434 Oct 12 02:33:15 AM UTC 24 Oct 12 02:33:21 AM UTC 24 770531486 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.102109958 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:21 AM UTC 24 36307775 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.787605080 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 12003140 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.1012921739 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 20778957 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1384139021 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 37009780 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3923768389 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 16934578 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2236176874 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 29831381 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3253455485 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 30686743 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.983301089 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 33933968 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1907173560 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 15802020 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2179353195 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 17293595 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.999790540 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 13339854 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2511892709 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 15420223 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3244529366 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 39063345 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1385624248 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 27055746 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.764526025 Oct 12 02:33:20 AM UTC 24 Oct 12 02:33:22 AM UTC 24 27289369 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3471176533 Oct 12 02:33:21 AM UTC 24 Oct 12 02:33:23 AM UTC 24 19461142 ps
T920 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.2045599798 Oct 12 02:33:21 AM UTC 24 Oct 12 02:33:23 AM UTC 24 28517812 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.60067822 Oct 12 02:33:21 AM UTC 24 Oct 12 02:33:23 AM UTC 24 17897015 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload_invalid.2010410316
Short name T15
Test name
Test status
Simulation time 338159331 ps
CPU time 4.18 seconds
Started Oct 12 06:28:58 AM UTC 24
Finished Oct 12 06:29:03 AM UTC 24
Peak memory 231312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010410316 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload_invalid.2010410316 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1507783192
Short name T23
Test name
Test status
Simulation time 5690275619 ps
CPU time 86.5 seconds
Started Oct 12 06:29:28 AM UTC 24
Finished Oct 12 06:30:56 AM UTC 24
Peak memory 290744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507783192 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1507783192 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.397225852
Short name T18
Test name
Test status
Simulation time 1073741888 ps
CPU time 32.73 seconds
Started Oct 12 06:28:48 AM UTC 24
Finished Oct 12 06:29:22 AM UTC 24
Peak memory 252292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=397225852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_w
ith_rand_reset.397225852 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.3520169291
Short name T6
Test name
Test status
Simulation time 14327585819 ps
CPU time 79.94 seconds
Started Oct 12 06:28:51 AM UTC 24
Finished Oct 12 06:30:13 AM UTC 24
Peak memory 275988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520169291 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3520169291 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.1342277788
Short name T129
Test name
Test status
Simulation time 54346023 ps
CPU time 3.3 seconds
Started Oct 12 02:32:22 AM UTC 24
Finished Oct 12 02:32:26 AM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342277788 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.1342277788 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.320854069
Short name T123
Test name
Test status
Simulation time 56346733 ps
CPU time 1.71 seconds
Started Oct 12 06:42:20 AM UTC 24
Finished Oct 12 06:42:23 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320854069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.320854069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.2568828258
Short name T9
Test name
Test status
Simulation time 119523532 ps
CPU time 1.78 seconds
Started Oct 12 07:00:17 AM UTC 24
Finished Oct 12 07:00:20 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568828258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2568828258 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1532030148
Short name T115
Test name
Test status
Simulation time 786085691 ps
CPU time 4.26 seconds
Started Oct 12 02:32:54 AM UTC 24
Finished Oct 12 02:33:00 AM UTC 24
Peak memory 228160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532030148 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.
1532030148 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.3470161305
Short name T16
Test name
Test status
Simulation time 1196449632 ps
CPU time 30.75 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:29:14 AM UTC 24
Peak memory 239344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470161305 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3470161305
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.2639031283
Short name T29
Test name
Test status
Simulation time 10595010033 ps
CPU time 405.09 seconds
Started Oct 12 06:33:12 AM UTC 24
Finished Oct 12 06:40:03 AM UTC 24
Peak memory 524324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639031283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2639031283 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.2912661092
Short name T67
Test name
Test status
Simulation time 2824004991 ps
CPU time 16.17 seconds
Started Oct 12 06:44:45 AM UTC 24
Finished Oct 12 06:45:02 AM UTC 24
Peak memory 251888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912661092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2912661092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.2737312096
Short name T803
Test name
Test status
Simulation time 16976146 ps
CPU time 1.04 seconds
Started Oct 12 02:32:57 AM UTC 24
Finished Oct 12 02:32:59 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737312096 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2737312096 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.727744556
Short name T50
Test name
Test status
Simulation time 4102134431 ps
CPU time 288.85 seconds
Started Oct 12 06:29:48 AM UTC 24
Finished Oct 12 06:34:41 AM UTC 24
Peak memory 315368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=727744556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_w
ith_rand_reset.727744556 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.535775721
Short name T70
Test name
Test status
Simulation time 64247294 ps
CPU time 1.93 seconds
Started Oct 12 07:01:06 AM UTC 24
Finished Oct 12 07:01:10 AM UTC 24
Peak memory 233876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535775721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.535775721 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.833113547
Short name T40
Test name
Test status
Simulation time 37654877710 ps
CPU time 264.37 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:33:12 AM UTC 24
Peak memory 387428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833113547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.833113547 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload_invalid.3280130002
Short name T28
Test name
Test status
Simulation time 173466856 ps
CPU time 3.46 seconds
Started Oct 12 06:39:19 AM UTC 24
Finished Oct 12 06:39:24 AM UTC 24
Peak memory 231368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280130002 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload_invalid.3280130002 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1979445361
Short name T794
Test name
Test status
Simulation time 452561505 ps
CPU time 3.77 seconds
Started Oct 12 02:32:52 AM UTC 24
Finished Oct 12 02:32:57 AM UTC 24
Peak memory 227912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979445361 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.
1979445361 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1194485059
Short name T144
Test name
Test status
Simulation time 79208506 ps
CPU time 1.7 seconds
Started Oct 12 02:32:20 AM UTC 24
Finished Oct 12 02:32:22 AM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194485059 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1194485059 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload_invalid.1672785955
Short name T101
Test name
Test status
Simulation time 249616241 ps
CPU time 6.16 seconds
Started Oct 12 06:48:06 AM UTC 24
Finished Oct 12 06:48:13 AM UTC 24
Peak memory 235828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672785955 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload_invalid.1672785955 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.1331378250
Short name T19
Test name
Test status
Simulation time 79631419 ps
CPU time 1.22 seconds
Started Oct 12 06:28:51 AM UTC 24
Finished Oct 12 06:28:53 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331378250 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1331378250 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.21621408
Short name T65
Test name
Test status
Simulation time 895018613 ps
CPU time 49.44 seconds
Started Oct 12 06:28:53 AM UTC 24
Finished Oct 12 06:29:44 AM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21621408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.21621408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.2462270698
Short name T21
Test name
Test status
Simulation time 15521838074 ps
CPU time 59.68 seconds
Started Oct 12 06:28:45 AM UTC 24
Finished Oct 12 06:29:46 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462270698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2462270698 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.885064963
Short name T169
Test name
Test status
Simulation time 5872870864 ps
CPU time 568.44 seconds
Started Oct 12 06:44:53 AM UTC 24
Finished Oct 12 06:54:29 AM UTC 24
Peak memory 247676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885064963 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.885064963 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3260318739
Short name T160
Test name
Test status
Simulation time 24049481 ps
CPU time 1.04 seconds
Started Oct 12 02:33:04 AM UTC 24
Finished Oct 12 02:33:06 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260318739 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3260318739 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2129484618
Short name T131
Test name
Test status
Simulation time 369484235 ps
CPU time 5.95 seconds
Started Oct 12 02:32:38 AM UTC 24
Finished Oct 12 02:32:45 AM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129484618 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2129484618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.3894209947
Short name T39
Test name
Test status
Simulation time 8166565632 ps
CPU time 278.49 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:33:26 AM UTC 24
Peak memory 464828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894209947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3894209947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.2108768437
Short name T85
Test name
Test status
Simulation time 4251003165 ps
CPU time 135.67 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:31:01 AM UTC 24
Peak memory 286652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108768437 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2108768
437 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.4120767164
Short name T156
Test name
Test status
Simulation time 3829718164 ps
CPU time 87.89 seconds
Started Oct 12 07:12:46 AM UTC 24
Finished Oct 12 07:14:16 AM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120767164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.4120767164 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.622026538
Short name T114
Test name
Test status
Simulation time 52204810 ps
CPU time 1.48 seconds
Started Oct 12 02:33:04 AM UTC 24
Finished Oct 12 02:33:07 AM UTC 24
Peak memory 226180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622026538 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.622026538 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.822481058
Short name T106
Test name
Test status
Simulation time 56224815 ps
CPU time 1.22 seconds
Started Oct 12 02:32:15 AM UTC 24
Finished Oct 12 02:32:18 AM UTC 24
Peak memory 216492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822481058 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.822481058 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.2425334676
Short name T11
Test name
Test status
Simulation time 4455335946 ps
CPU time 36.79 seconds
Started Oct 12 06:31:15 AM UTC 24
Finished Oct 12 06:31:54 AM UTC 24
Peak memory 267708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425334676 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2425334676 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3983201783
Short name T167
Test name
Test status
Simulation time 235147768 ps
CPU time 2.41 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:06 AM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983201783 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3983201783 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2945278380
Short name T177
Test name
Test status
Simulation time 258441436 ps
CPU time 4.9 seconds
Started Oct 12 02:33:06 AM UTC 24
Finished Oct 12 02:33:12 AM UTC 24
Peak memory 217276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945278380 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2945278380 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.226410180
Short name T175
Test name
Test status
Simulation time 350020995 ps
CPU time 2.82 seconds
Started Oct 12 02:33:07 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 227696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226410180 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.226410180 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.1900024753
Short name T12
Test name
Test status
Simulation time 1388713003 ps
CPU time 7.68 seconds
Started Oct 12 06:28:44 AM UTC 24
Finished Oct 12 06:28:52 AM UTC 24
Peak memory 230816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900024753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.1900024753 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.912035444
Short name T269
Test name
Test status
Simulation time 3097715106 ps
CPU time 40.71 seconds
Started Oct 12 06:44:05 AM UTC 24
Finished Oct 12 06:44:47 AM UTC 24
Peak memory 230944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912035444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.912035444 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.3193511392
Short name T234
Test name
Test status
Simulation time 59762845157 ps
CPU time 335.57 seconds
Started Oct 12 06:36:34 AM UTC 24
Finished Oct 12 06:42:14 AM UTC 24
Peak memory 475064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193511392 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.3193511392 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1758616540
Short name T133
Test name
Test status
Simulation time 116650913 ps
CPU time 1.36 seconds
Started Oct 12 02:32:23 AM UTC 24
Finished Oct 12 02:32:25 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758616540 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1758616540 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.2131910289
Short name T291
Test name
Test status
Simulation time 10386169082 ps
CPU time 169.55 seconds
Started Oct 12 06:43:34 AM UTC 24
Finished Oct 12 06:46:27 AM UTC 24
Peak memory 315512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131910289 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2131910289 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.3911437800
Short name T767
Test name
Test status
Simulation time 1417731702 ps
CPU time 10.09 seconds
Started Oct 12 02:32:26 AM UTC 24
Finished Oct 12 02:32:38 AM UTC 24
Peak memory 227448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911437800 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3911437800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.765190235
Short name T769
Test name
Test status
Simulation time 975967588 ps
CPU time 12.31 seconds
Started Oct 12 02:32:26 AM UTC 24
Finished Oct 12 02:32:40 AM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765190235 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.765190235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2103029497
Short name T138
Test name
Test status
Simulation time 204935613 ps
CPU time 2.28 seconds
Started Oct 12 02:32:28 AM UTC 24
Finished Oct 12 02:32:31 AM UTC 24
Peak memory 227776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2103029497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_
mem_rw_with_rand_reset.2103029497 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2066324965
Short name T179
Test name
Test status
Simulation time 16167945 ps
CPU time 1.37 seconds
Started Oct 12 02:32:25 AM UTC 24
Finished Oct 12 02:32:28 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066324965 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2066324965 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1801325167
Short name T132
Test name
Test status
Simulation time 16672160 ps
CPU time 1.25 seconds
Started Oct 12 02:32:23 AM UTC 24
Finished Oct 12 02:32:25 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801325167 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1801325167 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.4143994233
Short name T761
Test name
Test status
Simulation time 16112676 ps
CPU time 1.05 seconds
Started Oct 12 02:32:18 AM UTC 24
Finished Oct 12 02:32:21 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143994233 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.4143994233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2186368037
Short name T762
Test name
Test status
Simulation time 63524386 ps
CPU time 3.01 seconds
Started Oct 12 02:32:27 AM UTC 24
Finished Oct 12 02:32:31 AM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186368037 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.2186368037 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2140763745
Short name T103
Test name
Test status
Simulation time 205065744 ps
CPU time 3.67 seconds
Started Oct 12 02:32:17 AM UTC 24
Finished Oct 12 02:32:22 AM UTC 24
Peak memory 228124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140763745 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.
2140763745 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2386220648
Short name T137
Test name
Test status
Simulation time 186456189 ps
CPU time 4.22 seconds
Started Oct 12 02:32:21 AM UTC 24
Finished Oct 12 02:32:26 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386220648 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2386220648 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.701986060
Short name T152
Test name
Test status
Simulation time 278033998 ps
CPU time 7.72 seconds
Started Oct 12 02:32:32 AM UTC 24
Finished Oct 12 02:32:40 AM UTC 24
Peak memory 217276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701986060 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.701986060 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.576833058
Short name T773
Test name
Test status
Simulation time 246617066 ps
CPU time 9.17 seconds
Started Oct 12 02:32:32 AM UTC 24
Finished Oct 12 02:32:42 AM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576833058 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.576833058 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.247663258
Short name T765
Test name
Test status
Simulation time 55980311 ps
CPU time 1.47 seconds
Started Oct 12 02:32:32 AM UTC 24
Finished Oct 12 02:32:34 AM UTC 24
Peak memory 226652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247663258 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.247663258 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2869039156
Short name T140
Test name
Test status
Simulation time 294061294 ps
CPU time 3.48 seconds
Started Oct 12 02:32:34 AM UTC 24
Finished Oct 12 02:32:38 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2869039156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_
mem_rw_with_rand_reset.2869039156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.4210734156
Short name T764
Test name
Test status
Simulation time 59072430 ps
CPU time 1.34 seconds
Started Oct 12 02:32:32 AM UTC 24
Finished Oct 12 02:32:34 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210734156 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.4210734156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.1762644137
Short name T134
Test name
Test status
Simulation time 24199441 ps
CPU time 1.12 seconds
Started Oct 12 02:32:31 AM UTC 24
Finished Oct 12 02:32:34 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762644137 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1762644137 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2971643701
Short name T145
Test name
Test status
Simulation time 32809284 ps
CPU time 1.69 seconds
Started Oct 12 02:32:30 AM UTC 24
Finished Oct 12 02:32:33 AM UTC 24
Peak memory 226664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971643701 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2971643701 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.3027445267
Short name T763
Test name
Test status
Simulation time 42726299 ps
CPU time 0.87 seconds
Started Oct 12 02:32:29 AM UTC 24
Finished Oct 12 02:32:31 AM UTC 24
Peak memory 216660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027445267 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3027445267 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.4017563287
Short name T768
Test name
Test status
Simulation time 318665187 ps
CPU time 3.03 seconds
Started Oct 12 02:32:34 AM UTC 24
Finished Oct 12 02:32:38 AM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017563287 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.4017563287 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3248726538
Short name T104
Test name
Test status
Simulation time 86709055 ps
CPU time 1.73 seconds
Started Oct 12 02:32:28 AM UTC 24
Finished Oct 12 02:32:31 AM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248726538 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.3248726538 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2752525983
Short name T105
Test name
Test status
Simulation time 302406947 ps
CPU time 2.18 seconds
Started Oct 12 02:32:28 AM UTC 24
Finished Oct 12 02:32:31 AM UTC 24
Peak memory 227912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752525983 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.
2752525983 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.1801795932
Short name T139
Test name
Test status
Simulation time 159720339 ps
CPU time 5.32 seconds
Started Oct 12 02:32:30 AM UTC 24
Finished Oct 12 02:32:37 AM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801795932 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1801795932 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.378741838
Short name T130
Test name
Test status
Simulation time 472959811 ps
CPU time 5 seconds
Started Oct 12 02:32:31 AM UTC 24
Finished Oct 12 02:32:37 AM UTC 24
Peak memory 217188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378741838 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.378741838 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.529219759
Short name T823
Test name
Test status
Simulation time 44387163 ps
CPU time 1.55 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:06 AM UTC 24
Peak memory 226456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=529219759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_
mem_rw_with_rand_reset.529219759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.729803076
Short name T821
Test name
Test status
Simulation time 40511999 ps
CPU time 1.27 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:05 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729803076 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.729803076 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3580610241
Short name T163
Test name
Test status
Simulation time 13868393 ps
CPU time 1.11 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:05 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580610241 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3580610241 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3860037355
Short name T828
Test name
Test status
Simulation time 70752184 ps
CPU time 2.61 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:07 AM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860037355 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.3860037355 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.23110880
Short name T820
Test name
Test status
Simulation time 33700967 ps
CPU time 1.39 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:05 AM UTC 24
Peak memory 216176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23110880 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.23110880 +enable_masking=
0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4024299621
Short name T824
Test name
Test status
Simulation time 65832044 ps
CPU time 1.96 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:06 AM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024299621 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw
.4024299621 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.4240431885
Short name T830
Test name
Test status
Simulation time 52158563 ps
CPU time 3.75 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:08 AM UTC 24
Peak memory 227484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240431885 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.4240431885 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3817474263
Short name T833
Test name
Test status
Simulation time 66918032 ps
CPU time 2.64 seconds
Started Oct 12 02:33:05 AM UTC 24
Finished Oct 12 02:33:08 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3817474263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr
_mem_rw_with_rand_reset.3817474263 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3525363604
Short name T827
Test name
Test status
Simulation time 76436921 ps
CPU time 1.2 seconds
Started Oct 12 02:33:04 AM UTC 24
Finished Oct 12 02:33:07 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525363604 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3525363604 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.275563232
Short name T832
Test name
Test status
Simulation time 72019451 ps
CPU time 2.28 seconds
Started Oct 12 02:33:05 AM UTC 24
Finished Oct 12 02:33:08 AM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275563232 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.275563232 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3732728950
Short name T829
Test name
Test status
Simulation time 61325034 ps
CPU time 2.04 seconds
Started Oct 12 02:33:04 AM UTC 24
Finished Oct 12 02:33:07 AM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732728950 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw
.3732728950 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.340021765
Short name T837
Test name
Test status
Simulation time 151602229 ps
CPU time 3.69 seconds
Started Oct 12 02:33:04 AM UTC 24
Finished Oct 12 02:33:09 AM UTC 24
Peak memory 227556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340021765 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.340021765 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.4081241482
Short name T835
Test name
Test status
Simulation time 662153232 ps
CPU time 2.84 seconds
Started Oct 12 02:33:04 AM UTC 24
Finished Oct 12 02:33:08 AM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081241482 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.4081241482 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2409440182
Short name T840
Test name
Test status
Simulation time 151074424 ps
CPU time 2.17 seconds
Started Oct 12 02:33:07 AM UTC 24
Finished Oct 12 02:33:10 AM UTC 24
Peak memory 226848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2409440182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr
_mem_rw_with_rand_reset.2409440182 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2331908655
Short name T834
Test name
Test status
Simulation time 45095056 ps
CPU time 1.28 seconds
Started Oct 12 02:33:06 AM UTC 24
Finished Oct 12 02:33:08 AM UTC 24
Peak memory 226664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331908655 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2331908655 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1688165495
Short name T831
Test name
Test status
Simulation time 47607321 ps
CPU time 0.97 seconds
Started Oct 12 02:33:06 AM UTC 24
Finished Oct 12 02:33:08 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688165495 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1688165495 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2420963675
Short name T841
Test name
Test status
Simulation time 209485268 ps
CPU time 2.17 seconds
Started Oct 12 02:33:07 AM UTC 24
Finished Oct 12 02:33:10 AM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420963675 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.2420963675 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2726731830
Short name T116
Test name
Test status
Simulation time 60384210 ps
CPU time 1.31 seconds
Started Oct 12 02:33:06 AM UTC 24
Finished Oct 12 02:33:08 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726731830 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2726731830 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.98364134
Short name T836
Test name
Test status
Simulation time 53368031 ps
CPU time 1.95 seconds
Started Oct 12 02:33:06 AM UTC 24
Finished Oct 12 02:33:09 AM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98364134 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.9
8364134 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.4244975898
Short name T847
Test name
Test status
Simulation time 618276638 ps
CPU time 4.08 seconds
Started Oct 12 02:33:06 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 227636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244975898 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.4244975898 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.295776856
Short name T853
Test name
Test status
Simulation time 50000305 ps
CPU time 2.29 seconds
Started Oct 12 02:33:08 AM UTC 24
Finished Oct 12 02:33:12 AM UTC 24
Peak memory 227492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=295776856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_
mem_rw_with_rand_reset.295776856 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3433836670
Short name T846
Test name
Test status
Simulation time 56235375 ps
CPU time 1.37 seconds
Started Oct 12 02:33:08 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433836670 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3433836670 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.872204622
Short name T844
Test name
Test status
Simulation time 92854806 ps
CPU time 0.98 seconds
Started Oct 12 02:33:08 AM UTC 24
Finished Oct 12 02:33:10 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872204622 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.872204622 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.427855731
Short name T851
Test name
Test status
Simulation time 97793596 ps
CPU time 1.8 seconds
Started Oct 12 02:33:08 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 226728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427855731 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.427855731 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1643701203
Short name T839
Test name
Test status
Simulation time 895374915 ps
CPU time 1.79 seconds
Started Oct 12 02:33:07 AM UTC 24
Finished Oct 12 02:33:10 AM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643701203 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1643701203 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2336273244
Short name T838
Test name
Test status
Simulation time 212839947 ps
CPU time 1.72 seconds
Started Oct 12 02:33:07 AM UTC 24
Finished Oct 12 02:33:10 AM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336273244 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw
.2336273244 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3292557661
Short name T848
Test name
Test status
Simulation time 263688449 ps
CPU time 2.65 seconds
Started Oct 12 02:33:07 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292557661 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3292557661 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1842398372
Short name T855
Test name
Test status
Simulation time 59635293 ps
CPU time 2.05 seconds
Started Oct 12 02:33:10 AM UTC 24
Finished Oct 12 02:33:13 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1842398372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr
_mem_rw_with_rand_reset.1842398372 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.97223409
Short name T849
Test name
Test status
Simulation time 48521277 ps
CPU time 1.29 seconds
Started Oct 12 02:33:09 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97223409 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.97223409 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.894494509
Short name T845
Test name
Test status
Simulation time 16632628 ps
CPU time 1.05 seconds
Started Oct 12 02:33:09 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894494509 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.894494509 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2450553181
Short name T858
Test name
Test status
Simulation time 117464946 ps
CPU time 2.39 seconds
Started Oct 12 02:33:10 AM UTC 24
Finished Oct 12 02:33:13 AM UTC 24
Peak memory 227680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450553181 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.2450553181 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2593858961
Short name T850
Test name
Test status
Simulation time 193218769 ps
CPU time 1.54 seconds
Started Oct 12 02:33:08 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593858961 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.2593858961 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.125922028
Short name T852
Test name
Test status
Simulation time 44853426 ps
CPU time 1.87 seconds
Started Oct 12 02:33:08 AM UTC 24
Finished Oct 12 02:33:11 AM UTC 24
Peak memory 226416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125922028 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.
125922028 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1272216822
Short name T856
Test name
Test status
Simulation time 121819185 ps
CPU time 3.35 seconds
Started Oct 12 02:33:09 AM UTC 24
Finished Oct 12 02:33:13 AM UTC 24
Peak memory 227764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272216822 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1272216822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1296953183
Short name T178
Test name
Test status
Simulation time 201128201 ps
CPU time 4.3 seconds
Started Oct 12 02:33:09 AM UTC 24
Finished Oct 12 02:33:14 AM UTC 24
Peak memory 227492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296953183 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1296953183 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1387698679
Short name T864
Test name
Test status
Simulation time 218285335 ps
CPU time 2.13 seconds
Started Oct 12 02:33:11 AM UTC 24
Finished Oct 12 02:33:14 AM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1387698679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr
_mem_rw_with_rand_reset.1387698679 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.3776466337
Short name T860
Test name
Test status
Simulation time 103515880 ps
CPU time 1.62 seconds
Started Oct 12 02:33:11 AM UTC 24
Finished Oct 12 02:33:14 AM UTC 24
Peak memory 216424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776466337 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3776466337 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.175973332
Short name T857
Test name
Test status
Simulation time 11180956 ps
CPU time 1.02 seconds
Started Oct 12 02:33:11 AM UTC 24
Finished Oct 12 02:33:13 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175973332 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.175973332 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3899347801
Short name T863
Test name
Test status
Simulation time 511558559 ps
CPU time 1.85 seconds
Started Oct 12 02:33:11 AM UTC 24
Finished Oct 12 02:33:14 AM UTC 24
Peak memory 226728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899347801 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3899347801 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1412070231
Short name T854
Test name
Test status
Simulation time 103088281 ps
CPU time 1.18 seconds
Started Oct 12 02:33:10 AM UTC 24
Finished Oct 12 02:33:12 AM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412070231 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.1412070231 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1293127351
Short name T862
Test name
Test status
Simulation time 264277113 ps
CPU time 2.96 seconds
Started Oct 12 02:33:10 AM UTC 24
Finished Oct 12 02:33:14 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293127351 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw
.1293127351 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.4007869311
Short name T870
Test name
Test status
Simulation time 677285107 ps
CPU time 4.35 seconds
Started Oct 12 02:33:10 AM UTC 24
Finished Oct 12 02:33:15 AM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007869311 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.4007869311 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.467715196
Short name T861
Test name
Test status
Simulation time 460718609 ps
CPU time 2.85 seconds
Started Oct 12 02:33:10 AM UTC 24
Finished Oct 12 02:33:14 AM UTC 24
Peak memory 217456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467715196 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.467715196 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1448087150
Short name T873
Test name
Test status
Simulation time 73885222 ps
CPU time 2.42 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:16 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1448087150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr
_mem_rw_with_rand_reset.1448087150 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1404672472
Short name T868
Test name
Test status
Simulation time 78752467 ps
CPU time 1.28 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:15 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404672472 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1404672472 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.575032672
Short name T867
Test name
Test status
Simulation time 12384792 ps
CPU time 1.08 seconds
Started Oct 12 02:33:12 AM UTC 24
Finished Oct 12 02:33:15 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575032672 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.575032672 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1882474577
Short name T874
Test name
Test status
Simulation time 940171721 ps
CPU time 2.75 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:16 AM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882474577 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.1882474577 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4253508931
Short name T859
Test name
Test status
Simulation time 30891846 ps
CPU time 1.37 seconds
Started Oct 12 02:33:11 AM UTC 24
Finished Oct 12 02:33:14 AM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253508931 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.4253508931 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2661918579
Short name T869
Test name
Test status
Simulation time 256321245 ps
CPU time 2.84 seconds
Started Oct 12 02:33:11 AM UTC 24
Finished Oct 12 02:33:15 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661918579 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw
.2661918579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2564725810
Short name T865
Test name
Test status
Simulation time 40441741 ps
CPU time 2.24 seconds
Started Oct 12 02:33:11 AM UTC 24
Finished Oct 12 02:33:15 AM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564725810 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2564725810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2506966988
Short name T168
Test name
Test status
Simulation time 60901470 ps
CPU time 2.27 seconds
Started Oct 12 02:33:12 AM UTC 24
Finished Oct 12 02:33:16 AM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506966988 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2506966988 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1177716388
Short name T879
Test name
Test status
Simulation time 279791687 ps
CPU time 2.63 seconds
Started Oct 12 02:33:14 AM UTC 24
Finished Oct 12 02:33:18 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1177716388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr
_mem_rw_with_rand_reset.1177716388 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.2410321662
Short name T843
Test name
Test status
Simulation time 23231588 ps
CPU time 1.33 seconds
Started Oct 12 02:33:14 AM UTC 24
Finished Oct 12 02:33:16 AM UTC 24
Peak memory 216372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410321662 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2410321662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1976676293
Short name T866
Test name
Test status
Simulation time 17050072 ps
CPU time 0.8 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:15 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976676293 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1976676293 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.4225004161
Short name T877
Test name
Test status
Simulation time 335675856 ps
CPU time 2.47 seconds
Started Oct 12 02:33:14 AM UTC 24
Finished Oct 12 02:33:17 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225004161 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.4225004161 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2574952414
Short name T842
Test name
Test status
Simulation time 18163479 ps
CPU time 1.5 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:15 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574952414 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2574952414 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1358546548
Short name T872
Test name
Test status
Simulation time 122383841 ps
CPU time 2.27 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:16 AM UTC 24
Peak memory 228184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358546548 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw
.1358546548 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1462281176
Short name T871
Test name
Test status
Simulation time 80751930 ps
CPU time 2.04 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:16 AM UTC 24
Peak memory 227688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462281176 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1462281176 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.825340293
Short name T875
Test name
Test status
Simulation time 403927040 ps
CPU time 2.73 seconds
Started Oct 12 02:33:13 AM UTC 24
Finished Oct 12 02:33:17 AM UTC 24
Peak memory 227620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825340293 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.825340293 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2546243949
Short name T891
Test name
Test status
Simulation time 92291971 ps
CPU time 2.66 seconds
Started Oct 12 02:33:15 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2546243949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr
_mem_rw_with_rand_reset.2546243949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2075926077
Short name T876
Test name
Test status
Simulation time 61688287 ps
CPU time 1.03 seconds
Started Oct 12 02:33:15 AM UTC 24
Finished Oct 12 02:33:17 AM UTC 24
Peak memory 216444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075926077 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2075926077 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3245423407
Short name T878
Test name
Test status
Simulation time 17769738 ps
CPU time 1.14 seconds
Started Oct 12 02:33:15 AM UTC 24
Finished Oct 12 02:33:18 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245423407 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3245423407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.5460649
Short name T881
Test name
Test status
Simulation time 46063897 ps
CPU time 1.56 seconds
Started Oct 12 02:33:15 AM UTC 24
Finished Oct 12 02:33:18 AM UTC 24
Peak memory 226660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5460649 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.5460649 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.255036355
Short name T809
Test name
Test status
Simulation time 31072109 ps
CPU time 1.5 seconds
Started Oct 12 02:33:14 AM UTC 24
Finished Oct 12 02:33:17 AM UTC 24
Peak memory 233684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255036355 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.255036355 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4069822704
Short name T893
Test name
Test status
Simulation time 196499187 ps
CPU time 2.99 seconds
Started Oct 12 02:33:15 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 234068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069822704 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw
.4069822704 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3342238282
Short name T883
Test name
Test status
Simulation time 102972490 ps
CPU time 2.6 seconds
Started Oct 12 02:33:15 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 227544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342238282 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3342238282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3920787434
Short name T173
Test name
Test status
Simulation time 770531486 ps
CPU time 4.26 seconds
Started Oct 12 02:33:15 AM UTC 24
Finished Oct 12 02:33:21 AM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920787434 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3920787434 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1357878736
Short name T900
Test name
Test status
Simulation time 37928177 ps
CPU time 2.49 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 229876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1357878736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr
_mem_rw_with_rand_reset.1357878736 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.4107880607
Short name T890
Test name
Test status
Simulation time 30633223 ps
CPU time 1.3 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 216424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107880607 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4107880607 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1365976780
Short name T882
Test name
Test status
Simulation time 92717744 ps
CPU time 0.87 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365976780 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1365976780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.826448342
Short name T903
Test name
Test status
Simulation time 344168928 ps
CPU time 2.74 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:21 AM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826448342 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.826448342 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.33163653
Short name T880
Test name
Test status
Simulation time 111894880 ps
CPU time 1.32 seconds
Started Oct 12 02:33:16 AM UTC 24
Finished Oct 12 02:33:18 AM UTC 24
Peak memory 226352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33163653 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.33163653 +enable_masking=
0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3691856666
Short name T889
Test name
Test status
Simulation time 168682671 ps
CPU time 2.4 seconds
Started Oct 12 02:33:16 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 227840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691856666 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw
.3691856666 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.494281089
Short name T885
Test name
Test status
Simulation time 80958396 ps
CPU time 2.3 seconds
Started Oct 12 02:33:16 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 227580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494281089 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.494281089 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2330551810
Short name T895
Test name
Test status
Simulation time 181302071 ps
CPU time 2.43 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 217188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330551810 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2330551810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3396544522
Short name T154
Test name
Test status
Simulation time 2548761233 ps
CPU time 11.98 seconds
Started Oct 12 02:32:40 AM UTC 24
Finished Oct 12 02:32:53 AM UTC 24
Peak memory 217336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396544522 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3396544522 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2712243810
Short name T782
Test name
Test status
Simulation time 509967735 ps
CPU time 9.7 seconds
Started Oct 12 02:32:39 AM UTC 24
Finished Oct 12 02:32:49 AM UTC 24
Peak memory 217208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712243810 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2712243810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.4229179734
Short name T771
Test name
Test status
Simulation time 19127469 ps
CPU time 1.55 seconds
Started Oct 12 02:32:38 AM UTC 24
Finished Oct 12 02:32:41 AM UTC 24
Peak memory 216368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229179734 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.4229179734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3344469310
Short name T775
Test name
Test status
Simulation time 34171861 ps
CPU time 3.31 seconds
Started Oct 12 02:32:41 AM UTC 24
Finished Oct 12 02:32:45 AM UTC 24
Peak memory 234492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3344469310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_
mem_rw_with_rand_reset.3344469310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3643949006
Short name T772
Test name
Test status
Simulation time 50938190 ps
CPU time 1.56 seconds
Started Oct 12 02:32:39 AM UTC 24
Finished Oct 12 02:32:41 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643949006 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3643949006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.1076176510
Short name T155
Test name
Test status
Simulation time 27793561 ps
CPU time 1.15 seconds
Started Oct 12 02:32:38 AM UTC 24
Finished Oct 12 02:32:41 AM UTC 24
Peak memory 216316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076176510 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1076176510 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.3628417714
Short name T770
Test name
Test status
Simulation time 25591953 ps
CPU time 1.77 seconds
Started Oct 12 02:32:37 AM UTC 24
Finished Oct 12 02:32:40 AM UTC 24
Peak memory 226664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628417714 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.3628417714 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.4287088121
Short name T766
Test name
Test status
Simulation time 104101784 ps
CPU time 1.06 seconds
Started Oct 12 02:32:35 AM UTC 24
Finished Oct 12 02:32:37 AM UTC 24
Peak memory 216660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287088121 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.4287088121 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3915303501
Short name T777
Test name
Test status
Simulation time 798500531 ps
CPU time 3.96 seconds
Started Oct 12 02:32:41 AM UTC 24
Finished Oct 12 02:32:46 AM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915303501 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3915303501 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.107635947
Short name T117
Test name
Test status
Simulation time 111484391 ps
CPU time 1.66 seconds
Started Oct 12 02:32:35 AM UTC 24
Finished Oct 12 02:32:38 AM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107635947 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.107635947 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2042013335
Short name T107
Test name
Test status
Simulation time 137995992 ps
CPU time 4.51 seconds
Started Oct 12 02:32:35 AM UTC 24
Finished Oct 12 02:32:41 AM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042013335 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.
2042013335 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.4145799841
Short name T141
Test name
Test status
Simulation time 168198943 ps
CPU time 3.72 seconds
Started Oct 12 02:32:37 AM UTC 24
Finished Oct 12 02:32:42 AM UTC 24
Peak memory 227552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145799841 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.4145799841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2850198415
Short name T887
Test name
Test status
Simulation time 15407830 ps
CPU time 1.09 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850198415 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2850198415 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.188469476
Short name T888
Test name
Test status
Simulation time 55229082 ps
CPU time 1.09 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188469476 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.188469476 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3789063450
Short name T884
Test name
Test status
Simulation time 12543994 ps
CPU time 0.95 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789063450 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3789063450 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1309744569
Short name T892
Test name
Test status
Simulation time 30891172 ps
CPU time 1.12 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309744569 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1309744569 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3594280608
Short name T886
Test name
Test status
Simulation time 22622457 ps
CPU time 0.89 seconds
Started Oct 12 02:33:17 AM UTC 24
Finished Oct 12 02:33:19 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594280608 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3594280608 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3897066235
Short name T894
Test name
Test status
Simulation time 41508575 ps
CPU time 0.77 seconds
Started Oct 12 02:33:18 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897066235 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3897066235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3794757810
Short name T896
Test name
Test status
Simulation time 16790599 ps
CPU time 0.99 seconds
Started Oct 12 02:33:18 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794757810 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3794757810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2599868753
Short name T897
Test name
Test status
Simulation time 38958731 ps
CPU time 0.96 seconds
Started Oct 12 02:33:18 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599868753 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2599868753 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2585719352
Short name T901
Test name
Test status
Simulation time 42265095 ps
CPU time 1.06 seconds
Started Oct 12 02:33:18 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585719352 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2585719352 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1966136848
Short name T898
Test name
Test status
Simulation time 46681960 ps
CPU time 0.84 seconds
Started Oct 12 02:33:18 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966136848 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1966136848 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2154350590
Short name T788
Test name
Test status
Simulation time 3220350865 ps
CPU time 7.46 seconds
Started Oct 12 02:32:45 AM UTC 24
Finished Oct 12 02:32:53 AM UTC 24
Peak memory 217336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154350590 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2154350590 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2173813205
Short name T802
Test name
Test status
Simulation time 642496230 ps
CPU time 13.11 seconds
Started Oct 12 02:32:45 AM UTC 24
Finished Oct 12 02:32:59 AM UTC 24
Peak memory 217196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173813205 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2173813205 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.4093704731
Short name T776
Test name
Test status
Simulation time 68777096 ps
CPU time 1.22 seconds
Started Oct 12 02:32:43 AM UTC 24
Finished Oct 12 02:32:46 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093704731 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4093704731 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.33517455
Short name T783
Test name
Test status
Simulation time 146669223 ps
CPU time 3.03 seconds
Started Oct 12 02:32:46 AM UTC 24
Finished Oct 12 02:32:50 AM UTC 24
Peak memory 229548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=33517455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_me
m_rw_with_rand_reset.33517455 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.317567172
Short name T778
Test name
Test status
Simulation time 184070664 ps
CPU time 1.64 seconds
Started Oct 12 02:32:44 AM UTC 24
Finished Oct 12 02:32:46 AM UTC 24
Peak memory 216488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317567172 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.317567172 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3531907938
Short name T159
Test name
Test status
Simulation time 43136613 ps
CPU time 1.17 seconds
Started Oct 12 02:32:42 AM UTC 24
Finished Oct 12 02:32:45 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531907938 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3531907938 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.1396640835
Short name T146
Test name
Test status
Simulation time 29617681 ps
CPU time 1.63 seconds
Started Oct 12 02:32:42 AM UTC 24
Finished Oct 12 02:32:45 AM UTC 24
Peak memory 226664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396640835 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.1396640835 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1339525958
Short name T774
Test name
Test status
Simulation time 20542115 ps
CPU time 1.07 seconds
Started Oct 12 02:32:42 AM UTC 24
Finished Oct 12 02:32:44 AM UTC 24
Peak memory 216600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339525958 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1339525958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1785070522
Short name T785
Test name
Test status
Simulation time 760984294 ps
CPU time 3.68 seconds
Started Oct 12 02:32:46 AM UTC 24
Finished Oct 12 02:32:51 AM UTC 24
Peak memory 227492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785070522 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.1785070522 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1096912072
Short name T108
Test name
Test status
Simulation time 25482647 ps
CPU time 1.55 seconds
Started Oct 12 02:32:41 AM UTC 24
Finished Oct 12 02:32:43 AM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096912072 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.1096912072 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4048394150
Short name T109
Test name
Test status
Simulation time 2663613544 ps
CPU time 4.59 seconds
Started Oct 12 02:32:41 AM UTC 24
Finished Oct 12 02:32:47 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048394150 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.
4048394150 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2132928169
Short name T779
Test name
Test status
Simulation time 148164642 ps
CPU time 3.42 seconds
Started Oct 12 02:32:42 AM UTC 24
Finished Oct 12 02:32:47 AM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132928169 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2132928169 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.3688568899
Short name T780
Test name
Test status
Simulation time 1095626761 ps
CPU time 3.95 seconds
Started Oct 12 02:32:42 AM UTC 24
Finished Oct 12 02:32:47 AM UTC 24
Peak memory 229816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688568899 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.3688568899 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3030676616
Short name T899
Test name
Test status
Simulation time 17838774 ps
CPU time 0.93 seconds
Started Oct 12 02:33:18 AM UTC 24
Finished Oct 12 02:33:20 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030676616 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3030676616 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1016520632
Short name T902
Test name
Test status
Simulation time 19797059 ps
CPU time 1.05 seconds
Started Oct 12 02:33:18 AM UTC 24
Finished Oct 12 02:33:21 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016520632 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1016520632 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.102109958
Short name T904
Test name
Test status
Simulation time 36307775 ps
CPU time 0.76 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:21 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102109958 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.102109958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.1012921739
Short name T906
Test name
Test status
Simulation time 20778957 ps
CPU time 0.85 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012921739 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1012921739 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.787605080
Short name T905
Test name
Test status
Simulation time 12003140 ps
CPU time 0.83 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787605080 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.787605080 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2236176874
Short name T909
Test name
Test status
Simulation time 29831381 ps
CPU time 1.03 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236176874 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2236176874 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1384139021
Short name T907
Test name
Test status
Simulation time 37009780 ps
CPU time 0.95 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384139021 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1384139021 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3923768389
Short name T908
Test name
Test status
Simulation time 16934578 ps
CPU time 0.94 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923768389 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3923768389 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.999790540
Short name T914
Test name
Test status
Simulation time 13339854 ps
CPU time 1.07 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999790540 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.999790540 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3244529366
Short name T916
Test name
Test status
Simulation time 39063345 ps
CPU time 1.03 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244529366 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3244529366 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1048515868
Short name T810
Test name
Test status
Simulation time 401268751 ps
CPU time 10.21 seconds
Started Oct 12 02:32:50 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 217272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048515868 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1048515868 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3918218712
Short name T819
Test name
Test status
Simulation time 293989032 ps
CPU time 13.37 seconds
Started Oct 12 02:32:50 AM UTC 24
Finished Oct 12 02:33:05 AM UTC 24
Peak memory 217272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918218712 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3918218712 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2885531607
Short name T786
Test name
Test status
Simulation time 87956461 ps
CPU time 1.55 seconds
Started Oct 12 02:32:48 AM UTC 24
Finished Oct 12 02:32:51 AM UTC 24
Peak memory 226648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885531607 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2885531607 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1764633583
Short name T789
Test name
Test status
Simulation time 164288422 ps
CPU time 2.23 seconds
Started Oct 12 02:32:51 AM UTC 24
Finished Oct 12 02:32:54 AM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1764633583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_
mem_rw_with_rand_reset.1764633583 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2014173309
Short name T787
Test name
Test status
Simulation time 13084670 ps
CPU time 1.03 seconds
Started Oct 12 02:32:49 AM UTC 24
Finished Oct 12 02:32:51 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014173309 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2014173309 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.3199313919
Short name T164
Test name
Test status
Simulation time 11705568 ps
CPU time 1.15 seconds
Started Oct 12 02:32:48 AM UTC 24
Finished Oct 12 02:32:50 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199313919 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3199313919 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.768523120
Short name T147
Test name
Test status
Simulation time 23313860 ps
CPU time 1.75 seconds
Started Oct 12 02:32:47 AM UTC 24
Finished Oct 12 02:32:50 AM UTC 24
Peak memory 226452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768523120 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.768523120 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.2877188147
Short name T781
Test name
Test status
Simulation time 31812590 ps
CPU time 1.09 seconds
Started Oct 12 02:32:47 AM UTC 24
Finished Oct 12 02:32:49 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877188147 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2877188147 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3090696199
Short name T791
Test name
Test status
Simulation time 158968953 ps
CPU time 3.33 seconds
Started Oct 12 02:32:51 AM UTC 24
Finished Oct 12 02:32:55 AM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090696199 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3090696199 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.310359071
Short name T118
Test name
Test status
Simulation time 217708999 ps
CPU time 1.76 seconds
Started Oct 12 02:32:46 AM UTC 24
Finished Oct 12 02:32:49 AM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310359071 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.310359071 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2245280313
Short name T153
Test name
Test status
Simulation time 1259871456 ps
CPU time 3.39 seconds
Started Oct 12 02:32:46 AM UTC 24
Finished Oct 12 02:32:50 AM UTC 24
Peak memory 234812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245280313 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.
2245280313 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.931539645
Short name T784
Test name
Test status
Simulation time 75588674 ps
CPU time 2.24 seconds
Started Oct 12 02:32:47 AM UTC 24
Finished Oct 12 02:32:50 AM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931539645 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.931539645 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.183487779
Short name T166
Test name
Test status
Simulation time 81464396 ps
CPU time 3.28 seconds
Started Oct 12 02:32:47 AM UTC 24
Finished Oct 12 02:32:52 AM UTC 24
Peak memory 229476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183487779 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.183487779 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3253455485
Short name T910
Test name
Test status
Simulation time 30686743 ps
CPU time 0.95 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253455485 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3253455485 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.983301089
Short name T911
Test name
Test status
Simulation time 33933968 ps
CPU time 0.95 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983301089 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.983301089 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1907173560
Short name T912
Test name
Test status
Simulation time 15802020 ps
CPU time 0.9 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907173560 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1907173560 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.764526025
Short name T918
Test name
Test status
Simulation time 27289369 ps
CPU time 1.04 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764526025 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.764526025 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2179353195
Short name T913
Test name
Test status
Simulation time 17293595 ps
CPU time 0.84 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179353195 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2179353195 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1385624248
Short name T917
Test name
Test status
Simulation time 27055746 ps
CPU time 0.93 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385624248 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1385624248 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2511892709
Short name T915
Test name
Test status
Simulation time 15420223 ps
CPU time 0.87 seconds
Started Oct 12 02:33:20 AM UTC 24
Finished Oct 12 02:33:22 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511892709 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2511892709 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3471176533
Short name T919
Test name
Test status
Simulation time 19461142 ps
CPU time 0.87 seconds
Started Oct 12 02:33:21 AM UTC 24
Finished Oct 12 02:33:23 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471176533 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3471176533 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.2045599798
Short name T920
Test name
Test status
Simulation time 28517812 ps
CPU time 0.93 seconds
Started Oct 12 02:33:21 AM UTC 24
Finished Oct 12 02:33:23 AM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045599798 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2045599798 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.60067822
Short name T921
Test name
Test status
Simulation time 17897015 ps
CPU time 0.99 seconds
Started Oct 12 02:33:21 AM UTC 24
Finished Oct 12 02:33:23 AM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60067822 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.60067822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3240194978
Short name T795
Test name
Test status
Simulation time 72213039 ps
CPU time 2.92 seconds
Started Oct 12 02:32:53 AM UTC 24
Finished Oct 12 02:32:57 AM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3240194978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_
mem_rw_with_rand_reset.3240194978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.118594835
Short name T790
Test name
Test status
Simulation time 89881275 ps
CPU time 1.35 seconds
Started Oct 12 02:32:52 AM UTC 24
Finished Oct 12 02:32:54 AM UTC 24
Peak memory 226676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118594835 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.118594835 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.116977867
Short name T158
Test name
Test status
Simulation time 18674335 ps
CPU time 1.16 seconds
Started Oct 12 02:32:52 AM UTC 24
Finished Oct 12 02:32:54 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116977867 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.116977867 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1715243300
Short name T792
Test name
Test status
Simulation time 106797742 ps
CPU time 2.04 seconds
Started Oct 12 02:32:52 AM UTC 24
Finished Oct 12 02:32:55 AM UTC 24
Peak memory 227708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715243300 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1715243300 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.4160984169
Short name T110
Test name
Test status
Simulation time 16533000 ps
CPU time 1.18 seconds
Started Oct 12 02:32:52 AM UTC 24
Finished Oct 12 02:32:54 AM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160984169 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.4160984169 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.4194731200
Short name T793
Test name
Test status
Simulation time 420053356 ps
CPU time 3.33 seconds
Started Oct 12 02:32:52 AM UTC 24
Finished Oct 12 02:32:56 AM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194731200 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4194731200 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3751739051
Short name T796
Test name
Test status
Simulation time 111036121 ps
CPU time 4.25 seconds
Started Oct 12 02:32:52 AM UTC 24
Finished Oct 12 02:32:57 AM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751739051 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.3751739051 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2839325945
Short name T801
Test name
Test status
Simulation time 42580813 ps
CPU time 2.09 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:32:59 AM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2839325945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_
mem_rw_with_rand_reset.2839325945 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.732671675
Short name T798
Test name
Test status
Simulation time 22241194 ps
CPU time 1.47 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:32:58 AM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732671675 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.732671675 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3770621345
Short name T165
Test name
Test status
Simulation time 33827021 ps
CPU time 1.14 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:32:58 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770621345 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3770621345 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1086873140
Short name T800
Test name
Test status
Simulation time 96579836 ps
CPU time 1.83 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:32:59 AM UTC 24
Peak memory 226676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086873140 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1086873140 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3956435688
Short name T111
Test name
Test status
Simulation time 95349027 ps
CPU time 1.34 seconds
Started Oct 12 02:32:53 AM UTC 24
Finished Oct 12 02:32:56 AM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956435688 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.3956435688 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.495258863
Short name T797
Test name
Test status
Simulation time 80132149 ps
CPU time 2.28 seconds
Started Oct 12 02:32:54 AM UTC 24
Finished Oct 12 02:32:58 AM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495258863 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.495258863 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.3632623013
Short name T176
Test name
Test status
Simulation time 132527370 ps
CPU time 3.01 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:33:00 AM UTC 24
Peak memory 217196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632623013 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.3632623013 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.4056871282
Short name T808
Test name
Test status
Simulation time 119592535 ps
CPU time 2.13 seconds
Started Oct 12 02:32:58 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 229748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4056871282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_
mem_rw_with_rand_reset.4056871282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3126230605
Short name T805
Test name
Test status
Simulation time 30269307 ps
CPU time 1.18 seconds
Started Oct 12 02:32:57 AM UTC 24
Finished Oct 12 02:33:00 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126230605 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3126230605 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.107549027
Short name T811
Test name
Test status
Simulation time 325564154 ps
CPU time 2.45 seconds
Started Oct 12 02:32:58 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107549027 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.107549027 +enable_m
asking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.9684730
Short name T799
Test name
Test status
Simulation time 59743636 ps
CPU time 1.53 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:32:59 AM UTC 24
Peak memory 226352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9684730 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.9684730 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.4139614955
Short name T804
Test name
Test status
Simulation time 109365355 ps
CPU time 2.35 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:32:59 AM UTC 24
Peak memory 234572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139614955 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.
4139614955 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.2079742259
Short name T806
Test name
Test status
Simulation time 382085758 ps
CPU time 3.41 seconds
Started Oct 12 02:32:56 AM UTC 24
Finished Oct 12 02:33:01 AM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079742259 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2079742259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2963989099
Short name T174
Test name
Test status
Simulation time 592098510 ps
CPU time 3.6 seconds
Started Oct 12 02:32:57 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 217196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963989099 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.2963989099 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1756853892
Short name T814
Test name
Test status
Simulation time 48180550 ps
CPU time 1.91 seconds
Started Oct 12 02:33:00 AM UTC 24
Finished Oct 12 02:33:03 AM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1756853892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_
mem_rw_with_rand_reset.1756853892 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.4283883658
Short name T812
Test name
Test status
Simulation time 64276041 ps
CPU time 1.23 seconds
Started Oct 12 02:33:00 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283883658 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4283883658 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1515119552
Short name T161
Test name
Test status
Simulation time 70381686 ps
CPU time 1.07 seconds
Started Oct 12 02:33:00 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515119552 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1515119552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.79474866
Short name T815
Test name
Test status
Simulation time 36687284 ps
CPU time 2.28 seconds
Started Oct 12 02:33:00 AM UTC 24
Finished Oct 12 02:33:03 AM UTC 24
Peak memory 227488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79474866 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.79474866 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1227198272
Short name T807
Test name
Test status
Simulation time 35129987 ps
CPU time 2.01 seconds
Started Oct 12 02:32:59 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227198272 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1227198272 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.4110173675
Short name T817
Test name
Test status
Simulation time 207942849 ps
CPU time 4.01 seconds
Started Oct 12 02:32:59 AM UTC 24
Finished Oct 12 02:33:04 AM UTC 24
Peak memory 227924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110173675 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.
4110173675 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.4182516300
Short name T813
Test name
Test status
Simulation time 101387620 ps
CPU time 2.46 seconds
Started Oct 12 02:32:59 AM UTC 24
Finished Oct 12 02:33:02 AM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182516300 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.4182516300 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.710401558
Short name T826
Test name
Test status
Simulation time 2481280745 ps
CPU time 5.82 seconds
Started Oct 12 02:33:00 AM UTC 24
Finished Oct 12 02:33:07 AM UTC 24
Peak memory 229808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710401558 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.710401558 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1438426815
Short name T822
Test name
Test status
Simulation time 47489426 ps
CPU time 1.78 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:06 AM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1438426815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_
mem_rw_with_rand_reset.1438426815 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1848243634
Short name T816
Test name
Test status
Simulation time 15981956 ps
CPU time 1.12 seconds
Started Oct 12 02:33:01 AM UTC 24
Finished Oct 12 02:33:03 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848243634 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1848243634 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.268216630
Short name T162
Test name
Test status
Simulation time 57777322 ps
CPU time 1.03 seconds
Started Oct 12 02:33:01 AM UTC 24
Finished Oct 12 02:33:03 AM UTC 24
Peak memory 216484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268216630 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.268216630 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3292918627
Short name T825
Test name
Test status
Simulation time 220792420 ps
CPU time 2.29 seconds
Started Oct 12 02:33:03 AM UTC 24
Finished Oct 12 02:33:06 AM UTC 24
Peak memory 227632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292918627 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3292918627 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2912732974
Short name T112
Test name
Test status
Simulation time 54325883 ps
CPU time 1.57 seconds
Started Oct 12 02:33:00 AM UTC 24
Finished Oct 12 02:33:03 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912732974 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.2912732974 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2861068386
Short name T113
Test name
Test status
Simulation time 77450326 ps
CPU time 1.84 seconds
Started Oct 12 02:33:00 AM UTC 24
Finished Oct 12 02:33:03 AM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861068386 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.
2861068386 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2789865046
Short name T818
Test name
Test status
Simulation time 244401871 ps
CPU time 2.67 seconds
Started Oct 12 02:33:01 AM UTC 24
Finished Oct 12 02:33:05 AM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789865046 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2789865046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3144905962
Short name T172
Test name
Test status
Simulation time 151157583 ps
CPU time 3.03 seconds
Started Oct 12 02:33:01 AM UTC 24
Finished Oct 12 02:33:05 AM UTC 24
Peak memory 227512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144905962 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.3144905962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.3273941231
Short name T188
Test name
Test status
Simulation time 10884254999 ps
CPU time 239.66 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:32:47 AM UTC 24
Peak memory 421744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273941231 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3273941231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.472311244
Short name T25
Test name
Test status
Simulation time 7345793487 ps
CPU time 156.78 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:31:23 AM UTC 24
Peak memory 370768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472311244 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.472311244 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.2247407299
Short name T80
Test name
Test status
Simulation time 2885183310 ps
CPU time 107.97 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:30:32 AM UTC 24
Peak memory 235052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247407299 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2247407299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.71039543
Short name T13
Test name
Test status
Simulation time 648547415 ps
CPU time 7.35 seconds
Started Oct 12 06:28:45 AM UTC 24
Finished Oct 12 06:28:53 AM UTC 24
Peak memory 228676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71039543 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.71039543 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.2787693757
Short name T32
Test name
Test status
Simulation time 2895697106 ps
CPU time 41.11 seconds
Started Oct 12 06:28:45 AM UTC 24
Finished Oct 12 06:29:27 AM UTC 24
Peak memory 235188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787693757 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2787693757 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3460370857
Short name T42
Test name
Test status
Simulation time 80022643405 ps
CPU time 402.91 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:35:31 AM UTC 24
Peak memory 571268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460370857 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3460370857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.4158603561
Short name T4
Test name
Test status
Simulation time 43009916 ps
CPU time 2.13 seconds
Started Oct 12 06:28:47 AM UTC 24
Finished Oct 12 06:28:50 AM UTC 24
Peak memory 230832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158603561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.4158603561 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.1171440517
Short name T381
Test name
Test status
Simulation time 62815238812 ps
CPU time 1582.58 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:55:22 AM UTC 24
Peak memory 1200020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171440517 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1171440517 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.2464984824
Short name T14
Test name
Test status
Simulation time 1459785552 ps
CPU time 14.75 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:28:58 AM UTC 24
Peak memory 235044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464984824 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2464984824 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload_invalid.1604605322
Short name T1
Test name
Test status
Simulation time 348528099 ps
CPU time 3.31 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:28:46 AM UTC 24
Peak memory 231008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604605322 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload_invalid.1604605322 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.2609831779
Short name T64
Test name
Test status
Simulation time 9214062913 ps
CPU time 48.28 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:29:31 AM UTC 24
Peak memory 235528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609831779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2609831779 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.289768928
Short name T650
Test name
Test status
Simulation time 856373634887 ps
CPU time 2769.29 seconds
Started Oct 12 06:28:48 AM UTC 24
Finished Oct 12 07:15:29 AM UTC 24
Peak memory 1277976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289768928 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.289768928 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.364039692
Short name T3
Test name
Test status
Simulation time 32526069 ps
CPU time 2.83 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:28:47 AM UTC 24
Peak memory 230964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364039692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.364039692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.986321914
Short name T2
Test name
Test status
Simulation time 62052063 ps
CPU time 2.48 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:28:47 AM UTC 24
Peak memory 230888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986321914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.986321914 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.2584471696
Short name T92
Test name
Test status
Simulation time 3127709215 ps
CPU time 60.88 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:29:44 AM UTC 24
Peak memory 255908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584471696 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2584471696
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.375728617
Short name T93
Test name
Test status
Simulation time 5857504082 ps
CPU time 62.22 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:29:46 AM UTC 24
Peak memory 253796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375728617 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.375728617 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3590853570
Short name T246
Test name
Test status
Simulation time 9274352263 ps
CPU time 860.87 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 06:43:14 AM UTC 24
Peak memory 710420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590853570 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3590853570
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.3893020783
Short name T506
Test name
Test status
Simulation time 234186266469 ps
CPU time 2165.79 seconds
Started Oct 12 06:28:43 AM UTC 24
Finished Oct 12 07:05:12 AM UTC 24
Peak memory 3037060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893020783 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3893020
783 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.1428480466
Short name T61
Test name
Test status
Simulation time 47434839 ps
CPU time 1.14 seconds
Started Oct 12 06:29:54 AM UTC 24
Finished Oct 12 06:29:56 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428480466 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1428480466 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.3085545941
Short name T194
Test name
Test status
Simulation time 19738996261 ps
CPU time 285.16 seconds
Started Oct 12 06:29:24 AM UTC 24
Finished Oct 12 06:34:13 AM UTC 24
Peak memory 325556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085545941 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3085545941 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.3115418271
Short name T52
Test name
Test status
Simulation time 3755217739 ps
CPU time 377.85 seconds
Started Oct 12 06:28:59 AM UTC 24
Finished Oct 12 06:35:22 AM UTC 24
Peak memory 245624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115418271 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3115418271 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.291308076
Short name T79
Test name
Test status
Simulation time 1104923837 ps
CPU time 38.64 seconds
Started Oct 12 06:29:45 AM UTC 24
Finished Oct 12 06:30:25 AM UTC 24
Peak memory 235236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291308076 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.291308076 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.600080344
Short name T95
Test name
Test status
Simulation time 444656888 ps
CPU time 10.45 seconds
Started Oct 12 06:29:45 AM UTC 24
Finished Oct 12 06:29:57 AM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600080344 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.600080344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.1915834524
Short name T22
Test name
Test status
Simulation time 2543503466 ps
CPU time 12.57 seconds
Started Oct 12 06:29:45 AM UTC 24
Finished Oct 12 06:29:59 AM UTC 24
Peak memory 231040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915834524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1915834524 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.2874065974
Short name T56
Test name
Test status
Simulation time 11295261616 ps
CPU time 173.97 seconds
Started Oct 12 06:29:28 AM UTC 24
Finished Oct 12 06:32:25 AM UTC 24
Peak memory 335936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874065974 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2874065974 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.4037435056
Short name T55
Test name
Test status
Simulation time 1628299970 ps
CPU time 125.52 seconds
Started Oct 12 06:29:34 AM UTC 24
Finished Oct 12 06:31:42 AM UTC 24
Peak memory 288572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037435056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.4037435056 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.1686546166
Short name T20
Test name
Test status
Simulation time 5019706130 ps
CPU time 9.1 seconds
Started Oct 12 06:29:44 AM UTC 24
Finished Oct 12 06:29:54 AM UTC 24
Peak memory 230896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686546166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1686546166 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.3530159683
Short name T5
Test name
Test status
Simulation time 46870793 ps
CPU time 2.91 seconds
Started Oct 12 06:29:46 AM UTC 24
Finished Oct 12 06:29:51 AM UTC 24
Peak memory 230808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530159683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3530159683 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.2018685603
Short name T270
Test name
Test status
Simulation time 36619473760 ps
CPU time 943.06 seconds
Started Oct 12 06:28:54 AM UTC 24
Finished Oct 12 06:44:48 AM UTC 24
Peak memory 1583032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018685603 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.2018685603 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.1891664614
Short name T33
Test name
Test status
Simulation time 10125766783 ps
CPU time 220.3 seconds
Started Oct 12 06:29:32 AM UTC 24
Finished Oct 12 06:33:16 AM UTC 24
Peak memory 444712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891664614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1891664614 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.1269249829
Short name T10
Test name
Test status
Simulation time 24080469062 ps
CPU time 80.47 seconds
Started Oct 12 06:29:52 AM UTC 24
Finished Oct 12 06:31:14 AM UTC 24
Peak memory 296392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269249829 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1269249829 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.2198923378
Short name T206
Test name
Test status
Simulation time 75231086513 ps
CPU time 438.62 seconds
Started Oct 12 06:28:54 AM UTC 24
Finished Oct 12 06:36:19 AM UTC 24
Peak memory 389248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198923378 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2198923378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.4078249181
Short name T322
Test name
Test status
Simulation time 37212732037 ps
CPU time 1179.25 seconds
Started Oct 12 06:29:48 AM UTC 24
Finished Oct 12 06:49:41 AM UTC 24
Peak memory 786652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078249181 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.4078249181 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2413622262
Short name T17
Test name
Test status
Simulation time 152056147 ps
CPU time 2.69 seconds
Started Oct 12 06:29:18 AM UTC 24
Finished Oct 12 06:29:22 AM UTC 24
Peak memory 231020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413622262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.2413622262 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3223327250
Short name T77
Test name
Test status
Simulation time 30782542 ps
CPU time 2.96 seconds
Started Oct 12 06:29:22 AM UTC 24
Finished Oct 12 06:29:26 AM UTC 24
Peak memory 230944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223327250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3223327250 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.4293334308
Short name T142
Test name
Test status
Simulation time 2690531656 ps
CPU time 47.37 seconds
Started Oct 12 06:29:04 AM UTC 24
Finished Oct 12 06:29:53 AM UTC 24
Peak memory 258000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293334308 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.4293334308
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.3258100148
Short name T94
Test name
Test status
Simulation time 586805046 ps
CPU time 41.22 seconds
Started Oct 12 06:29:04 AM UTC 24
Finished Oct 12 06:29:46 AM UTC 24
Peak memory 230900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258100148 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3258100148
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.2596425871
Short name T412
Test name
Test status
Simulation time 124799674603 ps
CPU time 1669.38 seconds
Started Oct 12 06:29:10 AM UTC 24
Finished Oct 12 06:57:19 AM UTC 24
Peak memory 2316188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596425871 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2596425871
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.949389816
Short name T337
Test name
Test status
Simulation time 62164512790 ps
CPU time 1333.29 seconds
Started Oct 12 06:29:13 AM UTC 24
Finished Oct 12 06:51:42 AM UTC 24
Peak memory 1711892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949389816 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.949389816 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.1637423796
Short name T181
Test name
Test status
Simulation time 9864537585 ps
CPU time 311.37 seconds
Started Oct 12 06:29:14 AM UTC 24
Finished Oct 12 06:34:30 AM UTC 24
Peak memory 444352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637423796 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1637423
796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.3624131786
Short name T531
Test name
Test status
Simulation time 233326967504 ps
CPU time 2213.48 seconds
Started Oct 12 06:29:15 AM UTC 24
Finished Oct 12 07:06:33 AM UTC 24
Peak memory 2906024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624131786 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3624131
786 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.3625310008
Short name T262
Test name
Test status
Simulation time 17783736 ps
CPU time 1.24 seconds
Started Oct 12 06:44:05 AM UTC 24
Finished Oct 12 06:44:07 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625310008 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3625310008 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.1649287101
Short name T290
Test name
Test status
Simulation time 6357118278 ps
CPU time 158.51 seconds
Started Oct 12 06:43:42 AM UTC 24
Finished Oct 12 06:46:24 AM UTC 24
Peak memory 356404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649287101 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1649287101 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.1701396757
Short name T309
Test name
Test status
Simulation time 21194946367 ps
CPU time 285.65 seconds
Started Oct 12 06:43:40 AM UTC 24
Finished Oct 12 06:48:31 AM UTC 24
Peak memory 245588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701396757 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1701396757 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.2722435322
Short name T263
Test name
Test status
Simulation time 1075831090 ps
CPU time 9.4 seconds
Started Oct 12 06:43:57 AM UTC 24
Finished Oct 12 06:44:07 AM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722435322 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2722435322 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.4207108707
Short name T274
Test name
Test status
Simulation time 1795234023 ps
CPU time 51.39 seconds
Started Oct 12 06:43:58 AM UTC 24
Finished Oct 12 06:44:51 AM UTC 24
Peak memory 235388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207108707 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.4207108707 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.1400361769
Short name T300
Test name
Test status
Simulation time 10358148918 ps
CPU time 213.48 seconds
Started Oct 12 06:43:42 AM UTC 24
Finished Oct 12 06:47:20 AM UTC 24
Peak memory 397344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400361769 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1400361769 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.575563394
Short name T31
Test name
Test status
Simulation time 43106883194 ps
CPU time 307.84 seconds
Started Oct 12 06:43:48 AM UTC 24
Finished Oct 12 06:49:00 AM UTC 24
Peak memory 350264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575563394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.575563394 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.3429332544
Short name T257
Test name
Test status
Simulation time 900430461 ps
CPU time 5.82 seconds
Started Oct 12 06:43:49 AM UTC 24
Finished Oct 12 06:43:56 AM UTC 24
Peak memory 230748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429332544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3429332544 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.2811738043
Short name T264
Test name
Test status
Simulation time 347000309 ps
CPU time 7.23 seconds
Started Oct 12 06:44:00 AM UTC 24
Finished Oct 12 06:44:08 AM UTC 24
Peak memory 235640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811738043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2811738043 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.3023993179
Short name T750
Test name
Test status
Simulation time 89592968882 ps
CPU time 3656.87 seconds
Started Oct 12 06:43:33 AM UTC 24
Finished Oct 12 07:45:10 AM UTC 24
Peak memory 4326592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023993179 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.3023993179 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload_invalid.3748796067
Short name T76
Test name
Test status
Simulation time 209831276 ps
CPU time 3.4 seconds
Started Oct 12 06:43:35 AM UTC 24
Finished Oct 12 06:43:40 AM UTC 24
Peak memory 231304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748796067 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload_invalid.3748796067 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.4068132307
Short name T187
Test name
Test status
Simulation time 732229510 ps
CPU time 8.42 seconds
Started Oct 12 06:43:32 AM UTC 24
Finished Oct 12 06:43:42 AM UTC 24
Peak memory 230944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068132307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.4068132307 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.2276434829
Short name T449
Test name
Test status
Simulation time 149253018907 ps
CPU time 996.31 seconds
Started Oct 12 06:44:04 AM UTC 24
Finished Oct 12 07:00:52 AM UTC 24
Peak memory 661820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276434829 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2276434829 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.1120480535
Short name T273
Test name
Test status
Simulation time 142364114 ps
CPU time 1.3 seconds
Started Oct 12 06:44:48 AM UTC 24
Finished Oct 12 06:44:51 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120480535 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1120480535 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.1644444680
Short name T271
Test name
Test status
Simulation time 4241537393 ps
CPU time 35.1 seconds
Started Oct 12 06:44:13 AM UTC 24
Finished Oct 12 06:44:49 AM UTC 24
Peak memory 255928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644444680 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1644444680 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.4006980337
Short name T54
Test name
Test status
Simulation time 699544089 ps
CPU time 25.39 seconds
Started Oct 12 06:44:12 AM UTC 24
Finished Oct 12 06:44:38 AM UTC 24
Peak memory 233008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006980337 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.4006980337 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.3785638008
Short name T275
Test name
Test status
Simulation time 1133981648 ps
CPU time 25.36 seconds
Started Oct 12 06:44:36 AM UTC 24
Finished Oct 12 06:45:03 AM UTC 24
Peak memory 235088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785638008 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3785638008 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.2412548944
Short name T280
Test name
Test status
Simulation time 1195827371 ps
CPU time 34.89 seconds
Started Oct 12 06:44:39 AM UTC 24
Finished Oct 12 06:45:15 AM UTC 24
Peak memory 235080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412548944 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2412548944 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.283090381
Short name T328
Test name
Test status
Simulation time 15255369378 ps
CPU time 356.48 seconds
Started Oct 12 06:44:14 AM UTC 24
Finished Oct 12 06:50:15 AM UTC 24
Peak memory 520192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283090381 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.283090381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.3095829626
Short name T267
Test name
Test status
Simulation time 335319817 ps
CPU time 3.71 seconds
Started Oct 12 06:44:31 AM UTC 24
Finished Oct 12 06:44:36 AM UTC 24
Peak memory 230956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095829626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3095829626 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.3906620821
Short name T268
Test name
Test status
Simulation time 1269754519 ps
CPU time 12.11 seconds
Started Oct 12 06:44:33 AM UTC 24
Finished Oct 12 06:44:46 AM UTC 24
Peak memory 230736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906620821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3906620821 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.2256921767
Short name T315
Test name
Test status
Simulation time 11263839409 ps
CPU time 291.59 seconds
Started Oct 12 06:44:08 AM UTC 24
Finished Oct 12 06:49:04 AM UTC 24
Peak memory 393184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256921767 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.2256921767 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.257216380
Short name T279
Test name
Test status
Simulation time 2359297839 ps
CPU time 63.21 seconds
Started Oct 12 06:44:08 AM UTC 24
Finished Oct 12 06:45:13 AM UTC 24
Peak memory 286644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257216380 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.257216380 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload_invalid.2736062564
Short name T265
Test name
Test status
Simulation time 136522906 ps
CPU time 1.57 seconds
Started Oct 12 06:44:09 AM UTC 24
Finished Oct 12 06:44:12 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736062564 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload_invalid.2736062564 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.4198234097
Short name T380
Test name
Test status
Simulation time 8915143642 ps
CPU time 622.51 seconds
Started Oct 12 06:44:47 AM UTC 24
Finished Oct 12 06:55:18 AM UTC 24
Peak memory 452920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198234097 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.4198234097 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.3838409326
Short name T283
Test name
Test status
Simulation time 13616988 ps
CPU time 1.19 seconds
Started Oct 12 06:45:19 AM UTC 24
Finished Oct 12 06:45:22 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838409326 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3838409326 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.1721703820
Short name T282
Test name
Test status
Simulation time 5879593895 ps
CPU time 23.16 seconds
Started Oct 12 06:44:57 AM UTC 24
Finished Oct 12 06:45:21 AM UTC 24
Peak memory 237460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721703820 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1721703820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.1655222181
Short name T284
Test name
Test status
Simulation time 981773438 ps
CPU time 18.84 seconds
Started Oct 12 06:45:09 AM UTC 24
Finished Oct 12 06:45:30 AM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655222181 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1655222181 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1749160014
Short name T287
Test name
Test status
Simulation time 1959147776 ps
CPU time 46.02 seconds
Started Oct 12 06:45:11 AM UTC 24
Finished Oct 12 06:45:59 AM UTC 24
Peak memory 235152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749160014 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1749160014 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2795400540
Short name T308
Test name
Test status
Simulation time 8907556277 ps
CPU time 178.5 seconds
Started Oct 12 06:45:04 AM UTC 24
Finished Oct 12 06:48:05 AM UTC 24
Peak memory 368568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795400540 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2795400540 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.1153669689
Short name T314
Test name
Test status
Simulation time 29821977999 ps
CPU time 234.41 seconds
Started Oct 12 06:45:04 AM UTC 24
Finished Oct 12 06:49:02 AM UTC 24
Peak memory 448444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153669689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1153669689 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.1310038539
Short name T281
Test name
Test status
Simulation time 5964301338 ps
CPU time 10.48 seconds
Started Oct 12 06:45:07 AM UTC 24
Finished Oct 12 06:45:19 AM UTC 24
Peak memory 230904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310038539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.1310038539 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.917784076
Short name T124
Test name
Test status
Simulation time 1002403122 ps
CPU time 10.03 seconds
Started Oct 12 06:45:14 AM UTC 24
Finished Oct 12 06:45:26 AM UTC 24
Peak memory 241268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917784076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.917784076 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.3445432983
Short name T313
Test name
Test status
Simulation time 31833529770 ps
CPU time 242.8 seconds
Started Oct 12 06:44:50 AM UTC 24
Finished Oct 12 06:48:57 AM UTC 24
Peak memory 481320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445432983 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.3445432983 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.2942881259
Short name T277
Test name
Test status
Simulation time 1712140401 ps
CPU time 16.81 seconds
Started Oct 12 06:44:51 AM UTC 24
Finished Oct 12 06:45:08 AM UTC 24
Peak memory 233220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942881259 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2942881259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload_invalid.210820417
Short name T127
Test name
Test status
Simulation time 67172531 ps
CPU time 2.98 seconds
Started Oct 12 06:44:52 AM UTC 24
Finished Oct 12 06:44:56 AM UTC 24
Peak memory 233152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210820417 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload_invalid.210820417 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.3606056759
Short name T278
Test name
Test status
Simulation time 2525501363 ps
CPU time 21.05 seconds
Started Oct 12 06:44:48 AM UTC 24
Finished Oct 12 06:45:11 AM UTC 24
Peak memory 231148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606056759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3606056759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.1141274370
Short name T345
Test name
Test status
Simulation time 4677740332 ps
CPU time 419.46 seconds
Started Oct 12 06:45:16 AM UTC 24
Finished Oct 12 06:52:22 AM UTC 24
Peak memory 376704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141274370 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1141274370 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.508542006
Short name T292
Test name
Test status
Simulation time 16968048 ps
CPU time 1.2 seconds
Started Oct 12 06:46:29 AM UTC 24
Finished Oct 12 06:46:32 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508542006 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.508542006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.789020304
Short name T326
Test name
Test status
Simulation time 4163340349 ps
CPU time 253.86 seconds
Started Oct 12 06:45:54 AM UTC 24
Finished Oct 12 06:50:11 AM UTC 24
Peak memory 323636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789020304 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.789020304 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.2594732867
Short name T151
Test name
Test status
Simulation time 3577709701 ps
CPU time 154.87 seconds
Started Oct 12 06:45:40 AM UTC 24
Finished Oct 12 06:48:17 AM UTC 24
Peak memory 237484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594732867 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2594732867 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2316027401
Short name T299
Test name
Test status
Simulation time 1975052903 ps
CPU time 56.5 seconds
Started Oct 12 06:46:19 AM UTC 24
Finished Oct 12 06:47:17 AM UTC 24
Peak memory 232820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316027401 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2316027401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.1804448556
Short name T297
Test name
Test status
Simulation time 10834571516 ps
CPU time 50.23 seconds
Started Oct 12 06:46:20 AM UTC 24
Finished Oct 12 06:47:12 AM UTC 24
Peak memory 243092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804448556 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1804448556 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.1446434166
Short name T296
Test name
Test status
Simulation time 27754552052 ps
CPU time 56.37 seconds
Started Oct 12 06:45:57 AM UTC 24
Finished Oct 12 06:46:55 AM UTC 24
Peak memory 270236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446434166 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1446434166 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.3462294015
Short name T331
Test name
Test status
Simulation time 49952289069 ps
CPU time 273.71 seconds
Started Oct 12 06:46:01 AM UTC 24
Finished Oct 12 06:50:38 AM UTC 24
Peak memory 497588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462294015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3462294015 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.3936953722
Short name T289
Test name
Test status
Simulation time 5904211469 ps
CPU time 14.94 seconds
Started Oct 12 06:46:03 AM UTC 24
Finished Oct 12 06:46:19 AM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936953722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3936953722 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.2693882590
Short name T8
Test name
Test status
Simulation time 44175763 ps
CPU time 1.88 seconds
Started Oct 12 06:46:25 AM UTC 24
Finished Oct 12 06:46:28 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693882590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2693882590 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.2838301082
Short name T738
Test name
Test status
Simulation time 102155412777 ps
CPU time 2774.95 seconds
Started Oct 12 06:45:23 AM UTC 24
Finished Oct 12 07:32:09 AM UTC 24
Peak memory 1779576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838301082 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.2838301082 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.2862282629
Short name T298
Test name
Test status
Simulation time 3927341642 ps
CPU time 105.1 seconds
Started Oct 12 06:45:28 AM UTC 24
Finished Oct 12 06:47:15 AM UTC 24
Peak memory 264116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862282629 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2862282629 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload_invalid.908724242
Short name T128
Test name
Test status
Simulation time 176097535 ps
CPU time 7.11 seconds
Started Oct 12 06:45:31 AM UTC 24
Finished Oct 12 06:45:39 AM UTC 24
Peak memory 231436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908724242 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload_invalid.908724242 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.1034450524
Short name T288
Test name
Test status
Simulation time 1811743011 ps
CPU time 37.17 seconds
Started Oct 12 06:45:22 AM UTC 24
Finished Oct 12 06:46:01 AM UTC 24
Peak memory 235296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034450524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.1034450524 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.83403141
Short name T384
Test name
Test status
Simulation time 39597813958 ps
CPU time 542.55 seconds
Started Oct 12 06:46:27 AM UTC 24
Finished Oct 12 06:55:37 AM UTC 24
Peak memory 397700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83403141 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.83403141 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.979138734
Short name T305
Test name
Test status
Simulation time 58090380 ps
CPU time 1.33 seconds
Started Oct 12 06:47:38 AM UTC 24
Finished Oct 12 06:47:40 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979138734 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.979138734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.2065242904
Short name T350
Test name
Test status
Simulation time 32479715497 ps
CPU time 341.62 seconds
Started Oct 12 06:46:56 AM UTC 24
Finished Oct 12 06:52:42 AM UTC 24
Peak memory 538524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065242904 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2065242904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.3560076808
Short name T343
Test name
Test status
Simulation time 7259718208 ps
CPU time 322.99 seconds
Started Oct 12 06:46:48 AM UTC 24
Finished Oct 12 06:52:16 AM UTC 24
Peak memory 243576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560076808 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3560076808 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2750937525
Short name T306
Test name
Test status
Simulation time 1317380658 ps
CPU time 20.19 seconds
Started Oct 12 06:47:20 AM UTC 24
Finished Oct 12 06:47:42 AM UTC 24
Peak memory 234936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750937525 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2750937525 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.701090630
Short name T302
Test name
Test status
Simulation time 412783837 ps
CPU time 5.5 seconds
Started Oct 12 06:47:26 AM UTC 24
Finished Oct 12 06:47:33 AM UTC 24
Peak memory 230824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701090630 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.701090630 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.534036729
Short name T333
Test name
Test status
Simulation time 8864040769 ps
CPU time 218.71 seconds
Started Oct 12 06:47:13 AM UTC 24
Finished Oct 12 06:50:55 AM UTC 24
Peak memory 366520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534036729 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.534036729 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.3205942780
Short name T347
Test name
Test status
Simulation time 12022151249 ps
CPU time 310.39 seconds
Started Oct 12 06:47:16 AM UTC 24
Finished Oct 12 06:52:31 AM UTC 24
Peak memory 380928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205942780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3205942780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.1213923010
Short name T301
Test name
Test status
Simulation time 2226305217 ps
CPU time 6.26 seconds
Started Oct 12 06:47:18 AM UTC 24
Finished Oct 12 06:47:26 AM UTC 24
Peak memory 230828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213923010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1213923010 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.910726489
Short name T304
Test name
Test status
Simulation time 54581289 ps
CPU time 2.17 seconds
Started Oct 12 06:47:34 AM UTC 24
Finished Oct 12 06:47:37 AM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910726489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.910726489 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.2425121413
Short name T454
Test name
Test status
Simulation time 25377232265 ps
CPU time 875.38 seconds
Started Oct 12 06:46:33 AM UTC 24
Finished Oct 12 07:01:18 AM UTC 24
Peak memory 1400812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425121413 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.2425121413 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.1535860774
Short name T332
Test name
Test status
Simulation time 7957771773 ps
CPU time 240.14 seconds
Started Oct 12 06:46:43 AM UTC 24
Finished Oct 12 06:50:47 AM UTC 24
Peak memory 409468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535860774 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1535860774 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload_invalid.2757696771
Short name T295
Test name
Test status
Simulation time 61743547 ps
CPU time 2.35 seconds
Started Oct 12 06:46:44 AM UTC 24
Finished Oct 12 06:46:47 AM UTC 24
Peak memory 231344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757696771 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload_invalid.2757696771 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.3910817741
Short name T294
Test name
Test status
Simulation time 310722832 ps
CPU time 7.89 seconds
Started Oct 12 06:46:33 AM UTC 24
Finished Oct 12 06:46:42 AM UTC 24
Peak memory 230968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910817741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3910817741 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.3485415732
Short name T472
Test name
Test status
Simulation time 57322995595 ps
CPU time 912.24 seconds
Started Oct 12 06:47:35 AM UTC 24
Finished Oct 12 07:02:58 AM UTC 24
Peak memory 688572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485415732 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3485415732 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.2213154340
Short name T316
Test name
Test status
Simulation time 18113475 ps
CPU time 1.27 seconds
Started Oct 12 06:49:03 AM UTC 24
Finished Oct 12 06:49:05 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213154340 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2213154340 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.1870268470
Short name T320
Test name
Test status
Simulation time 5120844114 ps
CPU time 66.46 seconds
Started Oct 12 06:48:14 AM UTC 24
Finished Oct 12 06:49:23 AM UTC 24
Peak memory 276408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870268470 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1870268470 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.152558857
Short name T433
Test name
Test status
Simulation time 6043970571 ps
CPU time 649.6 seconds
Started Oct 12 06:48:06 AM UTC 24
Finished Oct 12 06:59:04 AM UTC 24
Peak memory 251740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152558857 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.152558857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.3278536929
Short name T321
Test name
Test status
Simulation time 6188206209 ps
CPU time 38.66 seconds
Started Oct 12 06:48:48 AM UTC 24
Finished Oct 12 06:49:28 AM UTC 24
Peak memory 235244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278536929 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3278536929 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.3194979277
Short name T319
Test name
Test status
Simulation time 1112561748 ps
CPU time 24.71 seconds
Started Oct 12 06:48:51 AM UTC 24
Finished Oct 12 06:49:17 AM UTC 24
Peak memory 235112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194979277 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3194979277 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.1705549968
Short name T356
Test name
Test status
Simulation time 4058252270 ps
CPU time 288.72 seconds
Started Oct 12 06:48:18 AM UTC 24
Finished Oct 12 06:53:12 AM UTC 24
Peak memory 327600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705549968 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1705549968 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.2799418862
Short name T364
Test name
Test status
Simulation time 12517809676 ps
CPU time 307.79 seconds
Started Oct 12 06:48:32 AM UTC 24
Finished Oct 12 06:53:44 AM UTC 24
Peak memory 348220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799418862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2799418862 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.1489694036
Short name T312
Test name
Test status
Simulation time 1853970285 ps
CPU time 16.57 seconds
Started Oct 12 06:48:32 AM UTC 24
Finished Oct 12 06:48:50 AM UTC 24
Peak memory 230840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489694036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1489694036 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.1819376316
Short name T317
Test name
Test status
Simulation time 619814080 ps
CPU time 9.6 seconds
Started Oct 12 06:48:58 AM UTC 24
Finished Oct 12 06:49:09 AM UTC 24
Peak memory 245748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819376316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1819376316 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.667787461
Short name T307
Test name
Test status
Simulation time 397027060 ps
CPU time 22.69 seconds
Started Oct 12 06:47:41 AM UTC 24
Finished Oct 12 06:48:05 AM UTC 24
Peak memory 241132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667787461 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.667787461 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.2675647788
Short name T318
Test name
Test status
Simulation time 39267976522 ps
CPU time 85.64 seconds
Started Oct 12 06:47:43 AM UTC 24
Finished Oct 12 06:49:11 AM UTC 24
Peak memory 264124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675647788 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2675647788 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.1200397264
Short name T310
Test name
Test status
Simulation time 9386278893 ps
CPU time 50.55 seconds
Started Oct 12 06:47:39 AM UTC 24
Finished Oct 12 06:48:31 AM UTC 24
Peak memory 231088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200397264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1200397264 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.795195596
Short name T388
Test name
Test status
Simulation time 16441053322 ps
CPU time 399.02 seconds
Started Oct 12 06:49:01 AM UTC 24
Finished Oct 12 06:55:46 AM UTC 24
Peak memory 418112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795195596 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.795195596 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.408684854
Short name T327
Test name
Test status
Simulation time 27614807 ps
CPU time 1.29 seconds
Started Oct 12 06:50:09 AM UTC 24
Finished Oct 12 06:50:12 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408684854 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.408684854 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.4101859988
Short name T351
Test name
Test status
Simulation time 143036990106 ps
CPU time 198.02 seconds
Started Oct 12 06:49:24 AM UTC 24
Finished Oct 12 06:52:45 AM UTC 24
Peak memory 407464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101859988 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.4101859988 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.1369409219
Short name T452
Test name
Test status
Simulation time 33093617768 ps
CPU time 700.69 seconds
Started Oct 12 06:49:18 AM UTC 24
Finished Oct 12 07:01:06 AM UTC 24
Peak memory 251804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369409219 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.1369409219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2927146341
Short name T324
Test name
Test status
Simulation time 135305819 ps
CPU time 5.32 seconds
Started Oct 12 06:49:49 AM UTC 24
Finished Oct 12 06:49:55 AM UTC 24
Peak memory 228852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927146341 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2927146341 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.3714335238
Short name T329
Test name
Test status
Simulation time 217768807 ps
CPU time 20.9 seconds
Started Oct 12 06:49:56 AM UTC 24
Finished Oct 12 06:50:18 AM UTC 24
Peak memory 235228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714335238 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3714335238 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.2886326819
Short name T349
Test name
Test status
Simulation time 9696988618 ps
CPU time 188.12 seconds
Started Oct 12 06:49:29 AM UTC 24
Finished Oct 12 06:52:40 AM UTC 24
Peak memory 374768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886326819 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2886326819 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.1512066808
Short name T367
Test name
Test status
Simulation time 11318515670 ps
CPU time 255.59 seconds
Started Oct 12 06:49:37 AM UTC 24
Finished Oct 12 06:53:56 AM UTC 24
Peak memory 329592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512066808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1512066808 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.2831920844
Short name T323
Test name
Test status
Simulation time 1618121271 ps
CPU time 4.95 seconds
Started Oct 12 06:49:42 AM UTC 24
Finished Oct 12 06:49:48 AM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831920844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2831920844 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.2660037880
Short name T68
Test name
Test status
Simulation time 2006978012 ps
CPU time 8.65 seconds
Started Oct 12 06:49:59 AM UTC 24
Finished Oct 12 06:50:09 AM UTC 24
Peak memory 241412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660037880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2660037880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.1509428190
Short name T485
Test name
Test status
Simulation time 330874266447 ps
CPU time 865.68 seconds
Started Oct 12 06:49:06 AM UTC 24
Finished Oct 12 07:03:42 AM UTC 24
Peak memory 1323128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509428190 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.1509428190 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.4227217492
Short name T362
Test name
Test status
Simulation time 21195317445 ps
CPU time 264.42 seconds
Started Oct 12 06:49:10 AM UTC 24
Finished Oct 12 06:53:39 AM UTC 24
Peak memory 444280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227217492 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.4227217492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.4234701575
Short name T325
Test name
Test status
Simulation time 3103770149 ps
CPU time 51.35 seconds
Started Oct 12 06:49:05 AM UTC 24
Finished Oct 12 06:49:58 AM UTC 24
Peak memory 235104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234701575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.4234701575 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.1731222421
Short name T493
Test name
Test status
Simulation time 44858513433 ps
CPU time 854.68 seconds
Started Oct 12 06:50:04 AM UTC 24
Finished Oct 12 07:04:30 AM UTC 24
Peak memory 661428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731222421 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1731222421 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.3214798294
Short name T339
Test name
Test status
Simulation time 59211926 ps
CPU time 1.35 seconds
Started Oct 12 06:51:46 AM UTC 24
Finished Oct 12 06:51:48 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214798294 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3214798294 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.1136406853
Short name T391
Test name
Test status
Simulation time 40960068562 ps
CPU time 314.07 seconds
Started Oct 12 06:50:39 AM UTC 24
Finished Oct 12 06:55:58 AM UTC 24
Peak memory 505844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136406853 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1136406853 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.27935402
Short name T471
Test name
Test status
Simulation time 16710770481 ps
CPU time 743.66 seconds
Started Oct 12 06:50:23 AM UTC 24
Finished Oct 12 07:02:56 AM UTC 24
Peak memory 251824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27935402 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.27935402 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3961082977
Short name T344
Test name
Test status
Simulation time 7822864619 ps
CPU time 52.98 seconds
Started Oct 12 06:51:25 AM UTC 24
Finished Oct 12 06:52:19 AM UTC 24
Peak memory 232952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961082977 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3961082977 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.3002366825
Short name T340
Test name
Test status
Simulation time 692404353 ps
CPU time 31.03 seconds
Started Oct 12 06:51:26 AM UTC 24
Finished Oct 12 06:51:58 AM UTC 24
Peak memory 232996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002366825 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3002366825 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.21727176
Short name T382
Test name
Test status
Simulation time 15515495348 ps
CPU time 280.28 seconds
Started Oct 12 06:50:47 AM UTC 24
Finished Oct 12 06:55:32 AM UTC 24
Peak memory 503656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21727176 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.21727176 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.1935104751
Short name T401
Test name
Test status
Simulation time 57301918795 ps
CPU time 348.52 seconds
Started Oct 12 06:50:56 AM UTC 24
Finished Oct 12 06:56:49 AM UTC 24
Peak memory 589696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935104751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1935104751 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.3957455107
Short name T335
Test name
Test status
Simulation time 6458372123 ps
CPU time 16.76 seconds
Started Oct 12 06:51:05 AM UTC 24
Finished Oct 12 06:51:24 AM UTC 24
Peak memory 230964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957455107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3957455107 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.2647945219
Short name T341
Test name
Test status
Simulation time 535057516 ps
CPU time 14.54 seconds
Started Oct 12 06:51:43 AM UTC 24
Finished Oct 12 06:51:59 AM UTC 24
Peak memory 235432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647945219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2647945219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.4261611782
Short name T434
Test name
Test status
Simulation time 12375402528 ps
CPU time 526.18 seconds
Started Oct 12 06:50:13 AM UTC 24
Finished Oct 12 06:59:06 AM UTC 24
Peak memory 585588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261611782 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.4261611782 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.2449159157
Short name T392
Test name
Test status
Simulation time 24928312090 ps
CPU time 338.75 seconds
Started Oct 12 06:50:16 AM UTC 24
Finished Oct 12 06:55:59 AM UTC 24
Peak memory 348080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449159157 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2449159157 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload_invalid.2816293342
Short name T330
Test name
Test status
Simulation time 33689781 ps
CPU time 2.44 seconds
Started Oct 12 06:50:19 AM UTC 24
Finished Oct 12 06:50:22 AM UTC 24
Peak memory 231340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816293342 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload_invalid.2816293342 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.1252554022
Short name T334
Test name
Test status
Simulation time 12341283260 ps
CPU time 50.61 seconds
Started Oct 12 06:50:13 AM UTC 24
Finished Oct 12 06:51:05 AM UTC 24
Peak memory 235488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252554022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1252554022 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.3893849775
Short name T739
Test name
Test status
Simulation time 78453864932 ps
CPU time 2425.57 seconds
Started Oct 12 06:51:43 AM UTC 24
Finished Oct 12 07:32:35 AM UTC 24
Peak memory 1241656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893849775 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3893849775 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.3209996109
Short name T352
Test name
Test status
Simulation time 63486612 ps
CPU time 1.23 seconds
Started Oct 12 06:52:45 AM UTC 24
Finished Oct 12 06:52:47 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209996109 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3209996109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.1736201211
Short name T357
Test name
Test status
Simulation time 8613939809 ps
CPU time 58.44 seconds
Started Oct 12 06:52:17 AM UTC 24
Finished Oct 12 06:53:18 AM UTC 24
Peak memory 276408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736201211 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1736201211 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.4152543407
Short name T556
Test name
Test status
Simulation time 28359527679 ps
CPU time 960.29 seconds
Started Oct 12 06:52:16 AM UTC 24
Finished Oct 12 07:08:29 AM UTC 24
Peak memory 266164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152543407 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.4152543407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.1816135313
Short name T353
Test name
Test status
Simulation time 1044101080 ps
CPU time 26.29 seconds
Started Oct 12 06:52:32 AM UTC 24
Finished Oct 12 06:52:59 AM UTC 24
Peak memory 230892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816135313 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1816135313 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1678993458
Short name T360
Test name
Test status
Simulation time 8486277866 ps
CPU time 54.56 seconds
Started Oct 12 06:52:33 AM UTC 24
Finished Oct 12 06:53:29 AM UTC 24
Peak memory 235060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678993458 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1678993458 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.3616315328
Short name T359
Test name
Test status
Simulation time 9290652370 ps
CPU time 65.43 seconds
Started Oct 12 06:52:20 AM UTC 24
Finished Oct 12 06:53:27 AM UTC 24
Peak memory 272308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616315328 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3616315328 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.3366654896
Short name T393
Test name
Test status
Simulation time 10288382930 ps
CPU time 228.27 seconds
Started Oct 12 06:52:23 AM UTC 24
Finished Oct 12 06:56:15 AM UTC 24
Peak memory 317344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366654896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3366654896 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.1726247262
Short name T348
Test name
Test status
Simulation time 190530755 ps
CPU time 2.8 seconds
Started Oct 12 06:52:28 AM UTC 24
Finished Oct 12 06:52:32 AM UTC 24
Peak memory 230704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726247262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1726247262 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.2991868756
Short name T73
Test name
Test status
Simulation time 72165316 ps
CPU time 1.84 seconds
Started Oct 12 06:52:41 AM UTC 24
Finished Oct 12 06:52:44 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991868756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2991868756 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.3007184822
Short name T468
Test name
Test status
Simulation time 60115962542 ps
CPU time 628.71 seconds
Started Oct 12 06:51:59 AM UTC 24
Finished Oct 12 07:02:36 AM UTC 24
Peak memory 913332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007184822 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.3007184822 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.1410961859
Short name T424
Test name
Test status
Simulation time 17754603353 ps
CPU time 386.67 seconds
Started Oct 12 06:51:59 AM UTC 24
Finished Oct 12 06:58:31 AM UTC 24
Peak memory 628736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410961859 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1410961859 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload_invalid.3645168719
Short name T102
Test name
Test status
Simulation time 164860424 ps
CPU time 4.63 seconds
Started Oct 12 06:52:11 AM UTC 24
Finished Oct 12 06:52:17 AM UTC 24
Peak memory 231440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645168719 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload_invalid.3645168719 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2892847631
Short name T346
Test name
Test status
Simulation time 2679702214 ps
CPU time 36.12 seconds
Started Oct 12 06:51:49 AM UTC 24
Finished Oct 12 06:52:27 AM UTC 24
Peak memory 235524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892847631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2892847631 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.3012508039
Short name T368
Test name
Test status
Simulation time 1363808237 ps
CPU time 83.99 seconds
Started Oct 12 06:52:43 AM UTC 24
Finished Oct 12 06:54:09 AM UTC 24
Peak memory 245292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012508039 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3012508039 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.3678160268
Short name T365
Test name
Test status
Simulation time 69841832 ps
CPU time 1.24 seconds
Started Oct 12 06:53:46 AM UTC 24
Finished Oct 12 06:53:48 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678160268 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3678160268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.571137917
Short name T378
Test name
Test status
Simulation time 1674005916 ps
CPU time 96.5 seconds
Started Oct 12 06:53:13 AM UTC 24
Finished Oct 12 06:54:51 AM UTC 24
Peak memory 276280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571137917 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.571137917 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.3510713777
Short name T617
Test name
Test status
Simulation time 31637079695 ps
CPU time 1200.12 seconds
Started Oct 12 06:53:11 AM UTC 24
Finished Oct 12 07:13:25 AM UTC 24
Peak memory 268208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510713777 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3510713777 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.28459170
Short name T370
Test name
Test status
Simulation time 2116585790 ps
CPU time 42.83 seconds
Started Oct 12 06:53:30 AM UTC 24
Finished Oct 12 06:54:15 AM UTC 24
Peak memory 235184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28459170 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.28459170 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.4200905257
Short name T366
Test name
Test status
Simulation time 488841928 ps
CPU time 12.44 seconds
Started Oct 12 06:53:39 AM UTC 24
Finished Oct 12 06:53:53 AM UTC 24
Peak memory 228768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200905257 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.4200905257 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.4220201470
Short name T358
Test name
Test status
Simulation time 446821568 ps
CPU time 6.23 seconds
Started Oct 12 06:53:19 AM UTC 24
Finished Oct 12 06:53:26 AM UTC 24
Peak memory 231020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220201470 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.4220201470 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.3265689094
Short name T403
Test name
Test status
Simulation time 20321180969 ps
CPU time 206.29 seconds
Started Oct 12 06:53:27 AM UTC 24
Finished Oct 12 06:56:57 AM UTC 24
Peak memory 366524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265689094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3265689094 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.2471877976
Short name T361
Test name
Test status
Simulation time 2000295830 ps
CPU time 9.71 seconds
Started Oct 12 06:53:28 AM UTC 24
Finished Oct 12 06:53:39 AM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471877976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2471877976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.1717540370
Short name T363
Test name
Test status
Simulation time 103681580 ps
CPU time 1.95 seconds
Started Oct 12 06:53:40 AM UTC 24
Finished Oct 12 06:53:43 AM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717540370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1717540370 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.3169312202
Short name T714
Test name
Test status
Simulation time 34870178428 ps
CPU time 1711.82 seconds
Started Oct 12 06:52:48 AM UTC 24
Finished Oct 12 07:21:40 AM UTC 24
Peak memory 1292204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169312202 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.3169312202 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.3258027344
Short name T418
Test name
Test status
Simulation time 35825811423 ps
CPU time 274.98 seconds
Started Oct 12 06:53:01 AM UTC 24
Finished Oct 12 06:57:40 AM UTC 24
Peak memory 479292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258027344 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3258027344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload_invalid.3523427049
Short name T355
Test name
Test status
Simulation time 316328439 ps
CPU time 6.13 seconds
Started Oct 12 06:53:03 AM UTC 24
Finished Oct 12 06:53:10 AM UTC 24
Peak memory 233348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523427049 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload_invalid.3523427049 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.1217710044
Short name T354
Test name
Test status
Simulation time 619463900 ps
CPU time 15.02 seconds
Started Oct 12 06:52:45 AM UTC 24
Finished Oct 12 06:53:02 AM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217710044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1217710044 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.3244768999
Short name T423
Test name
Test status
Simulation time 12672959754 ps
CPU time 280.12 seconds
Started Oct 12 06:53:44 AM UTC 24
Finished Oct 12 06:58:29 AM UTC 24
Peak memory 516028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244768999 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3244768999 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.2194196410
Short name T62
Test name
Test status
Simulation time 18783667 ps
CPU time 1.24 seconds
Started Oct 12 06:31:24 AM UTC 24
Finished Oct 12 06:31:26 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194196410 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2194196410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.459139279
Short name T36
Test name
Test status
Simulation time 39535909222 ps
CPU time 216.32 seconds
Started Oct 12 06:30:39 AM UTC 24
Finished Oct 12 06:34:19 AM UTC 24
Peak memory 434284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459139279 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.459139279 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.2057381934
Short name T24
Test name
Test status
Simulation time 5502584917 ps
CPU time 20.01 seconds
Started Oct 12 06:30:40 AM UTC 24
Finished Oct 12 06:31:02 AM UTC 24
Peak memory 251824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057381934 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2057381934 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.735546970
Short name T51
Test name
Test status
Simulation time 2865893632 ps
CPU time 289.81 seconds
Started Oct 12 06:30:06 AM UTC 24
Finished Oct 12 06:35:00 AM UTC 24
Peak memory 249720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735546970 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.735546970 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2542222646
Short name T143
Test name
Test status
Simulation time 1148123755 ps
CPU time 31.91 seconds
Started Oct 12 06:31:02 AM UTC 24
Finished Oct 12 06:31:35 AM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542222646 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2542222646 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.2160583411
Short name T60
Test name
Test status
Simulation time 352938811 ps
CPU time 23.26 seconds
Started Oct 12 06:31:02 AM UTC 24
Finished Oct 12 06:31:27 AM UTC 24
Peak memory 230828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160583411 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2160583411 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.4019481270
Short name T59
Test name
Test status
Simulation time 11131317236 ps
CPU time 80.96 seconds
Started Oct 12 06:31:05 AM UTC 24
Finished Oct 12 06:32:28 AM UTC 24
Peak memory 230984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019481270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.4019481270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.2031196250
Short name T57
Test name
Test status
Simulation time 4038798522 ps
CPU time 197.96 seconds
Started Oct 12 06:30:45 AM UTC 24
Finished Oct 12 06:34:07 AM UTC 24
Peak memory 302976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031196250 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.2031196250 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.2830086258
Short name T35
Test name
Test status
Simulation time 96766453313 ps
CPU time 306.39 seconds
Started Oct 12 06:30:57 AM UTC 24
Finished Oct 12 06:36:08 AM UTC 24
Peak memory 393088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830086258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2830086258 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.3025289041
Short name T49
Test name
Test status
Simulation time 760133614 ps
CPU time 4.22 seconds
Started Oct 12 06:30:59 AM UTC 24
Finished Oct 12 06:31:04 AM UTC 24
Peak memory 230764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025289041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3025289041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.1526771974
Short name T46
Test name
Test status
Simulation time 66294175 ps
CPU time 1.46 seconds
Started Oct 12 06:31:08 AM UTC 24
Finished Oct 12 06:31:11 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526771974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1526771974 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.2791912001
Short name T231
Test name
Test status
Simulation time 93126863809 ps
CPU time 687.03 seconds
Started Oct 12 06:29:57 AM UTC 24
Finished Oct 12 06:41:32 AM UTC 24
Peak memory 1150888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791912001 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.2791912001 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.1160422515
Short name T86
Test name
Test status
Simulation time 13544197725 ps
CPU time 451.93 seconds
Started Oct 12 06:30:47 AM UTC 24
Finished Oct 12 06:38:24 AM UTC 24
Peak memory 530752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160422515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1160422515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.643990494
Short name T96
Test name
Test status
Simulation time 2155141373 ps
CPU time 68.67 seconds
Started Oct 12 06:29:58 AM UTC 24
Finished Oct 12 06:31:09 AM UTC 24
Peak memory 288696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643990494 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.643990494 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload_invalid.429449625
Short name T26
Test name
Test status
Simulation time 397286853 ps
CPU time 4.09 seconds
Started Oct 12 06:30:00 AM UTC 24
Finished Oct 12 06:30:06 AM UTC 24
Peak memory 231416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429449625 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload_invalid.429449625 +enable_masking=0 +s
w_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.4208050568
Short name T83
Test name
Test status
Simulation time 3815097115 ps
CPU time 48.11 seconds
Started Oct 12 06:29:55 AM UTC 24
Finished Oct 12 06:30:44 AM UTC 24
Peak memory 230956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208050568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.4208050568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.345800063
Short name T53
Test name
Test status
Simulation time 9601432200 ps
CPU time 774.78 seconds
Started Oct 12 06:31:09 AM UTC 24
Finished Oct 12 06:44:13 AM UTC 24
Peak memory 608176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345800063 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.345800063 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.2183102566
Short name T44
Test name
Test status
Simulation time 4079282776 ps
CPU time 117.32 seconds
Started Oct 12 06:31:11 AM UTC 24
Finished Oct 12 06:33:11 AM UTC 24
Peak memory 282680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2183102566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_
with_rand_reset.2183102566 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.1025122826
Short name T81
Test name
Test status
Simulation time 413113994 ps
CPU time 4.28 seconds
Started Oct 12 06:30:33 AM UTC 24
Finished Oct 12 06:30:39 AM UTC 24
Peak memory 230916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025122826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.1025122826 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.891313849
Short name T82
Test name
Test status
Simulation time 110399067 ps
CPU time 4.39 seconds
Started Oct 12 06:30:34 AM UTC 24
Finished Oct 12 06:30:40 AM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891313849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.891313849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.400865510
Short name T416
Test name
Test status
Simulation time 18501248386 ps
CPU time 1622.16 seconds
Started Oct 12 06:30:07 AM UTC 24
Finished Oct 12 06:57:27 AM UTC 24
Peak memory 1191704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400865510 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.400865510 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.523052567
Short name T425
Test name
Test status
Simulation time 35112240099 ps
CPU time 1679.93 seconds
Started Oct 12 06:30:14 AM UTC 24
Finished Oct 12 06:58:33 AM UTC 24
Peak memory 1142556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523052567 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.523052567 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1532608901
Short name T120
Test name
Test status
Simulation time 3463591288 ps
CPU time 41.09 seconds
Started Oct 12 06:30:25 AM UTC 24
Finished Oct 12 06:31:07 AM UTC 24
Peak memory 239464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532608901 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1532608901
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.1218437024
Short name T84
Test name
Test status
Simulation time 290489483 ps
CPU time 19.05 seconds
Started Oct 12 06:30:26 AM UTC 24
Finished Oct 12 06:30:46 AM UTC 24
Peak memory 228916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218437024 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1218437024
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.468054926
Short name T184
Test name
Test status
Simulation time 119537897722 ps
CPU time 258.58 seconds
Started Oct 12 06:30:28 AM UTC 24
Finished Oct 12 06:34:51 AM UTC 24
Peak memory 282580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468054926 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.46805492
6 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2426339973
Short name T592
Test name
Test status
Simulation time 121217439936 ps
CPU time 2434.11 seconds
Started Oct 12 06:30:29 AM UTC 24
Finished Oct 12 07:11:29 AM UTC 24
Peak memory 2977580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426339973 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2426339
973 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.4096923996
Short name T376
Test name
Test status
Simulation time 29673188 ps
CPU time 1.04 seconds
Started Oct 12 06:54:39 AM UTC 24
Finished Oct 12 06:54:41 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096923996 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4096923996 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.59866772
Short name T256
Test name
Test status
Simulation time 5007398147 ps
CPU time 336.02 seconds
Started Oct 12 06:54:15 AM UTC 24
Finished Oct 12 06:59:56 AM UTC 24
Peak memory 350140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59866772 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.59866772 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.1962342310
Short name T585
Test name
Test status
Simulation time 26564194626 ps
CPU time 1002.5 seconds
Started Oct 12 06:54:15 AM UTC 24
Finished Oct 12 07:11:09 AM UTC 24
Peak memory 270256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962342310 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1962342310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.764279401
Short name T417
Test name
Test status
Simulation time 5425849819 ps
CPU time 189.81 seconds
Started Oct 12 06:54:16 AM UTC 24
Finished Oct 12 06:57:29 AM UTC 24
Peak memory 298932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764279401 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.764279401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.1188839719
Short name T394
Test name
Test status
Simulation time 2699517886 ps
CPU time 114.44 seconds
Started Oct 12 06:54:18 AM UTC 24
Finished Oct 12 06:56:15 AM UTC 24
Peak memory 278512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188839719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1188839719 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.131639401
Short name T373
Test name
Test status
Simulation time 402552681 ps
CPU time 2.71 seconds
Started Oct 12 06:54:29 AM UTC 24
Finished Oct 12 06:54:33 AM UTC 24
Peak memory 230896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131639401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.131639401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.1916613974
Short name T375
Test name
Test status
Simulation time 61798694 ps
CPU time 2.02 seconds
Started Oct 12 06:54:34 AM UTC 24
Finished Oct 12 06:54:38 AM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916613974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1916613974 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.1632728475
Short name T595
Test name
Test status
Simulation time 210105242807 ps
CPU time 1061.93 seconds
Started Oct 12 06:53:54 AM UTC 24
Finished Oct 12 07:11:48 AM UTC 24
Peak memory 886832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632728475 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.1632728475 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.1545569368
Short name T400
Test name
Test status
Simulation time 14260025481 ps
CPU time 168.37 seconds
Started Oct 12 06:53:58 AM UTC 24
Finished Oct 12 06:56:49 AM UTC 24
Peak memory 386996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545569368 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1545569368 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload_invalid.2035096124
Short name T369
Test name
Test status
Simulation time 67093118 ps
CPU time 2.61 seconds
Started Oct 12 06:54:10 AM UTC 24
Finished Oct 12 06:54:14 AM UTC 24
Peak memory 231364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035096124 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload_invalid.2035096124 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.2039763270
Short name T372
Test name
Test status
Simulation time 418637938 ps
CPU time 27.32 seconds
Started Oct 12 06:53:49 AM UTC 24
Finished Oct 12 06:54:17 AM UTC 24
Peak memory 231048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039763270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2039763270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.3209118535
Short name T443
Test name
Test status
Simulation time 11930406957 ps
CPU time 354.12 seconds
Started Oct 12 06:54:36 AM UTC 24
Finished Oct 12 07:00:35 AM UTC 24
Peak memory 305608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209118535 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3209118535 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.2288795751
Short name T387
Test name
Test status
Simulation time 17194139 ps
CPU time 1.23 seconds
Started Oct 12 06:55:39 AM UTC 24
Finished Oct 12 06:55:41 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288795751 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2288795751 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.1298440637
Short name T406
Test name
Test status
Simulation time 6278328927 ps
CPU time 111.43 seconds
Started Oct 12 06:55:11 AM UTC 24
Finished Oct 12 06:57:05 AM UTC 24
Peak memory 268200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298440637 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1298440637 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.2028582200
Short name T528
Test name
Test status
Simulation time 24424384356 ps
CPU time 675.13 seconds
Started Oct 12 06:54:57 AM UTC 24
Finished Oct 12 07:06:21 AM UTC 24
Peak memory 247664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028582200 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2028582200 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.1238666291
Short name T405
Test name
Test status
Simulation time 24106189419 ps
CPU time 99.4 seconds
Started Oct 12 06:55:19 AM UTC 24
Finished Oct 12 06:57:00 AM UTC 24
Peak memory 272304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238666291 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1238666291 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.2865820889
Short name T383
Test name
Test status
Simulation time 108114558 ps
CPU time 8.69 seconds
Started Oct 12 06:55:24 AM UTC 24
Finished Oct 12 06:55:34 AM UTC 24
Peak memory 235292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865820889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2865820889 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.1314501395
Short name T386
Test name
Test status
Simulation time 3352972832 ps
CPU time 5.29 seconds
Started Oct 12 06:55:33 AM UTC 24
Finished Oct 12 06:55:39 AM UTC 24
Peak memory 230812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314501395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1314501395 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.1516592362
Short name T385
Test name
Test status
Simulation time 43296086 ps
CPU time 2.02 seconds
Started Oct 12 06:55:35 AM UTC 24
Finished Oct 12 06:55:38 AM UTC 24
Peak memory 230876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516592362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1516592362 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.1333169603
Short name T742
Test name
Test status
Simulation time 120576878325 ps
CPU time 2414.24 seconds
Started Oct 12 06:54:48 AM UTC 24
Finished Oct 12 07:35:30 AM UTC 24
Peak memory 2932712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333169603 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.1333169603 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.3098800331
Short name T407
Test name
Test status
Simulation time 4870152803 ps
CPU time 138.49 seconds
Started Oct 12 06:54:51 AM UTC 24
Finished Oct 12 06:57:12 AM UTC 24
Peak memory 286700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098800331 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3098800331 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload_invalid.2055469563
Short name T379
Test name
Test status
Simulation time 97864745 ps
CPU time 3.49 seconds
Started Oct 12 06:54:52 AM UTC 24
Finished Oct 12 06:54:56 AM UTC 24
Peak memory 231416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055469563 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload_invalid.2055469563 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.352503792
Short name T377
Test name
Test status
Simulation time 425582721 ps
CPU time 3.97 seconds
Started Oct 12 06:54:42 AM UTC 24
Finished Oct 12 06:54:47 AM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352503792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.352503792 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.927652231
Short name T436
Test name
Test status
Simulation time 26740454246 ps
CPU time 205.95 seconds
Started Oct 12 06:55:38 AM UTC 24
Finished Oct 12 06:59:07 AM UTC 24
Peak memory 272244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927652231 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.927652231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.2272528070
Short name T399
Test name
Test status
Simulation time 41447630 ps
CPU time 1.14 seconds
Started Oct 12 06:56:21 AM UTC 24
Finished Oct 12 06:56:24 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272528070 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2272528070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.4064504554
Short name T398
Test name
Test status
Simulation time 2873703539 ps
CPU time 23.36 seconds
Started Oct 12 06:55:59 AM UTC 24
Finished Oct 12 06:56:23 AM UTC 24
Peak memory 239508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064504554 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.4064504554 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.4127469328
Short name T402
Test name
Test status
Simulation time 6232779255 ps
CPU time 54.31 seconds
Started Oct 12 06:55:58 AM UTC 24
Finished Oct 12 06:56:54 AM UTC 24
Peak memory 235376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127469328 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.4127469328 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1810453087
Short name T456
Test name
Test status
Simulation time 55695602758 ps
CPU time 332.25 seconds
Started Oct 12 06:56:01 AM UTC 24
Finished Oct 12 07:01:38 AM UTC 24
Peak memory 458732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810453087 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1810453087 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.259551151
Short name T438
Test name
Test status
Simulation time 11432216729 ps
CPU time 188.19 seconds
Started Oct 12 06:56:16 AM UTC 24
Finished Oct 12 06:59:27 AM UTC 24
Peak memory 333748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259551151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.259551151 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.135433622
Short name T397
Test name
Test status
Simulation time 1065136659 ps
CPU time 3.77 seconds
Started Oct 12 06:56:16 AM UTC 24
Finished Oct 12 06:56:21 AM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135433622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.135433622 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.1945587255
Short name T396
Test name
Test status
Simulation time 47769844 ps
CPU time 2.06 seconds
Started Oct 12 06:56:17 AM UTC 24
Finished Oct 12 06:56:20 AM UTC 24
Peak memory 230892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945587255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1945587255 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.1531292026
Short name T755
Test name
Test status
Simulation time 1392928102608 ps
CPU time 3962.7 seconds
Started Oct 12 06:55:42 AM UTC 24
Finished Oct 12 08:02:30 AM UTC 24
Peak memory 3774488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531292026 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.1531292026 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.3860926456
Short name T422
Test name
Test status
Simulation time 20131613359 ps
CPU time 153.22 seconds
Started Oct 12 06:55:46 AM UTC 24
Finished Oct 12 06:58:22 AM UTC 24
Peak memory 360508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860926456 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3860926456 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload_invalid.869991823
Short name T390
Test name
Test status
Simulation time 290534719 ps
CPU time 5.14 seconds
Started Oct 12 06:55:51 AM UTC 24
Finished Oct 12 06:55:57 AM UTC 24
Peak memory 231412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869991823 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload_invalid.869991823 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.198154294
Short name T389
Test name
Test status
Simulation time 814010534 ps
CPU time 8.82 seconds
Started Oct 12 06:55:40 AM UTC 24
Finished Oct 12 06:55:50 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198154294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.198154294 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.2938753488
Short name T462
Test name
Test status
Simulation time 3964028979 ps
CPU time 347.53 seconds
Started Oct 12 06:56:21 AM UTC 24
Finished Oct 12 07:02:14 AM UTC 24
Peak memory 460912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938753488 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2938753488 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.3048298291
Short name T410
Test name
Test status
Simulation time 19221201 ps
CPU time 1.18 seconds
Started Oct 12 06:57:14 AM UTC 24
Finished Oct 12 06:57:16 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048298291 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3048298291 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.1692880624
Short name T469
Test name
Test status
Simulation time 14278999291 ps
CPU time 334.19 seconds
Started Oct 12 06:56:58 AM UTC 24
Finished Oct 12 07:02:37 AM UTC 24
Peak memory 524208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692880624 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1692880624 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.3161850134
Short name T574
Test name
Test status
Simulation time 35607963067 ps
CPU time 778.56 seconds
Started Oct 12 06:56:55 AM UTC 24
Finished Oct 12 07:10:03 AM UTC 24
Peak memory 251832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161850134 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3161850134 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.3291418992
Short name T446
Test name
Test status
Simulation time 14644747978 ps
CPU time 227.95 seconds
Started Oct 12 06:56:58 AM UTC 24
Finished Oct 12 07:00:49 AM UTC 24
Peak memory 458852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291418992 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3291418992 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.1764016341
Short name T440
Test name
Test status
Simulation time 32256123021 ps
CPU time 169.24 seconds
Started Oct 12 06:57:01 AM UTC 24
Finished Oct 12 06:59:53 AM UTC 24
Peak memory 399292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764016341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1764016341 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.1268656813
Short name T411
Test name
Test status
Simulation time 835671084 ps
CPU time 8.72 seconds
Started Oct 12 06:57:06 AM UTC 24
Finished Oct 12 06:57:16 AM UTC 24
Peak memory 230760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268656813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1268656813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.4086150781
Short name T415
Test name
Test status
Simulation time 2914270073 ps
CPU time 8.95 seconds
Started Oct 12 06:57:13 AM UTC 24
Finished Oct 12 06:57:24 AM UTC 24
Peak memory 235508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086150781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.4086150781 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2010348266
Short name T707
Test name
Test status
Simulation time 63487202077 ps
CPU time 1415.9 seconds
Started Oct 12 06:56:25 AM UTC 24
Finished Oct 12 07:20:17 AM UTC 24
Peak memory 1200056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010348266 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2010348266 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.1917669211
Short name T408
Test name
Test status
Simulation time 1011740410 ps
CPU time 21.67 seconds
Started Oct 12 06:56:50 AM UTC 24
Finished Oct 12 06:57:13 AM UTC 24
Peak memory 235144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917669211 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1917669211 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload_invalid.2733920078
Short name T404
Test name
Test status
Simulation time 294495366 ps
CPU time 5.51 seconds
Started Oct 12 06:56:51 AM UTC 24
Finished Oct 12 06:56:57 AM UTC 24
Peak memory 231392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733920078 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload_invalid.2733920078 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.3688150784
Short name T409
Test name
Test status
Simulation time 11493618857 ps
CPU time 46.64 seconds
Started Oct 12 06:56:24 AM UTC 24
Finished Oct 12 06:57:13 AM UTC 24
Peak memory 231104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688150784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3688150784 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.371437013
Short name T483
Test name
Test status
Simulation time 22827561900 ps
CPU time 381.55 seconds
Started Oct 12 06:57:13 AM UTC 24
Finished Oct 12 07:03:40 AM UTC 24
Peak memory 327996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371437013 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.371437013 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.752767740
Short name T421
Test name
Test status
Simulation time 38529267 ps
CPU time 1.25 seconds
Started Oct 12 06:57:56 AM UTC 24
Finished Oct 12 06:57:58 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752767740 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.752767740 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.2422344677
Short name T442
Test name
Test status
Simulation time 29512943450 ps
CPU time 187.27 seconds
Started Oct 12 06:57:24 AM UTC 24
Finished Oct 12 07:00:35 AM UTC 24
Peak memory 354232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422344677 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2422344677 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.1411915057
Short name T604
Test name
Test status
Simulation time 24100950982 ps
CPU time 886.77 seconds
Started Oct 12 06:57:24 AM UTC 24
Finished Oct 12 07:12:22 AM UTC 24
Peak memory 264236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411915057 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1411915057 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.3969457189
Short name T467
Test name
Test status
Simulation time 18067853780 ps
CPU time 299.77 seconds
Started Oct 12 06:57:28 AM UTC 24
Finished Oct 12 07:02:32 AM UTC 24
Peak memory 495476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969457189 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3969457189 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.2296668019
Short name T478
Test name
Test status
Simulation time 23425960487 ps
CPU time 341.46 seconds
Started Oct 12 06:57:30 AM UTC 24
Finished Oct 12 07:03:16 AM UTC 24
Peak memory 552820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296668019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2296668019 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.2148452365
Short name T419
Test name
Test status
Simulation time 1086526459 ps
CPU time 10.45 seconds
Started Oct 12 06:57:40 AM UTC 24
Finished Oct 12 06:57:52 AM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148452365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2148452365 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.2367164246
Short name T420
Test name
Test status
Simulation time 45056817 ps
CPU time 1.91 seconds
Started Oct 12 06:57:52 AM UTC 24
Finished Oct 12 06:57:54 AM UTC 24
Peak memory 233884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367164246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2367164246 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.4127000900
Short name T568
Test name
Test status
Simulation time 27233601202 ps
CPU time 709.12 seconds
Started Oct 12 06:57:17 AM UTC 24
Finished Oct 12 07:09:15 AM UTC 24
Peak memory 1214392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127000900 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.4127000900 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.878768777
Short name T428
Test name
Test status
Simulation time 2803867176 ps
CPU time 79.44 seconds
Started Oct 12 06:57:20 AM UTC 24
Finished Oct 12 06:58:41 AM UTC 24
Peak memory 280552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878768777 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.878768777 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.1637510174
Short name T414
Test name
Test status
Simulation time 128998697 ps
CPU time 5.25 seconds
Started Oct 12 06:57:17 AM UTC 24
Finished Oct 12 06:57:23 AM UTC 24
Peak memory 231040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637510174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1637510174 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.1312537129
Short name T473
Test name
Test status
Simulation time 5623907994 ps
CPU time 307.68 seconds
Started Oct 12 06:57:53 AM UTC 24
Finished Oct 12 07:03:05 AM UTC 24
Peak memory 334140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312537129 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1312537129 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.592294774
Short name T435
Test name
Test status
Simulation time 83377847 ps
CPU time 1.27 seconds
Started Oct 12 06:59:04 AM UTC 24
Finished Oct 12 06:59:06 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592294774 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.592294774 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.4184871919
Short name T461
Test name
Test status
Simulation time 4605136009 ps
CPU time 203.02 seconds
Started Oct 12 06:58:39 AM UTC 24
Finished Oct 12 07:02:06 AM UTC 24
Peak memory 313320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184871919 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.4184871919 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.2717225435
Short name T596
Test name
Test status
Simulation time 9052679744 ps
CPU time 796.45 seconds
Started Oct 12 06:58:34 AM UTC 24
Finished Oct 12 07:12:00 AM UTC 24
Peak memory 251824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717225435 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2717225435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2725230510
Short name T448
Test name
Test status
Simulation time 3665857607 ps
CPU time 129.89 seconds
Started Oct 12 06:58:39 AM UTC 24
Finished Oct 12 07:00:52 AM UTC 24
Peak memory 274296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725230510 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2725230510 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.3353293193
Short name T439
Test name
Test status
Simulation time 5696083164 ps
CPU time 63.46 seconds
Started Oct 12 06:58:43 AM UTC 24
Finished Oct 12 06:59:48 AM UTC 24
Peak memory 300988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353293193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3353293193 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.1701502918
Short name T431
Test name
Test status
Simulation time 2128493469 ps
CPU time 7.8 seconds
Started Oct 12 06:58:51 AM UTC 24
Finished Oct 12 06:59:00 AM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701502918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1701502918 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.2756335584
Short name T432
Test name
Test status
Simulation time 101188017 ps
CPU time 1.77 seconds
Started Oct 12 06:59:01 AM UTC 24
Finished Oct 12 06:59:04 AM UTC 24
Peak memory 232008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756335584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2756335584 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.798422600
Short name T748
Test name
Test status
Simulation time 26552373871 ps
CPU time 2581.42 seconds
Started Oct 12 06:58:23 AM UTC 24
Finished Oct 12 07:41:53 AM UTC 24
Peak memory 1876024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798422600 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.798422600 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.1014448500
Short name T496
Test name
Test status
Simulation time 4270888685 ps
CPU time 361.25 seconds
Started Oct 12 06:58:29 AM UTC 24
Finished Oct 12 07:04:36 AM UTC 24
Peak memory 376912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014448500 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1014448500 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload_invalid.3071947061
Short name T427
Test name
Test status
Simulation time 834749680 ps
CPU time 5.43 seconds
Started Oct 12 06:58:32 AM UTC 24
Finished Oct 12 06:58:39 AM UTC 24
Peak memory 231304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071947061 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload_invalid.3071947061 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.1679723692
Short name T426
Test name
Test status
Simulation time 1137156485 ps
CPU time 38.15 seconds
Started Oct 12 06:57:59 AM UTC 24
Finished Oct 12 06:58:38 AM UTC 24
Peak memory 231164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679723692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1679723692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.2936718353
Short name T640
Test name
Test status
Simulation time 72846031601 ps
CPU time 933.89 seconds
Started Oct 12 06:59:01 AM UTC 24
Finished Oct 12 07:14:46 AM UTC 24
Peak memory 1102200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936718353 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2936718353 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.2666177367
Short name T444
Test name
Test status
Simulation time 16233741 ps
CPU time 1.3 seconds
Started Oct 12 07:00:35 AM UTC 24
Finished Oct 12 07:00:38 AM UTC 24
Peak memory 214020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666177367 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.2666177367 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.3042625977
Short name T484
Test name
Test status
Simulation time 4106951324 ps
CPU time 249.42 seconds
Started Oct 12 06:59:29 AM UTC 24
Finished Oct 12 07:03:42 AM UTC 24
Peak memory 315372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042625977 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3042625977 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.2226926587
Short name T563
Test name
Test status
Simulation time 6526430734 ps
CPU time 580.96 seconds
Started Oct 12 06:59:14 AM UTC 24
Finished Oct 12 07:09:03 AM UTC 24
Peak memory 251820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226926587 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2226926587 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.713304863
Short name T460
Test name
Test status
Simulation time 4097937333 ps
CPU time 124.2 seconds
Started Oct 12 06:59:49 AM UTC 24
Finished Oct 12 07:01:55 AM UTC 24
Peak memory 274540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713304863 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.713304863 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.2966498793
Short name T518
Test name
Test status
Simulation time 4090780553 ps
CPU time 348.55 seconds
Started Oct 12 06:59:54 AM UTC 24
Finished Oct 12 07:05:48 AM UTC 24
Peak memory 368532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966498793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2966498793 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.2500289129
Short name T441
Test name
Test status
Simulation time 3683624203 ps
CPU time 17.49 seconds
Started Oct 12 06:59:57 AM UTC 24
Finished Oct 12 07:00:16 AM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500289129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2500289129 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.1136002726
Short name T744
Test name
Test status
Simulation time 185897894798 ps
CPU time 2271.76 seconds
Started Oct 12 06:59:06 AM UTC 24
Finished Oct 12 07:37:23 AM UTC 24
Peak memory 1617816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136002726 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.1136002726 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.1439660619
Short name T450
Test name
Test status
Simulation time 1078826740 ps
CPU time 103.27 seconds
Started Oct 12 06:59:07 AM UTC 24
Finished Oct 12 07:00:53 AM UTC 24
Peak memory 259892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439660619 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1439660619 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload_invalid.235404420
Short name T437
Test name
Test status
Simulation time 343333907 ps
CPU time 3.93 seconds
Started Oct 12 06:59:08 AM UTC 24
Finished Oct 12 06:59:13 AM UTC 24
Peak memory 231368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235404420 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload_invalid.235404420 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.1389942370
Short name T445
Test name
Test status
Simulation time 4113797446 ps
CPU time 96.92 seconds
Started Oct 12 06:59:05 AM UTC 24
Finished Oct 12 07:00:44 AM UTC 24
Peak memory 235496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389942370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1389942370 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.2882720745
Short name T548
Test name
Test status
Simulation time 96861795151 ps
CPU time 442.52 seconds
Started Oct 12 07:00:21 AM UTC 24
Finished Oct 12 07:07:50 AM UTC 24
Peak memory 743352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882720745 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2882720745 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.3654910271
Short name T453
Test name
Test status
Simulation time 12807265 ps
CPU time 1.19 seconds
Started Oct 12 07:01:11 AM UTC 24
Finished Oct 12 07:01:13 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654910271 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3654910271 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.3205179524
Short name T466
Test name
Test status
Simulation time 2250263729 ps
CPU time 96.83 seconds
Started Oct 12 07:00:52 AM UTC 24
Finished Oct 12 07:02:31 AM UTC 24
Peak memory 282484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205179524 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3205179524 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.1677087501
Short name T455
Test name
Test status
Simulation time 1495946085 ps
CPU time 34.82 seconds
Started Oct 12 07:00:50 AM UTC 24
Finished Oct 12 07:01:26 AM UTC 24
Peak memory 235288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677087501 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1677087501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.1790468222
Short name T464
Test name
Test status
Simulation time 17064948723 ps
CPU time 86.28 seconds
Started Oct 12 07:00:53 AM UTC 24
Finished Oct 12 07:02:21 AM UTC 24
Peak memory 276404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790468222 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1790468222 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.4089890766
Short name T538
Test name
Test status
Simulation time 11854256127 ps
CPU time 378.71 seconds
Started Oct 12 07:00:53 AM UTC 24
Finished Oct 12 07:07:17 AM UTC 24
Peak memory 563072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089890766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.4089890766 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.2521667431
Short name T451
Test name
Test status
Simulation time 1008923005 ps
CPU time 10.28 seconds
Started Oct 12 07:00:54 AM UTC 24
Finished Oct 12 07:01:06 AM UTC 24
Peak memory 230816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521667431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2521667431 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.2879613299
Short name T470
Test name
Test status
Simulation time 3500189712 ps
CPU time 134.16 seconds
Started Oct 12 07:00:39 AM UTC 24
Finished Oct 12 07:02:55 AM UTC 24
Peak memory 370784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879613299 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.2879613299 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.253712199
Short name T513
Test name
Test status
Simulation time 14336750266 ps
CPU time 287.56 seconds
Started Oct 12 07:00:42 AM UTC 24
Finished Oct 12 07:05:33 AM UTC 24
Peak memory 356460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253712199 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.253712199 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload_invalid.2151055122
Short name T447
Test name
Test status
Simulation time 599400362 ps
CPU time 5.36 seconds
Started Oct 12 07:00:45 AM UTC 24
Finished Oct 12 07:00:51 AM UTC 24
Peak memory 231368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151055122 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload_invalid.2151055122 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.2048265617
Short name T459
Test name
Test status
Simulation time 2534217354 ps
CPU time 73.86 seconds
Started Oct 12 07:00:35 AM UTC 24
Finished Oct 12 07:01:51 AM UTC 24
Peak memory 233044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048265617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2048265617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.1498645142
Short name T735
Test name
Test status
Simulation time 282128135064 ps
CPU time 1656.59 seconds
Started Oct 12 07:01:08 AM UTC 24
Finished Oct 12 07:29:03 AM UTC 24
Peak memory 809220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498645142 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1498645142 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.4154540355
Short name T465
Test name
Test status
Simulation time 45345706 ps
CPU time 1.19 seconds
Started Oct 12 07:02:22 AM UTC 24
Finished Oct 12 07:02:24 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154540355 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.4154540355 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.3516689050
Short name T489
Test name
Test status
Simulation time 4178624098 ps
CPU time 118.22 seconds
Started Oct 12 07:01:51 AM UTC 24
Finished Oct 12 07:03:52 AM UTC 24
Peak memory 309164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516689050 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3516689050 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.2698336478
Short name T482
Test name
Test status
Simulation time 11155740969 ps
CPU time 116.4 seconds
Started Oct 12 07:01:40 AM UTC 24
Finished Oct 12 07:03:39 AM UTC 24
Peak memory 235428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698336478 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2698336478 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.2073583000
Short name T511
Test name
Test status
Simulation time 6254605503 ps
CPU time 207.8 seconds
Started Oct 12 07:01:52 AM UTC 24
Finished Oct 12 07:05:23 AM UTC 24
Peak memory 325604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073583000 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2073583000 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.746599688
Short name T533
Test name
Test status
Simulation time 39537373435 ps
CPU time 283.67 seconds
Started Oct 12 07:01:56 AM UTC 24
Finished Oct 12 07:06:44 AM UTC 24
Peak memory 503728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746599688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.746599688 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.3332492718
Short name T463
Test name
Test status
Simulation time 1860589511 ps
CPU time 10.38 seconds
Started Oct 12 07:02:06 AM UTC 24
Finished Oct 12 07:02:18 AM UTC 24
Peak memory 230840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332492718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3332492718 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.2509562505
Short name T69
Test name
Test status
Simulation time 3631540569 ps
CPU time 48.92 seconds
Started Oct 12 07:02:15 AM UTC 24
Finished Oct 12 07:03:05 AM UTC 24
Peak memory 256236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509562505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2509562505 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.1754318840
Short name T723
Test name
Test status
Simulation time 73869960267 ps
CPU time 1333.2 seconds
Started Oct 12 07:01:19 AM UTC 24
Finished Oct 12 07:23:47 AM UTC 24
Peak memory 1921136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754318840 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.1754318840 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.1436255274
Short name T480
Test name
Test status
Simulation time 6517018811 ps
CPU time 112.93 seconds
Started Oct 12 07:01:27 AM UTC 24
Finished Oct 12 07:03:22 AM UTC 24
Peak memory 284596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436255274 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1436255274 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.806993470
Short name T457
Test name
Test status
Simulation time 392351582 ps
CPU time 24.46 seconds
Started Oct 12 07:01:14 AM UTC 24
Finished Oct 12 07:01:39 AM UTC 24
Peak memory 233016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806993470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.806993470 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.2779732058
Short name T171
Test name
Test status
Simulation time 9590336681 ps
CPU time 207.22 seconds
Started Oct 12 07:02:19 AM UTC 24
Finished Oct 12 07:05:49 AM UTC 24
Peak memory 268160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779732058 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2779732058 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.1835422123
Short name T474
Test name
Test status
Simulation time 37713187 ps
CPU time 1.17 seconds
Started Oct 12 07:03:06 AM UTC 24
Finished Oct 12 07:03:09 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835422123 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1835422123 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.428064351
Short name T510
Test name
Test status
Simulation time 7090809514 ps
CPU time 152.02 seconds
Started Oct 12 07:02:48 AM UTC 24
Finished Oct 12 07:05:22 AM UTC 24
Peak memory 352120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428064351 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.428064351 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.3871358317
Short name T537
Test name
Test status
Simulation time 14862148344 ps
CPU time 262.82 seconds
Started Oct 12 07:02:38 AM UTC 24
Finished Oct 12 07:07:05 AM UTC 24
Peak memory 241560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871358317 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3871358317 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.2226692025
Short name T495
Test name
Test status
Simulation time 38144141218 ps
CPU time 98.4 seconds
Started Oct 12 07:02:52 AM UTC 24
Finished Oct 12 07:04:32 AM UTC 24
Peak memory 272484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226692025 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2226692025 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.551026337
Short name T499
Test name
Test status
Simulation time 7880929269 ps
CPU time 111.51 seconds
Started Oct 12 07:02:56 AM UTC 24
Finished Oct 12 07:04:50 AM UTC 24
Peak memory 333856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551026337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.551026337 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.3036562965
Short name T476
Test name
Test status
Simulation time 1887433421 ps
CPU time 12.45 seconds
Started Oct 12 07:02:57 AM UTC 24
Finished Oct 12 07:03:11 AM UTC 24
Peak memory 230824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036562965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3036562965 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.1202941494
Short name T477
Test name
Test status
Simulation time 438359860 ps
CPU time 11.14 seconds
Started Oct 12 07:02:59 AM UTC 24
Finished Oct 12 07:03:11 AM UTC 24
Peak memory 235440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202941494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1202941494 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.2437911830
Short name T498
Test name
Test status
Simulation time 5198645257 ps
CPU time 134.57 seconds
Started Oct 12 07:02:32 AM UTC 24
Finished Oct 12 07:04:49 AM UTC 24
Peak memory 294840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437911830 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.2437911830 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.1132475678
Short name T536
Test name
Test status
Simulation time 4013582103 ps
CPU time 266.61 seconds
Started Oct 12 07:02:33 AM UTC 24
Finished Oct 12 07:07:03 AM UTC 24
Peak memory 343936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132475678 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1132475678 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.2646614801
Short name T475
Test name
Test status
Simulation time 25971642261 ps
CPU time 42.88 seconds
Started Oct 12 07:02:25 AM UTC 24
Finished Oct 12 07:03:09 AM UTC 24
Peak memory 235632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646614801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2646614801 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.50626599
Short name T481
Test name
Test status
Simulation time 715568181 ps
CPU time 20.41 seconds
Started Oct 12 07:03:06 AM UTC 24
Finished Oct 12 07:03:28 AM UTC 24
Peak memory 239488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50626599 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.50626599 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.575641579
Short name T63
Test name
Test status
Simulation time 98545775 ps
CPU time 1.31 seconds
Started Oct 12 06:33:58 AM UTC 24
Finished Oct 12 06:34:00 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575641579 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.575641579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.728014692
Short name T198
Test name
Test status
Simulation time 5123422873 ps
CPU time 132.44 seconds
Started Oct 12 06:32:55 AM UTC 24
Finished Oct 12 06:35:10 AM UTC 24
Peak memory 321432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728014692 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.728014692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.752215043
Short name T119
Test name
Test status
Simulation time 769029189 ps
CPU time 15.66 seconds
Started Oct 12 06:32:58 AM UTC 24
Finished Oct 12 06:33:15 AM UTC 24
Peak memory 239464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752215043 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.752215043 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.3426772109
Short name T149
Test name
Test status
Simulation time 17244863499 ps
CPU time 731.34 seconds
Started Oct 12 06:31:43 AM UTC 24
Finished Oct 12 06:44:03 AM UTC 24
Peak memory 257888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426772109 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3426772109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.719513326
Short name T192
Test name
Test status
Simulation time 1002065571 ps
CPU time 25.18 seconds
Started Oct 12 06:33:17 AM UTC 24
Finished Oct 12 06:33:43 AM UTC 24
Peak memory 235340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719513326 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.719513326 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.1138473884
Short name T193
Test name
Test status
Simulation time 3202108234 ps
CPU time 31.71 seconds
Started Oct 12 06:33:24 AM UTC 24
Finished Oct 12 06:33:57 AM UTC 24
Peak memory 235192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138473884 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1138473884 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2252640849
Short name T41
Test name
Test status
Simulation time 19368030697 ps
CPU time 67.57 seconds
Started Oct 12 06:33:27 AM UTC 24
Finished Oct 12 06:34:36 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252640849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2252640849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3023888300
Short name T217
Test name
Test status
Simulation time 105055303630 ps
CPU time 337.43 seconds
Started Oct 12 06:33:08 AM UTC 24
Finished Oct 12 06:38:50 AM UTC 24
Peak memory 470904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023888300 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3023888300 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.3577480007
Short name T74
Test name
Test status
Simulation time 506941007 ps
CPU time 5.45 seconds
Started Oct 12 06:33:15 AM UTC 24
Finished Oct 12 06:33:22 AM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577480007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3577480007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.4024262894
Short name T7
Test name
Test status
Simulation time 159677789 ps
CPU time 2.1 seconds
Started Oct 12 06:33:44 AM UTC 24
Finished Oct 12 06:33:47 AM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024262894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.4024262894 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.3993052410
Short name T549
Test name
Test status
Simulation time 20349977474 ps
CPU time 2160.15 seconds
Started Oct 12 06:31:28 AM UTC 24
Finished Oct 12 07:07:52 AM UTC 24
Peak memory 1540052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993052410 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3993052410 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.493501889
Short name T66
Test name
Test status
Simulation time 3123709497 ps
CPU time 148.2 seconds
Started Oct 12 06:33:12 AM UTC 24
Finished Oct 12 06:35:43 AM UTC 24
Peak memory 295220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493501889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.493501889 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.3527246689
Short name T58
Test name
Test status
Simulation time 5432545690 ps
CPU time 51.05 seconds
Started Oct 12 06:33:53 AM UTC 24
Finished Oct 12 06:34:45 AM UTC 24
Peak memory 282212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527246689 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3527246689 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.3145322641
Short name T34
Test name
Test status
Simulation time 29493209163 ps
CPU time 180.26 seconds
Started Oct 12 06:31:31 AM UTC 24
Finished Oct 12 06:34:35 AM UTC 24
Peak memory 391156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145322641 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3145322641 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload_invalid.1320038081
Short name T27
Test name
Test status
Simulation time 556247590 ps
CPU time 6.17 seconds
Started Oct 12 06:31:36 AM UTC 24
Finished Oct 12 06:31:43 AM UTC 24
Peak memory 231552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320038081 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload_invalid.1320038081 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.1028371033
Short name T185
Test name
Test status
Simulation time 7480000845 ps
CPU time 53.72 seconds
Started Oct 12 06:31:27 AM UTC 24
Finished Oct 12 06:32:23 AM UTC 24
Peak memory 231088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028371033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1028371033 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.1647607826
Short name T395
Test name
Test status
Simulation time 89843766861 ps
CPU time 1334.42 seconds
Started Oct 12 06:33:47 AM UTC 24
Finished Oct 12 06:56:16 AM UTC 24
Peak memory 1116644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647607826 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1647607826 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.3868484112
Short name T189
Test name
Test status
Simulation time 137743664 ps
CPU time 2.68 seconds
Started Oct 12 06:32:51 AM UTC 24
Finished Oct 12 06:32:55 AM UTC 24
Peak memory 230964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868484112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.3868484112 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2621795619
Short name T190
Test name
Test status
Simulation time 235570659 ps
CPU time 2.83 seconds
Started Oct 12 06:32:53 AM UTC 24
Finished Oct 12 06:32:57 AM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621795619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2621795619 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.781665538
Short name T458
Test name
Test status
Simulation time 40755490374 ps
CPU time 1786.05 seconds
Started Oct 12 06:31:44 AM UTC 24
Finished Oct 12 07:01:51 AM UTC 24
Peak memory 1203996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781665538 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.781665538 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.2859049479
Short name T594
Test name
Test status
Simulation time 142162797181 ps
CPU time 2358.75 seconds
Started Oct 12 06:31:54 AM UTC 24
Finished Oct 12 07:11:39 AM UTC 24
Peak memory 3022608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859049479 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2859049479
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2103806786
Short name T191
Test name
Test status
Simulation time 3444034046 ps
CPU time 42.02 seconds
Started Oct 12 06:32:23 AM UTC 24
Finished Oct 12 06:33:07 AM UTC 24
Peak memory 239400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103806786 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2103806786
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.1048297681
Short name T336
Test name
Test status
Simulation time 451442263212 ps
CPU time 1143.39 seconds
Started Oct 12 06:32:25 AM UTC 24
Finished Oct 12 06:51:42 AM UTC 24
Peak memory 1726364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048297681 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1048297681
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1413245208
Short name T524
Test name
Test status
Simulation time 21193201593 ps
CPU time 1990.83 seconds
Started Oct 12 06:32:29 AM UTC 24
Finished Oct 12 07:06:01 AM UTC 24
Peak memory 1333036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413245208 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1413245
208 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.3868096247
Short name T186
Test name
Test status
Simulation time 39197412618 ps
CPU time 457.35 seconds
Started Oct 12 06:32:48 AM UTC 24
Finished Oct 12 06:40:31 AM UTC 24
Peak memory 362280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868096247 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3868096
247 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.3457590484
Short name T488
Test name
Test status
Simulation time 20262551 ps
CPU time 1.01 seconds
Started Oct 12 07:03:43 AM UTC 24
Finished Oct 12 07:03:45 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457590484 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3457590484 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.1155867608
Short name T545
Test name
Test status
Simulation time 9672147760 ps
CPU time 251.05 seconds
Started Oct 12 07:03:19 AM UTC 24
Finished Oct 12 07:07:34 AM UTC 24
Peak memory 405372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155867608 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1155867608 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.267743020
Short name T492
Test name
Test status
Simulation time 3000855211 ps
CPU time 64.01 seconds
Started Oct 12 07:03:18 AM UTC 24
Finished Oct 12 07:04:24 AM UTC 24
Peak memory 233088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267743020 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.267743020 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2220851964
Short name T534
Test name
Test status
Simulation time 9548356452 ps
CPU time 211.26 seconds
Started Oct 12 07:03:23 AM UTC 24
Finished Oct 12 07:06:58 AM UTC 24
Peak memory 382896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220851964 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2220851964 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.914280406
Short name T501
Test name
Test status
Simulation time 4571961548 ps
CPU time 79.92 seconds
Started Oct 12 07:03:29 AM UTC 24
Finished Oct 12 07:04:51 AM UTC 24
Peak memory 317364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914280406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.914280406 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.3790403218
Short name T486
Test name
Test status
Simulation time 1877549823 ps
CPU time 5.09 seconds
Started Oct 12 07:03:36 AM UTC 24
Finished Oct 12 07:03:42 AM UTC 24
Peak memory 230824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790403218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3790403218 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.3463369314
Short name T487
Test name
Test status
Simulation time 45898977 ps
CPU time 2.62 seconds
Started Oct 12 07:03:40 AM UTC 24
Finished Oct 12 07:03:44 AM UTC 24
Peak memory 230828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463369314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.3463369314 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.3026101295
Short name T573
Test name
Test status
Simulation time 11882635941 ps
CPU time 400.23 seconds
Started Oct 12 07:03:11 AM UTC 24
Finished Oct 12 07:09:56 AM UTC 24
Peak memory 684152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026101295 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.3026101295 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.44200032
Short name T500
Test name
Test status
Simulation time 17999030856 ps
CPU time 95.99 seconds
Started Oct 12 07:03:12 AM UTC 24
Finished Oct 12 07:04:50 AM UTC 24
Peak memory 300932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44200032 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.44200032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload_invalid.3600188610
Short name T479
Test name
Test status
Simulation time 265713679 ps
CPU time 4.47 seconds
Started Oct 12 07:03:13 AM UTC 24
Finished Oct 12 07:03:18 AM UTC 24
Peak memory 231476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600188610 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload_invalid.3600188610 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.1075559515
Short name T490
Test name
Test status
Simulation time 3023860347 ps
CPU time 46.36 seconds
Started Oct 12 07:03:09 AM UTC 24
Finished Oct 12 07:03:57 AM UTC 24
Peak memory 231112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075559515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1075559515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.2583778736
Short name T733
Test name
Test status
Simulation time 59475713237 ps
CPU time 1497.45 seconds
Started Oct 12 07:03:41 AM UTC 24
Finished Oct 12 07:28:56 AM UTC 24
Peak memory 1438008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583778736 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2583778736 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.2120980473
Short name T497
Test name
Test status
Simulation time 54343606 ps
CPU time 1.26 seconds
Started Oct 12 07:04:34 AM UTC 24
Finished Oct 12 07:04:36 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120980473 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2120980473 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.751341408
Short name T503
Test name
Test status
Simulation time 8493227792 ps
CPU time 62.03 seconds
Started Oct 12 07:03:53 AM UTC 24
Finished Oct 12 07:04:57 AM UTC 24
Peak memory 282548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751341408 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.751341408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.3197189553
Short name T695
Test name
Test status
Simulation time 45148011429 ps
CPU time 924.81 seconds
Started Oct 12 07:03:46 AM UTC 24
Finished Oct 12 07:19:22 AM UTC 24
Peak memory 266164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197189553 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.3197189553 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.4246916801
Short name T540
Test name
Test status
Simulation time 20906330895 ps
CPU time 200.23 seconds
Started Oct 12 07:03:58 AM UTC 24
Finished Oct 12 07:07:22 AM UTC 24
Peak memory 374712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246916801 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.4246916801 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.3651478855
Short name T505
Test name
Test status
Simulation time 1833739228 ps
CPU time 58.77 seconds
Started Oct 12 07:04:11 AM UTC 24
Finished Oct 12 07:05:12 AM UTC 24
Peak memory 284540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651478855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3651478855 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.3613425960
Short name T494
Test name
Test status
Simulation time 1819572567 ps
CPU time 6.49 seconds
Started Oct 12 07:04:24 AM UTC 24
Finished Oct 12 07:04:32 AM UTC 24
Peak memory 230748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613425960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3613425960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.2684741895
Short name T502
Test name
Test status
Simulation time 3682636936 ps
CPU time 24.78 seconds
Started Oct 12 07:04:30 AM UTC 24
Finished Oct 12 07:04:57 AM UTC 24
Peak memory 249904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684741895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2684741895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2961006023
Short name T754
Test name
Test status
Simulation time 414982036209 ps
CPU time 3265.57 seconds
Started Oct 12 07:03:44 AM UTC 24
Finished Oct 12 07:58:46 AM UTC 24
Peak memory 3753848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961006023 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2961006023 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.3381925962
Short name T564
Test name
Test status
Simulation time 3698345640 ps
CPU time 313.08 seconds
Started Oct 12 07:03:46 AM UTC 24
Finished Oct 12 07:09:03 AM UTC 24
Peak memory 364476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381925962 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3381925962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.1760020909
Short name T491
Test name
Test status
Simulation time 2143844340 ps
CPU time 25.69 seconds
Started Oct 12 07:03:44 AM UTC 24
Finished Oct 12 07:04:11 AM UTC 24
Peak memory 231032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760020909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1760020909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.235622152
Short name T725
Test name
Test status
Simulation time 51460099443 ps
CPU time 1185.58 seconds
Started Oct 12 07:04:33 AM UTC 24
Finished Oct 12 07:24:32 AM UTC 24
Peak memory 1366488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235622152 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.235622152 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.3084749146
Short name T508
Test name
Test status
Simulation time 14769588 ps
CPU time 1.22 seconds
Started Oct 12 07:05:17 AM UTC 24
Finished Oct 12 07:05:19 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084749146 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3084749146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.1959959354
Short name T554
Test name
Test status
Simulation time 7974105443 ps
CPU time 212.83 seconds
Started Oct 12 07:04:51 AM UTC 24
Finished Oct 12 07:08:27 AM UTC 24
Peak memory 419940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959959354 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1959959354 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.2625374341
Short name T632
Test name
Test status
Simulation time 6750702823 ps
CPU time 565.02 seconds
Started Oct 12 07:04:51 AM UTC 24
Finished Oct 12 07:14:23 AM UTC 24
Peak memory 251768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625374341 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2625374341 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.1219377441
Short name T514
Test name
Test status
Simulation time 4084031428 ps
CPU time 43.78 seconds
Started Oct 12 07:04:57 AM UTC 24
Finished Oct 12 07:05:43 AM UTC 24
Peak memory 264112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219377441 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1219377441 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.2242807359
Short name T525
Test name
Test status
Simulation time 3086937167 ps
CPU time 70.42 seconds
Started Oct 12 07:04:58 AM UTC 24
Finished Oct 12 07:06:11 AM UTC 24
Peak memory 266172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242807359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2242807359 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.3486201631
Short name T509
Test name
Test status
Simulation time 2917408663 ps
CPU time 16.61 seconds
Started Oct 12 07:05:02 AM UTC 24
Finished Oct 12 07:05:19 AM UTC 24
Peak memory 230956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486201631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3486201631 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.3014336991
Short name T507
Test name
Test status
Simulation time 49150370 ps
CPU time 2.12 seconds
Started Oct 12 07:05:13 AM UTC 24
Finished Oct 12 07:05:16 AM UTC 24
Peak memory 230892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014336991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3014336991 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.133671202
Short name T758
Test name
Test status
Simulation time 99090274189 ps
CPU time 3948.83 seconds
Started Oct 12 07:04:37 AM UTC 24
Finished Oct 12 08:11:10 AM UTC 24
Peak memory 4159512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133671202 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.133671202 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.302305328
Short name T516
Test name
Test status
Simulation time 3330640222 ps
CPU time 54.81 seconds
Started Oct 12 07:04:50 AM UTC 24
Finished Oct 12 07:05:46 AM UTC 24
Peak memory 257884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302305328 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.302305328 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.3022839516
Short name T504
Test name
Test status
Simulation time 761041257 ps
CPU time 22.43 seconds
Started Oct 12 07:04:37 AM UTC 24
Finished Oct 12 07:05:00 AM UTC 24
Peak memory 233092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022839516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3022839516 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.1803154812
Short name T737
Test name
Test status
Simulation time 99355753211 ps
CPU time 1581.01 seconds
Started Oct 12 07:05:14 AM UTC 24
Finished Oct 12 07:31:54 AM UTC 24
Peak memory 876452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803154812 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1803154812 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.3416502696
Short name T522
Test name
Test status
Simulation time 13546871 ps
CPU time 1.18 seconds
Started Oct 12 07:05:50 AM UTC 24
Finished Oct 12 07:05:52 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416502696 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3416502696 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.40665875
Short name T583
Test name
Test status
Simulation time 102819803611 ps
CPU time 301.22 seconds
Started Oct 12 07:05:34 AM UTC 24
Finished Oct 12 07:10:40 AM UTC 24
Peak memory 483384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40665875 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.40665875 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.2328045257
Short name T593
Test name
Test status
Simulation time 10149454835 ps
CPU time 359.98 seconds
Started Oct 12 07:05:28 AM UTC 24
Finished Oct 12 07:11:34 AM UTC 24
Peak memory 243576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328045257 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2328045257 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.2155488728
Short name T553
Test name
Test status
Simulation time 24241530964 ps
CPU time 160.95 seconds
Started Oct 12 07:05:43 AM UTC 24
Finished Oct 12 07:08:27 AM UTC 24
Peak memory 286584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155488728 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2155488728 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.2275421277
Short name T526
Test name
Test status
Simulation time 904845346 ps
CPU time 25.98 seconds
Started Oct 12 07:05:44 AM UTC 24
Finished Oct 12 07:06:11 AM UTC 24
Peak memory 251816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275421277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2275421277 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.2358385504
Short name T520
Test name
Test status
Simulation time 115192730 ps
CPU time 1.76 seconds
Started Oct 12 07:05:48 AM UTC 24
Finished Oct 12 07:05:50 AM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358385504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2358385504 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.3960464442
Short name T521
Test name
Test status
Simulation time 77724777 ps
CPU time 1.53 seconds
Started Oct 12 07:05:49 AM UTC 24
Finished Oct 12 07:05:51 AM UTC 24
Peak memory 233988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960464442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3960464442 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.3143263071
Short name T730
Test name
Test status
Simulation time 155096586670 ps
CPU time 1298.82 seconds
Started Oct 12 07:05:20 AM UTC 24
Finished Oct 12 07:27:14 AM UTC 24
Peak memory 1976216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143263071 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.3143263071 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.2175328467
Short name T602
Test name
Test status
Simulation time 90737755133 ps
CPU time 409.89 seconds
Started Oct 12 07:05:23 AM UTC 24
Finished Oct 12 07:12:18 AM UTC 24
Peak memory 583604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175328467 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2175328467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload_invalid.4167014067
Short name T512
Test name
Test status
Simulation time 126097247 ps
CPU time 2.41 seconds
Started Oct 12 07:05:24 AM UTC 24
Finished Oct 12 07:05:28 AM UTC 24
Peak memory 231348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167014067 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload_invalid.4167014067 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.2711617037
Short name T515
Test name
Test status
Simulation time 4125427287 ps
CPU time 21.56 seconds
Started Oct 12 07:05:20 AM UTC 24
Finished Oct 12 07:05:43 AM UTC 24
Peak memory 230980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711617037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2711617037 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.1696913419
Short name T672
Test name
Test status
Simulation time 123368210132 ps
CPU time 647.05 seconds
Started Oct 12 07:05:49 AM UTC 24
Finished Oct 12 07:16:44 AM UTC 24
Peak memory 569660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696913419 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1696913419 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.398071513
Short name T532
Test name
Test status
Simulation time 49532989 ps
CPU time 1.19 seconds
Started Oct 12 07:06:34 AM UTC 24
Finished Oct 12 07:06:36 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398071513 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.398071513 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.321961257
Short name T558
Test name
Test status
Simulation time 94062407192 ps
CPU time 154.95 seconds
Started Oct 12 07:06:02 AM UTC 24
Finished Oct 12 07:08:39 AM UTC 24
Peak memory 327576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321961257 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.321961257 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.719009949
Short name T550
Test name
Test status
Simulation time 2389148692 ps
CPU time 113.32 seconds
Started Oct 12 07:05:57 AM UTC 24
Finished Oct 12 07:07:53 AM UTC 24
Peak memory 235112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719009949 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.719009949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.1461510861
Short name T544
Test name
Test status
Simulation time 8575391430 ps
CPU time 79.9 seconds
Started Oct 12 07:06:12 AM UTC 24
Finished Oct 12 07:07:34 AM UTC 24
Peak memory 294832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461510861 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1461510861 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.3405337171
Short name T579
Test name
Test status
Simulation time 15302055392 ps
CPU time 250.72 seconds
Started Oct 12 07:06:12 AM UTC 24
Finished Oct 12 07:10:26 AM UTC 24
Peak memory 350132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405337171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3405337171 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.1565367081
Short name T530
Test name
Test status
Simulation time 4146374345 ps
CPU time 10.06 seconds
Started Oct 12 07:06:22 AM UTC 24
Finished Oct 12 07:06:33 AM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565367081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1565367081 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.1026821282
Short name T529
Test name
Test status
Simulation time 140864385 ps
CPU time 2 seconds
Started Oct 12 07:06:22 AM UTC 24
Finished Oct 12 07:06:25 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026821282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1026821282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.2215250026
Short name T747
Test name
Test status
Simulation time 98355752487 ps
CPU time 2095.7 seconds
Started Oct 12 07:05:51 AM UTC 24
Finished Oct 12 07:41:11 AM UTC 24
Peak memory 2510892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215250026 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.2215250026 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.1116378897
Short name T625
Test name
Test status
Simulation time 138668171191 ps
CPU time 491.2 seconds
Started Oct 12 07:05:52 AM UTC 24
Finished Oct 12 07:14:10 AM UTC 24
Peak memory 706560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116378897 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1116378897 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload_invalid.2346453465
Short name T523
Test name
Test status
Simulation time 28410470 ps
CPU time 2.34 seconds
Started Oct 12 07:05:53 AM UTC 24
Finished Oct 12 07:05:57 AM UTC 24
Peak memory 233360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346453465 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload_invalid.2346453465 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.1514465541
Short name T527
Test name
Test status
Simulation time 1543735115 ps
CPU time 28.52 seconds
Started Oct 12 07:05:51 AM UTC 24
Finished Oct 12 07:06:21 AM UTC 24
Peak memory 235252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514465541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1514465541 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.2210088249
Short name T724
Test name
Test status
Simulation time 39956796807 ps
CPU time 1063.96 seconds
Started Oct 12 07:06:26 AM UTC 24
Finished Oct 12 07:24:23 AM UTC 24
Peak memory 1534272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210088249 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2210088249 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.3043645034
Short name T543
Test name
Test status
Simulation time 14778462 ps
CPU time 1.22 seconds
Started Oct 12 07:07:29 AM UTC 24
Finished Oct 12 07:07:32 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043645034 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3043645034 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.2044380659
Short name T542
Test name
Test status
Simulation time 1174739454 ps
CPU time 22.72 seconds
Started Oct 12 07:07:05 AM UTC 24
Finished Oct 12 07:07:29 AM UTC 24
Peak memory 249768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044380659 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2044380659 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.316071467
Short name T628
Test name
Test status
Simulation time 57329544101 ps
CPU time 431.85 seconds
Started Oct 12 07:07:02 AM UTC 24
Finished Oct 12 07:14:19 AM UTC 24
Peak memory 251836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316071467 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.316071467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.722944265
Short name T560
Test name
Test status
Simulation time 8431158412 ps
CPU time 92.7 seconds
Started Oct 12 07:07:06 AM UTC 24
Finished Oct 12 07:08:41 AM UTC 24
Peak memory 288888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722944265 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.722944265 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.1958285995
Short name T571
Test name
Test status
Simulation time 2168621550 ps
CPU time 152.64 seconds
Started Oct 12 07:07:18 AM UTC 24
Finished Oct 12 07:09:53 AM UTC 24
Peak memory 317368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958285995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1958285995 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.506769911
Short name T546
Test name
Test status
Simulation time 4749897880 ps
CPU time 13.54 seconds
Started Oct 12 07:07:19 AM UTC 24
Finished Oct 12 07:07:34 AM UTC 24
Peak memory 230780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506769911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.506769911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.4068880902
Short name T541
Test name
Test status
Simulation time 123528265 ps
CPU time 1.99 seconds
Started Oct 12 07:07:23 AM UTC 24
Finished Oct 12 07:07:26 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068880902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4068880902 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.953194196
Short name T729
Test name
Test status
Simulation time 33397229175 ps
CPU time 1220.5 seconds
Started Oct 12 07:06:37 AM UTC 24
Finished Oct 12 07:27:13 AM UTC 24
Peak memory 1822648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953194196 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.953194196 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.1394671598
Short name T561
Test name
Test status
Simulation time 6381585829 ps
CPU time 125.74 seconds
Started Oct 12 07:06:45 AM UTC 24
Finished Oct 12 07:08:54 AM UTC 24
Peak memory 280440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394671598 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1394671598 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload_invalid.3262850710
Short name T535
Test name
Test status
Simulation time 76530394 ps
CPU time 1.31 seconds
Started Oct 12 07:06:58 AM UTC 24
Finished Oct 12 07:07:01 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262850710 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload_invalid.3262850710 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.599901956
Short name T539
Test name
Test status
Simulation time 2770351728 ps
CPU time 42.42 seconds
Started Oct 12 07:06:34 AM UTC 24
Finished Oct 12 07:07:18 AM UTC 24
Peak memory 231216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599901956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.599901956 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.3905873047
Short name T713
Test name
Test status
Simulation time 75840983064 ps
CPU time 841.6 seconds
Started Oct 12 07:07:27 AM UTC 24
Finished Oct 12 07:21:39 AM UTC 24
Peak memory 492084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905873047 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3905873047 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.2972715881
Short name T557
Test name
Test status
Simulation time 81641170 ps
CPU time 1.12 seconds
Started Oct 12 07:08:29 AM UTC 24
Finished Oct 12 07:08:31 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972715881 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2972715881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.3821266203
Short name T590
Test name
Test status
Simulation time 4404392782 ps
CPU time 205.92 seconds
Started Oct 12 07:07:51 AM UTC 24
Finished Oct 12 07:11:20 AM UTC 24
Peak memory 333872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821266203 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3821266203 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.2902959642
Short name T696
Test name
Test status
Simulation time 8192096416 ps
CPU time 699.3 seconds
Started Oct 12 07:07:40 AM UTC 24
Finished Oct 12 07:19:28 AM UTC 24
Peak memory 249696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902959642 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2902959642 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.1748182303
Short name T555
Test name
Test status
Simulation time 15878301739 ps
CPU time 35.22 seconds
Started Oct 12 07:07:51 AM UTC 24
Finished Oct 12 07:08:27 AM UTC 24
Peak memory 235068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748182303 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1748182303 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.3496532280
Short name T586
Test name
Test status
Simulation time 45653163563 ps
CPU time 196.49 seconds
Started Oct 12 07:07:53 AM UTC 24
Finished Oct 12 07:11:13 AM UTC 24
Peak memory 386996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496532280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3496532280 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.4039649275
Short name T551
Test name
Test status
Simulation time 7400024150 ps
CPU time 17.76 seconds
Started Oct 12 07:07:54 AM UTC 24
Finished Oct 12 07:08:13 AM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039649275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.4039649275 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.3861250695
Short name T559
Test name
Test status
Simulation time 3747471391 ps
CPU time 24.47 seconds
Started Oct 12 07:08:14 AM UTC 24
Finished Oct 12 07:08:40 AM UTC 24
Peak memory 251892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861250695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3861250695 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3276174261
Short name T757
Test name
Test status
Simulation time 163159295442 ps
CPU time 3539.05 seconds
Started Oct 12 07:07:35 AM UTC 24
Finished Oct 12 08:07:12 AM UTC 24
Peak memory 4048840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276174261 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3276174261 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.1497014112
Short name T607
Test name
Test status
Simulation time 40090370816 ps
CPU time 299.55 seconds
Started Oct 12 07:07:35 AM UTC 24
Finished Oct 12 07:12:38 AM UTC 24
Peak memory 446500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497014112 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1497014112 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload_invalid.3978590947
Short name T547
Test name
Test status
Simulation time 50943534 ps
CPU time 3.23 seconds
Started Oct 12 07:07:35 AM UTC 24
Finished Oct 12 07:07:39 AM UTC 24
Peak memory 231360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978590947 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload_invalid.3978590947 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.3464273780
Short name T552
Test name
Test status
Simulation time 4696742578 ps
CPU time 41.38 seconds
Started Oct 12 07:07:32 AM UTC 24
Finished Oct 12 07:08:15 AM UTC 24
Peak memory 233084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464273780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3464273780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.1709822019
Short name T572
Test name
Test status
Simulation time 1058092305 ps
CPU time 96.26 seconds
Started Oct 12 07:08:16 AM UTC 24
Finished Oct 12 07:09:55 AM UTC 24
Peak memory 235068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709822019 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1709822019 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.682767455
Short name T567
Test name
Test status
Simulation time 13804866 ps
CPU time 1.2 seconds
Started Oct 12 07:09:06 AM UTC 24
Finished Oct 12 07:09:08 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682767455 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.682767455 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.2510646713
Short name T588
Test name
Test status
Simulation time 7151304537 ps
CPU time 150.08 seconds
Started Oct 12 07:08:41 AM UTC 24
Finished Oct 12 07:11:14 AM UTC 24
Peak memory 350260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510646713 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2510646713 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.3477308898
Short name T722
Test name
Test status
Simulation time 18813370511 ps
CPU time 871.99 seconds
Started Oct 12 07:08:40 AM UTC 24
Finished Oct 12 07:23:23 AM UTC 24
Peak memory 260020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477308898 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3477308898 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.336165243
Short name T615
Test name
Test status
Simulation time 4242480998 ps
CPU time 255.41 seconds
Started Oct 12 07:08:42 AM UTC 24
Finished Oct 12 07:13:02 AM UTC 24
Peak memory 311408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336165243 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.336165243 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.3889328246
Short name T630
Test name
Test status
Simulation time 53368854626 ps
CPU time 321.65 seconds
Started Oct 12 07:08:55 AM UTC 24
Finished Oct 12 07:14:22 AM UTC 24
Peak memory 368764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889328246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3889328246 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.3118954070
Short name T565
Test name
Test status
Simulation time 100493551 ps
CPU time 2.06 seconds
Started Oct 12 07:09:01 AM UTC 24
Finished Oct 12 07:09:04 AM UTC 24
Peak memory 230496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118954070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3118954070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.3764162026
Short name T566
Test name
Test status
Simulation time 41166243 ps
CPU time 1.98 seconds
Started Oct 12 07:09:03 AM UTC 24
Finished Oct 12 07:09:07 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764162026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3764162026 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.3930979411
Short name T582
Test name
Test status
Simulation time 19613926168 ps
CPU time 128.5 seconds
Started Oct 12 07:08:29 AM UTC 24
Finished Oct 12 07:10:40 AM UTC 24
Peak memory 409520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930979411 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.3930979411 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.3827939051
Short name T569
Test name
Test status
Simulation time 8986405716 ps
CPU time 47.18 seconds
Started Oct 12 07:08:30 AM UTC 24
Finished Oct 12 07:09:19 AM UTC 24
Peak memory 274296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827939051 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3827939051 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.3828034811
Short name T562
Test name
Test status
Simulation time 579668767 ps
CPU time 30.02 seconds
Started Oct 12 07:08:29 AM UTC 24
Finished Oct 12 07:09:00 AM UTC 24
Peak memory 232996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828034811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3828034811 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.4043966326
Short name T651
Test name
Test status
Simulation time 76643345943 ps
CPU time 393.58 seconds
Started Oct 12 07:09:05 AM UTC 24
Finished Oct 12 07:15:44 AM UTC 24
Peak memory 366516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043966326 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.4043966326 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.3557863666
Short name T578
Test name
Test status
Simulation time 19735388 ps
CPU time 1.25 seconds
Started Oct 12 07:10:12 AM UTC 24
Finished Oct 12 07:10:14 AM UTC 24
Peak memory 214136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557863666 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3557863666 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.2323530883
Short name T608
Test name
Test status
Simulation time 3253928582 ps
CPU time 162.36 seconds
Started Oct 12 07:09:54 AM UTC 24
Finished Oct 12 07:12:40 AM UTC 24
Peak memory 296880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323530883 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.2323530883 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.2197122353
Short name T710
Test name
Test status
Simulation time 12757646116 ps
CPU time 633.92 seconds
Started Oct 12 07:09:51 AM UTC 24
Finished Oct 12 07:20:33 AM UTC 24
Peak memory 249720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197122353 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2197122353 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.594433841
Short name T584
Test name
Test status
Simulation time 2654084172 ps
CPU time 69.99 seconds
Started Oct 12 07:09:55 AM UTC 24
Finished Oct 12 07:11:07 AM UTC 24
Peak memory 264060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594433841 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.594433841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.1103485469
Short name T612
Test name
Test status
Simulation time 17244294809 ps
CPU time 175.31 seconds
Started Oct 12 07:09:58 AM UTC 24
Finished Oct 12 07:12:56 AM UTC 24
Peak memory 311164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103485469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1103485469 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.2302679947
Short name T577
Test name
Test status
Simulation time 845484611 ps
CPU time 8.58 seconds
Started Oct 12 07:10:04 AM UTC 24
Finished Oct 12 07:10:13 AM UTC 24
Peak memory 230708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302679947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2302679947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.3808890020
Short name T575
Test name
Test status
Simulation time 108970774 ps
CPU time 1.73 seconds
Started Oct 12 07:10:06 AM UTC 24
Finished Oct 12 07:10:08 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808890020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3808890020 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.3149560940
Short name T668
Test name
Test status
Simulation time 19932340789 ps
CPU time 435.75 seconds
Started Oct 12 07:09:09 AM UTC 24
Finished Oct 12 07:16:31 AM UTC 24
Peak memory 526316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149560940 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.3149560940 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.2616631825
Short name T638
Test name
Test status
Simulation time 12881038491 ps
CPU time 316.8 seconds
Started Oct 12 07:09:16 AM UTC 24
Finished Oct 12 07:14:37 AM UTC 24
Peak memory 360424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616631825 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2616631825 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.3375476845
Short name T576
Test name
Test status
Simulation time 2686633587 ps
CPU time 61.9 seconds
Started Oct 12 07:09:08 AM UTC 24
Finished Oct 12 07:10:11 AM UTC 24
Peak memory 235500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375476845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3375476845 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.2715230980
Short name T611
Test name
Test status
Simulation time 10643022173 ps
CPU time 158.45 seconds
Started Oct 12 07:10:10 AM UTC 24
Finished Oct 12 07:12:51 AM UTC 24
Peak memory 319744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715230980 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2715230980 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.2437843788
Short name T589
Test name
Test status
Simulation time 49139737 ps
CPU time 1.18 seconds
Started Oct 12 07:11:14 AM UTC 24
Finished Oct 12 07:11:16 AM UTC 24
Peak memory 214136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437843788 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2437843788 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.3715937354
Short name T587
Test name
Test status
Simulation time 6646647454 ps
CPU time 34.75 seconds
Started Oct 12 07:10:37 AM UTC 24
Finished Oct 12 07:11:13 AM UTC 24
Peak memory 251880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715937354 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3715937354 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.1473983810
Short name T727
Test name
Test status
Simulation time 32052217889 ps
CPU time 905.81 seconds
Started Oct 12 07:10:32 AM UTC 24
Finished Oct 12 07:25:50 AM UTC 24
Peak memory 252012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473983810 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1473983810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.2345590538
Short name T601
Test name
Test status
Simulation time 5624927386 ps
CPU time 93.64 seconds
Started Oct 12 07:10:41 AM UTC 24
Finished Oct 12 07:12:16 AM UTC 24
Peak memory 270392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345590538 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2345590538 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.96285470
Short name T605
Test name
Test status
Simulation time 1178331053 ps
CPU time 99.55 seconds
Started Oct 12 07:10:42 AM UTC 24
Finished Oct 12 07:12:23 AM UTC 24
Peak memory 280684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96285470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.96285470 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.3096046785
Short name T591
Test name
Test status
Simulation time 1743397340 ps
CPU time 11.85 seconds
Started Oct 12 07:11:09 AM UTC 24
Finished Oct 12 07:11:22 AM UTC 24
Peak memory 230952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096046785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3096046785 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.2268300519
Short name T519
Test name
Test status
Simulation time 89463345 ps
CPU time 2.1 seconds
Started Oct 12 07:11:10 AM UTC 24
Finished Oct 12 07:11:13 AM UTC 24
Peak memory 230860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268300519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2268300519 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2609713505
Short name T642
Test name
Test status
Simulation time 6371672424 ps
CPU time 275.08 seconds
Started Oct 12 07:10:15 AM UTC 24
Finished Oct 12 07:14:54 AM UTC 24
Peak memory 417716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609713505 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2609713505 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.3108033474
Short name T673
Test name
Test status
Simulation time 3902126199 ps
CPU time 376.84 seconds
Started Oct 12 07:10:27 AM UTC 24
Finished Oct 12 07:16:50 AM UTC 24
Peak memory 366524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108033474 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3108033474 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload_invalid.560136419
Short name T581
Test name
Test status
Simulation time 254562093 ps
CPU time 2.93 seconds
Started Oct 12 07:10:27 AM UTC 24
Finished Oct 12 07:10:31 AM UTC 24
Peak memory 231340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560136419 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload_invalid.560136419 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.1260660670
Short name T580
Test name
Test status
Simulation time 2585827438 ps
CPU time 11.4 seconds
Started Oct 12 07:10:14 AM UTC 24
Finished Oct 12 07:10:27 AM UTC 24
Peak memory 231092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260660670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1260660670 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.1303547426
Short name T752
Test name
Test status
Simulation time 89041016009 ps
CPU time 2514.81 seconds
Started Oct 12 07:11:14 AM UTC 24
Finished Oct 12 07:53:37 AM UTC 24
Peak memory 1411528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303547426 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1303547426 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.2068397947
Short name T203
Test name
Test status
Simulation time 17371307 ps
CPU time 1.25 seconds
Started Oct 12 06:35:43 AM UTC 24
Finished Oct 12 06:35:46 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068397947 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2068397947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.2388493880
Short name T222
Test name
Test status
Simulation time 66975877327 ps
CPU time 310.9 seconds
Started Oct 12 06:34:51 AM UTC 24
Finished Oct 12 06:40:06 AM UTC 24
Peak memory 530300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388493880 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2388493880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.1633876141
Short name T202
Test name
Test status
Simulation time 3537608833 ps
CPU time 39.06 seconds
Started Oct 12 06:34:51 AM UTC 24
Finished Oct 12 06:35:32 AM UTC 24
Peak memory 258036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633876141 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1633876141 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.922452706
Short name T148
Test name
Test status
Simulation time 7786938244 ps
CPU time 249.52 seconds
Started Oct 12 06:34:27 AM UTC 24
Finished Oct 12 06:38:41 AM UTC 24
Peak memory 241528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922452706 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.922452706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.1729495149
Short name T201
Test name
Test status
Simulation time 405478242 ps
CPU time 7.36 seconds
Started Oct 12 06:35:23 AM UTC 24
Finished Oct 12 06:35:31 AM UTC 24
Peak memory 230832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729495149 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1729495149 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.4265481422
Short name T207
Test name
Test status
Simulation time 6806011544 ps
CPU time 48.9 seconds
Started Oct 12 06:35:30 AM UTC 24
Finished Oct 12 06:36:20 AM UTC 24
Peak memory 235192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265481422 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.4265481422 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.327593027
Short name T205
Test name
Test status
Simulation time 6596791076 ps
CPU time 30.09 seconds
Started Oct 12 06:35:31 AM UTC 24
Finished Oct 12 06:36:02 AM UTC 24
Peak memory 231036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327593027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.327593027 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1982492507
Short name T210
Test name
Test status
Simulation time 18593286609 ps
CPU time 170.76 seconds
Started Oct 12 06:34:53 AM UTC 24
Finished Oct 12 06:37:48 AM UTC 24
Peak memory 274308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982492507 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1982492507 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.2832869514
Short name T37
Test name
Test status
Simulation time 11297972468 ps
CPU time 118.54 seconds
Started Oct 12 06:35:11 AM UTC 24
Finished Oct 12 06:37:12 AM UTC 24
Peak memory 352172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832869514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2832869514 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.1460444745
Short name T75
Test name
Test status
Simulation time 2966263536 ps
CPU time 12.39 seconds
Started Oct 12 06:35:17 AM UTC 24
Finished Oct 12 06:35:30 AM UTC 24
Peak memory 230780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460444745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1460444745 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.1575446770
Short name T45
Test name
Test status
Simulation time 311496043 ps
CPU time 1.86 seconds
Started Oct 12 06:35:32 AM UTC 24
Finished Oct 12 06:35:35 AM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575446770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1575446770 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.3078993103
Short name T260
Test name
Test status
Simulation time 227705850518 ps
CPU time 588.5 seconds
Started Oct 12 06:34:08 AM UTC 24
Finished Oct 12 06:44:04 AM UTC 24
Peak memory 980980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078993103 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.3078993103 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.4140375938
Short name T89
Test name
Test status
Simulation time 41528301634 ps
CPU time 315.45 seconds
Started Oct 12 06:35:02 AM UTC 24
Finished Oct 12 06:40:21 AM UTC 24
Peak memory 485692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140375938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.4140375938 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.1401741121
Short name T78
Test name
Test status
Simulation time 4718787046 ps
CPU time 75.77 seconds
Started Oct 12 06:35:35 AM UTC 24
Finished Oct 12 06:36:53 AM UTC 24
Peak memory 292312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401741121 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1401741121 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.926081127
Short name T235
Test name
Test status
Simulation time 9635199712 ps
CPU time 479.01 seconds
Started Oct 12 06:34:14 AM UTC 24
Finished Oct 12 06:42:19 AM UTC 24
Peak memory 391040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926081127 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.926081127 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload_invalid.1557821913
Short name T43
Test name
Test status
Simulation time 95867982 ps
CPU time 5.78 seconds
Started Oct 12 06:34:19 AM UTC 24
Finished Oct 12 06:34:26 AM UTC 24
Peak memory 231364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557821913 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload_invalid.1557821913 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.3385081926
Short name T195
Test name
Test status
Simulation time 1999858360 ps
CPU time 26.49 seconds
Started Oct 12 06:34:01 AM UTC 24
Finished Oct 12 06:34:29 AM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385081926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3385081926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.2965864913
Short name T87
Test name
Test status
Simulation time 3790841951 ps
CPU time 213.33 seconds
Started Oct 12 06:35:32 AM UTC 24
Finished Oct 12 06:39:09 AM UTC 24
Peak memory 301512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965864913 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2965864913 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.773904933
Short name T196
Test name
Test status
Simulation time 229072676 ps
CPU time 3.29 seconds
Started Oct 12 06:34:46 AM UTC 24
Finished Oct 12 06:34:50 AM UTC 24
Peak memory 230972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773904933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.773904933 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.972216805
Short name T197
Test name
Test status
Simulation time 215270277 ps
CPU time 3.55 seconds
Started Oct 12 06:34:48 AM UTC 24
Finished Oct 12 06:34:53 AM UTC 24
Peak memory 231020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972216805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.972216805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.3936217752
Short name T570
Test name
Test status
Simulation time 61103237531 ps
CPU time 2097.54 seconds
Started Oct 12 06:34:29 AM UTC 24
Finished Oct 12 07:09:50 AM UTC 24
Peak memory 3157780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936217752 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3936217752
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.2604821814
Short name T200
Test name
Test status
Simulation time 3421836729 ps
CPU time 57.09 seconds
Started Oct 12 06:34:31 AM UTC 24
Finished Oct 12 06:35:29 AM UTC 24
Peak memory 253736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604821814 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2604821814
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.2563083717
Short name T199
Test name
Test status
Simulation time 6963514954 ps
CPU time 38.7 seconds
Started Oct 12 06:34:36 AM UTC 24
Finished Oct 12 06:35:16 AM UTC 24
Peak memory 239400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563083717 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2563083717
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.3958059735
Short name T311
Test name
Test status
Simulation time 8894755631 ps
CPU time 841.68 seconds
Started Oct 12 06:34:36 AM UTC 24
Finished Oct 12 06:48:47 AM UTC 24
Peak memory 700180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958059735 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3958059735
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.2832728306
Short name T182
Test name
Test status
Simulation time 9005123300 ps
CPU time 235.74 seconds
Started Oct 12 06:34:37 AM UTC 24
Finished Oct 12 06:38:36 AM UTC 24
Peak memory 446264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832728306 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2832728
306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.1641882175
Short name T243
Test name
Test status
Simulation time 449070556756 ps
CPU time 487.43 seconds
Started Oct 12 06:34:42 AM UTC 24
Finished Oct 12 06:42:56 AM UTC 24
Peak memory 360228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641882175 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1641882
175 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.1916681839
Short name T599
Test name
Test status
Simulation time 59336583 ps
CPU time 1.29 seconds
Started Oct 12 07:12:01 AM UTC 24
Finished Oct 12 07:12:04 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916681839 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1916681839 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.2093985697
Short name T620
Test name
Test status
Simulation time 12086180975 ps
CPU time 134.65 seconds
Started Oct 12 07:11:31 AM UTC 24
Finished Oct 12 07:13:48 AM UTC 24
Peak memory 356220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093985697 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2093985697 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.583598206
Short name T664
Test name
Test status
Simulation time 8813510423 ps
CPU time 290.77 seconds
Started Oct 12 07:11:23 AM UTC 24
Finished Oct 12 07:16:18 AM UTC 24
Peak memory 243712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583598206 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.583598206 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.1261271375
Short name T669
Test name
Test status
Simulation time 14584658355 ps
CPU time 292.99 seconds
Started Oct 12 07:11:35 AM UTC 24
Finished Oct 12 07:16:32 AM UTC 24
Peak memory 432052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261271375 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1261271375 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.1468488400
Short name T683
Test name
Test status
Simulation time 33209428840 ps
CPU time 371.54 seconds
Started Oct 12 07:11:40 AM UTC 24
Finished Oct 12 07:17:56 AM UTC 24
Peak memory 573476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468488400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1468488400 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.673525822
Short name T598
Test name
Test status
Simulation time 3623559673 ps
CPU time 11.87 seconds
Started Oct 12 07:11:49 AM UTC 24
Finished Oct 12 07:12:02 AM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673525822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.673525822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.2035091328
Short name T597
Test name
Test status
Simulation time 41751131 ps
CPU time 2.11 seconds
Started Oct 12 07:11:57 AM UTC 24
Finished Oct 12 07:12:00 AM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035091328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2035091328 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.357554313
Short name T753
Test name
Test status
Simulation time 110630068184 ps
CPU time 2749.45 seconds
Started Oct 12 07:11:15 AM UTC 24
Finished Oct 12 07:57:35 AM UTC 24
Peak memory 1884012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357554313 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.357554313 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.3893800177
Short name T619
Test name
Test status
Simulation time 8970349770 ps
CPU time 146.01 seconds
Started Oct 12 07:11:17 AM UTC 24
Finished Oct 12 07:13:46 AM UTC 24
Peak memory 299008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893800177 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3893800177 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.4175057450
Short name T600
Test name
Test status
Simulation time 3682950625 ps
CPU time 52.73 seconds
Started Oct 12 07:11:14 AM UTC 24
Finished Oct 12 07:12:09 AM UTC 24
Peak memory 235436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175057450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.4175057450 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.644405245
Short name T726
Test name
Test status
Simulation time 17410381756 ps
CPU time 786.05 seconds
Started Oct 12 07:12:01 AM UTC 24
Finished Oct 12 07:25:18 AM UTC 24
Peak memory 496064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644405245 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.644405245 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.2728846775
Short name T610
Test name
Test status
Simulation time 25411848 ps
CPU time 1.29 seconds
Started Oct 12 07:12:44 AM UTC 24
Finished Oct 12 07:12:46 AM UTC 24
Peak memory 214136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728846775 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2728846775 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.2876761493
Short name T616
Test name
Test status
Simulation time 6385577944 ps
CPU time 56.87 seconds
Started Oct 12 07:12:22 AM UTC 24
Finished Oct 12 07:13:20 AM UTC 24
Peak memory 247672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876761493 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2876761493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.3872231641
Short name T623
Test name
Test status
Simulation time 2308785708 ps
CPU time 103.75 seconds
Started Oct 12 07:12:20 AM UTC 24
Finished Oct 12 07:14:06 AM UTC 24
Peak memory 235068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872231641 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3872231641 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.3195249969
Short name T645
Test name
Test status
Simulation time 36726596809 ps
CPU time 170.86 seconds
Started Oct 12 07:12:22 AM UTC 24
Finished Oct 12 07:15:16 AM UTC 24
Peak memory 325552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195249969 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3195249969 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.1292725424
Short name T614
Test name
Test status
Simulation time 1021899645 ps
CPU time 34.27 seconds
Started Oct 12 07:12:24 AM UTC 24
Finished Oct 12 07:13:00 AM UTC 24
Peak memory 261952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292725424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1292725424 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.136622598
Short name T609
Test name
Test status
Simulation time 1462821109 ps
CPU time 11.66 seconds
Started Oct 12 07:12:31 AM UTC 24
Finished Oct 12 07:12:44 AM UTC 24
Peak memory 230900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136622598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.136622598 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.2153032311
Short name T98
Test name
Test status
Simulation time 67826370 ps
CPU time 1.61 seconds
Started Oct 12 07:12:39 AM UTC 24
Finished Oct 12 07:12:42 AM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153032311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2153032311 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.156569210
Short name T756
Test name
Test status
Simulation time 359718560139 ps
CPU time 3155.5 seconds
Started Oct 12 07:12:04 AM UTC 24
Finished Oct 12 08:05:14 AM UTC 24
Peak memory 3590124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156569210 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.156569210 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.519915102
Short name T690
Test name
Test status
Simulation time 36237779671 ps
CPU time 405.88 seconds
Started Oct 12 07:12:10 AM UTC 24
Finished Oct 12 07:19:01 AM UTC 24
Peak memory 599928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519915102 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.519915102 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload_invalid.2851958775
Short name T603
Test name
Test status
Simulation time 174778808 ps
CPU time 2.97 seconds
Started Oct 12 07:12:17 AM UTC 24
Finished Oct 12 07:12:21 AM UTC 24
Peak memory 231476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851958775 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload_invalid.2851958775 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.2495766697
Short name T613
Test name
Test status
Simulation time 4014355443 ps
CPU time 52.65 seconds
Started Oct 12 07:12:02 AM UTC 24
Finished Oct 12 07:12:57 AM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495766697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2495766697 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.3213387454
Short name T704
Test name
Test status
Simulation time 18776992857 ps
CPU time 427.93 seconds
Started Oct 12 07:12:40 AM UTC 24
Finished Oct 12 07:19:54 AM UTC 24
Peak memory 774128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213387454 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3213387454 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.1215946245
Short name T621
Test name
Test status
Simulation time 41643561 ps
CPU time 1.21 seconds
Started Oct 12 07:13:47 AM UTC 24
Finished Oct 12 07:13:49 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215946245 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1215946245 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.1931827585
Short name T643
Test name
Test status
Simulation time 5118680640 ps
CPU time 128.6 seconds
Started Oct 12 07:13:01 AM UTC 24
Finished Oct 12 07:15:13 AM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931827585 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1931827585 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.2844136591
Short name T732
Test name
Test status
Simulation time 44454105281 ps
CPU time 890.66 seconds
Started Oct 12 07:12:58 AM UTC 24
Finished Oct 12 07:28:01 AM UTC 24
Peak memory 268204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844136591 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2844136591 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1892578751
Short name T626
Test name
Test status
Simulation time 5777179994 ps
CPU time 65.83 seconds
Started Oct 12 07:13:02 AM UTC 24
Finished Oct 12 07:14:10 AM UTC 24
Peak memory 264120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892578751 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1892578751 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.1201673488
Short name T689
Test name
Test status
Simulation time 10078296734 ps
CPU time 301.99 seconds
Started Oct 12 07:13:21 AM UTC 24
Finished Oct 12 07:18:28 AM UTC 24
Peak memory 514032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201673488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1201673488 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.4030570484
Short name T618
Test name
Test status
Simulation time 3095141183 ps
CPU time 15.03 seconds
Started Oct 12 07:13:25 AM UTC 24
Finished Oct 12 07:13:42 AM UTC 24
Peak memory 230812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030570484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.4030570484 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.1245219307
Short name T71
Test name
Test status
Simulation time 55439418 ps
CPU time 2.15 seconds
Started Oct 12 07:13:43 AM UTC 24
Finished Oct 12 07:13:46 AM UTC 24
Peak memory 230740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245219307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1245219307 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.741658860
Short name T746
Test name
Test status
Simulation time 81273492566 ps
CPU time 1684.17 seconds
Started Oct 12 07:12:47 AM UTC 24
Finished Oct 12 07:41:11 AM UTC 24
Peak memory 2150376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741658860 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.741658860 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.3789879396
Short name T629
Test name
Test status
Simulation time 8099460675 ps
CPU time 235.4 seconds
Started Oct 12 07:12:52 AM UTC 24
Finished Oct 12 07:16:51 AM UTC 24
Peak memory 460728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789879396 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3789879396 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.2667755194
Short name T743
Test name
Test status
Simulation time 16626803710 ps
CPU time 1330.49 seconds
Started Oct 12 07:13:47 AM UTC 24
Finished Oct 12 07:36:13 AM UTC 24
Peak memory 766272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667755194 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2667755194 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.566247023
Short name T633
Test name
Test status
Simulation time 47334627 ps
CPU time 1.2 seconds
Started Oct 12 07:14:24 AM UTC 24
Finished Oct 12 07:14:26 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566247023 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.566247023 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.587762297
Short name T703
Test name
Test status
Simulation time 102284394042 ps
CPU time 338.01 seconds
Started Oct 12 07:14:10 AM UTC 24
Finished Oct 12 07:19:53 AM UTC 24
Peak memory 489376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587762297 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.587762297 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3680926810
Short name T745
Test name
Test status
Simulation time 282392448346 ps
CPU time 1379.58 seconds
Started Oct 12 07:14:07 AM UTC 24
Finished Oct 12 07:37:24 AM UTC 24
Peak memory 278452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680926810 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3680926810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.4125650177
Short name T646
Test name
Test status
Simulation time 9485311154 ps
CPU time 63.6 seconds
Started Oct 12 07:14:10 AM UTC 24
Finished Oct 12 07:15:16 AM UTC 24
Peak memory 255864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125650177 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.4125650177 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.234935814
Short name T660
Test name
Test status
Simulation time 1368314427 ps
CPU time 106.23 seconds
Started Oct 12 07:14:14 AM UTC 24
Finished Oct 12 07:16:02 AM UTC 24
Peak memory 284540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234935814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.234935814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.2345425278
Short name T635
Test name
Test status
Simulation time 2346104185 ps
CPU time 9.4 seconds
Started Oct 12 07:14:17 AM UTC 24
Finished Oct 12 07:14:28 AM UTC 24
Peak memory 230804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345425278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2345425278 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.985963262
Short name T631
Test name
Test status
Simulation time 65849490 ps
CPU time 1.9 seconds
Started Oct 12 07:14:20 AM UTC 24
Finished Oct 12 07:14:23 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985963262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.985963262 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.53170238
Short name T720
Test name
Test status
Simulation time 5941058464 ps
CPU time 533.82 seconds
Started Oct 12 07:13:50 AM UTC 24
Finished Oct 12 07:22:51 AM UTC 24
Peak memory 604088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53170238 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.53170238 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.1797727505
Short name T654
Test name
Test status
Simulation time 18631529081 ps
CPU time 116.13 seconds
Started Oct 12 07:13:55 AM UTC 24
Finished Oct 12 07:15:53 AM UTC 24
Peak memory 325556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797727505 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1797727505 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload_invalid.3376775476
Short name T627
Test name
Test status
Simulation time 229519856 ps
CPU time 4.24 seconds
Started Oct 12 07:14:07 AM UTC 24
Finished Oct 12 07:14:12 AM UTC 24
Peak memory 231416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376775476 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload_invalid.3376775476 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.3163222355
Short name T639
Test name
Test status
Simulation time 1063007912 ps
CPU time 54.53 seconds
Started Oct 12 07:13:49 AM UTC 24
Finished Oct 12 07:14:45 AM UTC 24
Peak memory 235196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163222355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3163222355 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.1010534008
Short name T634
Test name
Test status
Simulation time 54142142 ps
CPU time 2.1 seconds
Started Oct 12 07:14:23 AM UTC 24
Finished Oct 12 07:14:26 AM UTC 24
Peak memory 230980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010534008 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1010534008 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.102269160
Short name T644
Test name
Test status
Simulation time 56291025 ps
CPU time 1.26 seconds
Started Oct 12 07:15:13 AM UTC 24
Finished Oct 12 07:15:16 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102269160 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.102269160 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.1909161237
Short name T656
Test name
Test status
Simulation time 8289114201 ps
CPU time 76.87 seconds
Started Oct 12 07:14:37 AM UTC 24
Finished Oct 12 07:15:56 AM UTC 24
Peak memory 294820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909161237 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1909161237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.4044808850
Short name T678
Test name
Test status
Simulation time 3630113781 ps
CPU time 156.54 seconds
Started Oct 12 07:14:36 AM UTC 24
Finished Oct 12 07:17:16 AM UTC 24
Peak memory 247860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044808850 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.4044808850 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.549801829
Short name T659
Test name
Test status
Simulation time 1882557317 ps
CPU time 79.19 seconds
Started Oct 12 07:14:39 AM UTC 24
Finished Oct 12 07:16:00 AM UTC 24
Peak memory 259960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549801829 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.549801829 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.2234206550
Short name T681
Test name
Test status
Simulation time 7483197355 ps
CPU time 168.92 seconds
Started Oct 12 07:14:46 AM UTC 24
Finished Oct 12 07:17:37 AM UTC 24
Peak memory 372772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234206550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2234206550 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.3666215726
Short name T641
Test name
Test status
Simulation time 461565474 ps
CPU time 2.43 seconds
Started Oct 12 07:14:47 AM UTC 24
Finished Oct 12 07:14:50 AM UTC 24
Peak memory 230716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666215726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3666215726 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.6416926
Short name T647
Test name
Test status
Simulation time 971440746 ps
CPU time 25.29 seconds
Started Oct 12 07:14:51 AM UTC 24
Finished Oct 12 07:15:18 AM UTC 24
Peak memory 251896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6416926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.6416926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.1785137207
Short name T680
Test name
Test status
Simulation time 7775457173 ps
CPU time 181.76 seconds
Started Oct 12 07:14:27 AM UTC 24
Finished Oct 12 07:17:32 AM UTC 24
Peak memory 341872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785137207 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.1785137207 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.2081681503
Short name T652
Test name
Test status
Simulation time 4281447863 ps
CPU time 76.03 seconds
Started Oct 12 07:14:27 AM UTC 24
Finished Oct 12 07:15:45 AM UTC 24
Peak memory 294884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081681503 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2081681503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload_invalid.2054885999
Short name T636
Test name
Test status
Simulation time 97830392 ps
CPU time 5.57 seconds
Started Oct 12 07:14:28 AM UTC 24
Finished Oct 12 07:14:35 AM UTC 24
Peak memory 231312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054885999 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload_invalid.2054885999 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.3923124100
Short name T637
Test name
Test status
Simulation time 1306663510 ps
CPU time 11.67 seconds
Started Oct 12 07:14:24 AM UTC 24
Finished Oct 12 07:14:37 AM UTC 24
Peak memory 230916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923124100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3923124100 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.1009136850
Short name T679
Test name
Test status
Simulation time 12296827584 ps
CPU time 147.22 seconds
Started Oct 12 07:14:55 AM UTC 24
Finished Oct 12 07:17:25 AM UTC 24
Peak memory 252288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009136850 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1009136850 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.4254701679
Short name T658
Test name
Test status
Simulation time 17254181 ps
CPU time 1.14 seconds
Started Oct 12 07:15:55 AM UTC 24
Finished Oct 12 07:15:57 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254701679 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.4254701679 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.2035744827
Short name T711
Test name
Test status
Simulation time 78879253345 ps
CPU time 333.89 seconds
Started Oct 12 07:15:24 AM UTC 24
Finished Oct 12 07:21:03 AM UTC 24
Peak memory 493412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035744827 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2035744827 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.3556788632
Short name T663
Test name
Test status
Simulation time 1311429841 ps
CPU time 52.18 seconds
Started Oct 12 07:15:21 AM UTC 24
Finished Oct 12 07:16:15 AM UTC 24
Peak memory 235556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556788632 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3556788632 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.4052105721
Short name T653
Test name
Test status
Simulation time 1243229816 ps
CPU time 24.17 seconds
Started Oct 12 07:15:24 AM UTC 24
Finished Oct 12 07:15:49 AM UTC 24
Peak memory 251760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052105721 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.4052105721 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.2111461465
Short name T715
Test name
Test status
Simulation time 11861531074 ps
CPU time 404.91 seconds
Started Oct 12 07:15:30 AM UTC 24
Finished Oct 12 07:22:21 AM UTC 24
Peak memory 536576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111461465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2111461465 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.621778941
Short name T655
Test name
Test status
Simulation time 2495164244 ps
CPU time 10.93 seconds
Started Oct 12 07:15:44 AM UTC 24
Finished Oct 12 07:15:56 AM UTC 24
Peak memory 230872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621778941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.621778941 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.2845232418
Short name T665
Test name
Test status
Simulation time 1289464678 ps
CPU time 32.41 seconds
Started Oct 12 07:15:46 AM UTC 24
Finished Oct 12 07:16:20 AM UTC 24
Peak memory 251816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845232418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2845232418 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.2646412432
Short name T749
Test name
Test status
Simulation time 30832868258 ps
CPU time 1678.68 seconds
Started Oct 12 07:15:16 AM UTC 24
Finished Oct 12 07:43:35 AM UTC 24
Peak memory 1156984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646412432 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.2646412432 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.581334799
Short name T657
Test name
Test status
Simulation time 387932737 ps
CPU time 38.58 seconds
Started Oct 12 07:15:16 AM UTC 24
Finished Oct 12 07:15:56 AM UTC 24
Peak memory 241580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581334799 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.581334799 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload_invalid.13026916
Short name T648
Test name
Test status
Simulation time 73600342 ps
CPU time 3.17 seconds
Started Oct 12 07:15:19 AM UTC 24
Finished Oct 12 07:15:23 AM UTC 24
Peak memory 231432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13026916 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload_invalid.13026916 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.3096743310
Short name T649
Test name
Test status
Simulation time 294935174 ps
CPU time 5.91 seconds
Started Oct 12 07:15:16 AM UTC 24
Finished Oct 12 07:15:23 AM UTC 24
Peak memory 231104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096743310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3096743310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.3464108137
Short name T716
Test name
Test status
Simulation time 36822519072 ps
CPU time 392.96 seconds
Started Oct 12 07:15:51 AM UTC 24
Finished Oct 12 07:22:29 AM UTC 24
Peak memory 301052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464108137 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3464108137 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.3684576939
Short name T667
Test name
Test status
Simulation time 46962739 ps
CPU time 1.19 seconds
Started Oct 12 07:16:23 AM UTC 24
Finished Oct 12 07:16:25 AM UTC 24
Peak memory 214136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684576939 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3684576939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.3858901942
Short name T662
Test name
Test status
Simulation time 421577893 ps
CPU time 7.45 seconds
Started Oct 12 07:16:03 AM UTC 24
Finished Oct 12 07:16:12 AM UTC 24
Peak memory 231028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858901942 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3858901942 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.378998542
Short name T731
Test name
Test status
Simulation time 15750727556 ps
CPU time 699.65 seconds
Started Oct 12 07:16:00 AM UTC 24
Finished Oct 12 07:27:49 AM UTC 24
Peak memory 251832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378998542 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.378998542 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2010461248
Short name T693
Test name
Test status
Simulation time 23838606132 ps
CPU time 185.05 seconds
Started Oct 12 07:16:07 AM UTC 24
Finished Oct 12 07:19:15 AM UTC 24
Peak memory 313396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010461248 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2010461248 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.4135879973
Short name T708
Test name
Test status
Simulation time 9028862444 ps
CPU time 248.84 seconds
Started Oct 12 07:16:12 AM UTC 24
Finished Oct 12 07:20:25 AM UTC 24
Peak memory 456632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135879973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4135879973 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.1224807479
Short name T666
Test name
Test status
Simulation time 5223555831 ps
CPU time 6.61 seconds
Started Oct 12 07:16:15 AM UTC 24
Finished Oct 12 07:16:23 AM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224807479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1224807479 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.2679221970
Short name T72
Test name
Test status
Simulation time 63188471 ps
CPU time 1.83 seconds
Started Oct 12 07:16:18 AM UTC 24
Finished Oct 12 07:16:21 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679221970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2679221970 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2041915447
Short name T759
Test name
Test status
Simulation time 77673073708 ps
CPU time 3352.17 seconds
Started Oct 12 07:15:58 AM UTC 24
Finished Oct 12 08:12:28 AM UTC 24
Peak memory 3837916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041915447 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2041915447 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.2141034799
Short name T717
Test name
Test status
Simulation time 51375730893 ps
CPU time 388.98 seconds
Started Oct 12 07:15:58 AM UTC 24
Finished Oct 12 07:22:33 AM UTC 24
Peak memory 565228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141034799 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2141034799 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload_invalid.2455389715
Short name T661
Test name
Test status
Simulation time 780303486 ps
CPU time 6.05 seconds
Started Oct 12 07:15:58 AM UTC 24
Finished Oct 12 07:16:05 AM UTC 24
Peak memory 231336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455389715 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload_invalid.2455389715 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.2039545540
Short name T675
Test name
Test status
Simulation time 7622572257 ps
CPU time 65.84 seconds
Started Oct 12 07:15:57 AM UTC 24
Finished Oct 12 07:17:04 AM UTC 24
Peak memory 235320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039545540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2039545540 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.2878002197
Short name T699
Test name
Test status
Simulation time 7631759552 ps
CPU time 188.37 seconds
Started Oct 12 07:16:21 AM UTC 24
Finished Oct 12 07:19:33 AM UTC 24
Peak memory 348188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878002197 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2878002197 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.1016614210
Short name T677
Test name
Test status
Simulation time 38480102 ps
CPU time 1.15 seconds
Started Oct 12 07:17:08 AM UTC 24
Finished Oct 12 07:17:10 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016614210 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1016614210 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.4193019114
Short name T674
Test name
Test status
Simulation time 409765577 ps
CPU time 7.04 seconds
Started Oct 12 07:16:44 AM UTC 24
Finished Oct 12 07:16:52 AM UTC 24
Peak memory 231024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193019114 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4193019114 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.4090131660
Short name T734
Test name
Test status
Simulation time 48093079295 ps
CPU time 732.1 seconds
Started Oct 12 07:16:37 AM UTC 24
Finished Oct 12 07:28:59 AM UTC 24
Peak memory 262064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090131660 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.4090131660 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.3077970561
Short name T705
Test name
Test status
Simulation time 16591005779 ps
CPU time 189.51 seconds
Started Oct 12 07:16:45 AM UTC 24
Finished Oct 12 07:19:58 AM UTC 24
Peak memory 339892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077970561 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3077970561 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.4085527004
Short name T698
Test name
Test status
Simulation time 3983878447 ps
CPU time 155.03 seconds
Started Oct 12 07:16:51 AM UTC 24
Finished Oct 12 07:19:29 AM UTC 24
Peak memory 348068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085527004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.4085527004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.1658180743
Short name T676
Test name
Test status
Simulation time 1932866020 ps
CPU time 13.7 seconds
Started Oct 12 07:16:52 AM UTC 24
Finished Oct 12 07:17:07 AM UTC 24
Peak memory 230708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658180743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1658180743 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.2719046895
Short name T685
Test name
Test status
Simulation time 8676359881 ps
CPU time 77.02 seconds
Started Oct 12 07:16:52 AM UTC 24
Finished Oct 12 07:18:11 AM UTC 24
Peak memory 266224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719046895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2719046895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.456368994
Short name T736
Test name
Test status
Simulation time 9276385192 ps
CPU time 909.18 seconds
Started Oct 12 07:16:26 AM UTC 24
Finished Oct 12 07:31:47 AM UTC 24
Peak memory 821172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456368994 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.456368994 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.2488944327
Short name T671
Test name
Test status
Simulation time 170477565 ps
CPU time 9.29 seconds
Started Oct 12 07:16:32 AM UTC 24
Finished Oct 12 07:16:43 AM UTC 24
Peak memory 233028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488944327 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2488944327 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.1816992575
Short name T670
Test name
Test status
Simulation time 606685529 ps
CPU time 11.95 seconds
Started Oct 12 07:16:24 AM UTC 24
Finished Oct 12 07:16:37 AM UTC 24
Peak memory 231024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816992575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1816992575 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.737892307
Short name T719
Test name
Test status
Simulation time 15064449645 ps
CPU time 333.6 seconds
Started Oct 12 07:17:06 AM UTC 24
Finished Oct 12 07:22:44 AM UTC 24
Peak memory 362796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737892307 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.737892307 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.2827052885
Short name T688
Test name
Test status
Simulation time 53691437 ps
CPU time 1.16 seconds
Started Oct 12 07:18:19 AM UTC 24
Finished Oct 12 07:18:21 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827052885 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2827052885 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.717086822
Short name T718
Test name
Test status
Simulation time 8746467367 ps
CPU time 291.78 seconds
Started Oct 12 07:17:39 AM UTC 24
Finished Oct 12 07:22:35 AM UTC 24
Peak memory 409496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717086822 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.717086822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.3167371161
Short name T684
Test name
Test status
Simulation time 2211725268 ps
CPU time 29.7 seconds
Started Oct 12 07:17:33 AM UTC 24
Finished Oct 12 07:18:04 AM UTC 24
Peak memory 231028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167371161 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3167371161 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3726127114
Short name T694
Test name
Test status
Simulation time 4872754970 ps
CPU time 96.04 seconds
Started Oct 12 07:17:43 AM UTC 24
Finished Oct 12 07:19:21 AM UTC 24
Peak memory 266100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726127114 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3726127114 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.1311890457
Short name T728
Test name
Test status
Simulation time 16083444717 ps
CPU time 495.07 seconds
Started Oct 12 07:17:57 AM UTC 24
Finished Oct 12 07:26:20 AM UTC 24
Peak memory 597948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311890457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1311890457 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.499138347
Short name T687
Test name
Test status
Simulation time 2717640653 ps
CPU time 12.38 seconds
Started Oct 12 07:18:04 AM UTC 24
Finished Oct 12 07:18:18 AM UTC 24
Peak memory 230780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499138347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.499138347 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.4213633034
Short name T686
Test name
Test status
Simulation time 41353202 ps
CPU time 1.91 seconds
Started Oct 12 07:18:13 AM UTC 24
Finished Oct 12 07:18:15 AM UTC 24
Peak memory 229840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213633034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.4213633034 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3173158454
Short name T751
Test name
Test status
Simulation time 18624814634 ps
CPU time 1777.43 seconds
Started Oct 12 07:17:17 AM UTC 24
Finished Oct 12 07:47:15 AM UTC 24
Peak memory 1376120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173158454 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3173158454 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.3778129533
Short name T706
Test name
Test status
Simulation time 3421452690 ps
CPU time 163.69 seconds
Started Oct 12 07:17:20 AM UTC 24
Finished Oct 12 07:20:07 AM UTC 24
Peak memory 292796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778129533 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3778129533 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.2389780902
Short name T682
Test name
Test status
Simulation time 1047722407 ps
CPU time 29.33 seconds
Started Oct 12 07:17:11 AM UTC 24
Finished Oct 12 07:17:42 AM UTC 24
Peak memory 231020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389780902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2389780902 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.2442441109
Short name T712
Test name
Test status
Simulation time 36145724824 ps
CPU time 199.24 seconds
Started Oct 12 07:18:17 AM UTC 24
Finished Oct 12 07:21:39 AM UTC 24
Peak memory 330228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442441109 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2442441109 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.1896446924
Short name T700
Test name
Test status
Simulation time 14203487 ps
CPU time 1.19 seconds
Started Oct 12 07:19:31 AM UTC 24
Finished Oct 12 07:19:33 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896446924 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1896446924 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.4249694198
Short name T702
Test name
Test status
Simulation time 4601323101 ps
CPU time 33.45 seconds
Started Oct 12 07:19:10 AM UTC 24
Finished Oct 12 07:19:45 AM UTC 24
Peak memory 237428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249694198 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.4249694198 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.4111048518
Short name T741
Test name
Test status
Simulation time 87001357113 ps
CPU time 947.63 seconds
Started Oct 12 07:19:09 AM UTC 24
Finished Oct 12 07:35:08 AM UTC 24
Peak memory 266076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111048518 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.4111048518 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.3891192220
Short name T697
Test name
Test status
Simulation time 1258727499 ps
CPU time 11.29 seconds
Started Oct 12 07:19:16 AM UTC 24
Finished Oct 12 07:19:29 AM UTC 24
Peak memory 230888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891192220 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3891192220 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.399259820
Short name T721
Test name
Test status
Simulation time 9462107339 ps
CPU time 230.24 seconds
Started Oct 12 07:19:22 AM UTC 24
Finished Oct 12 07:23:16 AM UTC 24
Peak memory 323504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399259820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.399259820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.2608387931
Short name T701
Test name
Test status
Simulation time 5235824425 ps
CPU time 13.8 seconds
Started Oct 12 07:19:24 AM UTC 24
Finished Oct 12 07:19:39 AM UTC 24
Peak memory 230828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608387931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2608387931 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.4148476269
Short name T97
Test name
Test status
Simulation time 60713146 ps
CPU time 1.92 seconds
Started Oct 12 07:19:28 AM UTC 24
Finished Oct 12 07:19:31 AM UTC 24
Peak memory 234688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148476269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.4148476269 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.180063194
Short name T760
Test name
Test status
Simulation time 264936012257 ps
CPU time 5012.26 seconds
Started Oct 12 07:18:29 AM UTC 24
Finished Oct 12 08:42:57 AM UTC 24
Peak memory 4886560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180063194 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.180063194 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.1347598607
Short name T709
Test name
Test status
Simulation time 3956174191 ps
CPU time 104.38 seconds
Started Oct 12 07:18:38 AM UTC 24
Finished Oct 12 07:20:25 AM UTC 24
Peak memory 331648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347598607 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1347598607 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload_invalid.3629005647
Short name T691
Test name
Test status
Simulation time 660115260 ps
CPU time 5.14 seconds
Started Oct 12 07:19:02 AM UTC 24
Finished Oct 12 07:19:08 AM UTC 24
Peak memory 233388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629005647 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload_invalid.3629005647 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.3638236046
Short name T692
Test name
Test status
Simulation time 3853136650 ps
CPU time 45.4 seconds
Started Oct 12 07:18:22 AM UTC 24
Finished Oct 12 07:19:09 AM UTC 24
Peak memory 231008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638236046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.3638236046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.2960545271
Short name T740
Test name
Test status
Simulation time 49979911060 ps
CPU time 872.76 seconds
Started Oct 12 07:19:31 AM UTC 24
Finished Oct 12 07:34:14 AM UTC 24
Peak memory 913384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960545271 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2960545271 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.3926656779
Short name T211
Test name
Test status
Simulation time 19968323 ps
CPU time 1.31 seconds
Started Oct 12 06:37:47 AM UTC 24
Finished Oct 12 06:37:50 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926656779 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3926656779 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.2899655277
Short name T229
Test name
Test status
Simulation time 11716169254 ps
CPU time 287.31 seconds
Started Oct 12 06:36:20 AM UTC 24
Finished Oct 12 06:41:11 AM UTC 24
Peak memory 501732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899655277 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2899655277 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.2837741743
Short name T121
Test name
Test status
Simulation time 6690727485 ps
CPU time 87.94 seconds
Started Oct 12 06:36:21 AM UTC 24
Finished Oct 12 06:37:51 AM UTC 24
Peak memory 294844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837741743 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2837741743 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.2188387425
Short name T150
Test name
Test status
Simulation time 15755484918 ps
CPU time 676.26 seconds
Started Oct 12 06:36:13 AM UTC 24
Finished Oct 12 06:47:38 AM UTC 24
Peak memory 249720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188387425 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2188387425 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.576327401
Short name T213
Test name
Test status
Simulation time 6462912852 ps
CPU time 41.26 seconds
Started Oct 12 06:37:15 AM UTC 24
Finished Oct 12 06:37:57 AM UTC 24
Peak memory 230960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576327401 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.576327401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.1481374403
Short name T212
Test name
Test status
Simulation time 3596956480 ps
CPU time 32.29 seconds
Started Oct 12 06:37:21 AM UTC 24
Finished Oct 12 06:37:54 AM UTC 24
Peak memory 235228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481374403 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1481374403 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.4172908545
Short name T180
Test name
Test status
Simulation time 7815816623 ps
CPU time 29 seconds
Started Oct 12 06:37:31 AM UTC 24
Finished Oct 12 06:38:01 AM UTC 24
Peak memory 230988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172908545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.4172908545 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.1580160132
Short name T99
Test name
Test status
Simulation time 1023087555 ps
CPU time 40.03 seconds
Started Oct 12 06:36:54 AM UTC 24
Finished Oct 12 06:37:35 AM UTC 24
Peak memory 264056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580160132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1580160132 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.2474608421
Short name T209
Test name
Test status
Simulation time 6387669251 ps
CPU time 15.86 seconds
Started Oct 12 06:37:13 AM UTC 24
Finished Oct 12 06:37:30 AM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474608421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2474608421 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.2145878264
Short name T122
Test name
Test status
Simulation time 43444067 ps
CPU time 2.09 seconds
Started Oct 12 06:37:35 AM UTC 24
Finished Oct 12 06:37:38 AM UTC 24
Peak memory 230812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145878264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2145878264 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.3047477442
Short name T413
Test name
Test status
Simulation time 23930341255 ps
CPU time 1271.31 seconds
Started Oct 12 06:35:54 AM UTC 24
Finished Oct 12 06:57:20 AM UTC 24
Peak memory 939952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047477442 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.3047477442 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.3368778968
Short name T91
Test name
Test status
Simulation time 12254479264 ps
CPU time 274.78 seconds
Started Oct 12 06:36:37 AM UTC 24
Finished Oct 12 06:41:16 AM UTC 24
Peak memory 469256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368778968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3368778968 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.2345958508
Short name T208
Test name
Test status
Simulation time 3465183653 ps
CPU time 31.49 seconds
Started Oct 12 06:36:04 AM UTC 24
Finished Oct 12 06:36:37 AM UTC 24
Peak memory 251960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345958508 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2345958508 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload_invalid.2307308474
Short name T125
Test name
Test status
Simulation time 82870678 ps
CPU time 2.5 seconds
Started Oct 12 06:36:09 AM UTC 24
Finished Oct 12 06:36:12 AM UTC 24
Peak memory 231284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307308474 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload_invalid.2307308474 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.853562961
Short name T204
Test name
Test status
Simulation time 918924494 ps
CPU time 5.37 seconds
Started Oct 12 06:35:47 AM UTC 24
Finished Oct 12 06:35:53 AM UTC 24
Peak memory 231004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853562961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.853562961 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.2731052572
Short name T237
Test name
Test status
Simulation time 19648514443 ps
CPU time 296.42 seconds
Started Oct 12 06:37:36 AM UTC 24
Finished Oct 12 06:42:36 AM UTC 24
Peak memory 348136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731052572 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2731052572 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.3173563805
Short name T219
Test name
Test status
Simulation time 55881631 ps
CPU time 1.26 seconds
Started Oct 12 06:38:59 AM UTC 24
Finished Oct 12 06:39:01 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173563805 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3173563805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.1188594222
Short name T240
Test name
Test status
Simulation time 9505207222 ps
CPU time 277.92 seconds
Started Oct 12 06:38:01 AM UTC 24
Finished Oct 12 06:42:43 AM UTC 24
Peak memory 432244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188594222 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1188594222 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.738922355
Short name T259
Test name
Test status
Simulation time 28114515378 ps
CPU time 352.48 seconds
Started Oct 12 06:38:02 AM UTC 24
Finished Oct 12 06:43:59 AM UTC 24
Peak memory 487348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738922355 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.738922355 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.2686205252
Short name T338
Test name
Test status
Simulation time 19068584572 ps
CPU time 816.45 seconds
Started Oct 12 06:37:59 AM UTC 24
Finished Oct 12 06:51:45 AM UTC 24
Peak memory 262140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686205252 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2686205252 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.448852961
Short name T218
Test name
Test status
Simulation time 814491085 ps
CPU time 20.63 seconds
Started Oct 12 06:38:37 AM UTC 24
Finished Oct 12 06:38:58 AM UTC 24
Peak memory 235232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448852961 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.448852961 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.533948556
Short name T216
Test name
Test status
Simulation time 268142153 ps
CPU time 7.57 seconds
Started Oct 12 06:38:39 AM UTC 24
Finished Oct 12 06:38:47 AM UTC 24
Peak memory 228660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533948556 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.533948556 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3391169290
Short name T220
Test name
Test status
Simulation time 21017086249 ps
CPU time 63.13 seconds
Started Oct 12 06:38:42 AM UTC 24
Finished Oct 12 06:39:47 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391169290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3391169290 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3394497791
Short name T276
Test name
Test status
Simulation time 23675212687 ps
CPU time 414.91 seconds
Started Oct 12 06:38:06 AM UTC 24
Finished Oct 12 06:45:06 AM UTC 24
Peak memory 536508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394497791 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3394497791 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.2752150280
Short name T100
Test name
Test status
Simulation time 15132656778 ps
CPU time 257.02 seconds
Started Oct 12 06:38:26 AM UTC 24
Finished Oct 12 06:42:48 AM UTC 24
Peak memory 415792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752150280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2752150280 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.555942767
Short name T215
Test name
Test status
Simulation time 2906518337 ps
CPU time 7.55 seconds
Started Oct 12 06:38:28 AM UTC 24
Finished Oct 12 06:38:37 AM UTC 24
Peak memory 230840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555942767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.555942767 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.2444342808
Short name T47
Test name
Test status
Simulation time 106446131 ps
CPU time 2.12 seconds
Started Oct 12 06:38:48 AM UTC 24
Finished Oct 12 06:38:51 AM UTC 24
Peak memory 230968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444342808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2444342808 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.2440266050
Short name T622
Test name
Test status
Simulation time 300635947611 ps
CPU time 2139.34 seconds
Started Oct 12 06:37:51 AM UTC 24
Finished Oct 12 07:13:54 AM UTC 24
Peak memory 2693024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440266050 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2440266050 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.536793849
Short name T88
Test name
Test status
Simulation time 3619528664 ps
CPU time 52.1 seconds
Started Oct 12 06:38:25 AM UTC 24
Finished Oct 12 06:39:19 AM UTC 24
Peak memory 243956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536793849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.536793849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.440207704
Short name T248
Test name
Test status
Simulation time 4857280341 ps
CPU time 321.24 seconds
Started Oct 12 06:37:52 AM UTC 24
Finished Oct 12 06:43:17 AM UTC 24
Peak memory 362400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440207704 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.440207704 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.2380257046
Short name T214
Test name
Test status
Simulation time 726543829 ps
CPU time 36.07 seconds
Started Oct 12 06:37:48 AM UTC 24
Finished Oct 12 06:38:26 AM UTC 24
Peak memory 230956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380257046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2380257046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.1623978542
Short name T517
Test name
Test status
Simulation time 233554725880 ps
CPU time 1597.75 seconds
Started Oct 12 06:38:51 AM UTC 24
Finished Oct 12 07:05:47 AM UTC 24
Peak memory 770416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623978542 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1623978542 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.1056504049
Short name T135
Test name
Test status
Simulation time 2518883637 ps
CPU time 113.01 seconds
Started Oct 12 06:38:52 AM UTC 24
Finished Oct 12 06:40:47 AM UTC 24
Peak memory 278636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1056504049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_
with_rand_reset.1056504049 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.421464083
Short name T226
Test name
Test status
Simulation time 53088622 ps
CPU time 1.27 seconds
Started Oct 12 06:40:54 AM UTC 24
Finished Oct 12 06:40:57 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421464083 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.421464083 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.3716598675
Short name T225
Test name
Test status
Simulation time 1366153221 ps
CPU time 64.21 seconds
Started Oct 12 06:39:48 AM UTC 24
Finished Oct 12 06:40:54 AM UTC 24
Peak memory 253816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716598675 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3716598675 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2556230484
Short name T238
Test name
Test status
Simulation time 4129135356 ps
CPU time 150.26 seconds
Started Oct 12 06:40:04 AM UTC 24
Finished Oct 12 06:42:38 AM UTC 24
Peak memory 282492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556230484 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2556230484 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.600734662
Short name T183
Test name
Test status
Simulation time 73486907476 ps
CPU time 631.76 seconds
Started Oct 12 06:39:25 AM UTC 24
Finished Oct 12 06:50:04 AM UTC 24
Peak memory 251832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600734662 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.600734662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.268189854
Short name T227
Test name
Test status
Simulation time 1188682773 ps
CPU time 31.69 seconds
Started Oct 12 06:40:26 AM UTC 24
Finished Oct 12 06:40:59 AM UTC 24
Peak memory 235316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268189854 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.268189854 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.3597936521
Short name T228
Test name
Test status
Simulation time 7926447704 ps
CPU time 30.89 seconds
Started Oct 12 06:40:30 AM UTC 24
Finished Oct 12 06:41:02 AM UTC 24
Peak memory 235184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597936521 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3597936521 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.212087087
Short name T232
Test name
Test status
Simulation time 12440841143 ps
CPU time 68.05 seconds
Started Oct 12 06:40:32 AM UTC 24
Finished Oct 12 06:41:42 AM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212087087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.212087087 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.424575092
Short name T224
Test name
Test status
Simulation time 17270410405 ps
CPU time 211.43 seconds
Started Oct 12 06:40:06 AM UTC 24
Finished Oct 12 06:43:41 AM UTC 24
Peak memory 305028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424575092 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.424575092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.3643949197
Short name T255
Test name
Test status
Simulation time 2254068687 ps
CPU time 189.26 seconds
Started Oct 12 06:40:22 AM UTC 24
Finished Oct 12 06:43:34 AM UTC 24
Peak memory 317372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643949197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3643949197 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.3441703076
Short name T223
Test name
Test status
Simulation time 436724664 ps
CPU time 5.26 seconds
Started Oct 12 06:40:23 AM UTC 24
Finished Oct 12 06:40:29 AM UTC 24
Peak memory 230756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441703076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3441703076 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.3338649946
Short name T48
Test name
Test status
Simulation time 35201643 ps
CPU time 1.61 seconds
Started Oct 12 06:40:32 AM UTC 24
Finished Oct 12 06:40:35 AM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338649946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3338649946 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.1991434775
Short name T342
Test name
Test status
Simulation time 25771829010 ps
CPU time 774.94 seconds
Started Oct 12 06:39:06 AM UTC 24
Finished Oct 12 06:52:11 AM UTC 24
Peak memory 1175420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991434775 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.1991434775 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.3238708033
Short name T90
Test name
Test status
Simulation time 1295940427 ps
CPU time 16.03 seconds
Started Oct 12 06:40:07 AM UTC 24
Finished Oct 12 06:40:24 AM UTC 24
Peak memory 235692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238708033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3238708033 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.4017329408
Short name T285
Test name
Test status
Simulation time 98305979982 ps
CPU time 396.65 seconds
Started Oct 12 06:39:09 AM UTC 24
Finished Oct 12 06:45:51 AM UTC 24
Peak memory 567232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017329408 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.4017329408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.629786956
Short name T221
Test name
Test status
Simulation time 11014960769 ps
CPU time 60.77 seconds
Started Oct 12 06:39:02 AM UTC 24
Finished Oct 12 06:40:05 AM UTC 24
Peak memory 231228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629786956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.629786956 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.1082366876
Short name T170
Test name
Test status
Simulation time 34530963578 ps
CPU time 1362.86 seconds
Started Oct 12 06:40:36 AM UTC 24
Finished Oct 12 07:03:35 AM UTC 24
Peak memory 614848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082366876 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1082366876 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.286538392
Short name T136
Test name
Test status
Simulation time 27855761385 ps
CPU time 108.65 seconds
Started Oct 12 06:40:48 AM UTC 24
Finished Oct 12 06:42:39 AM UTC 24
Peak memory 313344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=286538392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_w
ith_rand_reset.286538392 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.2051885568
Short name T239
Test name
Test status
Simulation time 47328354 ps
CPU time 1.18 seconds
Started Oct 12 06:42:37 AM UTC 24
Finished Oct 12 06:42:39 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051885568 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2051885568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.2615581429
Short name T286
Test name
Test status
Simulation time 40237553833 ps
CPU time 274.32 seconds
Started Oct 12 06:41:17 AM UTC 24
Finished Oct 12 06:45:55 AM UTC 24
Peak memory 456568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615581429 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2615581429 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.4270074186
Short name T272
Test name
Test status
Simulation time 18737099250 ps
CPU time 209.31 seconds
Started Oct 12 06:41:17 AM UTC 24
Finished Oct 12 06:44:50 AM UTC 24
Peak memory 411604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270074186 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.4270074186 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.3697942912
Short name T371
Test name
Test status
Simulation time 326852133266 ps
CPU time 770.97 seconds
Started Oct 12 06:41:16 AM UTC 24
Finished Oct 12 06:54:16 AM UTC 24
Peak memory 268280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697942912 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3697942912 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.293354487
Short name T236
Test name
Test status
Simulation time 130753612 ps
CPU time 12.77 seconds
Started Oct 12 06:42:08 AM UTC 24
Finished Oct 12 06:42:22 AM UTC 24
Peak memory 230952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293354487 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.293354487 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.447833325
Short name T241
Test name
Test status
Simulation time 2617828877 ps
CPU time 32.52 seconds
Started Oct 12 06:42:10 AM UTC 24
Finished Oct 12 06:42:44 AM UTC 24
Peak memory 235300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447833325 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.447833325 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.1390344364
Short name T252
Test name
Test status
Simulation time 10901811777 ps
CPU time 73.4 seconds
Started Oct 12 06:42:15 AM UTC 24
Finished Oct 12 06:43:30 AM UTC 24
Peak memory 231044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390344364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1390344364 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.4216711352
Short name T266
Test name
Test status
Simulation time 11014979112 ps
CPU time 176.12 seconds
Started Oct 12 06:41:33 AM UTC 24
Finished Oct 12 06:44:32 AM UTC 24
Peak memory 309312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216711352 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.4216711352 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.408440870
Short name T157
Test name
Test status
Simulation time 8529316725 ps
CPU time 88.57 seconds
Started Oct 12 06:41:42 AM UTC 24
Finished Oct 12 06:43:13 AM UTC 24
Peak memory 300984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408440870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.408440870 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.3322437629
Short name T233
Test name
Test status
Simulation time 6570049019 ps
CPU time 11.57 seconds
Started Oct 12 06:41:54 AM UTC 24
Finished Oct 12 06:42:07 AM UTC 24
Peak memory 230844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322437629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3322437629 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.3807699706
Short name T429
Test name
Test status
Simulation time 10421689817 ps
CPU time 1057.24 seconds
Started Oct 12 06:41:00 AM UTC 24
Finished Oct 12 06:58:49 AM UTC 24
Peak memory 862068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807699706 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.3807699706 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.2337305330
Short name T244
Test name
Test status
Simulation time 5512410738 ps
CPU time 81.66 seconds
Started Oct 12 06:41:38 AM UTC 24
Finished Oct 12 06:43:02 AM UTC 24
Peak memory 268608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337305330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2337305330 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.289644978
Short name T38
Test name
Test status
Simulation time 2369084974 ps
CPU time 32.79 seconds
Started Oct 12 06:41:03 AM UTC 24
Finished Oct 12 06:41:37 AM UTC 24
Peak memory 257980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289644978 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.289644978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload_invalid.2885074995
Short name T126
Test name
Test status
Simulation time 51217565 ps
CPU time 3.48 seconds
Started Oct 12 06:41:12 AM UTC 24
Finished Oct 12 06:41:16 AM UTC 24
Peak memory 231424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885074995 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload_invalid.2885074995 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.3398037069
Short name T230
Test name
Test status
Simulation time 913876401 ps
CPU time 16.53 seconds
Started Oct 12 06:40:58 AM UTC 24
Finished Oct 12 06:41:15 AM UTC 24
Peak memory 233028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398037069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3398037069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.1869796008
Short name T430
Test name
Test status
Simulation time 30886836978 ps
CPU time 986.26 seconds
Started Oct 12 06:42:22 AM UTC 24
Finished Oct 12 06:58:59 AM UTC 24
Peak memory 612784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869796008 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1869796008 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.2940956596
Short name T254
Test name
Test status
Simulation time 12762045 ps
CPU time 1.23 seconds
Started Oct 12 06:43:31 AM UTC 24
Finished Oct 12 06:43:33 AM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940956596 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2940956596 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.2900689978
Short name T261
Test name
Test status
Simulation time 2378766716 ps
CPU time 73.52 seconds
Started Oct 12 06:42:49 AM UTC 24
Finished Oct 12 06:44:04 AM UTC 24
Peak memory 262048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900689978 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2900689978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.25539403
Short name T245
Test name
Test status
Simulation time 1019836155 ps
CPU time 20.78 seconds
Started Oct 12 06:42:49 AM UTC 24
Finished Oct 12 06:43:11 AM UTC 24
Peak memory 247480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25539403 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.25539403 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.688073500
Short name T374
Test name
Test status
Simulation time 21056642102 ps
CPU time 701 seconds
Started Oct 12 06:42:45 AM UTC 24
Finished Oct 12 06:54:34 AM UTC 24
Peak memory 257976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688073500 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.688073500 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.1197243128
Short name T253
Test name
Test status
Simulation time 825923143 ps
CPU time 16.02 seconds
Started Oct 12 06:43:15 AM UTC 24
Finished Oct 12 06:43:33 AM UTC 24
Peak memory 228672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197243128 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1197243128 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.1700958392
Short name T258
Test name
Test status
Simulation time 1487338706 ps
CPU time 37.71 seconds
Started Oct 12 06:43:17 AM UTC 24
Finished Oct 12 06:43:57 AM UTC 24
Peak memory 232896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700958392 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1700958392 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.573903304
Short name T251
Test name
Test status
Simulation time 458824153 ps
CPU time 8.99 seconds
Started Oct 12 06:43:19 AM UTC 24
Finished Oct 12 06:43:29 AM UTC 24
Peak memory 230964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573903304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.573903304 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.1940334299
Short name T249
Test name
Test status
Simulation time 4944186250 ps
CPU time 24.96 seconds
Started Oct 12 06:42:57 AM UTC 24
Finished Oct 12 06:43:23 AM UTC 24
Peak memory 251780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940334299 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1940334299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.4108026386
Short name T30
Test name
Test status
Simulation time 2803186114 ps
CPU time 208.77 seconds
Started Oct 12 06:43:11 AM UTC 24
Finished Oct 12 06:46:43 AM UTC 24
Peak memory 335872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108026386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.4108026386 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.3803030808
Short name T247
Test name
Test status
Simulation time 1030657492 ps
CPU time 2.41 seconds
Started Oct 12 06:43:13 AM UTC 24
Finished Oct 12 06:43:17 AM UTC 24
Peak memory 230692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803030808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3803030808 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.4126740642
Short name T250
Test name
Test status
Simulation time 52557831 ps
CPU time 1.89 seconds
Started Oct 12 06:43:24 AM UTC 24
Finished Oct 12 06:43:27 AM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126740642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.4126740642 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.983169327
Short name T606
Test name
Test status
Simulation time 62836940230 ps
CPU time 1769.94 seconds
Started Oct 12 06:42:40 AM UTC 24
Finished Oct 12 07:12:31 AM UTC 24
Peak memory 1316764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983169327 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.983169327 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.1623690045
Short name T293
Test name
Test status
Simulation time 25262741727 ps
CPU time 205.27 seconds
Started Oct 12 06:43:03 AM UTC 24
Finished Oct 12 06:46:32 AM UTC 24
Peak memory 379252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623690045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1623690045 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.1789441559
Short name T303
Test name
Test status
Simulation time 6252964698 ps
CPU time 288.55 seconds
Started Oct 12 06:42:40 AM UTC 24
Finished Oct 12 06:47:33 AM UTC 24
Peak memory 331752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789441559 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1789441559 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.3319521894
Short name T242
Test name
Test status
Simulation time 311502643 ps
CPU time 8.78 seconds
Started Oct 12 06:42:38 AM UTC 24
Finished Oct 12 06:42:48 AM UTC 24
Peak memory 231004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319521894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3319521894 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.1156843572
Short name T624
Test name
Test status
Simulation time 72114297397 ps
CPU time 1817.6 seconds
Started Oct 12 06:43:28 AM UTC 24
Finished Oct 12 07:14:06 AM UTC 24
Peak memory 1415428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156843572 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1156843572 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest
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