Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45235194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

52123176

1

T1

438

T2

421

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52645403	1			T1	307		T2	303		T3	1
values[0x0]	21650677	1			T1	136		T2	124		T3	5
values[0x1]	23062290	1			T1	150		T2	158		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35165602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

62192768

1

T1

469

T2

457

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	313939	1			T2	4		T5	5		T12	17
valid_sources[0x01]	292246	1			T2	1		T4	3		T5	9
valid_sources[0x02]	298961	1			T2	2		T5	5		T12	4
valid_sources[0x03]	353249	1			T2	2		T5	11		T12	11
valid_sources[0x04]	296234	1			T5	6		T12	10		T13	2
valid_sources[0x05]	301722	1			T2	3		T5	14		T12	9
valid_sources[0x06]	494908	1			T2	4		T5	12		T12	16
valid_sources[0x07]	297103	1			T2	4		T5	16		T12	9
valid_sources[0x08]	296066	1			T2	1		T5	6		T12	8
valid_sources[0x09]	320662	1			T2	3		T5	8		T12	13
valid_sources[0x0a]	326589	1			T2	2		T5	4		T12	11
valid_sources[0x0b]	421765	1			T2	1		T5	9		T12	8
valid_sources[0x0c]	295374	1			T2	3		T5	15		T12	5
valid_sources[0x0d]	294594	1			T2	2		T5	4		T12	6
valid_sources[0x0e]	328313	1			T2	2		T5	6		T12	10
valid_sources[0x0f]	328190	1			T4	2		T5	16		T12	7
valid_sources[0x10]	292216	1			T2	1		T5	5		T12	3
valid_sources[0x11]	530920	1			T2	1		T5	2		T12	10
valid_sources[0x12]	297670	1			T5	12		T12	7		T14	11
valid_sources[0x13]	307286	1			T2	4		T5	6		T12	9
valid_sources[0x14]	315275	1			T2	4		T5	5		T12	10
valid_sources[0x15]	298307	1			T2	4		T4	2		T5	5
valid_sources[0x16]	296578	1			T2	2		T5	7		T12	15
valid_sources[0x17]	297466	1			T2	4		T5	11		T12	16
valid_sources[0x18]	292876	1			T2	2		T5	5		T12	17
valid_sources[0x19]	293190	1			T2	5		T4	2		T5	12
valid_sources[0x1a]	402341	1			T2	4		T5	7		T12	18
valid_sources[0x1b]	295545	1			T2	1		T5	8		T12	16
valid_sources[0x1c]	461918	1			T2	1		T5	5		T12	6
valid_sources[0x1d]	297128	1			T2	2		T5	14		T12	9
valid_sources[0x1e]	294778	1			T2	2		T4	4		T5	8
valid_sources[0x1f]	368590	1			T2	4		T5	5		T12	14
valid_sources[0x20]	294228	1			T2	2		T4	1		T5	6
valid_sources[0x21]	351661	1			T2	2		T4	2		T5	6
valid_sources[0x22]	293792	1			T2	2		T3	1		T4	1
valid_sources[0x23]	292953	1			T2	2		T5	8		T12	5
valid_sources[0x24]	295735	1			T2	2		T3	1		T4	1
valid_sources[0x25]	296535	1			T5	8		T12	17		T13	3
valid_sources[0x26]	293286	1			T2	4		T5	6		T12	8
valid_sources[0x27]	328153	1			T4	3		T5	6		T12	11
valid_sources[0x28]	409746	1			T2	5		T4	1		T5	8
valid_sources[0x29]	291874	1			T2	1		T5	11		T12	4
valid_sources[0x2a]	295959	1			T2	1		T4	21		T5	5
valid_sources[0x2b]	296700	1			T2	1		T5	10		T12	4
valid_sources[0x2c]	293986	1			T2	3		T5	17		T12	14
valid_sources[0x2d]	293022	1			T2	2		T5	2		T12	8
valid_sources[0x2e]	297289	1			T2	5		T5	16		T12	18
valid_sources[0x2f]	1418420	1			T2	2		T5	5		T12	7
valid_sources[0x30]	292490	1			T2	3		T4	1		T5	5
valid_sources[0x31]	292569	1			T2	1		T5	7		T12	18
valid_sources[0x32]	298023	1			T2	3		T4	6		T5	14
valid_sources[0x33]	293424	1			T2	1		T4	4		T5	13
valid_sources[0x34]	295766	1			T2	1		T5	7		T12	9
valid_sources[0x35]	397437	1			T2	3		T4	12		T5	4
valid_sources[0x36]	295984	1			T2	1		T4	3		T5	6
valid_sources[0x37]	296352	1			T2	1		T5	10		T12	11
valid_sources[0x38]	296636	1			T5	4		T12	7		T14	4
valid_sources[0x39]	303028	1			T4	8		T5	13		T12	11
valid_sources[0x3a]	921596	1			T2	1		T5	6		T12	6
valid_sources[0x3b]	293486	1			T4	2		T5	5		T12	10
valid_sources[0x3c]	313575	1			T2	1		T5	13		T12	10
valid_sources[0x3d]	297054	1			T2	3		T5	7		T12	16
valid_sources[0x3e]	295948	1			T2	2		T5	12		T12	4
valid_sources[0x3f]	293558	1			T2	3		T5	7		T12	9
valid_sources[0x40]	310739	1			T3	1		T5	11		T12	9
valid_sources[0x41]	293631	1			T2	1		T5	8		T12	15
valid_sources[0x42]	298249	1			T2	3		T3	1		T5	3
valid_sources[0x43]	292119	1			T2	1		T5	9		T12	14
valid_sources[0x44]	294272	1			T2	2		T5	11		T12	7
valid_sources[0x45]	291869	1			T2	2		T5	1		T12	11
valid_sources[0x46]	296372	1			T2	5		T5	1		T12	12
valid_sources[0x47]	338288	1			T2	4		T5	8		T12	11
valid_sources[0x48]	476221	1			T2	2		T5	9		T12	8
valid_sources[0x49]	488838	1			T2	2		T4	1		T5	15
valid_sources[0x4a]	294324	1			T2	1		T5	6		T12	9
valid_sources[0x4b]	332851	1			T5	7		T12	13		T15	39
valid_sources[0x4c]	1176911	1			T2	1		T5	10		T12	10
valid_sources[0x4d]	427733	1			T2	4		T3	1		T5	12
valid_sources[0x4e]	293626	1			T2	3		T5	8		T12	11
valid_sources[0x4f]	296014	1			T2	4		T5	8		T12	18
valid_sources[0x50]	294979	1			T2	3		T4	2		T5	11
valid_sources[0x51]	354836	1			T2	2		T5	8		T12	11
valid_sources[0x52]	308416	1			T5	6		T12	17		T15	66
valid_sources[0x53]	323511	1			T2	5		T5	10		T12	12
valid_sources[0x54]	293831	1			T2	2		T4	4		T5	9
valid_sources[0x55]	423726	1			T2	3		T5	10		T12	7
valid_sources[0x56]	423181	1			T2	5		T5	9		T12	3
valid_sources[0x57]	1167356	1			T2	3		T4	1		T5	2
valid_sources[0x58]	683109	1			T2	1		T5	6		T12	17
valid_sources[0x59]	294158	1			T2	1		T5	8		T12	8
valid_sources[0x5a]	294770	1			T2	2		T5	9		T12	8
valid_sources[0x5b]	360756	1			T2	1		T5	1		T12	4
valid_sources[0x5c]	1522017	1			T2	3		T4	2		T5	16
valid_sources[0x5d]	290872	1			T4	2		T5	5		T12	8
valid_sources[0x5e]	293825	1			T2	4		T5	7		T12	8
valid_sources[0x5f]	295323	1			T2	1		T5	7		T12	12
valid_sources[0x60]	294740	1			T2	1		T5	15		T12	15
valid_sources[0x61]	432596	1			T2	1		T5	16		T12	8
valid_sources[0x62]	293155	1			T2	2		T5	11		T12	10
valid_sources[0x63]	418973	1			T2	5		T5	14		T12	11
valid_sources[0x64]	1233308	1			T2	3		T5	8		T12	14
valid_sources[0x65]	1074243	1			T2	3		T4	5		T5	10
valid_sources[0x66]	490871	1			T2	2		T4	2		T5	19
valid_sources[0x67]	291908	1			T2	4		T5	6		T12	14
valid_sources[0x68]	293890	1			T2	1		T5	7		T12	7
valid_sources[0x69]	293297	1			T2	4		T5	10		T12	7
valid_sources[0x6a]	295633	1			T2	3		T5	13		T12	15
valid_sources[0x6b]	1054955	1			T2	4		T5	4		T12	10
valid_sources[0x6c]	293448	1			T2	3		T5	5		T12	9
valid_sources[0x6d]	293735	1			T2	2		T5	9		T12	10
valid_sources[0x6e]	494161	1			T2	3		T5	15		T12	14
valid_sources[0x6f]	339334	1			T2	3		T5	11		T12	13
valid_sources[0x70]	303711	1			T2	4		T5	9		T12	7
valid_sources[0x71]	474145	1			T5	7		T12	17		T13	4
valid_sources[0x72]	295934	1			T2	2		T5	5		T12	7
valid_sources[0x73]	293098	1			T2	3		T5	4		T12	9
valid_sources[0x74]	293073	1			T2	4		T5	6		T12	8
valid_sources[0x75]	309662	1			T2	2		T4	1		T5	7
valid_sources[0x76]	291772	1			T2	5		T5	12		T12	13
valid_sources[0x77]	298801	1			T2	3		T5	2		T12	8
valid_sources[0x78]	299068	1			T2	5		T5	3		T12	8
valid_sources[0x79]	304251	1			T2	2		T5	9		T12	12
valid_sources[0x7a]	294103	1			T2	5		T4	1		T5	11
valid_sources[0x7b]	322805	1			T2	2		T5	13		T12	11
valid_sources[0x7c]	295696	1			T2	2		T5	2		T12	8
valid_sources[0x7d]	300846	1			T2	3		T4	8		T5	11
valid_sources[0x7e]	294930	1			T4	1		T5	11		T12	8
valid_sources[0x7f]	301227	1			T4	1		T5	9		T12	12
valid_sources[0x80]	293584	1			T2	3		T5	8		T12	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24897763

1

T1

216

T2

203

T3

1

values[0x0]

all_enables

biggest_size

14345411

1

T1

109

T2

94

T3

2

values[0x1]

all_enables

biggest_size

12880002

1

T1

113

T2

124

T3

1