Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257657726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203418333

1

T1

1396

T2

1408

T3

578

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	243529048	1			T1	1099		T2	1139		T3	126
values[0x0]	104575181	1			T1	475		T2	507		T3	319
values[0x1]	112971830	1			T1	535		T2	540		T3	264

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200915718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

260160341

1

T1

1552

T2

1589

T3

614

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6183921	1			T1	7		T3	5		T12	41
valid_sources[0x01]	1363325	1			T1	7		T3	3		T12	48
valid_sources[0x02]	1328571	1			T1	8		T3	7		T12	43
valid_sources[0x03]	4232132	1			T1	3		T3	4		T12	65
valid_sources[0x04]	1340261	1			T1	10		T12	59		T13	246
valid_sources[0x05]	2672423	1			T1	13		T3	2		T12	59
valid_sources[0x06]	1335680	1			T1	7		T3	4		T12	33
valid_sources[0x07]	1997595	1			T1	5		T3	4		T12	29
valid_sources[0x08]	1326694	1			T1	6		T3	1		T12	57
valid_sources[0x09]	1337644	1			T1	10		T3	3		T12	52
valid_sources[0x0a]	1332124	1			T1	13		T3	4		T12	57
valid_sources[0x0b]	1330235	1			T1	12		T3	1		T12	49
valid_sources[0x0c]	3755192	1			T1	9		T3	1		T12	36
valid_sources[0x0d]	1337974	1			T1	8		T3	4		T12	39
valid_sources[0x0e]	1334936	1			T1	6		T3	4		T12	47
valid_sources[0x0f]	1321910	1			T1	4		T12	56		T13	55
valid_sources[0x10]	1331385	1			T1	13		T3	5		T12	42
valid_sources[0x11]	1336838	1			T1	9		T12	41		T13	35
valid_sources[0x12]	1417066	1			T1	6		T12	38		T13	53
valid_sources[0x13]	1333776	1			T1	9		T3	3		T12	30
valid_sources[0x14]	1332678	1			T1	6		T3	1		T12	41
valid_sources[0x15]	3402949	1			T1	7		T3	4		T12	57
valid_sources[0x16]	3480135	1			T1	18		T3	2		T12	60
valid_sources[0x17]	1333645	1			T1	6		T3	1		T12	47
valid_sources[0x18]	1455211	1			T1	5		T3	5		T12	35
valid_sources[0x19]	1787527	1			T1	3		T3	3		T12	48
valid_sources[0x1a]	1333085	1			T1	6		T3	3		T12	31
valid_sources[0x1b]	2266221	1			T1	5		T3	2		T12	91
valid_sources[0x1c]	1333919	1			T1	10		T3	2		T12	46
valid_sources[0x1d]	1800288	1			T1	15		T3	4		T12	31
valid_sources[0x1e]	1335895	1			T1	9		T3	4		T12	58
valid_sources[0x1f]	2198373	1			T1	8		T3	5		T12	48
valid_sources[0x20]	2357130	1			T1	8		T3	3		T12	38
valid_sources[0x21]	1475016	1			T1	12		T3	1		T12	57
valid_sources[0x22]	1337731	1			T1	11		T3	3		T12	57
valid_sources[0x23]	1998048	1			T1	9		T3	1		T12	55
valid_sources[0x24]	1328620	1			T1	12		T3	3		T12	42
valid_sources[0x25]	1463132	1			T1	6		T3	4		T12	44
valid_sources[0x26]	2189260	1			T1	10		T3	3		T12	33
valid_sources[0x27]	1379891	1			T1	8		T3	2		T12	54
valid_sources[0x28]	1366583	1			T1	11		T3	3		T12	54
valid_sources[0x29]	1423442	1			T1	8		T3	3		T12	54
valid_sources[0x2a]	1511966	1			T1	9		T12	47		T13	19
valid_sources[0x2b]	1340185	1			T1	11		T3	2		T12	28
valid_sources[0x2c]	1333355	1			T1	3		T3	2		T12	36
valid_sources[0x2d]	1338439	1			T1	7		T3	2		T12	51
valid_sources[0x2e]	1977568	1			T1	6		T3	7		T12	48
valid_sources[0x2f]	1331362	1			T1	9		T3	5		T12	57
valid_sources[0x30]	3131313	1			T1	9		T3	3		T12	37
valid_sources[0x31]	1501760	1			T1	9		T12	69		T13	19
valid_sources[0x32]	2189360	1			T1	5		T3	2		T12	48
valid_sources[0x33]	1335171	1			T1	4		T3	2		T12	34
valid_sources[0x34]	1393937	1			T1	8		T3	1		T12	52
valid_sources[0x35]	1488595	1			T1	10		T12	37		T13	103
valid_sources[0x36]	1334367	1			T1	10		T3	3		T12	40
valid_sources[0x37]	1332062	1			T1	6		T3	1		T12	48
valid_sources[0x38]	1334860	1			T1	10		T3	3		T12	39
valid_sources[0x39]	3849758	1			T1	13		T3	2		T12	42
valid_sources[0x3a]	2248271	1			T1	8		T3	1		T12	37
valid_sources[0x3b]	1486652	1			T1	8		T3	2		T12	49
valid_sources[0x3c]	1329777	1			T1	12		T3	2		T12	41
valid_sources[0x3d]	1332559	1			T1	4		T3	2		T12	44
valid_sources[0x3e]	1338849	1			T1	17		T3	1		T12	54
valid_sources[0x3f]	1587169	1			T1	10		T3	6		T12	55
valid_sources[0x40]	1337400	1			T1	7		T3	2		T12	30
valid_sources[0x41]	1338411	1			T1	5		T3	4		T12	36
valid_sources[0x42]	1437910	1			T1	4		T12	76		T4	7
valid_sources[0x43]	1336132	1			T1	11		T3	4		T12	54
valid_sources[0x44]	4655986	1			T1	5		T3	2		T12	44
valid_sources[0x45]	1334940	1			T1	6		T3	4		T12	64
valid_sources[0x46]	1441228	1			T1	4		T12	46		T13	2
valid_sources[0x47]	1351083	1			T1	5		T3	2		T12	39
valid_sources[0x48]	1338454	1			T1	7		T12	39		T13	128
valid_sources[0x49]	1393488	1			T1	10		T3	3		T12	38
valid_sources[0x4a]	3616298	1			T1	13		T3	2		T12	45
valid_sources[0x4b]	1423368	1			T1	9		T3	4		T12	57
valid_sources[0x4c]	1333400	1			T1	9		T3	4		T12	44
valid_sources[0x4d]	1978664	1			T1	7		T3	1		T12	34
valid_sources[0x4e]	1362543	1			T1	1		T3	3		T12	43
valid_sources[0x4f]	3373097	1			T1	6		T3	5		T12	31
valid_sources[0x50]	1335273	1			T1	4		T3	4		T12	43
valid_sources[0x51]	1376538	1			T1	4		T3	2		T12	25
valid_sources[0x52]	1338437	1			T1	8		T3	3		T12	49
valid_sources[0x53]	1328097	1			T1	5		T3	2		T12	51
valid_sources[0x54]	1362043	1			T1	7		T3	3		T12	56
valid_sources[0x55]	1407938	1			T1	5		T3	3		T12	42
valid_sources[0x56]	1851774	1			T1	8		T3	4		T12	68
valid_sources[0x57]	1338229	1			T1	3		T3	2		T12	31
valid_sources[0x58]	1332378	1			T1	8		T3	5		T12	43
valid_sources[0x59]	1327720	1			T1	7		T3	4		T12	49
valid_sources[0x5a]	1334464	1			T1	3		T3	3		T12	68
valid_sources[0x5b]	1330369	1			T1	8		T3	5		T12	67
valid_sources[0x5c]	1336643	1			T1	14		T3	8		T12	32
valid_sources[0x5d]	3763024	1			T1	13		T3	3		T12	36
valid_sources[0x5e]	1776862	1			T1	7		T3	4		T12	36
valid_sources[0x5f]	1334173	1			T1	16		T3	2		T12	34
valid_sources[0x60]	1335068	1			T1	6		T3	4		T12	58
valid_sources[0x61]	2057744	1			T1	2		T3	1		T12	41
valid_sources[0x62]	1342928	1			T1	8		T3	1		T12	28
valid_sources[0x63]	1332864	1			T1	6		T3	3		T12	59
valid_sources[0x64]	1419276	1			T1	9		T3	1		T12	33
valid_sources[0x65]	1336482	1			T1	9		T3	1		T12	45
valid_sources[0x66]	3367536	1			T1	4		T3	2		T12	46
valid_sources[0x67]	1983715	1			T1	18		T3	5		T12	31
valid_sources[0x68]	1332200	1			T1	9		T3	6		T12	72
valid_sources[0x69]	1335886	1			T1	6		T3	4		T12	54
valid_sources[0x6a]	1345132	1			T1	11		T3	2		T12	29
valid_sources[0x6b]	1340177	1			T1	13		T3	2		T12	61
valid_sources[0x6c]	1325698	1			T1	11		T3	2		T12	37
valid_sources[0x6d]	1983257	1			T1	10		T3	2		T12	65
valid_sources[0x6e]	1330945	1			T1	6		T12	28		T4	27
valid_sources[0x6f]	1511064	1			T1	9		T3	1		T12	34
valid_sources[0x70]	1337644	1			T1	4		T3	4		T12	46
valid_sources[0x71]	2053224	1			T1	6		T3	4		T12	46
valid_sources[0x72]	1789613	1			T1	5		T3	5		T12	56
valid_sources[0x73]	1345259	1			T1	13		T3	3		T12	39
valid_sources[0x74]	2222466	1			T1	13		T3	3		T12	45
valid_sources[0x75]	1333437	1			T1	10		T3	4		T12	64
valid_sources[0x76]	1333809	1			T1	11		T3	2		T12	37
valid_sources[0x77]	3395882	1			T1	13		T3	2		T12	52
valid_sources[0x78]	1331615	1			T1	3		T3	5		T12	51
valid_sources[0x79]	2055132	1			T1	8		T3	3		T12	44
valid_sources[0x7a]	1332211	1			T1	5		T12	45		T13	44
valid_sources[0x7b]	1338815	1			T1	9		T3	3		T12	39
valid_sources[0x7c]	1332115	1			T1	18		T3	4		T12	39
valid_sources[0x7d]	2208207	1			T1	11		T3	2		T12	37
valid_sources[0x7e]	1345870	1			T1	9		T3	3		T12	45
valid_sources[0x7f]	1333498	1			T1	13		T3	4		T12	45
valid_sources[0x80]	2237140	1			T1	12		T3	1		T12	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88982086

1

T1

682

T2

714

T3

23

values[0x0]

all_enables

biggest_size

61569415

1

T1

356

T2

363

T3

302

values[0x1]

all_enables

biggest_size

52866832

1

T1

358

T2

331

T3

253