Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257675071

1

T1

713

T2

778

T3

131

full_word

203419416

1

T1

1396

T2

1408

T3

578

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	461094197	1			T1	2109		T2	2186		T3	709
auto[TlIntgErrCmd]	86	1			T56	3		T108	7		T109	5
auto[TlIntgErrData]	101	1			T56	5		T108	6		T109	9
auto[TlIntgErrBoth]	103	1			T56	2		T108	7		T109	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243532737

1

T1

1099

T2

1139

T3

126

auto[1]

217561750

1

T1

1010

T2

1047

T3

583

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154550225	1			T1	417		T2	425		T3	103
auto[TlIntgErrNone]	partial	auto[1]	103124579	1			T1	296		T2	353		T3	28
auto[TlIntgErrNone]	full_word	auto[0]	88982391	1			T1	682		T2	714		T3	23
auto[TlIntgErrNone]	full_word	auto[1]	114437002	1			T1	714		T2	694		T3	555
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T56	1		T108	3		T109	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T56	2		T108	3		T109	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T109	1		T161	1		T165	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T108	1		T164	1		T166	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T56	1		T108	5		T109	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T56	4		T108	1		T109	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T109	1		T167	1		T166	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T109	1		T128	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T108	5		T109	1		T128	2
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T56	2		T108	2		T109	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T168	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T162	1		T164	2		-	-