Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45257819

1

T1

155

T2

164

T3

6

full_word

52124569

1

T1

438

T2

421

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	97382068	1			T1	593		T2	585		T3	10
auto[TlIntgErrCmd]	91	1			T121	4		T122	2		T123	8
auto[TlIntgErrData]	109	1			T121	9		T122	4		T123	5
auto[TlIntgErrBoth]	120	1			T121	7		T122	4		T123	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52651026

1

T1

307

T2

303

T3

1

auto[1]

44731362

1

T1

286

T2

282

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27752696	1			T1	91		T2	100		T4	4
auto[TlIntgErrNone]	partial	auto[1]	17504824	1			T1	64		T2	64		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	24898186	1			T1	216		T2	203		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	27226362	1			T1	222		T2	218		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T121	1		T123	4		T156	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T121	3		T122	2		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T176	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T123	1		T175	1		T177	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T121	6		T122	2		T123	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T121	3		T122	2		T123	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T156	1		T172	1		T178	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T156	1		T172	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T121	3		T122	2		T123	4
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T121	4		T122	1		T123	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T123	1		T172	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T122	1		T156	1		T132	1