Unified Coverage Report :: Module :: kmac_msgfifo

Module : kmac_msgfifo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00			100.00	91.67	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_msgfifo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo	97.92	100.00			100.00	91.67	100.00

---

Module Instance : tb.dut.u_msgfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00			100.00	91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	95.00		100.00	93.75	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_msgfifo	98.30	100.00	93.18			100.00	100.00
u_packer	97.50	100.00	100.00			90.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_msgfifo

	Line No.	Total	Covered	Percent
TOTAL		34	34	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	140	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	185	3	3	100.00
ALWAYS	193	16	16	100.00
CONT_ASSIGN	238	1	1	100.00
ALWAYS	242	3	3	100.00

137                       // converted into 3-D form so the endianess here is not a problem.
138        1/1            assign fifo_wdata.data = packer_wdata;
           Tests:       T1 T2 T3 
139                       always_comb begin
140        1/1              fifo_wdata.strb = '0;
           Tests:       T1 T2 T3 
141        1/1              for (int i = 0 ; i < OutWidth/8 ; i++) begin
           Tests:       T1 T2 T3 
142        1/1                fifo_wdata.strb[i] = packer_wmask[8*i];
           Tests:       T1 T2 T3 
143                         end
144                       end
145                     
146                       // MsgFIFO
147                       prim_fifo_sync #(
148                         .Width  ($bits(fifo_t)),
149                         .Pass   (1'b 1),
150                         .Depth  (MsgDepth),
151                         .Secure (EnMasking)
152                       ) u_msgfifo (
153                         .clk_i,
154                         .rst_ni,
155                         .clr_i   (prim_mubi_pkg::mubi4_test_true_strict(clear_i)),
156                     
157                         .wvalid_i(fifo_wvalid),
158                         .wready_o(fifo_wready),
159                         .wdata_i (fifo_wdata),
160                     
161                         .rvalid_o (fifo_rvalid),
162                         .rready_i (fifo_rready),
163                         .rdata_o  (fifo_rdata),
164                     
165                         .full_o  (fifo_full_o),
166                         .depth_o (fifo_depth_o),
167                         .err_o   (fifo_err)
168                     
169                       );
170                     
171        1/1            assign fifo_wvalid = packer_wvalid;
           Tests:       T1 T2 T3 
172        1/1            assign packer_wready = fifo_wready;
           Tests:       T1 T2 T3 
173                     
174        1/1            assign msg_valid_o = fifo_rvalid;
           Tests:       T1 T2 T3 
175        1/1            assign fifo_rready = msg_ready_i;
           Tests:       T1 T2 T3 
176        1/1            assign msg_data_o  = fifo_rdata.data;
           Tests:       T1 T2 T3 
177        1/1            assign msg_strb_o  = fifo_rdata.strb;
           Tests:       T1 T2 T3 
178                     
179        1/1            assign fifo_empty_o = !fifo_rvalid;
           Tests:       T1 T2 T3 
180                     
181                       // Flush (process from outside) handling
182                       flush_st_e flush_st, flush_st_d;
183                     
184                       always_ff @(posedge clk_i or negedge rst_ni) begin
185        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
186        1/1                flush_st <= FlushIdle;
           Tests:       T1 T2 T3 
187                         end else begin
188        1/1                flush_st <= flush_st_d;
           Tests:       T1 T2 T3 
189                         end
190                       end
191                     
192                       always_comb begin
193        1/1              flush_st_d = flush_st;
           Tests:       T1 T2 T3 
194                     
195        1/1              msgfifo_flush_done = 1'b 0;
           Tests:       T1 T2 T3 
196                     
197        1/1              unique case (flush_st)
           Tests:       T1 T2 T3 
198                           FlushIdle: begin
199        1/1                  if (process_i) begin
           Tests:       T1 T2 T3 
200        1/1                    flush_st_d = FlushPacker;
           Tests:       T1 T2 T4 
201                             end else begin
202        1/1                    flush_st_d = FlushIdle;
           Tests:       T1 T2 T3 
203                             end
204                           end
205                     
206                           FlushPacker: begin
207        1/1                  if (packer_flush_done) begin
           Tests:       T1 T2 T4 
208        1/1                    flush_st_d = FlushFifo;
           Tests:       T1 T2 T4 
209                             end else begin
210        1/1                    flush_st_d = FlushPacker;
           Tests:       T1 T2 T4 
211                             end
212                           end
213                     
214                           FlushFifo: begin
215        1/1                  if (fifo_empty_o) begin
           Tests:       T1 T2 T4 
216        1/1                    flush_st_d = FlushClear;
           Tests:       T1 T2 T5 
217                     
218        1/1                    msgfifo_flush_done = 1'b 1;
           Tests:       T1 T2 T5 
219                             end else begin
220        1/1                    flush_st_d = FlushFifo;
           Tests:       T4 T5 T12 
221                             end
222                           end
223                     
224                           FlushClear: begin
225        1/1                  if (prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin
           Tests:       T1 T2 T5 
226        1/1                    flush_st_d = FlushIdle;
           Tests:       T1 T2 T5 
227                             end else begin
228        1/1                    flush_st_d = FlushClear;
           Tests:       T1 T2 T5 
229                             end
230                           end
231                     
232                           default: begin
233                             flush_st_d = FlushIdle;
234                           end
235                         endcase
236                       end
237                     
238        1/1            assign process_o = msgfifo_flush_done;
           Tests:       T1 T2 T3 
239                     
240                       // Error assign
241                       always_comb begin : error_logic
242        1/1              err_o = '{
           Tests:       T1 T2 T3 
243                           valid: 1'b 0,
244                           code: kmac_pkg::ErrNone,
245                           info: '0
246                         };
247                     
248                         // Priority case -> if .. else if
249        1/1              if (packer_err) begin
           Tests:       T1 T2 T3 
250        unreachable        err_o = '{
251                             // If EnProtection is 0, packer_err is tied to 0
252                             valid: 1'b 1,
253                             code:  kmac_pkg::ErrPackerIntegrity,
254                             info:  kmac_pkg::ErrInfoW'(flush_st)
255                           };
256        1/1              end else if (fifo_err) begin
           Tests:       T1 T2 T3 
257        unreachable        err_o = '{
258                             valid: 1'b 1,
259                             code:  kmac_pkg::ErrMsgFifoIntegrity,
260                             info:  kmac_pkg::ErrInfoW'(flush_st)
261                           };
262                         end
                        MISSING_ELSE

---

FSM Coverage for Module : kmac_msgfifo

Summary for FSM :: flush_st

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: flush_st

---

states	Line No.	Covered	Tests
FlushClear	216	Covered	T1,T2,T5
FlushFifo	208	Covered	T1,T2,T4
FlushIdle	202	Covered	T1,T2,T3
FlushPacker	200	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
FlushClear->FlushIdle	226	Covered	T1,T2,T5
FlushFifo->FlushClear	216	Covered	T1,T2,T5
FlushIdle->FlushPacker	200	Covered	T1,T2,T4
FlushPacker->FlushFifo	208	Covered	T1,T2,T4

---

Branch Coverage for Module : kmac_msgfifo

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
IF	185	2	2	100.00
CASE	197	9	8	88.89
IF	249	1	1	100.00

185            if (!rst_ni) begin
               -1-  
186              flush_st <= FlushIdle;
                 ==>
187            end else begin
188              flush_st <= flush_st_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

197            unique case (flush_st)
                      -1-  
198              FlushIdle: begin
199                if (process_i) begin
                   -2-  
200                  flush_st_d = FlushPacker;
                     ==>
201                end else begin
202                  flush_st_d = FlushIdle;
                     ==>
203                end
204              end
205        
206              FlushPacker: begin
207                if (packer_flush_done) begin
                   -3-  
208                  flush_st_d = FlushFifo;
                     ==>
209                end else begin
210                  flush_st_d = FlushPacker;
                     ==>
211                end
212              end
213        
214              FlushFifo: begin
215                if (fifo_empty_o) begin
                   -4-     
216                  flush_st_d = FlushClear;
                     ==>
217        
218                  msgfifo_flush_done = 1'b 1;
219                end else begin
220                  flush_st_d = FlushFifo;
                     ==>
221                end
222              end
223        
224              FlushClear: begin
225                if (prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin
                   -5-  
226                  flush_st_d = FlushIdle;
                     ==>
227                end else begin
228                  flush_st_d = FlushClear;
                     ==>
229                end
230              end
231        
232              default: begin
233                flush_st_d = FlushIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
FlushIdle	1	-	-	-	Covered	T1,T2,T4
FlushIdle	0	-	-	-	Covered	T1,T2,T3
FlushPacker	-	1	-	-	Covered	T1,T2,T4
FlushPacker	-	0	-	-	Covered	T1,T2,T4
FlushFifo	-	-	1	-	Covered	T1,T2,T5
FlushFifo	-	-	0	-	Covered	T4,T5,T12
FlushClear	-	-	-	1	Covered	T1,T2,T5
FlushClear	-	-	-	0	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

249            if (packer_err) begin
               -1-  
250              err_o = '{
                 ==> (Unreachable)
251                // If EnProtection is 0, packer_err is tied to 0
252                valid: 1'b 1,
253                code:  kmac_pkg::ErrPackerIntegrity,
254                info:  kmac_pkg::ErrInfoW'(flush_st)
255              };
256            end else if (fifo_err) begin
                        -2-     
257              err_o = '{
                 ==> (Unreachable)
258                valid: 1'b 1,
259                code:  kmac_pkg::ErrMsgFifoIntegrity,
260                info:  kmac_pkg::ErrInfoW'(flush_st)
261              };
262            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Unreachable
0	1	Unreachable
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_msgfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FlushStInValid_A	614716435	614566771	0	0
MessageValid_a	614716435	25676940	0	0
PackerDoneDelay_A	614716435	614566771	0	0
PackerDoneValid_a	614716435	54358	0	0

FlushStInValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614716435	614566771	0	0
T1	7436	7347	0	0
T2	5376	5298	0	0
T3	1047	994	0	0
T4	5269	5126	0	0
T5	7591	7504	0	0
T12	6627	6557	0	0
T13	12546	12448	0	0
T14	124983	124920	0	0
T15	103804	103705	0	0
T16	3333	3283	0	0

MessageValid_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	614716435	25676940	0	0
T1	7436	57	0	0
T2	5376	55	0	0
T3	1047	0	0	0
T4	5269	182	0	0
T5	7591	33	0	0
T12	6627	381	0	0
T13	12546	11	0	0
T14	124983	0	0	0
T15	103804	774	0	0
T16	3333	125	0	0
T17	0	1072	0	0
T18	0	55	0	0

PackerDoneDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614716435	614566771	0	0
T1	7436	7347	0	0
T2	5376	5298	0	0
T3	1047	994	0	0
T4	5269	5126	0	0
T5	7591	7504	0	0
T12	6627	6557	0	0
T13	12546	12448	0	0
T14	124983	124920	0	0
T15	103804	103705	0	0
T16	3333	3283	0	0

PackerDoneValid_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	614716435	54358	0	0
T1	7436	3	0	0
T2	5376	3	0	0
T3	1047	0	0	0
T4	5269	1	0	0
T5	7591	15	0	0
T12	6627	2	0	0
T13	12546	12	0	0
T14	124983	13	0	0
T15	103804	73	0	0
T16	3333	3	0	0
T17	0	9	0	0