Line Coverage for Module :
kmac_app
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 222 | 212 | 95.50 |
| ALWAYS | 219 | 6 | 5 | 83.33 |
| ALWAYS | 233 | 0 | 0 | |
| ALWAYS | 233 | 4 | 4 | 100.00 |
| ALWAYS | 258 | 6 | 6 | 100.00 |
| ALWAYS | 277 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
| ALWAYS | 305 | 3 | 3 | 100.00 |
| ALWAYS | 314 | 3 | 3 | 100.00 |
| ALWAYS | 317 | 1 | 0 | 0.00 |
| ALWAYS | 322 | 95 | 88 | 92.63 |
| CONT_ASSIGN | 582 | 1 | 1 | 100.00 |
| ALWAYS | 588 | 3 | 3 | 100.00 |
| ALWAYS | 611 | 18 | 18 | 100.00 |
| ALWAYS | 655 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 686 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 697 | 1 | 1 | 100.00 |
| ALWAYS | 719 | 13 | 13 | 100.00 |
| ALWAYS | 744 | 6 | 6 | 100.00 |
| ALWAYS | 772 | 3 | 3 | 100.00 |
| ALWAYS | 782 | 20 | 20 | 100.00 |
| ALWAYS | 833 | 8 | 7 | 87.50 |
| ALWAYS | 862 | 16 | 16 | 100.00 |
| ALWAYS | 889 | 3 | 3 | 100.00 |
218 always_ff @(posedge clk_i or negedge rst_ni) begin
219 2/2 if (!rst_ni) service_rejected_error <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
220 1/2 ==> else if (service_rejected_error_set) service_rejected_error <= 1'b 1;
Tests: T1 T2 T3
221 2/2 else if (service_rejected_error_clr) service_rejected_error <= 1'b 0;
Tests: T1 T2 T3 | T5 T13 T14
MISSING_ELSE
222 end
223
224 ////////////////////////////
225 // Application Mux/ Demux //
226 ////////////////////////////
227
228
229 // Processing return data.
230 // sends to only selected app intf.
231 // clear digest right after done to not leak info to other interface
232 always_comb begin
233 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
Tests: T1 T2 T3
234 1/1 if (i == app_id) begin
Tests: T1 T2 T3
235 1/1 app_o[i] = '{
Tests: T1 T2 T3
236 ready: app_data_ready | fsm_data_ready,
237 done: app_digest_done | fsm_digest_done_q,
238 digest_share0: app_digest[0],
239 digest_share1: app_digest[1],
240 // if fsm asserts done, should be an error case.
241 error: error_i | fsm_digest_done_q | sparse_fsm_error_o
242 | service_rejected_error
243 };
244 end else begin
245 1/1 app_o[i] = '{
Tests: T1 T2 T3
246 ready: 1'b 0,
247 done: 1'b 0,
248 digest_share0: '0,
249 digest_share1: '0,
250 error: 1'b 0
251 };
252 end
253 end // for {i, NumAppIntf, i++}
254 end // aiways_comb
255
256 // app_id latch
257 always_ff @(posedge clk_i or negedge rst_ni) begin
258 2/2 if (!rst_ni) app_id <= AppIdxW'(0) ; // Do not select any
Tests: T1 T2 T3 | T1 T2 T3
259 2/2 else if (clr_appid) app_id <= AppIdxW'(0);
Tests: T1 T2 T3 | T5 T13 T14
260 2/2 else if (set_appid) app_id <= app_id_d;
Tests: T1 T2 T3 | T4 T5 T13
MISSING_ELSE
261 end
262
263 // app_id selection as of now, app_id uses Priority. The assumption is that
264 // the request normally does not collide. (ROM_CTRL activates very early
265 // stage at the boot sequence)
266 //
267 // If this assumption is not true, consider RR arbiter.
268
269 // Prep for arbiter
270 logic [NumAppIntf-1:0] app_reqs;
271 logic [NumAppIntf-1:0] unused_app_gnts;
272 logic [$clog2(NumAppIntf)-1:0] arb_idx;
273 logic arb_valid;
274 logic arb_ready;
275
276 always_comb begin
277 1/1 app_reqs = '0;
Tests: T4 T5 T13
278 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
Tests: T4 T5 T13
279 1/1 app_reqs[i] = app_i[i].valid;
Tests: T4 T5 T13
280 end
281 end
282
283 prim_arbiter_fixed #(
284 .N (NumAppIntf),
285 .DW(1),
286 .EnDataPort(1'b 0)
287 ) u_appid_arb (
288 .clk_i,
289 .rst_ni,
290
291 .req_i (app_reqs),
292 .data_i ('{default:'0}),
293 .gnt_o (unused_app_gnts),
294 .idx_o (arb_idx),
295
296 .valid_o (arb_valid),
297 .data_o (), // not used
298 .ready_i (arb_ready)
299 );
300
301 1/1 assign app_id_d = AppIdxW'(arb_idx);
Tests: T19 T20 T21
302 1/1 assign arb_ready = set_appid;
Tests: T4 T5 T13
303
304 always_ff @(posedge clk_i or negedge rst_ni) begin
305 2/2 if (!rst_ni) fsm_digest_done_q <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
306 1/1 else fsm_digest_done_q <= fsm_digest_done_d;
Tests: T1 T2 T3
307 end
308
309 /////////
310 // FSM //
311 /////////
312
313 // State register
314 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle):
314.1 `ifdef SIMULATION
314.2 prim_sparse_fsm_flop #(
314.3 .StateEnumT(st_e),
314.4 .Width($bits(st_e)),
314.5 .ResetValue($bits(st_e)'(StIdle)),
314.6 .EnableAlertTriggerSVA(1),
314.7 .CustomForceName("st")
314.8 ) u_state_regs (
314.9 .clk_i ( clk_i ),
314.10 .rst_ni ( rst_ni ),
314.11 .state_i ( st_d ),
314.12 .state_o ( )
314.13 );
314.14 always_ff @(posedge clk_i or negedge rst_ni) begin
314.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
314.16 1/1 st <= StIdle;
Tests: T1 T2 T3
314.17 end else begin
314.18 1/1 st <= st_d;
Tests: T1 T2 T3
314.19 end
314.20 end
314.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (st === u_state_regs.state_o))
314.22 else begin
314.23 `ifdef UVM
314.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
314.25 "../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv", 314, "", 1);
314.26 `else
314.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
314.28 `PRIM_STRINGIFY(u_state_regs_A));
314.29 `endif
314.30 end
314.31 `else
314.32 prim_sparse_fsm_flop #(
314.33 .StateEnumT(st_e),
314.34 .Width($bits(st_e)),
314.35 .ResetValue($bits(st_e)'(StIdle)),
314.36 .EnableAlertTriggerSVA(1)
314.37 ) u_state_regs (
314.38 .clk_i ( `PRIM_FLOP_CLK ),
314.39 .rst_ni ( `PRIM_FLOP_RST ),
314.40 .state_i ( st_d ),
314.41 .state_o ( st )
314.42 );
314.43 `endif315
316 // Create a lint error to reduce the risk of accidentally enabling this feature.
317 0/1 ==> `ASSERT_STATIC_LINT_ERROR(KmacSecIdleAcceptSwMsgNonDefault, SecIdleAcceptSwMsg == 0)
ASSERT_STATIC_LINT_ERROR(KmacSecIdleAcceptSwMsgNonDefault, SecIdleAcceptSwMsg == 0):
317.1 localparam int KmacSecIdleAcceptSwMsgNonDefault = (SecIdleAcceptSwMsg == 0) ? 1 : 2;
317.2 always_comb begin
317.3 logic unused_assert_static_lint_error;
317.4 0/1 ==> unused_assert_static_lint_error = KmacSecIdleAcceptSwMsgNonDefault'(1'b1);
317.5 end318
319 // Next State & output logic
320 // SEC_CM: FSM.SPARSE
321 always_comb begin
322 1/1 st_d = st;
Tests: T1 T2 T3
323
324 1/1 mux_sel = SecIdleAcceptSwMsg ? SelSw : SelNone;
Tests: T1 T2 T3
325
326 // app_id control
327 1/1 set_appid = 1'b 0;
Tests: T1 T2 T3
328 1/1 clr_appid = 1'b 0;
Tests: T1 T2 T3
329
330 // Commands
331 1/1 cmd_o = CmdNone;
Tests: T1 T2 T3
332
333 // Software output
334 1/1 absorbed_o = prim_mubi_pkg::MuBi4False;
Tests: T1 T2 T3
335
336 // Error
337 1/1 fsm_err = '{valid: 1'b 0, code: ErrNone, info: '0};
Tests: T1 T2 T3
338 1/1 sparse_fsm_error_o = 1'b 0;
Tests: T1 T2 T3
339
340 1/1 clear_after_error_o = prim_mubi_pkg::MuBi4False;
Tests: T1 T2 T3
341
342 1/1 service_rejected_error_set = 1'b 0;
Tests: T1 T2 T3
343 1/1 service_rejected_error_clr = 1'b 0;
Tests: T1 T2 T3
344
345 // If error happens, FSM asserts data ready but discard incoming msg
346 1/1 fsm_data_ready = 1'b 0;
Tests: T1 T2 T3
347 1/1 fsm_digest_done_d = 1'b 0;
Tests: T1 T2 T3
348
349 1/1 unique case (st)
Tests: T1 T2 T3
350 StIdle: begin
351 1/1 if (arb_valid) begin
Tests: T1 T2 T3
352 1/1 st_d = StAppCfg;
Tests: T4 T5 T13
353
354 // choose app_id
355 1/1 set_appid = 1'b 1;
Tests: T4 T5 T13
356 1/1 end else if (sw_cmd_i == CmdStart) begin
Tests: T1 T2 T3
357 1/1 st_d = StSw;
Tests: T1 T2 T5
358 // Software initiates the sequence
359 1/1 cmd_o = CmdStart;
Tests: T1 T2 T5
360 end else begin
361 1/1 st_d = StIdle;
Tests: T1 T2 T3
362 end
363 end
364
365 StAppCfg: begin
366 1/1 if (AppCfg[app_id].Mode == AppKMAC &&
Tests: T4 T5 T13
367 prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)) begin
368 // Check if the entropy is not configured but it is needed in
369 // `AppCfg[app_id]` (KMAC mode).
370 //
371 // SW is not properly configured, report and not request Hashing
372 // Return the app with errors
373 0/1 ==> st_d = StError;
374
375 0/1 ==> service_rejected_error_set = 1'b 1;
376
377 end else begin
378 // As Cfg is stable now, it sends cmd
379 1/1 st_d = StAppMsg;
Tests: T4 T5 T13
380
381 // App initiates the data
382 1/1 cmd_o = CmdStart;
Tests: T4 T5 T13
383 end
384 end
385
386 StAppMsg: begin
387 1/1 mux_sel = SelApp;
Tests: T4 T5 T13
388 1/1 if (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last) begin
Tests: T4 T5 T13
389 1/1 if (AppCfg[app_id].Mode == AppKMAC) begin
Tests: T4 T5 T13
390 1/1 st_d = StAppOutLen;
Tests: T4 T5 T13
391 end else begin
392 1/1 st_d = StAppProcess;
Tests: T19 T20 T21
393 end
394 end else begin
395 1/1 st_d = StAppMsg;
Tests: T4 T5 T13
396 end
397 end
398
399 StAppOutLen: begin
400 1/1 mux_sel = SelOutLen;
Tests: T4 T5 T13
401
402 1/1 if (kmac_valid_o && kmac_ready_i) begin
Tests: T4 T5 T13
403 1/1 st_d = StAppProcess;
Tests: T4 T5 T13
404 end else begin
405 1/1 st_d = StAppOutLen;
Tests: T22 T23 T24
406 end
407 end
408
409 StAppProcess: begin
410 1/1 cmd_o = CmdProcess;
Tests: T4 T5 T13
411 1/1 st_d = StAppWait;
Tests: T4 T5 T13
412 end
413
414 StAppWait: begin
415 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
Tests: T4 T5 T13
416 // Send digest to KeyMgr and complete the op
417 1/1 st_d = StIdle;
Tests: T5 T13 T19
418 1/1 cmd_o = CmdDone;
Tests: T5 T13 T19
419
420 1/1 clr_appid = 1'b 1;
Tests: T5 T13 T19
421 end else begin
422 1/1 st_d = StAppWait;
Tests: T4 T5 T13
423 end
424 end
425
426 StSw: begin
427 1/1 mux_sel = SelSw;
Tests: T1 T2 T5
428
429 1/1 cmd_o = sw_cmd_i;
Tests: T1 T2 T5
430 1/1 absorbed_o = absorbed_i;
Tests: T1 T2 T5
431
432 1/1 if (sw_cmd_i == CmdDone) begin
Tests: T1 T2 T5
433 1/1 st_d = StIdle;
Tests: T1 T2 T12
434 end else begin
435 1/1 st_d = StSw;
Tests: T1 T2 T5
436 end
437 end
438
439 StKeyMgrErrKeyNotValid: begin
440 1/1 st_d = StError;
Tests: T5 T13 T14
441
442 // As mux_sel is not set to SelApp, app_data_ready is still 0.
443 // This logic won't accept the requests from the selected App.
444 1/1 fsm_err.valid = 1'b 1;
Tests: T5 T13 T14
445 1/1 fsm_err.code = ErrKeyNotValid;
Tests: T5 T13 T14
446 1/1 fsm_err.info = 24'(app_id);
Tests: T5 T13 T14
447 end
448
449 StError: begin
450 // In this state, the state machine flush out the request
451 1/1 st_d = StError;
Tests: T5 T13 T14
452
453 // Absorb data on the app interface.
454 1/1 fsm_data_ready = ~err_during_sw_q;
Tests: T5 T13 T14
455
456 // Next step depends on two conditions:
457 // 1) Error being processed by SW
458 // 2) Last data provided from the app interface (so that the app interface is completely)
459 // drained. If the error occurred during a SW operation, the app interface is not
460 // involved, so this condition gets skipped.
461 1/1 unique case ({err_processed_i,
Tests: T5 T13 T14
462 (app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q})
463 2'b00: begin
464 // Error not processed by SW and not last data from app interface -> keep current state.
465 1/1 st_d = StError;
Tests: T5 T13 T14
466 end
467 2'b01: begin
468 // Error not processed by SW but last data from app interface:
469 // 1. Send garbage digest to the app interface (in the next cycle) to complete the
470 // transaction.
471 1/1 fsm_digest_done_d = ~err_during_sw_q;
Tests: T5 T13 T14
472 1/1 if (service_rejected_error) begin
Tests: T5 T13 T14
473 // 2.a) Service was rejected because an app interface tried to configure KMAC while no
474 // entropy was available. It is assumed that SW is not loaded yet, so don't wait for
475 // SW to process the error. The last data from the app interface has now arrived, but
476 // we don't need to wait for the SHA3 core to have absorbed it because the data never
477 // entered the SHA3 core: the request from the app interface was terminated during the
478 // configuration phase.
479 0/1 ==> st_d = StErrorServiceRejected;
480 end else begin
481 // 2.b) If service was not rejected, wait for SW to process the error.
482 1/1 st_d = StErrorAwaitSw;
Tests: T5 T13 T14
483 end
484 end
485 2'b10: begin
486 // Error processed by SW but not last data from app interface -> wait for app interface.
487 1/1 st_d = StErrorAwaitApp;
Tests: T5 T25 T26
488 end
489 2'b11: begin
490 // Error processed by SW and last data from app interface:
491 // Send garbage digest to the app interface (in the next cycle) to complete the
492 // transaction.
493 1/1 fsm_digest_done_d = ~err_during_sw_q;
Tests: T27 T28 T29
494 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
495 // but serves to bring the SHA3 engine back to the idle state).
496 1/1 cmd_o = CmdProcess;
Tests: T27 T28 T29
497 1/1 st_d = StErrorWaitAbsorbed;
Tests: T27 T28 T29
498 end
499 default: st_d = StError;
500 endcase
501 end
502
503 StErrorAwaitSw: begin
504 // Just wait for SW to process the error.
505 1/1 if (err_processed_i) begin
Tests: T5 T13 T14
506 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
507 // but serves to bring the SHA3 engine back to the idle state).
508 1/1 cmd_o = CmdProcess;
Tests: T5 T13 T14
509 1/1 st_d = StErrorWaitAbsorbed;
Tests: T5 T13 T14
510 end
MISSING_ELSE
511 end
512
513 StErrorAwaitApp: begin
514 // Keep absorbing data on the app interface until the last data.
515 1/1 fsm_data_ready = 1'b1;
Tests: T5 T25 T26
516 1/1 if (app_i[app_id].valid && app_i[app_id].last) begin
Tests: T5 T25 T26
517 // Send garbage digest to the app interface (in the next cycle) to complete the
518 // transaction.
519 1/1 fsm_digest_done_d = 1'b1;
Tests: T5 T25 T26
520 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
521 // but serves to bring the SHA3 engine back to the idle state).
522 1/1 cmd_o = CmdProcess;
Tests: T5 T25 T26
523 1/1 st_d = StErrorWaitAbsorbed;
Tests: T5 T25 T26
524 end
MISSING_ELSE
525 end
526
527 StErrorWaitAbsorbed: begin
528 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
Tests: T5 T13 T14
529 // Clear internal variables, send done command, and return to idle.
530 1/1 clr_appid = 1'b1;
Tests: T5 T13 T14
531 1/1 clear_after_error_o = prim_mubi_pkg::MuBi4True;
Tests: T5 T13 T14
532 1/1 service_rejected_error_clr = 1'b1;
Tests: T5 T13 T14
533 1/1 cmd_o = CmdDone;
Tests: T5 T13 T14
534 1/1 st_d = StIdle;
Tests: T5 T13 T14
535 // If error originated from SW, report 'absorbed' to SW.
536 1/1 if (err_during_sw_q) begin
Tests: T5 T13 T14
537 1/1 absorbed_o = prim_mubi_pkg::MuBi4True;
Tests: T5 T13 T30
538 end
MISSING_ELSE
539 end
MISSING_ELSE
540 end
541
542 StErrorServiceRejected: begin
543 // Clear internal variables and return to idle.
544 0/1 ==> clr_appid = 1'b1;
545 0/1 ==> clear_after_error_o = prim_mubi_pkg::MuBi4True;
546 0/1 ==> service_rejected_error_clr = 1'b1;
547 0/1 ==> st_d = StIdle;
548 end
549
550 StTerminalError: begin
551 // this state is terminal
552 1/1 st_d = st;
Tests: T4 T6 T7
553 1/1 sparse_fsm_error_o = 1'b 1;
Tests: T4 T6 T7
554 1/1 fsm_err.valid = 1'b 1;
Tests: T4 T6 T7
555 1/1 fsm_err.code = ErrFatalError;
Tests: T4 T6 T7
556 1/1 fsm_err.info = 24'(app_id);
Tests: T4 T6 T7
557 end
558
559 default: begin
560 st_d = StTerminalError;
561 sparse_fsm_error_o = 1'b 1;
562 end
563 endcase
564
565 // SEC_CM: FSM.GLOBAL_ESC, FSM.LOCAL_ESC
566 // Unconditionally jump into the terminal error state
567 // if the life cycle controller triggers an escalation.
568 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
Tests: T1 T2 T3
569 1/1 st_d = StTerminalError;
Tests: T4 T6 T7
570 end
MISSING_ELSE
571
572 // Handle errors outside the terminal error state.
573 1/1 if (st_d != StTerminalError) begin
Tests: T1 T2 T3
574 // Key from keymgr is used but not valid, so abort into the invalid key error state.
575 1/1 if (keymgr_key_used && !keymgr_key_i.valid) begin
Tests: T1 T2 T3
576 1/1 st_d = StKeyMgrErrKeyNotValid;
Tests: T5 T13 T14
577 end
MISSING_ELSE
578 end
MISSING_ELSE
579 end
580
581 // Track errors occurring in SW mode.
582 1/1 assign err_during_sw_d =
Tests: T1 T2 T3
583 (mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}) ? 1'b1 : // set
584 (st_d == StIdle) ? 1'b0 : // clear
585 err_during_sw_q; // hold
586
587 always_ff @(posedge clk_i or negedge rst_ni) begin
588 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
589 1/1 err_during_sw_q <= 1'b0;
Tests: T1 T2 T3
590 end else begin
591 1/1 err_during_sw_q <= err_during_sw_d;
Tests: T1 T2 T3
592 end
593 end
594
595 //////////////
596 // Datapath //
597 //////////////
598
599 // Encoded output length
600 assign encoded_outlen = EncodedOutLen[SelDigSize];
601 assign encoded_outlen_mask = EncodedOutLenMask[SelKeySize];
602
603 // Data mux
604 // This is the main part of the KeyMgr interface logic.
605 // The FSM selects KeyMgr interface in a cycle after it receives the first
606 // valid data from KeyMgr. The ready signal to the KeyMgr data interface
607 // represents the MSG_FIFO ready, only when it is in StKeyMgrMsg state.
608 // After KeyMgr sends last beat, the kmac interface (to MSG_FIFO) is switched
609 // to OutLen. OutLen is pre-defined values. See `EncodeOutLen` parameter above.
610 always_comb begin
611 1/1 app_data_ready = 1'b 0;
Tests: T1 T2 T3
612 1/1 sw_ready_o = 1'b 1;
Tests: T1 T2 T3
613
614 1/1 kmac_valid_o = 1'b 0;
Tests: T1 T2 T3
615 1/1 kmac_data_o = '0;
Tests: T1 T2 T3
616 1/1 kmac_mask_o = '0;
Tests: T1 T2 T3
617
618 1/1 unique case (mux_sel_buf_kmac)
Tests: T1 T2 T3
619 SelApp: begin
620 // app_id is valid at this time
621 1/1 kmac_valid_o = app_i[app_id].valid;
Tests: T4 T5 T13
622 1/1 kmac_data_o = app_i[app_id].data;
Tests: T4 T5 T13
623 // Expand strb to bits. prim_packer inside MSG_FIFO accepts the bit masks
624 1/1 for (int i = 0 ; i < $bits(app_i[app_id].strb) ; i++) begin
Tests: T4 T5 T13
625 1/1 kmac_mask_o[8*i+:8] = {8{app_i[app_id].strb[i]}};
Tests: T4 T5 T13
626 end
627 1/1 app_data_ready = kmac_ready_i;
Tests: T4 T5 T13
628 end
629
630 SelOutLen: begin
631 // Write encoded output length value
632 1/1 kmac_valid_o = 1'b 1; // always write
Tests: T4 T5 T13
633 1/1 kmac_data_o = MsgWidth'(encoded_outlen);
Tests: T4 T5 T13
634 1/1 kmac_mask_o = MsgWidth'(encoded_outlen_mask);
Tests: T4 T5 T13
635 end
636
637 SelSw: begin
638 1/1 kmac_valid_o = sw_valid_i;
Tests: T1 T2 T5
639 1/1 kmac_data_o = sw_data_i ;
Tests: T1 T2 T5
640 1/1 kmac_mask_o = sw_mask_i ;
Tests: T1 T2 T5
641 1/1 sw_ready_o = kmac_ready_i ;
Tests: T1 T2 T5
642 end
643
644 default: begin // Incl. SelNone
645 kmac_valid_o = 1'b 0;
646 kmac_data_o = '0;
647 kmac_mask_o = '0;
648 end
649
650 endcase
651 end
652
653 // Error checking for Mux
654 always_comb begin
655 1/1 mux_err = '{valid: 1'b 0, code: ErrNone, info: '0};
Tests: T1 T2 T3
656
657 1/1 if (mux_sel_buf_err_check != SelSw && sw_valid_i) begin
Tests: T1 T2 T3
658 // If SW writes message into FIFO
659 1/1 mux_err = '{
Tests: T4 T5 T13
660 valid: 1'b 1,
661 code: ErrSwPushedMsgFifo,
662 info: 24'({8'h 00, 8'(st), 8'(mux_sel_buf_err_check)})
663 };
664 1/1 end else if (app_active_o && sw_cmd_i != CmdNone) begin
Tests: T1 T2 T3
665 // If SW issues command except start
666 1/1 mux_err = '{
Tests: T19 T31 T32
667 valid: 1'b 1,
668 code: ErrSwIssuedCmdInAppActive,
669 info: 24'(sw_cmd_i)
670 };
671 end
MISSING_ELSE
672 end
673
674 logic [AppMuxWidth-1:0] mux_sel_buf_output_logic;
675 1/1 assign mux_sel_buf_output = app_mux_sel_e'(mux_sel_buf_output_logic);
Tests: T1 T2 T3
676
677 // SEC_CM: LOGIC.INTEGRITY
678 prim_sec_anchor_buf #(
679 .Width(AppMuxWidth)
680 ) u_prim_buf_state_output_sel (
681 .in_i(mux_sel),
682 .out_o(mux_sel_buf_output_logic)
683 );
684
685 logic [AppMuxWidth-1:0] mux_sel_buf_err_check_logic;
686 1/1 assign mux_sel_buf_err_check = app_mux_sel_e'(mux_sel_buf_err_check_logic);
Tests: T1 T2 T3
687
688 // SEC_CM: LOGIC.INTEGRITY
689 prim_sec_anchor_buf #(
690 .Width(AppMuxWidth)
691 ) u_prim_buf_state_err_check (
692 .in_i(mux_sel),
693 .out_o(mux_sel_buf_err_check_logic)
694 );
695
696 logic [AppMuxWidth-1:0] mux_sel_buf_kmac_logic;
697 1/1 assign mux_sel_buf_kmac = app_mux_sel_e'(mux_sel_buf_kmac_logic);
Tests: T1 T2 T3
698
699 // SEC_CM: LOGIC.INTEGRITY
700 prim_sec_anchor_buf #(
701 .Width(AppMuxWidth)
702 ) u_prim_buf_state_kmac_sel (
703 .in_i(mux_sel),
704 .out_o(mux_sel_buf_kmac_logic)
705 );
706
707 // SEC_CM: LOGIC.INTEGRITY
708 logic reg_state_valid;
709 prim_sec_anchor_buf #(
710 .Width(1)
711 ) u_prim_buf_state_output_valid (
712 .in_i(reg_state_valid),
713 .out_o(reg_state_valid_o)
714 );
715
716 // Keccak state Demux
717 // Keccak state --> Register output is enabled when state is in StSw
718 always_comb begin
719 1/1 reg_state_valid = 1'b 0;
Tests: T1 T2 T3
720 1/1 reg_state_o = '{default:'0};
Tests: T1 T2 T3
721 1/1 if ((mux_sel_buf_output == SelSw) &&
Tests: T1 T2 T3
722 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
723 1/1 reg_state_valid = keccak_state_valid_i;
Tests: T1 T2 T5
724 1/1 reg_state_o = keccak_state_i;
Tests: T1 T2 T5
725 // If key is sideloaded and KMAC is SW initiated
726 // hide the capacity from SW by zeroing (see #17508)
727 1/1 if (keymgr_key_en_i) begin
Tests: T1 T2 T5
728 1/1 for (int i = 0; i < Share; i++) begin
Tests: T5 T13 T17
729 1/1 unique case (reg_keccak_strength_i)
Tests: T5 T13 T17
730 1/1 L128: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L128]] = '0;
Tests: T5 T13 T19
731 1/1 L224: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L224]] = '0;
Tests: T19 T33 T32
732 1/1 L256: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L256]] = '0;
Tests: T5 T13 T17
733 1/1 L384: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L384]] = '0;
Tests: T34 T35 T36
734 1/1 L512: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L512]] = '0;
Tests: T37 T38 T39
735 default: reg_state_o[i] = '0;
736 endcase
737 end
738 end
MISSING_ELSE
739 end
MISSING_ELSE
740 end
741
742 // Keccak state --> KeyMgr
743 always_comb begin
744 1/1 app_digest_done = 1'b 0;
Tests: T1 T2 T3
745 1/1 app_digest = '{default:'0};
Tests: T1 T2 T3
746 1/1 if (st == StAppWait && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i) &&
Tests: T1 T2 T3
747 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
748 // SHA3 engine has calculated the hash. Return the data to KeyMgr
749 1/1 app_digest_done = 1'b 1;
Tests: T5 T13 T19
750
751 // digest has always 2 entries. If !EnMasking, second is tied to 0.
752 1/1 for (int i = 0 ; i < Share ; i++) begin
Tests: T5 T13 T19
753 // Return the portion of state.
754 1/1 app_digest[i] = keccak_state_i[i][AppDigestW-1:0];
Tests: T5 T13 T19
755 end
756 end
MISSING_ELSE
757 end
758
759
760 // Secret Key Mux
761
762 // Prepare merged key if EnMasking is not set.
763 // Combine share keys into unpacked array for logic below to assign easily.
764 // SEC_CM: KEY.SIDELOAD
765 logic [MaxKeyLen-1:0] keymgr_key [Share];
766 if (EnMasking == 1) begin : g_masked_key
767 for (genvar i = 0; i < Share; i++) begin : gen_key_pad
768 assign keymgr_key[i] = {(MaxKeyLen-KeyMgrKeyW)'(0), keymgr_key_i.key[i]};
769 end
770 end else begin : g_unmasked_key
771 always_comb begin
772 1/1 keymgr_key[0] = '0;
Tests: T4 T5 T13
773 1/1 for (int i = 0; i < keymgr_pkg::Shares; i++) begin
Tests: T4 T5 T13
774 1/1 keymgr_key[0][KeyMgrKeyW-1:0] ^= keymgr_key_i.key[i];
Tests: T4 T5 T13
775 end
776 end
777 end
778
779 // Sideloaded key manage: Keep use sideloaded key for KMAC AppIntf until the
780 // hashing operation is finished.
781 always_comb begin
782 1/1 keymgr_key_used = 1'b0;
Tests: T1 T2 T3
783 1/1 key_len_o = reg_key_len_i;
Tests: T1 T2 T3
784 1/1 for (int i = 0 ; i < Share; i++) begin
Tests: T1 T2 T3
785 1/1 key_data_o[i] = reg_key_data_i[i];
Tests: T1 T2 T3
786 end
787 // The key is considered invalid in all cases that are not listed below (which includes idle and
788 // error states).
789 1/1 key_valid_o = 1'b0;
Tests: T1 T2 T3
790
791 1/1 unique case (st)
Tests: T1 T2 T3
792 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
793 // Key from keymgr is actually used if the current HW app interface does *keyed* MAC.
794 1/1 keymgr_key_used = AppCfg[app_id].Mode == AppKMAC;
Tests: T4 T5 T13
795 1/1 key_len_o = SideloadedKey;
Tests: T4 T5 T13
796 1/1 for (int i = 0 ; i < Share; i++) begin
Tests: T4 T5 T13
797 1/1 key_data_o[i] = keymgr_key[i];
Tests: T4 T5 T13
798 end
799 // Key is valid if the current HW app interface does *keyed* MAC and the key provided by
800 // keymgr is valid.
801 1/1 key_valid_o = keymgr_key_used && keymgr_key_i.valid;
Tests: T4 T5 T13
802 end
803
804 StSw: begin
805 1/1 if (keymgr_key_en_i) begin
Tests: T1 T2 T5
806 // Key from keymgr is actually used if *keyed* MAC is enabled.
807 1/1 keymgr_key_used = kmac_en_o;
Tests: T5 T13 T17
808 1/1 key_len_o = SideloadedKey;
Tests: T5 T13 T17
809 1/1 for (int i = 0 ; i < Share; i++) begin
Tests: T5 T13 T17
810 1/1 key_data_o[i] = keymgr_key[i];
Tests: T5 T13 T17
811 end
812 end
MISSING_ELSE
813 // Key is valid if SW does *keyed* MAC and ...
814 1/1 if (kmac_en_o) begin
Tests: T1 T2 T5
815 1/1 if (!keymgr_key_en_i) begin
Tests: T1 T2 T5
816 // ... it uses the key from kmac's CSR, or ...
817 1/1 key_valid_o = 1'b1;
Tests: T1 T2 T12
818 end else begin
819 // ... it uses the key provided by keymgr and that one is valid.
820 1/1 key_valid_o = keymgr_key_i.valid;
Tests: T5 T13 T17
821 end
822 end
MISSING_ELSE
823 end
824
825 default: ;
826 endcase
827 end
828
829 // Prefix Demux
830 // For SW, always prefix register.
831 // For App intf, check PrefixMode cfg and if 1, use Prefix cfg.
832 always_comb begin
833 1/1 sha3_prefix_o = '0;
Tests: T1 T2 T3
834
835 1/1 unique case (st)
Tests: T1 T2 T3
836 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
837 // Check app intf cfg
838 1/1 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
Tests: T4 T5 T13
839 1/1 if (app_id == i) begin
Tests: T4 T5 T13
840 1/1 if (AppCfg[i].PrefixMode == 1'b 0) begin
Tests: T4 T5 T13
841 0/1 ==> sha3_prefix_o = reg_prefix_i;
842 end else begin
843 1/1 sha3_prefix_o = AppCfg[i].Prefix;
Tests: T4 T5 T13
844 end
845 end
MISSING_ELSE
846 end
847 end
848
849 StSw: begin
850 1/1 sha3_prefix_o = reg_prefix_i;
Tests: T1 T2 T5
851 end
852
853 default: begin
854 sha3_prefix_o = reg_prefix_i;
855 end
856 endcase
857 end
858
859 // KMAC en / SHA3 mode / Strength
860 // by default, it uses reg cfg. When app intf reqs come, it uses AppCfg.
861 always_ff @(posedge clk_i or negedge rst_ni) begin
862 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
863 1/1 kmac_en_o <= 1'b 0;
Tests: T1 T2 T3
864 1/1 sha3_mode_o <= sha3_pkg::Sha3;
Tests: T1 T2 T3
865 1/1 keccak_strength_o <= sha3_pkg::L256;
Tests: T1 T2 T3
866 1/1 end else if (clr_appid) begin
Tests: T1 T2 T3
867 // As App completed, latch reg value
868 1/1 kmac_en_o <= reg_kmac_en_i;
Tests: T5 T13 T14
869 1/1 sha3_mode_o <= reg_sha3_mode_i;
Tests: T5 T13 T14
870 1/1 keccak_strength_o <= reg_keccak_strength_i;
Tests: T5 T13 T14
871 1/1 end else if (set_appid) begin
Tests: T1 T2 T3
872 1/1 kmac_en_o <= AppCfg[arb_idx].Mode == AppKMAC ? 1'b 1 : 1'b 0;
Tests: T4 T5 T13
873 1/1 sha3_mode_o <= AppCfg[arb_idx].Mode == AppSHA3
Tests: T4 T5 T13
874 ? sha3_pkg::Sha3 : sha3_pkg::CShake;
875 1/1 keccak_strength_o <= AppCfg[arb_idx].Strength ;
Tests: T4 T5 T13
876 1/1 end else if (st == StIdle) begin
Tests: T1 T2 T3
877 1/1 kmac_en_o <= reg_kmac_en_i;
Tests: T1 T2 T3
878 1/1 sha3_mode_o <= reg_sha3_mode_i;
Tests: T1 T2 T3
879 1/1 keccak_strength_o <= reg_keccak_strength_i;
Tests: T1 T2 T3
880 end
MISSING_ELSE
881 end
882
883 // Status
884 assign app_active_o = (st inside {StAppCfg, StAppMsg, StAppOutLen,
885 StAppProcess, StAppWait});
886
887 // Error Reporting ==========================================================
888 always_comb begin
889 1/1 priority casez ({fsm_err.valid, mux_err.valid})
Tests: T1 T2 T3
890 1/1 2'b ?1: error_o = mux_err;
Tests: T4 T5 T13
891 1/1 2'b 10: error_o = fsm_err;
Tests: T4 T5 T13
892 default: error_o = '{valid: 1'b0, code: ErrNone, info: '0};
Cond Coverage for Module :
kmac_app
| Total | Covered | Percent |
|---|
| Conditions | 73 | 66 | 90.41 |
| Logical | 73 | 66 | 90.41 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 234
EXPRESSION (i == app_id)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 235
EXPRESSION (app_data_ready | fsm_data_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T13,T14 |
| 1 | 0 | Covered | T4,T5,T13 |
LINE 235
EXPRESSION (app_digest_done | fsm_digest_done_q)
-------1------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T13,T14 |
| 1 | 0 | Covered | T5,T13,T19 |
LINE 235
EXPRESSION (error_i | fsm_digest_done_q | sparse_fsm_error_o | service_rejected_error)
---1--- --------2-------- ---------3-------- -----------4----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Not Covered | |
| 0 | 0 | 1 | 0 | Covered | T4,T6,T7 |
| 0 | 1 | 0 | 0 | Covered | T5,T13,T14 |
| 1 | 0 | 0 | 0 | Covered | T40,T41,T42 |
LINE 356
EXPRESSION (sw_cmd_i == CmdStart)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T5 |
LINE 388
EXPRESSION (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last)
---------1--------- ---------2--------- ---------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T21,T22,T24 |
| 1 | 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | 1 | Covered | T4,T5,T13 |
LINE 389
EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T20,T21 |
| 1 | Covered | T4,T5,T13 |
LINE 402
EXPRESSION (kmac_valid_o && kmac_ready_i)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | T22,T23,T24 |
| 1 | 1 | Covered | T4,T5,T13 |
LINE 432
EXPRESSION (sw_cmd_i == CmdDone)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T5 |
| 1 | Covered | T1,T2,T12 |
LINE 516
EXPRESSION (app_i[app_id].valid && app_i[app_id].last)
---------1--------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T5,T25,T26 |
| 1 | 1 | Covered | T5,T25,T26 |
LINE 573
EXPRESSION (st_d != StTerminalError)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 575
EXPRESSION (keymgr_key_used && ((!keymgr_key_i.valid)))
-------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T5,T13,T14 |
LINE 582
EXPRESSION (((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid})) ? 1'b1 : ((st_d == StIdle) ? 1'b0 : err_during_sw_q))
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T13,T30 |
LINE 582
SUB-EXPRESSION ((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}))
---------1-------- -----------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T13,T14 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T5,T13,T30 |
LINE 582
SUB-EXPRESSION (mux_sel == SelSw)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T5 |
LINE 582
SUB-EXPRESSION ((st_d == StIdle) ? 1'b0 : err_during_sw_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 582
SUB-EXPRESSION (st_d == StIdle)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 657
EXPRESSION ((mux_sel_buf_err_check != SelSw) && sw_valid_i)
----------------1--------------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T4,T5,T13 |
LINE 657
SUB-EXPRESSION (mux_sel_buf_err_check != SelSw)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (app_active_o && (sw_cmd_i != CmdNone))
------1----- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T19,T31,T32 |
LINE 664
SUB-EXPRESSION (sw_cmd_i != CmdNone)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 794
EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T20,T21 |
| 1 | Covered | T4,T5,T13 |
LINE 801
EXPRESSION (keymgr_key_used && keymgr_key_i.valid)
-------1------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T32,T43,T44 |
| 1 | 0 | Covered | T5,T13,T14 |
| 1 | 1 | Covered | T4,T5,T13 |
LINE 839
EXPRESSION (app_id == i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T13 |
| 1 | Covered | T4,T5,T13 |
LINE 840
EXPRESSION (kmac_pkg::AppCfg[i].PrefixMode == 1'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T13 |
| 1 | Not Covered | |
LINE 872
EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC) ? 1'b1 : 1'b0)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T20,T21 |
| 1 | Covered | T4,T5,T13 |
LINE 872
SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T20,T21 |
| 1 | Covered | T4,T5,T13 |
LINE 873
EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3) ? Sha3 : CShake)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T13 |
| 1 | Not Covered | |
LINE 873
SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T13 |
| 1 | Not Covered | |
LINE 876
EXPRESSION (st == StIdle)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
kmac_app
Summary for FSM :: st
| Total | Covered | Percent | |
| States |
14 |
13 |
92.86 |
(Not included in score) |
| Transitions |
45 |
23 |
51.11 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st
| states | Line No. | Covered | Tests |
| StAppCfg |
352 |
Covered |
T4,T5,T13 |
| StAppMsg |
379 |
Covered |
T4,T5,T13 |
| StAppOutLen |
390 |
Covered |
T4,T5,T13 |
| StAppProcess |
392 |
Covered |
T4,T5,T13 |
| StAppWait |
411 |
Covered |
T4,T5,T13 |
| StError |
373 |
Covered |
T5,T13,T14 |
| StErrorAwaitApp |
487 |
Covered |
T5,T25,T26 |
| StErrorAwaitSw |
482 |
Covered |
T5,T13,T14 |
| StErrorServiceRejected |
479 |
Not Covered |
|
| StErrorWaitAbsorbed |
497 |
Covered |
T5,T13,T14 |
| StIdle |
361 |
Covered |
T1,T2,T3 |
| StKeyMgrErrKeyNotValid |
576 |
Covered |
T5,T13,T14 |
| StSw |
357 |
Covered |
T1,T2,T5 |
| StTerminalError |
569 |
Covered |
T4,T6,T7 |
| transitions | Line No. | Covered | Tests |
| StAppCfg->StAppMsg |
379 |
Covered |
T4,T5,T13 |
| StAppCfg->StError |
373 |
Not Covered |
|
| StAppCfg->StKeyMgrErrKeyNotValid |
576 |
Covered |
T13,T14,T45 |
| StAppCfg->StTerminalError |
569 |
Not Covered |
|
| StAppMsg->StAppOutLen |
390 |
Covered |
T4,T5,T13 |
| StAppMsg->StAppProcess |
392 |
Covered |
T19,T20,T21 |
| StAppMsg->StKeyMgrErrKeyNotValid |
576 |
Covered |
T5,T13,T30 |
| StAppMsg->StTerminalError |
569 |
Covered |
T46,T47,T48 |
| StAppOutLen->StAppProcess |
403 |
Covered |
T4,T5,T13 |
| StAppOutLen->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StAppOutLen->StTerminalError |
569 |
Not Covered |
|
| StAppProcess->StAppWait |
411 |
Covered |
T4,T5,T13 |
| StAppProcess->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StAppProcess->StTerminalError |
569 |
Not Covered |
|
| StAppWait->StIdle |
417 |
Covered |
T5,T13,T19 |
| StAppWait->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StAppWait->StTerminalError |
569 |
Covered |
T4 |
| StError->StErrorAwaitApp |
487 |
Covered |
T5,T25,T26 |
| StError->StErrorAwaitSw |
482 |
Covered |
T5,T13,T14 |
| StError->StErrorServiceRejected |
479 |
Not Covered |
|
| StError->StErrorWaitAbsorbed |
497 |
Covered |
T27,T28,T29 |
| StError->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StError->StTerminalError |
569 |
Not Covered |
|
| StErrorAwaitApp->StErrorWaitAbsorbed |
523 |
Covered |
T5,T25,T26 |
| StErrorAwaitApp->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StErrorAwaitApp->StTerminalError |
569 |
Not Covered |
|
| StErrorAwaitSw->StErrorWaitAbsorbed |
509 |
Covered |
T5,T13,T14 |
| StErrorAwaitSw->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StErrorAwaitSw->StTerminalError |
569 |
Not Covered |
|
| StErrorServiceRejected->StIdle |
547 |
Not Covered |
|
| StErrorServiceRejected->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StErrorServiceRejected->StTerminalError |
569 |
Not Covered |
|
| StErrorWaitAbsorbed->StIdle |
534 |
Covered |
T5,T13,T14 |
| StErrorWaitAbsorbed->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StErrorWaitAbsorbed->StTerminalError |
569 |
Not Covered |
|
| StIdle->StAppCfg |
352 |
Covered |
T4,T5,T13 |
| StIdle->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
| StIdle->StSw |
357 |
Covered |
T1,T2,T5 |
| StIdle->StTerminalError |
569 |
Covered |
T7,T10,T11 |
| StKeyMgrErrKeyNotValid->StError |
440 |
Covered |
T5,T13,T14 |
| StKeyMgrErrKeyNotValid->StTerminalError |
569 |
Not Covered |
|
| StSw->StIdle |
433 |
Covered |
T1,T2,T12 |
| StSw->StKeyMgrErrKeyNotValid |
576 |
Covered |
T5,T13,T30 |
| StSw->StTerminalError |
569 |
Covered |
T6,T49,T50 |
| StTerminalError->StKeyMgrErrKeyNotValid |
576 |
Not Covered |
|
Branch Coverage for Module :
kmac_app
| Line No. | Total | Covered | Percent |
| Branches |
|
89 |
83 |
93.26 |
| TERNARY |
582 |
3 |
3 |
100.00 |
| IF |
219 |
4 |
3 |
75.00 |
| IF |
234 |
2 |
2 |
100.00 |
| IF |
258 |
4 |
4 |
100.00 |
| IF |
305 |
2 |
2 |
100.00 |
| IF |
314 |
2 |
2 |
100.00 |
| CASE |
349 |
32 |
28 |
87.50 |
| IF |
568 |
2 |
2 |
100.00 |
| IF |
573 |
3 |
3 |
100.00 |
| IF |
588 |
2 |
2 |
100.00 |
| CASE |
618 |
4 |
4 |
100.00 |
| IF |
657 |
3 |
3 |
100.00 |
| IF |
721 |
3 |
3 |
100.00 |
| IF |
746 |
2 |
2 |
100.00 |
| CASE |
791 |
7 |
7 |
100.00 |
| CASE |
835 |
3 |
3 |
100.00 |
| IF |
862 |
8 |
7 |
87.50 |
| CASE |
889 |
3 |
3 |
100.00 |
582 assign err_during_sw_d =
583 (mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}) ? 1'b1 : // set
-1-
==>
584 (st_d == StIdle) ? 1'b0 : // clear
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T5,T13,T30 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T4 |
219 if (!rst_ni) service_rejected_error <= 1'b 0;
-1-
==>
220 else if (service_rejected_error_set) service_rejected_error <= 1'b 1;
-2-
==>
221 else if (service_rejected_error_clr) service_rejected_error <= 1'b 0;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Covered |
T5,T13,T14 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
234 if (i == app_id) begin
-1-
235 app_o[i] = '{
==>
236 ready: app_data_ready | fsm_data_ready,
237 done: app_digest_done | fsm_digest_done_q,
238 digest_share0: app_digest[0],
239 digest_share1: app_digest[1],
240 // if fsm asserts done, should be an error case.
241 error: error_i | fsm_digest_done_q | sparse_fsm_error_o
242 | service_rejected_error
243 };
244 end else begin
245 app_o[i] = '{
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
258 if (!rst_ni) app_id <= AppIdxW'(0) ; // Do not select any
-1-
==>
259 else if (clr_appid) app_id <= AppIdxW'(0);
-2-
==>
260 else if (set_appid) app_id <= app_id_d;
-3-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T5,T13,T14 |
| 0 |
0 |
1 |
Covered |
T4,T5,T13 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
305 if (!rst_ni) fsm_digest_done_q <= 1'b 0;
-1-
==>
306 else fsm_digest_done_q <= fsm_digest_done_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
314 `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, st_e, StIdle)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
349 unique case (st)
-1-
350 StIdle: begin
351 if (arb_valid) begin
-2-
352 st_d = StAppCfg;
==>
353
354 // choose app_id
355 set_appid = 1'b 1;
356 end else if (sw_cmd_i == CmdStart) begin
-3-
357 st_d = StSw;
==>
358 // Software initiates the sequence
359 cmd_o = CmdStart;
360 end else begin
361 st_d = StIdle;
==>
362 end
363 end
364
365 StAppCfg: begin
366 if (AppCfg[app_id].Mode == AppKMAC &&
-4-
367 prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)) begin
368 // Check if the entropy is not configured but it is needed in
369 // `AppCfg[app_id]` (KMAC mode).
370 //
371 // SW is not properly configured, report and not request Hashing
372 // Return the app with errors
373 st_d = StError;
==>
374
375 service_rejected_error_set = 1'b 1;
376
377 end else begin
378 // As Cfg is stable now, it sends cmd
379 st_d = StAppMsg;
==>
380
381 // App initiates the data
382 cmd_o = CmdStart;
383 end
384 end
385
386 StAppMsg: begin
387 mux_sel = SelApp;
388 if (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last) begin
-5-
389 if (AppCfg[app_id].Mode == AppKMAC) begin
-6-
390 st_d = StAppOutLen;
==>
391 end else begin
392 st_d = StAppProcess;
==>
393 end
394 end else begin
395 st_d = StAppMsg;
==>
396 end
397 end
398
399 StAppOutLen: begin
400 mux_sel = SelOutLen;
401
402 if (kmac_valid_o && kmac_ready_i) begin
-7-
403 st_d = StAppProcess;
==>
404 end else begin
405 st_d = StAppOutLen;
==>
406 end
407 end
408
409 StAppProcess: begin
410 cmd_o = CmdProcess;
==>
411 st_d = StAppWait;
412 end
413
414 StAppWait: begin
415 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
-8-
416 // Send digest to KeyMgr and complete the op
417 st_d = StIdle;
==>
418 cmd_o = CmdDone;
419
420 clr_appid = 1'b 1;
421 end else begin
422 st_d = StAppWait;
==>
423 end
424 end
425
426 StSw: begin
427 mux_sel = SelSw;
428
429 cmd_o = sw_cmd_i;
430 absorbed_o = absorbed_i;
431
432 if (sw_cmd_i == CmdDone) begin
-9-
433 st_d = StIdle;
==>
434 end else begin
435 st_d = StSw;
==>
436 end
437 end
438
439 StKeyMgrErrKeyNotValid: begin
440 st_d = StError;
==>
441
442 // As mux_sel is not set to SelApp, app_data_ready is still 0.
443 // This logic won't accept the requests from the selected App.
444 fsm_err.valid = 1'b 1;
445 fsm_err.code = ErrKeyNotValid;
446 fsm_err.info = 24'(app_id);
447 end
448
449 StError: begin
450 // In this state, the state machine flush out the request
451 st_d = StError;
452
453 // Absorb data on the app interface.
454 fsm_data_ready = ~err_during_sw_q;
455
456 // Next step depends on two conditions:
457 // 1) Error being processed by SW
458 // 2) Last data provided from the app interface (so that the app interface is completely)
459 // drained. If the error occurred during a SW operation, the app interface is not
460 // involved, so this condition gets skipped.
461 unique case ({err_processed_i,
-10-
462 (app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q})
463 2'b00: begin
464 // Error not processed by SW and not last data from app interface -> keep current state.
465 st_d = StError;
==>
466 end
467 2'b01: begin
468 // Error not processed by SW but last data from app interface:
469 // 1. Send garbage digest to the app interface (in the next cycle) to complete the
470 // transaction.
471 fsm_digest_done_d = ~err_during_sw_q;
472 if (service_rejected_error) begin
-11-
473 // 2.a) Service was rejected because an app interface tried to configure KMAC while no
474 // entropy was available. It is assumed that SW is not loaded yet, so don't wait for
475 // SW to process the error. The last data from the app interface has now arrived, but
476 // we don't need to wait for the SHA3 core to have absorbed it because the data never
477 // entered the SHA3 core: the request from the app interface was terminated during the
478 // configuration phase.
479 st_d = StErrorServiceRejected;
==>
480 end else begin
481 // 2.b) If service was not rejected, wait for SW to process the error.
482 st_d = StErrorAwaitSw;
==>
483 end
484 end
485 2'b10: begin
486 // Error processed by SW but not last data from app interface -> wait for app interface.
487 st_d = StErrorAwaitApp;
==>
488 end
489 2'b11: begin
490 // Error processed by SW and last data from app interface:
491 // Send garbage digest to the app interface (in the next cycle) to complete the
492 // transaction.
493 fsm_digest_done_d = ~err_during_sw_q;
==>
494 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
495 // but serves to bring the SHA3 engine back to the idle state).
496 cmd_o = CmdProcess;
497 st_d = StErrorWaitAbsorbed;
498 end
499 default: st_d = StError;
==>
500 endcase
501 end
502
503 StErrorAwaitSw: begin
504 // Just wait for SW to process the error.
505 if (err_processed_i) begin
-12-
506 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
507 // but serves to bring the SHA3 engine back to the idle state).
508 cmd_o = CmdProcess;
==>
509 st_d = StErrorWaitAbsorbed;
510 end
MISSING_ELSE
==>
511 end
512
513 StErrorAwaitApp: begin
514 // Keep absorbing data on the app interface until the last data.
515 fsm_data_ready = 1'b1;
516 if (app_i[app_id].valid && app_i[app_id].last) begin
-13-
517 // Send garbage digest to the app interface (in the next cycle) to complete the
518 // transaction.
519 fsm_digest_done_d = 1'b1;
==>
520 // Flush the message FIFO and let the SHA3 engine compute a digest (which won't be used
521 // but serves to bring the SHA3 engine back to the idle state).
522 cmd_o = CmdProcess;
523 st_d = StErrorWaitAbsorbed;
524 end
MISSING_ELSE
==>
525 end
526
527 StErrorWaitAbsorbed: begin
528 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) begin
-14-
529 // Clear internal variables, send done command, and return to idle.
530 clr_appid = 1'b1;
531 clear_after_error_o = prim_mubi_pkg::MuBi4True;
532 service_rejected_error_clr = 1'b1;
533 cmd_o = CmdDone;
534 st_d = StIdle;
535 // If error originated from SW, report 'absorbed' to SW.
536 if (err_during_sw_q) begin
-15-
537 absorbed_o = prim_mubi_pkg::MuBi4True;
==>
538 end
MISSING_ELSE
==>
539 end
MISSING_ELSE
==>
540 end
541
542 StErrorServiceRejected: begin
543 // Clear internal variables and return to idle.
544 clr_appid = 1'b1;
==>
545 clear_after_error_o = prim_mubi_pkg::MuBi4True;
546 service_rejected_error_clr = 1'b1;
547 st_d = StIdle;
548 end
549
550 StTerminalError: begin
551 // this state is terminal
552 st_d = st;
==>
553 sparse_fsm_error_o = 1'b 1;
554 fsm_err.valid = 1'b 1;
555 fsm_err.code = ErrFatalError;
556 fsm_err.info = 24'(app_id);
557 end
558
559 default: begin
560 st_d = StTerminalError;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
| StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| StIdle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T5 |
| StIdle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StAppCfg |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StAppCfg |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| StAppMsg |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| StAppMsg |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T20,T21 |
| StAppMsg |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| StAppOutLen |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| StAppOutLen |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T22,T23,T24 |
| StAppProcess |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| StAppWait |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T13,T19 |
| StAppWait |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| StSw |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T12 |
| StSw |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T5 |
| StKeyMgrErrKeyNotValid |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T13,T14 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b00 |
- |
- |
- |
- |
- |
Covered |
T5,T13,T14 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b01 |
1 |
- |
- |
- |
- |
Not Covered |
|
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b01 |
0 |
- |
- |
- |
- |
Covered |
T5,T13,T14 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b10 |
- |
- |
- |
- |
- |
Covered |
T5,T25,T26 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
2'b11 |
- |
- |
- |
- |
- |
Covered |
T27,T28,T29 |
| StError |
- |
- |
- |
- |
- |
- |
- |
- |
default |
- |
- |
- |
- |
- |
Not Covered |
|
| StErrorAwaitSw |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T5,T13,T14 |
| StErrorAwaitSw |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T5,T13,T14 |
| StErrorAwaitApp |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T5,T25,T26 |
| StErrorAwaitApp |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T5,T25,T26 |
| StErrorWaitAbsorbed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
Covered |
T5,T13,T30 |
| StErrorWaitAbsorbed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
Covered |
T5,T13,T14 |
| StErrorWaitAbsorbed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T5,T13,T14 |
| StErrorServiceRejected |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StTerminalError |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T6,T7 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T10,T11 |
568 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) begin
-1-
569 st_d = StTerminalError;
==>
570 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T6,T7 |
| 0 |
Covered |
T1,T2,T3 |
573 if (st_d != StTerminalError) begin
-1-
574 // Key from keymgr is used but not valid, so abort into the invalid key error state.
575 if (keymgr_key_used && !keymgr_key_i.valid) begin
-2-
576 st_d = StKeyMgrErrKeyNotValid;
==>
577 end
MISSING_ELSE
==>
578 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T5,T13,T14 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T4,T6,T7 |
588 if (!rst_ni) begin
-1-
589 err_during_sw_q <= 1'b0;
==>
590 end else begin
591 err_during_sw_q <= err_during_sw_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
618 unique case (mux_sel_buf_kmac)
-1-
619 SelApp: begin
620 // app_id is valid at this time
621 kmac_valid_o = app_i[app_id].valid;
==>
622 kmac_data_o = app_i[app_id].data;
623 // Expand strb to bits. prim_packer inside MSG_FIFO accepts the bit masks
624 for (int i = 0 ; i < $bits(app_i[app_id].strb) ; i++) begin
625 kmac_mask_o[8*i+:8] = {8{app_i[app_id].strb[i]}};
626 end
627 app_data_ready = kmac_ready_i;
628 end
629
630 SelOutLen: begin
631 // Write encoded output length value
632 kmac_valid_o = 1'b 1; // always write
==>
633 kmac_data_o = MsgWidth'(encoded_outlen);
634 kmac_mask_o = MsgWidth'(encoded_outlen_mask);
635 end
636
637 SelSw: begin
638 kmac_valid_o = sw_valid_i;
==>
639 kmac_data_o = sw_data_i ;
640 kmac_mask_o = sw_mask_i ;
641 sw_ready_o = kmac_ready_i ;
642 end
643
644 default: begin // Incl. SelNone
645 kmac_valid_o = 1'b 0;
==>
Branches:
| -1- | Status | Tests |
| SelApp |
Covered |
T4,T5,T13 |
| SelOutLen |
Covered |
T4,T5,T13 |
| SelSw |
Covered |
T1,T2,T5 |
| default |
Covered |
T1,T2,T3 |
657 if (mux_sel_buf_err_check != SelSw && sw_valid_i) begin
-1-
658 // If SW writes message into FIFO
659 mux_err = '{
==>
660 valid: 1'b 1,
661 code: ErrSwPushedMsgFifo,
662 info: 24'({8'h 00, 8'(st), 8'(mux_sel_buf_err_check)})
663 };
664 end else if (app_active_o && sw_cmd_i != CmdNone) begin
-2-
665 // If SW issues command except start
666 mux_err = '{
==>
667 valid: 1'b 1,
668 code: ErrSwIssuedCmdInAppActive,
669 info: 24'(sw_cmd_i)
670 };
671 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T13 |
| 0 |
1 |
Covered |
T19,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
721 if ((mux_sel_buf_output == SelSw) &&
-1-
722 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
723 reg_state_valid = keccak_state_valid_i;
724 reg_state_o = keccak_state_i;
725 // If key is sideloaded and KMAC is SW initiated
726 // hide the capacity from SW by zeroing (see #17508)
727 if (keymgr_key_en_i) begin
-2-
728 for (int i = 0; i < Share; i++) begin
==>
729 unique case (reg_keccak_strength_i)
730 L128: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L128]] = '0;
731 L224: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L224]] = '0;
732 L256: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L256]] = '0;
733 L384: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L384]] = '0;
734 L512: reg_state_o[i][sha3_pkg::StateW-1-:KeccakBitCapacity[L512]] = '0;
735 default: reg_state_o[i] = '0;
736 endcase
737 end
738 end
MISSING_ELSE
==>
739 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T5,T13,T17 |
| 1 |
0 |
Covered |
T1,T2,T12 |
| 0 |
- |
Covered |
T1,T2,T3 |
746 if (st == StAppWait && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i) &&
-1-
747 lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)) begin
748 // SHA3 engine has calculated the hash. Return the data to KeyMgr
749 app_digest_done = 1'b 1;
==>
750
751 // digest has always 2 entries. If !EnMasking, second is tied to 0.
752 for (int i = 0 ; i < Share ; i++) begin
753 // Return the portion of state.
754 app_digest[i] = keccak_state_i[i][AppDigestW-1:0];
755 end
756 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T13,T19 |
| 0 |
Covered |
T1,T2,T3 |
791 unique case (st)
-1-
792 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
793 // Key from keymgr is actually used if the current HW app interface does *keyed* MAC.
794 keymgr_key_used = AppCfg[app_id].Mode == AppKMAC;
==>
795 key_len_o = SideloadedKey;
796 for (int i = 0 ; i < Share; i++) begin
797 key_data_o[i] = keymgr_key[i];
798 end
799 // Key is valid if the current HW app interface does *keyed* MAC and the key provided by
800 // keymgr is valid.
801 key_valid_o = keymgr_key_used && keymgr_key_i.valid;
802 end
803
804 StSw: begin
805 if (keymgr_key_en_i) begin
-2-
806 // Key from keymgr is actually used if *keyed* MAC is enabled.
807 keymgr_key_used = kmac_en_o;
==>
808 key_len_o = SideloadedKey;
809 for (int i = 0 ; i < Share; i++) begin
810 key_data_o[i] = keymgr_key[i];
811 end
812 end
MISSING_ELSE
==>
813 // Key is valid if SW does *keyed* MAC and ...
814 if (kmac_en_o) begin
-3-
815 if (!keymgr_key_en_i) begin
-4-
816 // ... it uses the key from kmac's CSR, or ...
817 key_valid_o = 1'b1;
==>
818 end else begin
819 // ... it uses the key provided by keymgr and that one is valid.
820 key_valid_o = keymgr_key_i.valid;
==>
821 end
822 end
MISSING_ELSE
==>
823 end
824
825 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait |
- |
- |
- |
Covered |
T4,T5,T13 |
| StSw |
1 |
- |
- |
Covered |
T5,T13,T17 |
| StSw |
0 |
- |
- |
Covered |
T1,T2,T12 |
| StSw |
- |
1 |
1 |
Covered |
T1,T2,T12 |
| StSw |
- |
1 |
0 |
Covered |
T5,T13,T17 |
| StSw |
- |
0 |
- |
Covered |
T12,T15,T17 |
| default |
- |
- |
- |
Covered |
T1,T2,T3 |
835 unique case (st)
-1-
836 StAppCfg, StAppMsg, StAppOutLen, StAppProcess, StAppWait: begin
837 // Check app intf cfg
838 for (int unsigned i = 0 ; i < NumAppIntf ; i++) begin
==>
839 if (app_id == i) begin
840 if (AppCfg[i].PrefixMode == 1'b 0) begin
841 sha3_prefix_o = reg_prefix_i;
842 end else begin
843 sha3_prefix_o = AppCfg[i].Prefix;
844 end
845 end
846 end
847 end
848
849 StSw: begin
850 sha3_prefix_o = reg_prefix_i;
==>
851 end
852
853 default: begin
854 sha3_prefix_o = reg_prefix_i;
==>
Branches:
| -1- | Status | Tests |
| StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait |
Covered |
T4,T5,T13 |
| StSw |
Covered |
T1,T2,T5 |
| default |
Covered |
T1,T2,T3 |
862 if (!rst_ni) begin
-1-
863 kmac_en_o <= 1'b 0;
==>
864 sha3_mode_o <= sha3_pkg::Sha3;
865 keccak_strength_o <= sha3_pkg::L256;
866 end else if (clr_appid) begin
-2-
867 // As App completed, latch reg value
868 kmac_en_o <= reg_kmac_en_i;
==>
869 sha3_mode_o <= reg_sha3_mode_i;
870 keccak_strength_o <= reg_keccak_strength_i;
871 end else if (set_appid) begin
-3-
872 kmac_en_o <= AppCfg[arb_idx].Mode == AppKMAC ? 1'b 1 : 1'b 0;
-4-
==>
==>
873 sha3_mode_o <= AppCfg[arb_idx].Mode == AppSHA3
874 ? sha3_pkg::Sha3 : sha3_pkg::CShake;
-5-
==>
==>
875 keccak_strength_o <= AppCfg[arb_idx].Strength ;
876 end else if (st == StIdle) begin
-6-
877 kmac_en_o <= reg_kmac_en_i;
==>
878 sha3_mode_o <= reg_sha3_mode_i;
879 keccak_strength_o <= reg_keccak_strength_i;
880 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T5,T13,T14 |
| 0 |
0 |
1 |
1 |
- |
- |
Covered |
T4,T5,T13 |
| 0 |
0 |
1 |
0 |
- |
- |
Covered |
T19,T20,T21 |
| 0 |
0 |
1 |
- |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
- |
0 |
- |
Covered |
T4,T5,T13 |
| 0 |
0 |
0 |
- |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
- |
- |
0 |
Covered |
T1,T2,T4 |
889 priority casez ({fsm_err.valid, mux_err.valid})
-1-
890 2'b ?1: error_o = mux_err;
==>
891 2'b 10: error_o = fsm_err;
==>
892 default: error_o = '{valid: 1'b0, code: ErrNone, info: '0};
==>
Branches:
| -1- | Status | Tests |
| 2'bz1 |
Covered |
T4,T5,T13 |
| 2'b10 |
Covered |
T4,T5,T13 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
kmac_app
Assertion Details
AppIntfInRange_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
704 |
704 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
SideloadKeySameToDigest_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
704 |
704 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T15 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
614716435 |
614566771 |
0 |
0 |
| T1 |
7436 |
7347 |
0 |
0 |
| T2 |
5376 |
5298 |
0 |
0 |
| T3 |
1047 |
994 |
0 |
0 |
| T4 |
5269 |
5126 |
0 |
0 |
| T5 |
7591 |
7504 |
0 |
0 |
| T12 |
6627 |
6557 |
0 |
0 |
| T13 |
12546 |
12448 |
0 |
0 |
| T14 |
124983 |
124920 |
0 |
0 |
| T15 |
103804 |
103705 |
0 |
0 |
| T16 |
3333 |
3283 |
0 |
0 |
Cover Directives for Properties: Details
AppIntfUseDifferentSizeKey_C
| Name | Attempts | Matches | Incomplete |
| Total |
614716435 |
2789 |
0 |
| T14 |
124983 |
10 |
0 |
| T15 |
103804 |
0 |
0 |
| T16 |
3333 |
0 |
0 |
| T17 |
79289 |
0 |
0 |
| T18 |
5278 |
0 |
0 |
| T19 |
238897 |
0 |
0 |
| T20 |
240722 |
32 |
0 |
| T21 |
0 |
3 |
0 |
| T22 |
0 |
6 |
0 |
| T23 |
0 |
6 |
0 |
| T34 |
0 |
10 |
0 |
| T45 |
0 |
11 |
0 |
| T51 |
38670 |
0 |
0 |
| T52 |
26339 |
0 |
0 |
| T53 |
114629 |
0 |
0 |
| T54 |
0 |
2 |
0 |
| T55 |
0 |
23 |
0 |
| T56 |
0 |
6 |
0 |
