Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	616217713	3749	0	0
entropy_period_rd_A	616217713	1469	0	0
intr_enable_rd_A	616217713	2337	0	0
prefix_0_rd_A	616217713	1689	0	0
prefix_10_rd_A	616217713	1735	0	0
prefix_1_rd_A	616217713	1594	0	0
prefix_2_rd_A	616217713	1716	0	0
prefix_3_rd_A	616217713	1762	0	0
prefix_4_rd_A	616217713	1720	0	0
prefix_5_rd_A	616217713	1772	0	0
prefix_6_rd_A	616217713	1747	0	0
prefix_7_rd_A	616217713	1809	0	0
prefix_8_rd_A	616217713	1747	0	0
prefix_9_rd_A	616217713	1854	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	3749	0	0
T50	3585	0	0	0
T62	463869	0	0	0
T66	188798	683	0	0
T67	0	654	0	0
T68	0	105	0	0
T75	14145	0	0	0
T116	822719	0	0	0
T117	38849	0	0	0
T121	0	2	0	0
T123	0	1	0	0
T125	0	3	0	0
T129	0	273	0	0
T133	0	12	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	738587	0	0	0
T137	827172	0	0	0
T138	853789	0	0	0
T139	37466	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1469	0	0
T106	5917	26	0	0
T113	3993	1	0	0
T123	23002	125	0	0
T130	3339	7	0	0
T135	7888	23	0	0
T150	11209	37	0	0
T151	2124	3	0	0
T152	5659	12	0	0
T153	73027	97	0	0
T154	2825	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	2337	0	0
T106	5917	20	0	0
T113	3993	11	0	0
T123	23002	177	0	0
T130	3339	8	0	0
T131	1490	25	0	0
T135	7888	19	0	0
T150	11209	38	0	0
T151	2124	16	0	0
T152	5659	3	0	0
T155	988	7	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1689	0	0
T106	5917	29	0	0
T113	3993	16	0	0
T123	23002	49	0	0
T130	3339	9	0	0
T135	7888	14	0	0
T150	11209	47	0	0
T152	5659	10	0	0
T153	73027	221	0	0
T154	2825	3	0	0
T156	25264	73	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1735	0	0
T106	5917	15	0	0
T113	3993	13	0	0
T123	23002	86	0	0
T130	3339	4	0	0
T135	7888	16	0	0
T150	11209	54	0	0
T151	2124	6	0	0
T152	5659	17	0	0
T153	73027	219	0	0
T154	2825	16	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1594	0	0
T106	5917	31	0	0
T113	3993	18	0	0
T123	23002	66	0	0
T130	3339	5	0	0
T135	7888	18	0	0
T150	11209	32	0	0
T152	5659	30	0	0
T153	73027	202	0	0
T154	2825	5	0	0
T156	25264	83	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1716	0	0
T106	5917	34	0	0
T113	3993	8	0	0
T123	23002	90	0	0
T130	3339	11	0	0
T133	6245	3	0	0
T135	7888	19	0	0
T150	11209	52	0	0
T152	5659	40	0	0
T153	73027	208	0	0
T154	2825	12	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1762	0	0
T106	5917	32	0	0
T113	3993	6	0	0
T123	23002	77	0	0
T129	13144	7	0	0
T130	3339	4	0	0
T135	7888	16	0	0
T150	11209	44	0	0
T152	5659	34	0	0
T153	73027	198	0	0
T154	2825	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1720	0	0
T106	5917	18	0	0
T108	2865	7	0	0
T113	3993	4	0	0
T123	23002	98	0	0
T130	3339	1	0	0
T135	7888	19	0	0
T150	11209	51	0	0
T153	73027	275	0	0
T154	2825	12	0	0
T156	25264	68	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1772	0	0
T106	5917	28	0	0
T113	3993	6	0	0
T123	23002	92	0	0
T130	3339	13	0	0
T135	7888	20	0	0
T150	11209	75	0	0
T151	2124	6	0	0
T152	5659	8	0	0
T153	73027	232	0	0
T154	2825	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1747	0	0
T106	5917	25	0	0
T113	3993	4	0	0
T123	23002	96	0	0
T130	3339	10	0	0
T135	7888	28	0	0
T150	11209	70	0	0
T151	2124	6	0	0
T152	5659	31	0	0
T153	73027	213	0	0
T154	2825	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1809	0	0
T106	5917	26	0	0
T113	3993	7	0	0
T123	23002	85	0	0
T130	3339	7	0	0
T135	7888	6	0	0
T150	11209	82	0	0
T152	5659	26	0	0
T153	73027	240	0	0
T154	2825	3	0	0
T156	25264	73	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1747	0	0
T106	5917	37	0	0
T113	3993	9	0	0
T123	23002	89	0	0
T130	3339	4	0	0
T135	7888	13	0	0
T150	11209	39	0	0
T151	2124	3	0	0
T152	5659	40	0	0
T153	73027	205	0	0
T154	2825	10	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616217713	1854	0	0
T106	5917	31	0	0
T113	3993	11	0	0
T123	23002	97	0	0
T130	3339	5	0	0
T135	7888	26	0	0
T150	11209	29	0	0
T151	2124	3	0	0
T152	5659	27	0	0
T153	73027	253	0	0
T154	2825	4	0	0