Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3528	0	0
entropy_period_rd_A	2147483647	1567	0	0
intr_enable_rd_A	2147483647	1934	0	0
prefix_0_rd_A	2147483647	1142	0	0
prefix_10_rd_A	2147483647	1114	0	0
prefix_1_rd_A	2147483647	1258	0	0
prefix_2_rd_A	2147483647	1055	0	0
prefix_3_rd_A	2147483647	1265	0	0
prefix_4_rd_A	2147483647	1246	0	0
prefix_5_rd_A	2147483647	1224	0	0
prefix_6_rd_A	2147483647	1240	0	0
prefix_7_rd_A	2147483647	1087	0	0
prefix_8_rd_A	2147483647	1083	0	0
prefix_9_rd_A	2147483647	1133	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3528	0	0
T54	6221	190	0	0
T55	2605	150	0	0
T107	6907	6	0	0
T108	21761	2	0	0
T109	11264	1	0	0
T111	12351	164	0	0
T121	2092	97	0	0
T123	2761	173	0	0
T124	8081	4	0	0
T128	12257	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1567	0	0
T56	15128	79	0	0
T97	4608	13	0	0
T108	21761	45	0	0
T124	8081	3	0	0
T127	9021	2	0	0
T128	12257	48	0	0
T129	12652	62	0	0
T139	2793	3	0	0
T140	26481	231	0	0
T141	3184	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1934	0	0
T56	15128	33	0	0
T97	4608	15	0	0
T108	21761	116	0	0
T124	8081	23	0	0
T127	9021	11	0	0
T128	12257	66	0	0
T139	2793	1	0	0
T140	26481	189	0	0
T141	3184	3	0	0
T142	971	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1142	0	0
T56	15128	54	0	0
T97	4608	12	0	0
T108	21761	34	0	0
T124	8081	14	0	0
T127	9021	9	0	0
T128	12257	41	0	0
T129	12652	35	0	0
T139	2793	2	0	0
T140	26481	233	0	0
T141	3184	11	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1114	0	0
T56	15128	44	0	0
T97	4608	16	0	0
T108	21761	38	0	0
T124	8081	2	0	0
T127	9021	10	0	0
T128	12257	24	0	0
T129	12652	22	0	0
T139	2793	5	0	0
T140	26481	218	0	0
T141	3184	11	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1258	0	0
T56	15128	52	0	0
T97	4608	16	0	0
T108	21761	83	0	0
T124	8081	2	0	0
T127	9021	2	0	0
T128	12257	41	0	0
T129	12652	47	0	0
T139	2793	3	0	0
T140	26481	235	0	0
T141	3184	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1055	0	0
T56	15128	48	0	0
T97	4608	14	0	0
T108	21761	42	0	0
T124	8081	6	0	0
T127	9021	8	0	0
T128	12257	34	0	0
T129	12652	30	0	0
T139	2793	8	0	0
T140	26481	182	0	0
T141	3184	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1265	0	0
T56	15128	41	0	0
T97	4608	10	0	0
T108	21761	56	0	0
T124	8081	3	0	0
T127	9021	7	0	0
T128	12257	43	0	0
T129	12652	52	0	0
T139	2793	2	0	0
T140	26481	233	0	0
T141	3184	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1246	0	0
T56	15128	35	0	0
T97	4608	14	0	0
T108	21761	46	0	0
T124	8081	10	0	0
T127	9021	13	0	0
T128	12257	64	0	0
T129	12652	42	0	0
T140	26481	192	0	0
T143	3037	1	0	0
T144	6809	36	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1224	0	0
T56	15128	45	0	0
T97	4608	19	0	0
T108	21761	36	0	0
T124	8081	11	0	0
T128	12257	43	0	0
T129	12652	53	0	0
T139	2793	1	0	0
T140	26481	200	0	0
T141	3184	2	0	0
T143	3037	14	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1240	0	0
T56	15128	37	0	0
T97	4608	10	0	0
T108	21761	57	0	0
T124	8081	5	0	0
T127	9021	14	0	0
T128	12257	36	0	0
T129	12652	46	0	0
T139	2793	6	0	0
T140	26481	238	0	0
T141	3184	16	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1087	0	0
T56	15128	33	0	0
T97	4608	10	0	0
T108	21761	46	0	0
T124	8081	15	0	0
T127	9021	10	0	0
T128	12257	34	0	0
T129	12652	32	0	0
T139	2793	3	0	0
T140	26481	222	0	0
T141	3184	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1083	0	0
T56	15128	35	0	0
T97	4608	21	0	0
T108	21761	31	0	0
T124	8081	10	0	0
T127	9021	10	0	0
T128	12257	32	0	0
T129	12652	20	0	0
T139	2793	8	0	0
T140	26481	205	0	0
T141	3184	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1133	0	0
T56	15128	32	0	0
T97	4608	25	0	0
T108	21761	48	0	0
T124	8081	3	0	0
T127	9021	6	0	0
T128	12257	26	0	0
T129	12652	36	0	0
T139	2793	7	0	0
T140	26481	195	0	0
T141	3184	3	0	0