Module Definition
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Module : prim_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_buf_0/prim_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3.u_keccak.u_prim_sec_anchor_buf.u_secure_anchor_buf
tb.dut.u_app_intf.u_prim_buf_state_output_sel.u_secure_anchor_buf
tb.dut.u_app_intf.u_prim_buf_state_err_check.u_secure_anchor_buf
tb.dut.u_app_intf.u_prim_buf_state_kmac_sel.u_secure_anchor_buf
tb.dut.u_app_intf.u_prim_buf_state_output_valid.u_secure_anchor_buf
tb.dut.u_sha3_done_sender.gen_prim_buf.u_prim_buf
tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[3].u_prim_buf.u_secure_anchor_buf



Module Instance : tb.dut.u_sha3.u_keccak.u_prim_sec_anchor_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_sec_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_output_sel.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf_state_output_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_err_check.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf_state_err_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_kmac_sel.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf_state_kmac_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_app_intf.u_prim_buf_state_output_valid.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf_state_output_valid


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_sha3_done_sender.gen_prim_buf.u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sha3_done_sender


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00

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