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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.15 96.19 92.52 100.00 73.55 94.61 99.03 96.15


Total test records in report: 919
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T779 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2933651688 Oct 15 01:03:24 PM UTC 24 Oct 15 01:03:28 PM UTC 24 40400646 ps
T780 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.1777865323 Oct 15 01:03:19 PM UTC 24 Oct 15 01:03:28 PM UTC 24 271713139 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.778974745 Oct 15 01:03:16 PM UTC 24 Oct 15 01:03:28 PM UTC 24 1460585973 ps
T781 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3131777951 Oct 15 01:03:26 PM UTC 24 Oct 15 01:03:28 PM UTC 24 11557701 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4072338166 Oct 15 01:03:26 PM UTC 24 Oct 15 01:03:29 PM UTC 24 108728788 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.4011179467 Oct 15 01:03:27 PM UTC 24 Oct 15 01:03:29 PM UTC 24 34945464 ps
T782 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.623251753 Oct 15 01:03:27 PM UTC 24 Oct 15 01:03:29 PM UTC 24 422199747 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.3285602601 Oct 15 01:03:26 PM UTC 24 Oct 15 01:03:29 PM UTC 24 34441686 ps
T783 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.531397004 Oct 15 01:03:27 PM UTC 24 Oct 15 01:03:30 PM UTC 24 36792528 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2297929460 Oct 15 01:03:26 PM UTC 24 Oct 15 01:03:30 PM UTC 24 126610785 ps
T784 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.612478479 Oct 15 01:03:21 PM UTC 24 Oct 15 01:03:30 PM UTC 24 507328424 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3730384989 Oct 15 01:03:27 PM UTC 24 Oct 15 01:03:30 PM UTC 24 107896389 ps
T785 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3421578730 Oct 15 01:03:27 PM UTC 24 Oct 15 01:03:31 PM UTC 24 88997716 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.3336428195 Oct 15 01:03:24 PM UTC 24 Oct 15 01:03:31 PM UTC 24 308113302 ps
T786 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3705603292 Oct 15 01:03:28 PM UTC 24 Oct 15 01:03:31 PM UTC 24 82104455 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2261858410 Oct 15 01:03:29 PM UTC 24 Oct 15 01:03:31 PM UTC 24 30039265 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1464299065 Oct 15 01:03:29 PM UTC 24 Oct 15 01:03:32 PM UTC 24 477789960 ps
T787 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.518475731 Oct 15 01:03:29 PM UTC 24 Oct 15 01:03:32 PM UTC 24 50531140 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1435456736 Oct 15 01:03:27 PM UTC 24 Oct 15 01:03:32 PM UTC 24 344374120 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3793407879 Oct 15 01:03:29 PM UTC 24 Oct 15 01:03:32 PM UTC 24 66391747 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2481987721 Oct 15 01:03:24 PM UTC 24 Oct 15 01:03:32 PM UTC 24 147850085 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.425953087 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:33 PM UTC 24 19890665 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1255482535 Oct 15 01:03:29 PM UTC 24 Oct 15 01:03:33 PM UTC 24 155285956 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1691164301 Oct 15 01:03:29 PM UTC 24 Oct 15 01:03:33 PM UTC 24 144810763 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3372784618 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:33 PM UTC 24 305215200 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3489903448 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:34 PM UTC 24 27117830 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.697762821 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:34 PM UTC 24 570897277 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1027693909 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:34 PM UTC 24 82544787 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.564387159 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:34 PM UTC 24 131164093 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.2984473061 Oct 15 01:03:29 PM UTC 24 Oct 15 01:03:34 PM UTC 24 408044806 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.3625853752 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:35 PM UTC 24 394276997 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3870858871 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:35 PM UTC 24 252645397 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.644213885 Oct 15 01:03:31 PM UTC 24 Oct 15 01:03:35 PM UTC 24 802943876 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.167231524 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:35 PM UTC 24 16678406 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3686523814 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:36 PM UTC 24 66293745 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.26705109 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:36 PM UTC 24 47056489 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1905139211 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:36 PM UTC 24 86869972 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1691750682 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:36 PM UTC 24 875736551 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3148864976 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:37 PM UTC 24 89389900 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.863410395 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 25804442 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.234903572 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:38 PM UTC 24 86843716 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1098878289 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:38 PM UTC 24 33950544 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2817394320 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:38 PM UTC 24 458077421 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3121014249 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:38 PM UTC 24 22585056 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3612803381 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:38 PM UTC 24 18254903 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.884589919 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:39 PM UTC 24 175726404 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1079303964 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 159669804 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.132910810 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:39 PM UTC 24 268030389 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1459479943 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:39 PM UTC 24 39339893 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.502426938 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:39 PM UTC 24 294346341 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1360391720 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:39 PM UTC 24 255350586 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2959709154 Oct 15 01:03:37 PM UTC 24 Oct 15 01:03:40 PM UTC 24 17266419 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1043762666 Oct 15 01:03:33 PM UTC 24 Oct 15 01:03:40 PM UTC 24 769545841 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.425663633 Oct 15 01:03:37 PM UTC 24 Oct 15 01:03:40 PM UTC 24 26626551 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.4073374675 Oct 15 01:03:37 PM UTC 24 Oct 15 01:03:40 PM UTC 24 25142233 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2146705979 Oct 15 01:03:37 PM UTC 24 Oct 15 01:03:40 PM UTC 24 123873877 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.105361601 Oct 15 01:03:27 PM UTC 24 Oct 15 01:03:40 PM UTC 24 1511271752 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.785145858 Oct 15 01:03:38 PM UTC 24 Oct 15 01:03:40 PM UTC 24 33108334 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2822369406 Oct 15 01:03:38 PM UTC 24 Oct 15 01:03:41 PM UTC 24 22671818 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1980847291 Oct 15 01:03:37 PM UTC 24 Oct 15 01:03:41 PM UTC 24 78934111 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1866494224 Oct 15 01:03:38 PM UTC 24 Oct 15 01:03:41 PM UTC 24 101933197 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1960050796 Oct 15 01:03:21 PM UTC 24 Oct 15 01:03:41 PM UTC 24 4596290598 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1987658727 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:41 PM UTC 24 96980862 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1244937688 Oct 15 01:03:38 PM UTC 24 Oct 15 01:03:41 PM UTC 24 41132522 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3360634452 Oct 15 01:03:37 PM UTC 24 Oct 15 01:03:41 PM UTC 24 174003627 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1535651570 Oct 15 01:03:37 PM UTC 24 Oct 15 01:03:42 PM UTC 24 121187940 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2278898909 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:42 PM UTC 24 1476262515 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3004297827 Oct 15 01:03:38 PM UTC 24 Oct 15 01:03:42 PM UTC 24 166415657 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3318479674 Oct 15 01:03:40 PM UTC 24 Oct 15 01:03:42 PM UTC 24 18269581 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1766771480 Oct 15 01:03:40 PM UTC 24 Oct 15 01:03:42 PM UTC 24 78291550 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1327196178 Oct 15 01:03:40 PM UTC 24 Oct 15 01:03:42 PM UTC 24 93104642 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3957333868 Oct 15 01:03:40 PM UTC 24 Oct 15 01:03:42 PM UTC 24 74419546 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2466581410 Oct 15 01:03:39 PM UTC 24 Oct 15 01:03:43 PM UTC 24 391233430 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2012149740 Oct 15 01:03:40 PM UTC 24 Oct 15 01:03:43 PM UTC 24 40991629 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2917998348 Oct 15 01:03:41 PM UTC 24 Oct 15 01:03:43 PM UTC 24 130768005 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3054400838 Oct 15 01:03:41 PM UTC 24 Oct 15 01:03:43 PM UTC 24 62648855 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.626909983 Oct 15 01:03:41 PM UTC 24 Oct 15 01:03:44 PM UTC 24 155318223 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2817716417 Oct 15 01:03:40 PM UTC 24 Oct 15 01:03:44 PM UTC 24 119529920 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2276631280 Oct 15 01:03:40 PM UTC 24 Oct 15 01:03:44 PM UTC 24 322781671 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2907931407 Oct 15 01:03:36 PM UTC 24 Oct 15 01:03:44 PM UTC 24 378739391 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.846120652 Oct 15 01:03:41 PM UTC 24 Oct 15 01:03:44 PM UTC 24 55344649 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.563834931 Oct 15 01:03:42 PM UTC 24 Oct 15 01:03:45 PM UTC 24 38451060 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.795489691 Oct 15 01:03:42 PM UTC 24 Oct 15 01:03:45 PM UTC 24 87948083 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.305901647 Oct 15 01:03:24 PM UTC 24 Oct 15 01:03:45 PM UTC 24 1871857403 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2778964680 Oct 15 01:03:43 PM UTC 24 Oct 15 01:03:45 PM UTC 24 94649621 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.138916229 Oct 15 01:03:41 PM UTC 24 Oct 15 01:03:45 PM UTC 24 1528994167 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3149560362 Oct 15 01:03:42 PM UTC 24 Oct 15 01:03:45 PM UTC 24 245216226 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3633599672 Oct 15 01:03:42 PM UTC 24 Oct 15 01:03:45 PM UTC 24 98406628 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3331287049 Oct 15 01:03:43 PM UTC 24 Oct 15 01:03:46 PM UTC 24 90466471 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2879036875 Oct 15 01:03:41 PM UTC 24 Oct 15 01:03:46 PM UTC 24 509059980 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3360691785 Oct 15 01:03:43 PM UTC 24 Oct 15 01:03:46 PM UTC 24 67063075 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3503152405 Oct 15 01:03:42 PM UTC 24 Oct 15 01:03:46 PM UTC 24 74293421 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.554215873 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:46 PM UTC 24 21471005 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.3701993152 Oct 15 01:03:41 PM UTC 24 Oct 15 01:03:46 PM UTC 24 184373362 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.187779320 Oct 15 01:03:43 PM UTC 24 Oct 15 01:03:46 PM UTC 24 598272226 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2039845358 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:46 PM UTC 24 13045920 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2497795659 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:46 PM UTC 24 64175659 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.710678083 Oct 15 01:03:43 PM UTC 24 Oct 15 01:03:47 PM UTC 24 506799560 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.937034571 Oct 15 01:03:43 PM UTC 24 Oct 15 01:03:47 PM UTC 24 102944716 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1345035933 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:47 PM UTC 24 49821025 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2052984638 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:47 PM UTC 24 130139212 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1626407292 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 40330107 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1103093319 Oct 15 01:03:45 PM UTC 24 Oct 15 01:03:48 PM UTC 24 21750945 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3232896194 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:48 PM UTC 24 46149217 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.68308306 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:48 PM UTC 24 129908614 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2044549784 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:48 PM UTC 24 153855501 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1334107870 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:48 PM UTC 24 33149878 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3757887713 Oct 15 01:03:42 PM UTC 24 Oct 15 01:03:48 PM UTC 24 353957030 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1847644143 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:48 PM UTC 24 122720771 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1860798233 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:49 PM UTC 24 256606293 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1669643834 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 27828583 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3220041119 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:49 PM UTC 24 466295611 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2524882948 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:49 PM UTC 24 50799577 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1530297613 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:49 PM UTC 24 21480607 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1730580653 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:49 PM UTC 24 46636535 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4091314956 Oct 15 01:03:44 PM UTC 24 Oct 15 01:03:50 PM UTC 24 382004157 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2145536612 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 87205833 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1617850046 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:50 PM UTC 24 178224078 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1669506219 Oct 15 01:03:46 PM UTC 24 Oct 15 01:03:50 PM UTC 24 433484190 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1250854613 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 65468595 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.116168335 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 122571908 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1702662492 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:50 PM UTC 24 129523618 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3226683578 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:50 PM UTC 24 12898091 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3815922645 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:51 PM UTC 24 44982415 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.20124099 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:51 PM UTC 24 157572511 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.305507968 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:51 PM UTC 24 89103667 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.540065243 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:51 PM UTC 24 467053814 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2429280575 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:52 PM UTC 24 38305653 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3021436533 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:52 PM UTC 24 80443975 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.4096154378 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:52 PM UTC 24 141302082 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1418978639 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:52 PM UTC 24 102422253 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.259189643 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:52 PM UTC 24 15184300 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1234409283 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:52 PM UTC 24 31034753 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3817057028 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:52 PM UTC 24 18402491 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3720215222 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:52 PM UTC 24 86720418 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1082782997 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:52 PM UTC 24 159138571 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3014648197 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:52 PM UTC 24 201758816 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2457631063 Oct 15 01:03:47 PM UTC 24 Oct 15 01:03:53 PM UTC 24 345828014 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3723914236 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:53 PM UTC 24 45022145 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2219502227 Oct 15 01:03:51 PM UTC 24 Oct 15 01:03:53 PM UTC 24 100961470 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3911589477 Oct 15 01:03:51 PM UTC 24 Oct 15 01:03:53 PM UTC 24 46781545 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.359951020 Oct 15 01:03:51 PM UTC 24 Oct 15 01:03:53 PM UTC 24 134412529 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.4095579252 Oct 15 01:03:49 PM UTC 24 Oct 15 01:03:53 PM UTC 24 40856066 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2784309901 Oct 15 01:03:51 PM UTC 24 Oct 15 01:03:53 PM UTC 24 10635017 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2906195962 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:53 PM UTC 24 36294608 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.4262911398 Oct 15 01:03:50 PM UTC 24 Oct 15 01:03:53 PM UTC 24 201575560 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.79980357 Oct 15 01:03:52 PM UTC 24 Oct 15 01:03:53 PM UTC 24 45257441 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.308825270 Oct 15 01:03:52 PM UTC 24 Oct 15 01:03:54 PM UTC 24 47793592 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1931557231 Oct 15 01:03:52 PM UTC 24 Oct 15 01:03:54 PM UTC 24 45261925 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1265609855 Oct 15 01:03:51 PM UTC 24 Oct 15 01:03:54 PM UTC 24 24917696 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3868057984 Oct 15 01:03:51 PM UTC 24 Oct 15 01:03:54 PM UTC 24 66494629 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3530253783 Oct 15 01:03:52 PM UTC 24 Oct 15 01:03:54 PM UTC 24 44668768 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2278939318 Oct 15 01:03:52 PM UTC 24 Oct 15 01:03:54 PM UTC 24 41284316 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.1796275217 Oct 15 01:03:52 PM UTC 24 Oct 15 01:03:54 PM UTC 24 15278365 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1515924348 Oct 15 01:03:48 PM UTC 24 Oct 15 01:03:54 PM UTC 24 221635115 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2161547265 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 13372358 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3947483598 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 46052640 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3636686501 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 36131843 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.46007967 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 40548144 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2020135620 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 13058169 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2710769759 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 13202607 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2785312094 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 14701554 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.975548923 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 25684499 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.969750998 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 44547615 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1733182366 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 74723137 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.810471565 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 70512790 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3554579397 Oct 15 01:03:53 PM UTC 24 Oct 15 01:03:55 PM UTC 24 43346105 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.431507480 Oct 15 01:03:54 PM UTC 24 Oct 15 01:03:56 PM UTC 24 25050719 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1023246600 Oct 15 01:03:54 PM UTC 24 Oct 15 01:03:56 PM UTC 24 24815232 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload_invalid.4169009986
Short name T5
Test name
Test status
Simulation time 154927103 ps
CPU time 4.25 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:04:00 PM UTC 24
Peak memory 231304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169009986 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload_invalid.4169009986 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.2958575409
Short name T21
Test name
Test status
Simulation time 3269907720 ps
CPU time 47.29 seconds
Started Oct 15 01:07:16 PM UTC 24
Finished Oct 15 01:08:05 PM UTC 24
Peak memory 266172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958575409 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2958575409 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.2559419716
Short name T121
Test name
Test status
Simulation time 314041507 ps
CPU time 3.68 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:21 PM UTC 24
Peak memory 216812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559419716 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.2559419716 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.2854197934
Short name T10
Test name
Test status
Simulation time 4265430654 ps
CPU time 79.02 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:05:17 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854197934 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2854197934 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.2329915621
Short name T19
Test name
Test status
Simulation time 3981731748 ps
CPU time 162.08 seconds
Started Oct 15 01:05:17 PM UTC 24
Finished Oct 15 01:08:01 PM UTC 24
Peak memory 329644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329915621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2329915621 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.127920453
Short name T66
Test name
Test status
Simulation time 7551984519 ps
CPU time 75.59 seconds
Started Oct 15 01:05:24 PM UTC 24
Finished Oct 15 01:06:41 PM UTC 24
Peak memory 278532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=127920453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_w
ith_rand_reset.127920453 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.4120964408
Short name T8
Test name
Test status
Simulation time 36544126 ps
CPU time 1.79 seconds
Started Oct 15 01:09:35 PM UTC 24
Finished Oct 15 01:09:37 PM UTC 24
Peak memory 233988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120964408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.4120964408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4105324613
Short name T106
Test name
Test status
Simulation time 348112703 ps
CPU time 2.37 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:25 PM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105324613 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.4105324613 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.277239605
Short name T23
Test name
Test status
Simulation time 6788493098 ps
CPU time 38.11 seconds
Started Oct 15 01:04:31 PM UTC 24
Finished Oct 15 01:05:10 PM UTC 24
Peak memory 245748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277239605 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.277239605 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.619225701
Short name T4
Test name
Test status
Simulation time 66710143 ps
CPU time 1.98 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:03:59 PM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619225701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.619225701 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.3156232749
Short name T70
Test name
Test status
Simulation time 2023742330 ps
CPU time 85.34 seconds
Started Oct 15 01:47:02 PM UTC 24
Finished Oct 15 01:48:30 PM UTC 24
Peak memory 268216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156232749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3156232749 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.4011179467
Short name T163
Test name
Test status
Simulation time 34945464 ps
CPU time 1.18 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:29 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011179467 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.4011179467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.206025518
Short name T57
Test name
Test status
Simulation time 22377926786 ps
CPU time 396.76 seconds
Started Oct 15 01:09:39 PM UTC 24
Finished Oct 15 01:16:20 PM UTC 24
Peak memory 328200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206025518 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.206025518 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1464299065
Short name T108
Test name
Test status
Simulation time 477789960 ps
CPU time 1.42 seconds
Started Oct 15 01:03:29 PM UTC 24
Finished Oct 15 01:03:32 PM UTC 24
Peak memory 226292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464299065 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.1464299065 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload_invalid.2490400851
Short name T30
Test name
Test status
Simulation time 195886820 ps
CPU time 6.6 seconds
Started Oct 15 01:05:47 PM UTC 24
Finished Oct 15 01:05:55 PM UTC 24
Peak memory 231524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490400851 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload_invalid.2490400851 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.3621758304
Short name T48
Test name
Test status
Simulation time 148534225 ps
CPU time 1.92 seconds
Started Oct 15 01:24:11 PM UTC 24
Finished Oct 15 01:24:13 PM UTC 24
Peak memory 229840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621758304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3621758304 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload_invalid.2808331355
Short name T27
Test name
Test status
Simulation time 359045479 ps
CPU time 6.17 seconds
Started Oct 15 01:33:07 PM UTC 24
Finished Oct 15 01:33:14 PM UTC 24
Peak memory 231416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808331355 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload_invalid.2808331355 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.2893181757
Short name T142
Test name
Test status
Simulation time 32914834 ps
CPU time 1.21 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:21 PM UTC 24
Peak memory 226052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893181757 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.2893181757 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.3072514825
Short name T9
Test name
Test status
Simulation time 41916581 ps
CPU time 1.57 seconds
Started Oct 15 01:30:56 PM UTC 24
Finished Oct 15 01:30:59 PM UTC 24
Peak memory 234504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072514825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3072514825 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.2633409954
Short name T3
Test name
Test status
Simulation time 61714415 ps
CPU time 1.04 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:03:59 PM UTC 24
Peak memory 213980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633409954 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2633409954 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.251774986
Short name T100
Test name
Test status
Simulation time 2300908072 ps
CPU time 47.01 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:04:48 PM UTC 24
Peak memory 235068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251774986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.251774986 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1691164301
Short name T109
Test name
Test status
Simulation time 144810763 ps
CPU time 2.78 seconds
Started Oct 15 01:03:29 PM UTC 24
Finished Oct 15 01:03:33 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691164301 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.
1691164301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3549713060
Short name T131
Test name
Test status
Simulation time 20730025 ps
CPU time 0.93 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:18 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549713060 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3549713060 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.3336428195
Short name T156
Test name
Test status
Simulation time 308113302 ps
CPU time 5.69 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:31 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336428195 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.3336428195 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.3564196883
Short name T157
Test name
Test status
Simulation time 31107860254 ps
CPU time 355.45 seconds
Started Oct 15 01:09:06 PM UTC 24
Finished Oct 15 01:15:07 PM UTC 24
Peak memory 522172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564196883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3564196883 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.3637088290
Short name T505
Test name
Test status
Simulation time 29015154375 ps
CPU time 1803.4 seconds
Started Oct 15 01:25:46 PM UTC 24
Finished Oct 15 01:56:10 PM UTC 24
Peak memory 755976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637088290 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3637088290 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3757887713
Short name T175
Test name
Test status
Simulation time 353957030 ps
CPU time 4.55 seconds
Started Oct 15 01:03:42 PM UTC 24
Finished Oct 15 01:03:48 PM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757887713 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3757887713 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.2400702770
Short name T85
Test name
Test status
Simulation time 1801696772 ps
CPU time 45.65 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:04:42 PM UTC 24
Peak memory 257832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400702770 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2400702770
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.3594635126
Short name T62
Test name
Test status
Simulation time 19328145203 ps
CPU time 81.4 seconds
Started Oct 15 01:05:19 PM UTC 24
Finished Oct 15 01:06:43 PM UTC 24
Peak memory 231048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594635126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3594635126 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1463846960
Short name T102
Test name
Test status
Simulation time 98077947 ps
CPU time 1.21 seconds
Started Oct 15 01:03:13 PM UTC 24
Finished Oct 15 01:03:16 PM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463846960 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1463846960 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.3701993152
Short name T176
Test name
Test status
Simulation time 184373362 ps
CPU time 3.91 seconds
Started Oct 15 01:03:41 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701993152 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3701993152 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1246469304
Short name T123
Test name
Test status
Simulation time 605354256 ps
CPU time 5.04 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:25 PM UTC 24
Peak memory 217452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246469304 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.1246469304 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.3639498360
Short name T14
Test name
Test status
Simulation time 1315589399 ps
CPU time 10.49 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:04:08 PM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639498360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3639498360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.1679263911
Short name T339
Test name
Test status
Simulation time 68467710614 ps
CPU time 399.23 seconds
Started Oct 15 01:28:37 PM UTC 24
Finished Oct 15 01:35:21 PM UTC 24
Peak memory 591848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679263911 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1679263911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2299866045
Short name T203
Test name
Test status
Simulation time 52583718579 ps
CPU time 302.6 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:09:02 PM UTC 24
Peak memory 442268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299866045 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2299866045 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.1481962207
Short name T355
Test name
Test status
Simulation time 15826677110 ps
CPU time 196.78 seconds
Started Oct 15 01:35:14 PM UTC 24
Finished Oct 15 01:38:34 PM UTC 24
Peak memory 323564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481962207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1481962207 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1617850046
Short name T870
Test name
Test status
Simulation time 178224078 ps
CPU time 2.74 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617850046 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1617850046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1987658727
Short name T132
Test name
Test status
Simulation time 96980862 ps
CPU time 4.18 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:41 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987658727 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.1987658727 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.3074034959
Short name T778
Test name
Test status
Simulation time 382532715 ps
CPU time 9.97 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:27 PM UTC 24
Peak memory 227512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074034959 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3074034959 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.1274822297
Short name T774
Test name
Test status
Simulation time 154530796 ps
CPU time 7.8 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:25 PM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274822297 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1274822297 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1332164768
Short name T130
Test name
Test status
Simulation time 33420432 ps
CPU time 1.15 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:18 PM UTC 24
Peak memory 226660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332164768 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1332164768 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2845545874
Short name T125
Test name
Test status
Simulation time 46038875 ps
CPU time 1.64 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2845545874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_
mem_rw_with_rand_reset.2845545874 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.2627172836
Short name T183
Test name
Test status
Simulation time 91644986 ps
CPU time 1.18 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:18 PM UTC 24
Peak memory 216380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627172836 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2627172836 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.2195063212
Short name T124
Test name
Test status
Simulation time 37745037 ps
CPU time 0.87 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:18 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195063212 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2195063212 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.394618667
Short name T140
Test name
Test status
Simulation time 241800220 ps
CPU time 1.46 seconds
Started Oct 15 01:03:13 PM UTC 24
Finished Oct 15 01:03:16 PM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394618667 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.394618667 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2194498360
Short name T767
Test name
Test status
Simulation time 37132405 ps
CPU time 0.64 seconds
Started Oct 15 01:03:13 PM UTC 24
Finished Oct 15 01:03:15 PM UTC 24
Peak memory 216468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194498360 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2194498360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1232996161
Short name T769
Test name
Test status
Simulation time 80798590 ps
CPU time 1.52 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 226664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232996161 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1232996161 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3050024684
Short name T103
Test name
Test status
Simulation time 64034782 ps
CPU time 2.19 seconds
Started Oct 15 01:03:13 PM UTC 24
Finished Oct 15 01:03:17 PM UTC 24
Peak memory 227924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050024684 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.
3050024684 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.243410747
Short name T68
Test name
Test status
Simulation time 80875186 ps
CPU time 1.49 seconds
Started Oct 15 01:03:14 PM UTC 24
Finished Oct 15 01:03:16 PM UTC 24
Peak memory 226676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243410747 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.243410747 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.1777865323
Short name T780
Test name
Test status
Simulation time 271713139 ps
CPU time 7.8 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:28 PM UTC 24
Peak memory 217196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777865323 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1777865323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.778974745
Short name T153
Test name
Test status
Simulation time 1460585973 ps
CPU time 10.11 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:28 PM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778974745 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.778974745 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.1274777346
Short name T770
Test name
Test status
Simulation time 24414272 ps
CPU time 1.59 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 216368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274777346 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1274777346 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3654466366
Short name T134
Test name
Test status
Simulation time 74224371 ps
CPU time 2.66 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:22 PM UTC 24
Peak memory 229748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3654466366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_
mem_rw_with_rand_reset.3654466366 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2726420404
Short name T182
Test name
Test status
Simulation time 28847428 ps
CPU time 1.28 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726420404 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2726420404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.338328314
Short name T141
Test name
Test status
Simulation time 45730325 ps
CPU time 1.82 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 226452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338328314 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.338328314 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.3823866800
Short name T768
Test name
Test status
Simulation time 14204645 ps
CPU time 0.99 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:18 PM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823866800 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3823866800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1553871697
Short name T150
Test name
Test status
Simulation time 224214921 ps
CPU time 2.76 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:23 PM UTC 24
Peak memory 227444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553871697 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1553871697 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2819242618
Short name T104
Test name
Test status
Simulation time 73678418 ps
CPU time 1.49 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819242618 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.2819242618 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.213408652
Short name T105
Test name
Test status
Simulation time 88619909 ps
CPU time 1.69 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213408652 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.2
13408652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.1266018701
Short name T133
Test name
Test status
Simulation time 64402400 ps
CPU time 1.91 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:19 PM UTC 24
Peak memory 228772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266018701 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1266018701 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.3208166647
Short name T122
Test name
Test status
Simulation time 464616697 ps
CPU time 3.46 seconds
Started Oct 15 01:03:16 PM UTC 24
Finished Oct 15 01:03:21 PM UTC 24
Peak memory 217196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208166647 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.3208166647 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1244937688
Short name T819
Test name
Test status
Simulation time 41132522 ps
CPU time 1.67 seconds
Started Oct 15 01:03:38 PM UTC 24
Finished Oct 15 01:03:41 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1244937688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr
_mem_rw_with_rand_reset.1244937688 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2822369406
Short name T815
Test name
Test status
Simulation time 22671818 ps
CPU time 1.32 seconds
Started Oct 15 01:03:38 PM UTC 24
Finished Oct 15 01:03:41 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822369406 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2822369406 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.785145858
Short name T167
Test name
Test status
Simulation time 33108334 ps
CPU time 1.14 seconds
Started Oct 15 01:03:38 PM UTC 24
Finished Oct 15 01:03:40 PM UTC 24
Peak memory 216436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785145858 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.785145858 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3004297827
Short name T823
Test name
Test status
Simulation time 166415657 ps
CPU time 2.3 seconds
Started Oct 15 01:03:38 PM UTC 24
Finished Oct 15 01:03:42 PM UTC 24
Peak memory 227392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004297827 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.3004297827 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.425663633
Short name T811
Test name
Test status
Simulation time 26626551 ps
CPU time 1.5 seconds
Started Oct 15 01:03:37 PM UTC 24
Finished Oct 15 01:03:40 PM UTC 24
Peak memory 226340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425663633 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.425663633 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3360634452
Short name T820
Test name
Test status
Simulation time 174003627 ps
CPU time 3.05 seconds
Started Oct 15 01:03:37 PM UTC 24
Finished Oct 15 01:03:41 PM UTC 24
Peak memory 227936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360634452 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw
.3360634452 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.4073374675
Short name T812
Test name
Test status
Simulation time 25142233 ps
CPU time 1.47 seconds
Started Oct 15 01:03:37 PM UTC 24
Finished Oct 15 01:03:40 PM UTC 24
Peak memory 226776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073374675 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.4073374675 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.1535651570
Short name T821
Test name
Test status
Simulation time 121187940 ps
CPU time 3.13 seconds
Started Oct 15 01:03:37 PM UTC 24
Finished Oct 15 01:03:42 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535651570 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1535651570 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2012149740
Short name T829
Test name
Test status
Simulation time 40991629 ps
CPU time 1.87 seconds
Started Oct 15 01:03:40 PM UTC 24
Finished Oct 15 01:03:43 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2012149740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr
_mem_rw_with_rand_reset.2012149740 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1766771480
Short name T825
Test name
Test status
Simulation time 78291550 ps
CPU time 1.11 seconds
Started Oct 15 01:03:40 PM UTC 24
Finished Oct 15 01:03:42 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766771480 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1766771480 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3318479674
Short name T824
Test name
Test status
Simulation time 18269581 ps
CPU time 1.03 seconds
Started Oct 15 01:03:40 PM UTC 24
Finished Oct 15 01:03:42 PM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318479674 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3318479674 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3957333868
Short name T827
Test name
Test status
Simulation time 74419546 ps
CPU time 1.45 seconds
Started Oct 15 01:03:40 PM UTC 24
Finished Oct 15 01:03:42 PM UTC 24
Peak memory 226660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957333868 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3957333868 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1866494224
Short name T817
Test name
Test status
Simulation time 101933197 ps
CPU time 1.28 seconds
Started Oct 15 01:03:38 PM UTC 24
Finished Oct 15 01:03:41 PM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866494224 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1866494224 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2466581410
Short name T828
Test name
Test status
Simulation time 391233430 ps
CPU time 3.15 seconds
Started Oct 15 01:03:39 PM UTC 24
Finished Oct 15 01:03:43 PM UTC 24
Peak memory 234164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466581410 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw
.2466581410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2276631280
Short name T834
Test name
Test status
Simulation time 322781671 ps
CPU time 3.09 seconds
Started Oct 15 01:03:40 PM UTC 24
Finished Oct 15 01:03:44 PM UTC 24
Peak memory 227808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276631280 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2276631280 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2817716417
Short name T833
Test name
Test status
Simulation time 119529920 ps
CPU time 3.02 seconds
Started Oct 15 01:03:40 PM UTC 24
Finished Oct 15 01:03:44 PM UTC 24
Peak memory 216928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817716417 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2817716417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.626909983
Short name T832
Test name
Test status
Simulation time 155318223 ps
CPU time 1.43 seconds
Started Oct 15 01:03:41 PM UTC 24
Finished Oct 15 01:03:44 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=626909983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_
mem_rw_with_rand_reset.626909983 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3054400838
Short name T831
Test name
Test status
Simulation time 62648855 ps
CPU time 1.06 seconds
Started Oct 15 01:03:41 PM UTC 24
Finished Oct 15 01:03:43 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054400838 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3054400838 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2917998348
Short name T830
Test name
Test status
Simulation time 130768005 ps
CPU time 1.02 seconds
Started Oct 15 01:03:41 PM UTC 24
Finished Oct 15 01:03:43 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917998348 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2917998348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.846120652
Short name T835
Test name
Test status
Simulation time 55344649 ps
CPU time 1.94 seconds
Started Oct 15 01:03:41 PM UTC 24
Finished Oct 15 01:03:44 PM UTC 24
Peak memory 226708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846120652 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.846120652 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1327196178
Short name T826
Test name
Test status
Simulation time 93104642 ps
CPU time 1.06 seconds
Started Oct 15 01:03:40 PM UTC 24
Finished Oct 15 01:03:42 PM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327196178 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.1327196178 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.138916229
Short name T840
Test name
Test status
Simulation time 1528994167 ps
CPU time 3.13 seconds
Started Oct 15 01:03:41 PM UTC 24
Finished Oct 15 01:03:45 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138916229 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.
138916229 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2879036875
Short name T844
Test name
Test status
Simulation time 509059980 ps
CPU time 3.48 seconds
Started Oct 15 01:03:41 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879036875 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2879036875 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3331287049
Short name T843
Test name
Test status
Simulation time 90466471 ps
CPU time 1.95 seconds
Started Oct 15 01:03:43 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 226376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3331287049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr
_mem_rw_with_rand_reset.3331287049 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.795489691
Short name T837
Test name
Test status
Simulation time 87948083 ps
CPU time 1.31 seconds
Started Oct 15 01:03:42 PM UTC 24
Finished Oct 15 01:03:45 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795489691 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.795489691 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.563834931
Short name T836
Test name
Test status
Simulation time 38451060 ps
CPU time 1.02 seconds
Started Oct 15 01:03:42 PM UTC 24
Finished Oct 15 01:03:45 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563834931 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.563834931 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.710678083
Short name T851
Test name
Test status
Simulation time 506799560 ps
CPU time 2.9 seconds
Started Oct 15 01:03:43 PM UTC 24
Finished Oct 15 01:03:47 PM UTC 24
Peak memory 227432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710678083 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.710678083 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3633599672
Short name T842
Test name
Test status
Simulation time 98406628 ps
CPU time 2.15 seconds
Started Oct 15 01:03:42 PM UTC 24
Finished Oct 15 01:03:45 PM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633599672 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.3633599672 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3503152405
Short name T846
Test name
Test status
Simulation time 74293421 ps
CPU time 2.58 seconds
Started Oct 15 01:03:42 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503152405 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw
.3503152405 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3149560362
Short name T841
Test name
Test status
Simulation time 245216226 ps
CPU time 2.01 seconds
Started Oct 15 01:03:42 PM UTC 24
Finished Oct 15 01:03:45 PM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149560362 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3149560362 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.68308306
Short name T858
Test name
Test status
Simulation time 129908614 ps
CPU time 2.51 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:48 PM UTC 24
Peak memory 229636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=68308306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_m
em_rw_with_rand_reset.68308306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2497795659
Short name T850
Test name
Test status
Simulation time 64175659 ps
CPU time 1.2 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 216432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497795659 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2497795659 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.554215873
Short name T847
Test name
Test status
Simulation time 21471005 ps
CPU time 0.94 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554215873 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.554215873 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2052984638
Short name T854
Test name
Test status
Simulation time 130139212 ps
CPU time 2.13 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:47 PM UTC 24
Peak memory 227512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052984638 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.2052984638 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2778964680
Short name T839
Test name
Test status
Simulation time 94649621 ps
CPU time 1.46 seconds
Started Oct 15 01:03:43 PM UTC 24
Finished Oct 15 01:03:45 PM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778964680 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.2778964680 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3360691785
Short name T845
Test name
Test status
Simulation time 67063075 ps
CPU time 1.94 seconds
Started Oct 15 01:03:43 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 226348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360691785 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw
.3360691785 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.187779320
Short name T848
Test name
Test status
Simulation time 598272226 ps
CPU time 2.36 seconds
Started Oct 15 01:03:43 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 227584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187779320 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.187779320 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.937034571
Short name T852
Test name
Test status
Simulation time 102944716 ps
CPU time 2.77 seconds
Started Oct 15 01:03:43 PM UTC 24
Finished Oct 15 01:03:47 PM UTC 24
Peak memory 234548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937034571 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.937034571 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3220041119
Short name T864
Test name
Test status
Simulation time 466295611 ps
CPU time 2.35 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:49 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3220041119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr
_mem_rw_with_rand_reset.3220041119 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2044549784
Short name T859
Test name
Test status
Simulation time 153855501 ps
CPU time 1.09 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:48 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044549784 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2044549784 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1103093319
Short name T856
Test name
Test status
Simulation time 21750945 ps
CPU time 0.95 seconds
Started Oct 15 01:03:45 PM UTC 24
Finished Oct 15 01:03:48 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103093319 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1103093319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1860798233
Short name T862
Test name
Test status
Simulation time 256606293 ps
CPU time 1.87 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:49 PM UTC 24
Peak memory 226660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860798233 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1860798233 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2039845358
Short name T849
Test name
Test status
Simulation time 13045920 ps
CPU time 0.9 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:46 PM UTC 24
Peak memory 216172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039845358 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2039845358 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3232896194
Short name T857
Test name
Test status
Simulation time 46149217 ps
CPU time 2.34 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:48 PM UTC 24
Peak memory 227796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232896194 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw
.3232896194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1345035933
Short name T853
Test name
Test status
Simulation time 49821025 ps
CPU time 1.46 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:47 PM UTC 24
Peak memory 226672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345035933 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1345035933 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4091314956
Short name T868
Test name
Test status
Simulation time 382004157 ps
CPU time 3.98 seconds
Started Oct 15 01:03:44 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 217196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091314956 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.4091314956 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1250854613
Short name T872
Test name
Test status
Simulation time 65468595 ps
CPU time 1.72 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1250854613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr
_mem_rw_with_rand_reset.1250854613 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2524882948
Short name T865
Test name
Test status
Simulation time 50799577 ps
CPU time 1.06 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:49 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524882948 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2524882948 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1334107870
Short name T860
Test name
Test status
Simulation time 33149878 ps
CPU time 0.82 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:48 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334107870 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1334107870 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1669643834
Short name T863
Test name
Test status
Simulation time 27828583 ps
CPU time 1.51 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 226660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669643834 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.1669643834 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1847644143
Short name T861
Test name
Test status
Simulation time 122720771 ps
CPU time 1.5 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:48 PM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847644143 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.1847644143 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1730580653
Short name T867
Test name
Test status
Simulation time 46636535 ps
CPU time 2.53 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:49 PM UTC 24
Peak memory 228120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730580653 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw
.1730580653 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1669506219
Short name T871
Test name
Test status
Simulation time 433484190 ps
CPU time 2.91 seconds
Started Oct 15 01:03:46 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669506219 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1669506219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.20124099
Short name T877
Test name
Test status
Simulation time 157572511 ps
CPU time 2.23 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:51 PM UTC 24
Peak memory 227512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=20124099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_m
em_rw_with_rand_reset.20124099 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.863410395
Short name T802
Test name
Test status
Simulation time 25804442 ps
CPU time 1.16 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863410395 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.863410395 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1530297613
Short name T866
Test name
Test status
Simulation time 21480607 ps
CPU time 0.9 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:49 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530297613 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1530297613 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.116168335
Short name T873
Test name
Test status
Simulation time 122571908 ps
CPU time 1.54 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 226668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116168335 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.116168335 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2145536612
Short name T869
Test name
Test status
Simulation time 87205833 ps
CPU time 1.26 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145536612 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2145536612 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1702662492
Short name T874
Test name
Test status
Simulation time 129523618 ps
CPU time 1.97 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702662492 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw
.1702662492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.1079303964
Short name T806
Test name
Test status
Simulation time 159669804 ps
CPU time 1.5 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 226672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079303964 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1079303964 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2457631063
Short name T889
Test name
Test status
Simulation time 345828014 ps
CPU time 3.98 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 217272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457631063 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2457631063 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3720215222
Short name T887
Test name
Test status
Simulation time 86720418 ps
CPU time 2.48 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3720215222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr
_mem_rw_with_rand_reset.3720215222 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3815922645
Short name T876
Test name
Test status
Simulation time 44982415 ps
CPU time 1.03 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:51 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815922645 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3815922645 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3226683578
Short name T875
Test name
Test status
Simulation time 12898091 ps
CPU time 0.76 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226683578 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3226683578 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.4095579252
Short name T894
Test name
Test status
Simulation time 40856066 ps
CPU time 2.63 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 227512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095579252 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.4095579252 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1626407292
Short name T855
Test name
Test status
Simulation time 40330107 ps
CPU time 1.22 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:50 PM UTC 24
Peak memory 226412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626407292 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.1626407292 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.540065243
Short name T879
Test name
Test status
Simulation time 467053814 ps
CPU time 2.73 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:51 PM UTC 24
Peak memory 234584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540065243 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.
540065243 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3014648197
Short name T888
Test name
Test status
Simulation time 201758816 ps
CPU time 3.72 seconds
Started Oct 15 01:03:47 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014648197 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3014648197 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1515924348
Short name T179
Test name
Test status
Simulation time 221635115 ps
CPU time 4.04 seconds
Started Oct 15 01:03:48 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515924348 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1515924348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2906195962
Short name T896
Test name
Test status
Simulation time 36294608 ps
CPU time 2.25 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2906195962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr
_mem_rw_with_rand_reset.2906195962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.3021436533
Short name T881
Test name
Test status
Simulation time 80443975 ps
CPU time 1.04 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021436533 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3021436533 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.4096154378
Short name T882
Test name
Test status
Simulation time 141302082 ps
CPU time 1.11 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096154378 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.4096154378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.4262911398
Short name T897
Test name
Test status
Simulation time 201575560 ps
CPU time 2.4 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262911398 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.4262911398 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.305507968
Short name T878
Test name
Test status
Simulation time 89103667 ps
CPU time 1.29 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:51 PM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305507968 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.305507968 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1418978639
Short name T883
Test name
Test status
Simulation time 102422253 ps
CPU time 2.31 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418978639 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw
.1418978639 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3723914236
Short name T890
Test name
Test status
Simulation time 45022145 ps
CPU time 2.73 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 227768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723914236 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3723914236 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1082782997
Short name T177
Test name
Test status
Simulation time 159138571 ps
CPU time 2.44 seconds
Started Oct 15 01:03:49 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082782997 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1082782997 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.612478479
Short name T784
Test name
Test status
Simulation time 507328424 ps
CPU time 7.25 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:30 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612478479 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.612478479 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1960050796
Short name T818
Test name
Test status
Simulation time 4596290598 ps
CPU time 18.33 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:41 PM UTC 24
Peak memory 217388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960050796 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1960050796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.598161054
Short name T772
Test name
Test status
Simulation time 57482303 ps
CPU time 1.37 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:24 PM UTC 24
Peak memory 216392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598161054 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.598161054 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2468551005
Short name T135
Test name
Test status
Simulation time 464101414 ps
CPU time 2.86 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:25 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2468551005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_
mem_rw_with_rand_reset.2468551005 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.2209007517
Short name T151
Test name
Test status
Simulation time 21911437 ps
CPU time 1.06 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:23 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209007517 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2209007517 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3581333979
Short name T160
Test name
Test status
Simulation time 18635642 ps
CPU time 0.94 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:23 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581333979 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3581333979 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.395514605
Short name T771
Test name
Test status
Simulation time 36875653 ps
CPU time 0.79 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:21 PM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395514605 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.395514605 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2855582287
Short name T152
Test name
Test status
Simulation time 257345085 ps
CPU time 2.23 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:25 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855582287 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.2855582287 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2859717139
Short name T113
Test name
Test status
Simulation time 40769297 ps
CPU time 1.36 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:21 PM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859717139 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.2859717139 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2573683551
Short name T114
Test name
Test status
Simulation time 56549645 ps
CPU time 2.39 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:22 PM UTC 24
Peak memory 227908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573683551 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.
2573683551 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.694371122
Short name T129
Test name
Test status
Simulation time 262928925 ps
CPU time 4.11 seconds
Started Oct 15 01:03:19 PM UTC 24
Finished Oct 15 01:03:24 PM UTC 24
Peak memory 227760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694371122 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.694371122 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2429280575
Short name T880
Test name
Test status
Simulation time 38305653 ps
CPU time 0.77 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429280575 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2429280575 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.259189643
Short name T884
Test name
Test status
Simulation time 15184300 ps
CPU time 1.02 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259189643 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.259189643 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3817057028
Short name T886
Test name
Test status
Simulation time 18402491 ps
CPU time 1.08 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817057028 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3817057028 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1234409283
Short name T885
Test name
Test status
Simulation time 31034753 ps
CPU time 0.91 seconds
Started Oct 15 01:03:50 PM UTC 24
Finished Oct 15 01:03:52 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234409283 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1234409283 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.359951020
Short name T893
Test name
Test status
Simulation time 134412529 ps
CPU time 0.93 seconds
Started Oct 15 01:03:51 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 216436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359951020 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.359951020 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2219502227
Short name T891
Test name
Test status
Simulation time 100961470 ps
CPU time 0.93 seconds
Started Oct 15 01:03:51 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 216432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219502227 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2219502227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2784309901
Short name T895
Test name
Test status
Simulation time 10635017 ps
CPU time 1.02 seconds
Started Oct 15 01:03:51 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784309901 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2784309901 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3911589477
Short name T892
Test name
Test status
Simulation time 46781545 ps
CPU time 0.88 seconds
Started Oct 15 01:03:51 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911589477 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3911589477 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3868057984
Short name T902
Test name
Test status
Simulation time 66494629 ps
CPU time 1.11 seconds
Started Oct 15 01:03:51 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868057984 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3868057984 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.1265609855
Short name T901
Test name
Test status
Simulation time 24917696 ps
CPU time 1.05 seconds
Started Oct 15 01:03:51 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265609855 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1265609855 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2481987721
Short name T789
Test name
Test status
Simulation time 147850085 ps
CPU time 7.33 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:32 PM UTC 24
Peak memory 217388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481987721 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2481987721 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.305901647
Short name T838
Test name
Test status
Simulation time 1871857403 ps
CPU time 19.56 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:45 PM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305901647 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.305901647 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.3434345028
Short name T775
Test name
Test status
Simulation time 67835145 ps
CPU time 1.28 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:26 PM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434345028 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3434345028 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3065626750
Short name T777
Test name
Test status
Simulation time 134154906 ps
CPU time 1.57 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:27 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3065626750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_
mem_rw_with_rand_reset.3065626750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.1006147570
Short name T776
Test name
Test status
Simulation time 66778175 ps
CPU time 1.33 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:26 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006147570 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1006147570 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.4043966849
Short name T155
Test name
Test status
Simulation time 20175615 ps
CPU time 1.12 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:26 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043966849 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.4043966849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.2071450740
Short name T143
Test name
Test status
Simulation time 110064793 ps
CPU time 1.83 seconds
Started Oct 15 01:03:22 PM UTC 24
Finished Oct 15 01:03:25 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071450740 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.2071450740 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3757778744
Short name T773
Test name
Test status
Simulation time 15041525 ps
CPU time 1.08 seconds
Started Oct 15 01:03:22 PM UTC 24
Finished Oct 15 01:03:24 PM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757778744 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3757778744 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2933651688
Short name T779
Test name
Test status
Simulation time 40400646 ps
CPU time 2.51 seconds
Started Oct 15 01:03:24 PM UTC 24
Finished Oct 15 01:03:28 PM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933651688 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2933651688 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.460438583
Short name T180
Test name
Test status
Simulation time 103569345 ps
CPU time 3.11 seconds
Started Oct 15 01:03:21 PM UTC 24
Finished Oct 15 01:03:26 PM UTC 24
Peak memory 227952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460438583 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.4
60438583 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.481829336
Short name T126
Test name
Test status
Simulation time 185114521 ps
CPU time 3.04 seconds
Started Oct 15 01:03:22 PM UTC 24
Finished Oct 15 01:03:26 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481829336 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.481829336 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2278939318
Short name T904
Test name
Test status
Simulation time 41284316 ps
CPU time 0.96 seconds
Started Oct 15 01:03:52 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278939318 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2278939318 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1931557231
Short name T900
Test name
Test status
Simulation time 45261925 ps
CPU time 0.89 seconds
Started Oct 15 01:03:52 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931557231 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1931557231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.79980357
Short name T898
Test name
Test status
Simulation time 45257441 ps
CPU time 0.86 seconds
Started Oct 15 01:03:52 PM UTC 24
Finished Oct 15 01:03:53 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79980357 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.79980357 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.1796275217
Short name T905
Test name
Test status
Simulation time 15278365 ps
CPU time 0.87 seconds
Started Oct 15 01:03:52 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796275217 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1796275217 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.308825270
Short name T899
Test name
Test status
Simulation time 47793592 ps
CPU time 0.76 seconds
Started Oct 15 01:03:52 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308825270 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.308825270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3530253783
Short name T903
Test name
Test status
Simulation time 44668768 ps
CPU time 0.85 seconds
Started Oct 15 01:03:52 PM UTC 24
Finished Oct 15 01:03:54 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530253783 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3530253783 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2161547265
Short name T906
Test name
Test status
Simulation time 13372358 ps
CPU time 0.8 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161547265 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2161547265 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3947483598
Short name T907
Test name
Test status
Simulation time 46052640 ps
CPU time 0.94 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947483598 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3947483598 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3636686501
Short name T908
Test name
Test status
Simulation time 36131843 ps
CPU time 0.93 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636686501 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3636686501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2785312094
Short name T912
Test name
Test status
Simulation time 14701554 ps
CPU time 1.01 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785312094 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2785312094 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.4139583692
Short name T181
Test name
Test status
Simulation time 390622070 ps
CPU time 8.89 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:37 PM UTC 24
Peak memory 227612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139583692 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.4139583692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.105361601
Short name T814
Test name
Test status
Simulation time 1511271752 ps
CPU time 11.97 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:40 PM UTC 24
Peak memory 217200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105361601 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.105361601 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.531397004
Short name T783
Test name
Test status
Simulation time 36792528 ps
CPU time 1.76 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:30 PM UTC 24
Peak memory 226648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531397004 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.531397004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3705603292
Short name T786
Test name
Test status
Simulation time 82104455 ps
CPU time 2.27 seconds
Started Oct 15 01:03:28 PM UTC 24
Finished Oct 15 01:03:31 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3705603292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_
mem_rw_with_rand_reset.3705603292 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.623251753
Short name T782
Test name
Test status
Simulation time 422199747 ps
CPU time 1.34 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:29 PM UTC 24
Peak memory 216436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623251753 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.623251753 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.3285602601
Short name T144
Test name
Test status
Simulation time 34441686 ps
CPU time 1.92 seconds
Started Oct 15 01:03:26 PM UTC 24
Finished Oct 15 01:03:29 PM UTC 24
Peak memory 226460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285602601 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.3285602601 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3131777951
Short name T781
Test name
Test status
Simulation time 11557701 ps
CPU time 0.98 seconds
Started Oct 15 01:03:26 PM UTC 24
Finished Oct 15 01:03:28 PM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131777951 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3131777951 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3421578730
Short name T785
Test name
Test status
Simulation time 88997716 ps
CPU time 2.58 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:31 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421578730 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3421578730 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4072338166
Short name T154
Test name
Test status
Simulation time 108728788 ps
CPU time 1.26 seconds
Started Oct 15 01:03:26 PM UTC 24
Finished Oct 15 01:03:29 PM UTC 24
Peak memory 226408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072338166 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.4072338166 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2297929460
Short name T107
Test name
Test status
Simulation time 126610785 ps
CPU time 2.21 seconds
Started Oct 15 01:03:26 PM UTC 24
Finished Oct 15 01:03:30 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297929460 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.
2297929460 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3730384989
Short name T127
Test name
Test status
Simulation time 107896389 ps
CPU time 2.84 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:30 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730384989 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3730384989 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1435456736
Short name T172
Test name
Test status
Simulation time 344374120 ps
CPU time 4.19 seconds
Started Oct 15 01:03:27 PM UTC 24
Finished Oct 15 01:03:32 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435456736 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.1435456736 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.46007967
Short name T909
Test name
Test status
Simulation time 40548144 ps
CPU time 0.92 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46007967 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.46007967 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.2710769759
Short name T911
Test name
Test status
Simulation time 13202607 ps
CPU time 0.91 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710769759 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2710769759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2020135620
Short name T910
Test name
Test status
Simulation time 13058169 ps
CPU time 0.94 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020135620 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2020135620 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.969750998
Short name T914
Test name
Test status
Simulation time 44547615 ps
CPU time 1 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969750998 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.969750998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.975548923
Short name T913
Test name
Test status
Simulation time 25684499 ps
CPU time 0.9 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975548923 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.975548923 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3554579397
Short name T917
Test name
Test status
Simulation time 43346105 ps
CPU time 0.9 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554579397 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3554579397 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1733182366
Short name T915
Test name
Test status
Simulation time 74723137 ps
CPU time 0.85 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733182366 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1733182366 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.810471565
Short name T916
Test name
Test status
Simulation time 70512790 ps
CPU time 0.9 seconds
Started Oct 15 01:03:53 PM UTC 24
Finished Oct 15 01:03:55 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810471565 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.810471565 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.431507480
Short name T918
Test name
Test status
Simulation time 25050719 ps
CPU time 1.01 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:03:56 PM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431507480 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.431507480 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1023246600
Short name T919
Test name
Test status
Simulation time 24815232 ps
CPU time 1.05 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:03:56 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023246600 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1023246600 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1027693909
Short name T794
Test name
Test status
Simulation time 82544787 ps
CPU time 2.33 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:34 PM UTC 24
Peak memory 229748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1027693909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_
mem_rw_with_rand_reset.1027693909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.518475731
Short name T787
Test name
Test status
Simulation time 50531140 ps
CPU time 1.36 seconds
Started Oct 15 01:03:29 PM UTC 24
Finished Oct 15 01:03:32 PM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518475731 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.518475731 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2261858410
Short name T165
Test name
Test status
Simulation time 30039265 ps
CPU time 0.9 seconds
Started Oct 15 01:03:29 PM UTC 24
Finished Oct 15 01:03:31 PM UTC 24
Peak memory 216532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261858410 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2261858410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3793407879
Short name T788
Test name
Test status
Simulation time 66391747 ps
CPU time 1.53 seconds
Started Oct 15 01:03:29 PM UTC 24
Finished Oct 15 01:03:32 PM UTC 24
Peak memory 226716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793407879 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.3793407879 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1255482535
Short name T790
Test name
Test status
Simulation time 155285956 ps
CPU time 2.69 seconds
Started Oct 15 01:03:29 PM UTC 24
Finished Oct 15 01:03:33 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255482535 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1255482535 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.2984473061
Short name T173
Test name
Test status
Simulation time 408044806 ps
CPU time 2.73 seconds
Started Oct 15 01:03:29 PM UTC 24
Finished Oct 15 01:03:34 PM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984473061 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.2984473061 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3870858871
Short name T796
Test name
Test status
Simulation time 252645397 ps
CPU time 2.97 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:35 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3870858871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_
mem_rw_with_rand_reset.3870858871 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3372784618
Short name T791
Test name
Test status
Simulation time 305215200 ps
CPU time 1.39 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:33 PM UTC 24
Peak memory 216424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372784618 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3372784618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.425953087
Short name T161
Test name
Test status
Simulation time 19890665 ps
CPU time 1 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:33 PM UTC 24
Peak memory 216540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425953087 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.425953087 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3489903448
Short name T792
Test name
Test status
Simulation time 27117830 ps
CPU time 1.79 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:34 PM UTC 24
Peak memory 226740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489903448 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.3489903448 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.564387159
Short name T110
Test name
Test status
Simulation time 131164093 ps
CPU time 2.48 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:34 PM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564387159 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.564387159 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.697762821
Short name T793
Test name
Test status
Simulation time 570897277 ps
CPU time 2.04 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:34 PM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697762821 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.6
97762821 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.3625853752
Short name T795
Test name
Test status
Simulation time 394276997 ps
CPU time 2.95 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:35 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625853752 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3625853752 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.644213885
Short name T797
Test name
Test status
Simulation time 802943876 ps
CPU time 3.52 seconds
Started Oct 15 01:03:31 PM UTC 24
Finished Oct 15 01:03:35 PM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644213885 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.644213885 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.234903572
Short name T803
Test name
Test status
Simulation time 86843716 ps
CPU time 3.02 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:38 PM UTC 24
Peak memory 229552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=234903572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_m
em_rw_with_rand_reset.234903572 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3686523814
Short name T798
Test name
Test status
Simulation time 66293745 ps
CPU time 1.1 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:36 PM UTC 24
Peak memory 226396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686523814 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3686523814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.167231524
Short name T162
Test name
Test status
Simulation time 16678406 ps
CPU time 1.12 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:35 PM UTC 24
Peak memory 216480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167231524 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.167231524 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1691750682
Short name T800
Test name
Test status
Simulation time 875736551 ps
CPU time 1.85 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:36 PM UTC 24
Peak memory 226740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691750682 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.1691750682 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.26705109
Short name T799
Test name
Test status
Simulation time 47056489 ps
CPU time 1.8 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:36 PM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26705109 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.26705109 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3148864976
Short name T801
Test name
Test status
Simulation time 89389900 ps
CPU time 2.47 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:37 PM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148864976 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.
3148864976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3218562138
Short name T128
Test name
Test status
Simulation time 164249687 ps
CPU time 2.94 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:37 PM UTC 24
Peak memory 234388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218562138 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3218562138 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1043762666
Short name T178
Test name
Test status
Simulation time 769545841 ps
CPU time 5.23 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:40 PM UTC 24
Peak memory 227344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043762666 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1043762666 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1360391720
Short name T809
Test name
Test status
Simulation time 255350586 ps
CPU time 2.29 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:39 PM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1360391720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_
mem_rw_with_rand_reset.1360391720 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3121014249
Short name T804
Test name
Test status
Simulation time 22585056 ps
CPU time 1.34 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:38 PM UTC 24
Peak memory 216216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121014249 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3121014249 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1098878289
Short name T164
Test name
Test status
Simulation time 33950544 ps
CPU time 0.88 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:38 PM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098878289 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1098878289 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.884589919
Short name T805
Test name
Test status
Simulation time 175726404 ps
CPU time 1.66 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:39 PM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884589919 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.884589919 +enable_m
asking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1905139211
Short name T112
Test name
Test status
Simulation time 86869972 ps
CPU time 1.51 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:36 PM UTC 24
Peak memory 226284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905139211 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1905139211 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2817394320
Short name T184
Test name
Test status
Simulation time 458077421 ps
CPU time 3.28 seconds
Started Oct 15 01:03:33 PM UTC 24
Finished Oct 15 01:03:38 PM UTC 24
Peak memory 234548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817394320 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.
2817394320 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2278898909
Short name T822
Test name
Test status
Simulation time 1476262515 ps
CPU time 4.71 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:42 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278898909 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2278898909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1980847291
Short name T816
Test name
Test status
Simulation time 78934111 ps
CPU time 2.66 seconds
Started Oct 15 01:03:37 PM UTC 24
Finished Oct 15 01:03:41 PM UTC 24
Peak memory 227292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1980847291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_
mem_rw_with_rand_reset.1980847291 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2959709154
Short name T810
Test name
Test status
Simulation time 17266419 ps
CPU time 1.49 seconds
Started Oct 15 01:03:37 PM UTC 24
Finished Oct 15 01:03:40 PM UTC 24
Peak memory 216372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959709154 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2959709154 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3612803381
Short name T166
Test name
Test status
Simulation time 18254903 ps
CPU time 1.15 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:38 PM UTC 24
Peak memory 216476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612803381 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3612803381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2146705979
Short name T813
Test name
Test status
Simulation time 123873877 ps
CPU time 1.67 seconds
Started Oct 15 01:03:37 PM UTC 24
Finished Oct 15 01:03:40 PM UTC 24
Peak memory 226428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146705979 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.2146705979 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1459479943
Short name T111
Test name
Test status
Simulation time 39339893 ps
CPU time 1.66 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:39 PM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459479943 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.1459479943 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.502426938
Short name T808
Test name
Test status
Simulation time 294346341 ps
CPU time 2.15 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:39 PM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502426938 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.5
02426938 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.132910810
Short name T807
Test name
Test status
Simulation time 268030389 ps
CPU time 1.76 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:39 PM UTC 24
Peak memory 226660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132910810 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.132910810 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2907931407
Short name T174
Test name
Test status
Simulation time 378739391 ps
CPU time 6.66 seconds
Started Oct 15 01:03:36 PM UTC 24
Finished Oct 15 01:03:44 PM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907931407 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.2907931407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.2805656039
Short name T136
Test name
Test status
Simulation time 10258267999 ps
CPU time 163.56 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:06:41 PM UTC 24
Peak memory 372636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805656039 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2805656039 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.2371709049
Short name T116
Test name
Test status
Simulation time 8481431840 ps
CPU time 187.5 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:07:06 PM UTC 24
Peak memory 380756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371709049 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.2371709049 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.2601686610
Short name T145
Test name
Test status
Simulation time 47950812977 ps
CPU time 379.5 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:10:19 PM UTC 24
Peak memory 252028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601686610 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2601686610 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3807931863
Short name T17
Test name
Test status
Simulation time 800918891 ps
CPU time 17 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:04:14 PM UTC 24
Peak memory 235184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807931863 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3807931863 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.259100281
Short name T12
Test name
Test status
Simulation time 84995712 ps
CPU time 6.89 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:04:04 PM UTC 24
Peak memory 228664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259100281 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.259100281 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.4055892609
Short name T20
Test name
Test status
Simulation time 48144750193 ps
CPU time 25.6 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:04:23 PM UTC 24
Peak memory 231152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055892609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.4055892609 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.701390650
Short name T32
Test name
Test status
Simulation time 9668254762 ps
CPU time 333.47 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:09:34 PM UTC 24
Peak memory 385004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701390650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.701390650 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.2387979204
Short name T372
Test name
Test status
Simulation time 95295302180 ps
CPU time 2220.8 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:41:19 PM UTC 24
Peak memory 1639680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387979204 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.2387979204 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.3891585069
Short name T41
Test name
Test status
Simulation time 7275584001 ps
CPU time 143.07 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:06:22 PM UTC 24
Peak memory 368936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891585069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3891585069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.1155899880
Short name T137
Test name
Test status
Simulation time 33086960354 ps
CPU time 171.89 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:06:49 PM UTC 24
Peak memory 387048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155899880 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1155899880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.2822608492
Short name T51
Test name
Test status
Simulation time 743696093 ps
CPU time 19.26 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:04:15 PM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822608492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2822608492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.2088344785
Short name T325
Test name
Test status
Simulation time 995271480032 ps
CPU time 1743.9 seconds
Started Oct 15 01:03:56 PM UTC 24
Finished Oct 15 01:33:19 PM UTC 24
Peak memory 1167624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088344785 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2088344785 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.830200967
Short name T1
Test name
Test status
Simulation time 275417656 ps
CPU time 2.22 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:03:58 PM UTC 24
Peak memory 231092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830200967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.830200967 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.1121870387
Short name T2
Test name
Test status
Simulation time 597488920 ps
CPU time 2.23 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:03:58 PM UTC 24
Peak memory 230972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121870387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1121870387 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.241375521
Short name T342
Test name
Test status
Simulation time 56916028529 ps
CPU time 1907.6 seconds
Started Oct 15 01:03:54 PM UTC 24
Finished Oct 15 01:36:03 PM UTC 24
Peak memory 2922364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241375521 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.241375521 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.4157332578
Short name T53
Test name
Test status
Simulation time 4776324421 ps
CPU time 25.51 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:04:21 PM UTC 24
Peak memory 239472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157332578 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.4157332578
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3585641108
Short name T15
Test name
Test status
Simulation time 1104285002 ps
CPU time 16.18 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:04:12 PM UTC 24
Peak memory 228812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585641108 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3585641108
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.1860644908
Short name T138
Test name
Test status
Simulation time 34151670430 ps
CPU time 188.2 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:07:06 PM UTC 24
Peak memory 442292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860644908 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1860644
908 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.1578069888
Short name T337
Test name
Test status
Simulation time 69931869929 ps
CPU time 1840.35 seconds
Started Oct 15 01:03:55 PM UTC 24
Finished Oct 15 01:34:56 PM UTC 24
Peak memory 1138452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578069888 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1578069
888 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.100248618
Short name T63
Test name
Test status
Simulation time 15482366 ps
CPU time 1.14 seconds
Started Oct 15 01:04:36 PM UTC 24
Finished Oct 15 01:04:39 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100248618 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.100248618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.3487902435
Short name T34
Test name
Test status
Simulation time 2768169261 ps
CPU time 58.08 seconds
Started Oct 15 01:04:12 PM UTC 24
Finished Oct 15 01:05:12 PM UTC 24
Peak memory 280476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487902435 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3487902435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.911416528
Short name T115
Test name
Test status
Simulation time 28510989849 ps
CPU time 185.15 seconds
Started Oct 15 01:04:13 PM UTC 24
Finished Oct 15 01:07:21 PM UTC 24
Peak memory 350104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911416528 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.911416528 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.2657441848
Short name T148
Test name
Test status
Simulation time 235833349767 ps
CPU time 563.53 seconds
Started Oct 15 01:03:59 PM UTC 24
Finished Oct 15 01:13:30 PM UTC 24
Peak memory 257952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657441848 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2657441848 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.325262806
Short name T99
Test name
Test status
Simulation time 943072636 ps
CPU time 32.75 seconds
Started Oct 15 01:04:21 PM UTC 24
Finished Oct 15 01:04:56 PM UTC 24
Peak memory 235208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325262806 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.325262806 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.52798127
Short name T96
Test name
Test status
Simulation time 1205696498 ps
CPU time 14.69 seconds
Started Oct 15 01:04:22 PM UTC 24
Finished Oct 15 01:04:38 PM UTC 24
Peak memory 235156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52798127 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.52798127 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.1614549046
Short name T55
Test name
Test status
Simulation time 3746367665 ps
CPU time 27.17 seconds
Started Oct 15 01:04:24 PM UTC 24
Finished Oct 15 01:04:53 PM UTC 24
Peak memory 231044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614549046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1614549046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.2463916881
Short name T22
Test name
Test status
Simulation time 6073396119 ps
CPU time 52.64 seconds
Started Oct 15 01:04:14 PM UTC 24
Finished Oct 15 01:05:08 PM UTC 24
Peak memory 251876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463916881 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2463916881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.1841923804
Short name T33
Test name
Test status
Simulation time 6948777011 ps
CPU time 261.22 seconds
Started Oct 15 01:04:15 PM UTC 24
Finished Oct 15 01:08:41 PM UTC 24
Peak memory 430136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841923804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1841923804 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.2885716790
Short name T45
Test name
Test status
Simulation time 2088824915 ps
CPU time 10.29 seconds
Started Oct 15 01:04:16 PM UTC 24
Finished Oct 15 01:04:28 PM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885716790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2885716790 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.2563911399
Short name T6
Test name
Test status
Simulation time 100246438 ps
CPU time 1.9 seconds
Started Oct 15 01:04:29 PM UTC 24
Finished Oct 15 01:04:33 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563911399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2563911399 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.2115068599
Short name T492
Test name
Test status
Simulation time 87298023382 ps
CPU time 3016.84 seconds
Started Oct 15 01:03:58 PM UTC 24
Finished Oct 15 01:54:56 PM UTC 24
Peak memory 3542984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115068599 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.2115068599 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.3129129757
Short name T40
Test name
Test status
Simulation time 3918947439 ps
CPU time 76.58 seconds
Started Oct 15 01:04:15 PM UTC 24
Finished Oct 15 01:05:34 PM UTC 24
Peak memory 307496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129129757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3129129757 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.1618734176
Short name T7
Test name
Test status
Simulation time 5956459770 ps
CPU time 25.06 seconds
Started Oct 15 01:04:34 PM UTC 24
Finished Oct 15 01:05:01 PM UTC 24
Peak memory 267716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618734176 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1618734176 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.1662916053
Short name T97
Test name
Test status
Simulation time 1201136195 ps
CPU time 30.67 seconds
Started Oct 15 01:03:58 PM UTC 24
Finished Oct 15 01:04:40 PM UTC 24
Peak memory 239468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662916053 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1662916053 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload_invalid.2059839606
Short name T13
Test name
Test status
Simulation time 697134858 ps
CPU time 3.57 seconds
Started Oct 15 01:03:59 PM UTC 24
Finished Oct 15 01:04:04 PM UTC 24
Peak memory 233408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059839606 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload_invalid.2059839606 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.4261220185
Short name T16
Test name
Test status
Simulation time 34029210 ps
CPU time 3.32 seconds
Started Oct 15 01:04:08 PM UTC 24
Finished Oct 15 01:04:13 PM UTC 24
Peak memory 231156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261220185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.4261220185 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.862426190
Short name T18
Test name
Test status
Simulation time 101539989 ps
CPU time 2.83 seconds
Started Oct 15 01:04:11 PM UTC 24
Finished Oct 15 01:04:15 PM UTC 24
Peak memory 230972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862426190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.862426190 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.3872486258
Short name T185
Test name
Test status
Simulation time 660664025 ps
CPU time 41.86 seconds
Started Oct 15 01:04:00 PM UTC 24
Finished Oct 15 01:04:43 PM UTC 24
Peak memory 232976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872486258 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3872486258
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.3008656249
Short name T413
Test name
Test status
Simulation time 88897850260 ps
CPU time 2510.12 seconds
Started Oct 15 01:04:00 PM UTC 24
Finished Oct 15 01:46:19 PM UTC 24
Peak memory 3045276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008656249 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3008656249
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.398257749
Short name T276
Test name
Test status
Simulation time 13095577063 ps
CPU time 1238.11 seconds
Started Oct 15 01:04:00 PM UTC 24
Finished Oct 15 01:24:52 PM UTC 24
Peak memory 919452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398257749 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.398257749 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.2738906209
Short name T52
Test name
Test status
Simulation time 274406939 ps
CPU time 14.6 seconds
Started Oct 15 01:04:01 PM UTC 24
Finished Oct 15 01:04:20 PM UTC 24
Peak memory 229028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738906209 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2738906209
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.31390230
Short name T480
Test name
Test status
Simulation time 325184067577 ps
CPU time 2961.67 seconds
Started Oct 15 01:04:05 PM UTC 24
Finished Oct 15 01:53:59 PM UTC 24
Peak memory 3655452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31390230 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.31390230
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.2971837878
Short name T412
Test name
Test status
Simulation time 305784510946 ps
CPU time 2503.8 seconds
Started Oct 15 01:04:05 PM UTC 24
Finished Oct 15 01:46:17 PM UTC 24
Peak memory 3047208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971837878 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2971837
878 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.3878937987
Short name T273
Test name
Test status
Simulation time 13278440 ps
CPU time 1.22 seconds
Started Oct 15 01:24:32 PM UTC 24
Finished Oct 15 01:24:34 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878937987 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3878937987 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.3077846585
Short name T290
Test name
Test status
Simulation time 8760708768 ps
CPU time 214.56 seconds
Started Oct 15 01:23:03 PM UTC 24
Finished Oct 15 01:26:41 PM UTC 24
Peak memory 313212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077846585 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.3077846585 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.4146947789
Short name T350
Test name
Test status
Simulation time 26550880334 ps
CPU time 899.54 seconds
Started Oct 15 01:22:26 PM UTC 24
Finished Oct 15 01:37:36 PM UTC 24
Peak memory 266172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146947789 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.4146947789 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1918845019
Short name T270
Test name
Test status
Simulation time 748678469 ps
CPU time 16.71 seconds
Started Oct 15 01:23:41 PM UTC 24
Finished Oct 15 01:23:59 PM UTC 24
Peak memory 235120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918845019 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1918845019 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.571597725
Short name T274
Test name
Test status
Simulation time 1054213490 ps
CPU time 35.5 seconds
Started Oct 15 01:24:00 PM UTC 24
Finished Oct 15 01:24:37 PM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571597725 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.571597725 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.1541888532
Short name T293
Test name
Test status
Simulation time 7052735433 ps
CPU time 265.35 seconds
Started Oct 15 01:23:08 PM UTC 24
Finished Oct 15 01:27:37 PM UTC 24
Peak memory 327612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541888532 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1541888532 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.2928855985
Short name T275
Test name
Test status
Simulation time 2538238021 ps
CPU time 76.49 seconds
Started Oct 15 01:23:26 PM UTC 24
Finished Oct 15 01:24:44 PM UTC 24
Peak memory 311276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928855985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2928855985 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.2267568856
Short name T269
Test name
Test status
Simulation time 4269002089 ps
CPU time 6.31 seconds
Started Oct 15 01:23:33 PM UTC 24
Finished Oct 15 01:23:41 PM UTC 24
Peak memory 230832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267568856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2267568856 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.1103559080
Short name T628
Test name
Test status
Simulation time 226074311922 ps
CPU time 3014.56 seconds
Started Oct 15 01:21:57 PM UTC 24
Finished Oct 15 02:12:44 PM UTC 24
Peak memory 3600580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103559080 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.1103559080 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.3741246012
Short name T268
Test name
Test status
Simulation time 4763583349 ps
CPU time 89.55 seconds
Started Oct 15 01:22:01 PM UTC 24
Finished Oct 15 01:23:32 PM UTC 24
Peak memory 292788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741246012 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3741246012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload_invalid.3834448980
Short name T101
Test name
Test status
Simulation time 775633313 ps
CPU time 6.55 seconds
Started Oct 15 01:22:16 PM UTC 24
Finished Oct 15 01:22:24 PM UTC 24
Peak memory 233464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834448980 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload_invalid.3834448980 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.1454108305
Short name T263
Test name
Test status
Simulation time 975971060 ps
CPU time 8.32 seconds
Started Oct 15 01:21:47 PM UTC 24
Finished Oct 15 01:21:56 PM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454108305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1454108305 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.3069864124
Short name T383
Test name
Test status
Simulation time 35640710535 ps
CPU time 1153.81 seconds
Started Oct 15 01:24:15 PM UTC 24
Finished Oct 15 01:43:41 PM UTC 24
Peak memory 477484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069864124 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3069864124 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.1131075684
Short name T287
Test name
Test status
Simulation time 14430846 ps
CPU time 1.23 seconds
Started Oct 15 01:25:47 PM UTC 24
Finished Oct 15 01:25:49 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131075684 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1131075684 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.2193122074
Short name T292
Test name
Test status
Simulation time 16319870670 ps
CPU time 129.09 seconds
Started Oct 15 01:25:18 PM UTC 24
Finished Oct 15 01:27:30 PM UTC 24
Peak memory 315312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193122074 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2193122074 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.1303796563
Short name T188
Test name
Test status
Simulation time 10524237215 ps
CPU time 506.36 seconds
Started Oct 15 01:24:56 PM UTC 24
Finished Oct 15 01:33:29 PM UTC 24
Peak memory 245664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303796563 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.1303796563 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2926925773
Short name T289
Test name
Test status
Simulation time 6388512327 ps
CPU time 47.99 seconds
Started Oct 15 01:25:30 PM UTC 24
Finished Oct 15 01:26:19 PM UTC 24
Peak memory 234960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926925773 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2926925773 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.2866369579
Short name T284
Test name
Test status
Simulation time 443260088 ps
CPU time 9.07 seconds
Started Oct 15 01:25:35 PM UTC 24
Finished Oct 15 01:25:45 PM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866369579 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2866369579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.4283829337
Short name T282
Test name
Test status
Simulation time 313171765 ps
CPU time 9.18 seconds
Started Oct 15 01:25:23 PM UTC 24
Finished Oct 15 01:25:34 PM UTC 24
Peak memory 235436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283829337 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.4283829337 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.433171348
Short name T305
Test name
Test status
Simulation time 12175837022 ps
CPU time 318.94 seconds
Started Oct 15 01:25:25 PM UTC 24
Finished Oct 15 01:30:49 PM UTC 24
Peak memory 565180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433171348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.433171348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.185503391
Short name T285
Test name
Test status
Simulation time 33711342 ps
CPU time 2.44 seconds
Started Oct 15 01:25:42 PM UTC 24
Finished Oct 15 01:25:46 PM UTC 24
Peak memory 230748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185503391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.185503391 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.3671995700
Short name T446
Test name
Test status
Simulation time 132273505452 ps
CPU time 1527.65 seconds
Started Oct 15 01:24:38 PM UTC 24
Finished Oct 15 01:50:22 PM UTC 24
Peak memory 1199992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671995700 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.3671995700 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.1093910032
Short name T281
Test name
Test status
Simulation time 1905906350 ps
CPU time 38.53 seconds
Started Oct 15 01:24:45 PM UTC 24
Finished Oct 15 01:25:25 PM UTC 24
Peak memory 251824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093910032 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1093910032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload_invalid.3086175380
Short name T277
Test name
Test status
Simulation time 22569903 ps
CPU time 1.72 seconds
Started Oct 15 01:24:53 PM UTC 24
Finished Oct 15 01:24:56 PM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086175380 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload_invalid.3086175380 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.2875931492
Short name T280
Test name
Test status
Simulation time 7705098818 ps
CPU time 47.5 seconds
Started Oct 15 01:24:35 PM UTC 24
Finished Oct 15 01:25:24 PM UTC 24
Peak memory 230956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875931492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2875931492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.9070759
Short name T300
Test name
Test status
Simulation time 100297886 ps
CPU time 1.22 seconds
Started Oct 15 01:28:33 PM UTC 24
Finished Oct 15 01:28:36 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9070759 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.9070759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.4138985443
Short name T316
Test name
Test status
Simulation time 47284407106 ps
CPU time 349 seconds
Started Oct 15 01:26:21 PM UTC 24
Finished Oct 15 01:32:15 PM UTC 24
Peak memory 438196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138985443 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.4138985443 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.31981957
Short name T169
Test name
Test status
Simulation time 6356672447 ps
CPU time 390.51 seconds
Started Oct 15 01:26:20 PM UTC 24
Finished Oct 15 01:32:56 PM UTC 24
Peak memory 245732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31981957 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.31981957 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.3309689613
Short name T295
Test name
Test status
Simulation time 583238334 ps
CPU time 29.34 seconds
Started Oct 15 01:27:38 PM UTC 24
Finished Oct 15 01:28:09 PM UTC 24
Peak memory 232868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309689613 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3309689613 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3263949244
Short name T298
Test name
Test status
Simulation time 6980031559 ps
CPU time 54.13 seconds
Started Oct 15 01:27:39 PM UTC 24
Finished Oct 15 01:28:35 PM UTC 24
Peak memory 245220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263949244 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3263949244 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2304475114
Short name T302
Test name
Test status
Simulation time 4788735406 ps
CPU time 163.64 seconds
Started Oct 15 01:26:42 PM UTC 24
Finished Oct 15 01:29:28 PM UTC 24
Peak memory 288696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304475114 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2304475114 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.1893852436
Short name T297
Test name
Test status
Simulation time 3569260756 ps
CPU time 86.66 seconds
Started Oct 15 01:27:04 PM UTC 24
Finished Oct 15 01:28:32 PM UTC 24
Peak memory 278636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893852436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1893852436 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.3322914427
Short name T294
Test name
Test status
Simulation time 1917433212 ps
CPU time 5.84 seconds
Started Oct 15 01:27:31 PM UTC 24
Finished Oct 15 01:27:38 PM UTC 24
Peak memory 230900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322914427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3322914427 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.1045375383
Short name T296
Test name
Test status
Simulation time 214581290 ps
CPU time 1.39 seconds
Started Oct 15 01:28:09 PM UTC 24
Finished Oct 15 01:28:12 PM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045375383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1045375383 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.3779797986
Short name T334
Test name
Test status
Simulation time 5155585875 ps
CPU time 502.67 seconds
Started Oct 15 01:25:50 PM UTC 24
Finished Oct 15 01:34:20 PM UTC 24
Peak memory 515960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779797986 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.3779797986 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.2470785531
Short name T319
Test name
Test status
Simulation time 18170316231 ps
CPU time 402.76 seconds
Started Oct 15 01:25:52 PM UTC 24
Finished Oct 15 01:32:40 PM UTC 24
Peak memory 384956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470785531 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2470785531 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload_invalid.1361776396
Short name T119
Test name
Test status
Simulation time 81537908 ps
CPU time 1.6 seconds
Started Oct 15 01:26:18 PM UTC 24
Finished Oct 15 01:26:21 PM UTC 24
Peak memory 230168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361776396 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload_invalid.1361776396 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.44638406
Short name T291
Test name
Test status
Simulation time 9509614265 ps
CPU time 73.54 seconds
Started Oct 15 01:25:47 PM UTC 24
Finished Oct 15 01:27:03 PM UTC 24
Peak memory 231088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44638406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.44638406 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.1209187624
Short name T60
Test name
Test status
Simulation time 17128901168 ps
CPU time 632.47 seconds
Started Oct 15 01:28:12 PM UTC 24
Finished Oct 15 01:38:53 PM UTC 24
Peak memory 348480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209187624 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1209187624 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.320957550
Short name T310
Test name
Test status
Simulation time 45622722 ps
CPU time 1.16 seconds
Started Oct 15 01:31:02 PM UTC 24
Finished Oct 15 01:31:04 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320957550 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.320957550 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.829866317
Short name T314
Test name
Test status
Simulation time 6560616663 ps
CPU time 144.74 seconds
Started Oct 15 01:29:41 PM UTC 24
Finished Oct 15 01:32:08 PM UTC 24
Peak memory 292784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829866317 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.829866317 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.1207312016
Short name T394
Test name
Test status
Simulation time 21460319642 ps
CPU time 881.22 seconds
Started Oct 15 01:29:29 PM UTC 24
Finished Oct 15 01:44:20 PM UTC 24
Peak memory 262268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207312016 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1207312016 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.3769952565
Short name T312
Test name
Test status
Simulation time 1424737006 ps
CPU time 29.06 seconds
Started Oct 15 01:30:50 PM UTC 24
Finished Oct 15 01:31:20 PM UTC 24
Peak memory 232816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769952565 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3769952565 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.1769265239
Short name T309
Test name
Test status
Simulation time 619889416 ps
CPU time 8.89 seconds
Started Oct 15 01:30:53 PM UTC 24
Finished Oct 15 01:31:03 PM UTC 24
Peak memory 232760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769265239 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1769265239 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.320311911
Short name T324
Test name
Test status
Simulation time 20351894398 ps
CPU time 204.05 seconds
Started Oct 15 01:29:50 PM UTC 24
Finished Oct 15 01:33:17 PM UTC 24
Peak memory 389052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320311911 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.320311911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.2418744279
Short name T44
Test name
Test status
Simulation time 12898626069 ps
CPU time 276.35 seconds
Started Oct 15 01:29:50 PM UTC 24
Finished Oct 15 01:34:30 PM UTC 24
Peak memory 337848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418744279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2418744279 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.1954659099
Short name T308
Test name
Test status
Simulation time 5491904521 ps
CPU time 12.11 seconds
Started Oct 15 01:30:48 PM UTC 24
Finished Oct 15 01:31:01 PM UTC 24
Peak memory 230828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954659099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1954659099 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1179304935
Short name T347
Test name
Test status
Simulation time 4392561774 ps
CPU time 487.85 seconds
Started Oct 15 01:28:37 PM UTC 24
Finished Oct 15 01:36:51 PM UTC 24
Peak memory 491404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179304935 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.1179304935 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.2463184681
Short name T301
Test name
Test status
Simulation time 2233838537 ps
CPU time 31.15 seconds
Started Oct 15 01:28:35 PM UTC 24
Finished Oct 15 01:29:08 PM UTC 24
Peak memory 231108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463184681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2463184681 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.2141130797
Short name T313
Test name
Test status
Simulation time 3856492480 ps
CPU time 52.42 seconds
Started Oct 15 01:30:59 PM UTC 24
Finished Oct 15 01:31:53 PM UTC 24
Peak memory 251888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141130797 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2141130797 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.1239999029
Short name T321
Test name
Test status
Simulation time 40782586 ps
CPU time 1.16 seconds
Started Oct 15 01:32:56 PM UTC 24
Finished Oct 15 01:32:59 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239999029 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1239999029 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.2188138272
Short name T315
Test name
Test status
Simulation time 634504313 ps
CPU time 15.23 seconds
Started Oct 15 01:31:54 PM UTC 24
Finished Oct 15 01:32:10 PM UTC 24
Peak memory 235108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188138272 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2188138272 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.3515215342
Short name T422
Test name
Test status
Simulation time 108444701439 ps
CPU time 976.29 seconds
Started Oct 15 01:31:31 PM UTC 24
Finished Oct 15 01:47:58 PM UTC 24
Peak memory 262048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515215342 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3515215342 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2021724982
Short name T318
Test name
Test status
Simulation time 52432818 ps
CPU time 4.96 seconds
Started Oct 15 01:32:24 PM UTC 24
Finished Oct 15 01:32:30 PM UTC 24
Peak memory 228844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021724982 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2021724982 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.285960515
Short name T322
Test name
Test status
Simulation time 1345030530 ps
CPU time 29.68 seconds
Started Oct 15 01:32:31 PM UTC 24
Finished Oct 15 01:33:02 PM UTC 24
Peak memory 235176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285960515 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.285960515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.2855170412
Short name T323
Test name
Test status
Simulation time 6828510660 ps
CPU time 54.59 seconds
Started Oct 15 01:32:09 PM UTC 24
Finished Oct 15 01:33:05 PM UTC 24
Peak memory 255876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855170412 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2855170412 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.3480183310
Short name T320
Test name
Test status
Simulation time 341628443 ps
CPU time 35.73 seconds
Started Oct 15 01:32:11 PM UTC 24
Finished Oct 15 01:32:48 PM UTC 24
Peak memory 249708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480183310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3480183310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.1926657240
Short name T317
Test name
Test status
Simulation time 670287420 ps
CPU time 6.57 seconds
Started Oct 15 01:32:16 PM UTC 24
Finished Oct 15 01:32:24 PM UTC 24
Peak memory 230744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926657240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1926657240 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.146732492
Short name T69
Test name
Test status
Simulation time 5025566937 ps
CPU time 22.09 seconds
Started Oct 15 01:32:41 PM UTC 24
Finished Oct 15 01:33:05 PM UTC 24
Peak memory 249912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146732492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.146732492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.1202642756
Short name T746
Test name
Test status
Simulation time 554741124476 ps
CPU time 3992.09 seconds
Started Oct 15 01:31:05 PM UTC 24
Finished Oct 15 02:38:22 PM UTC 24
Peak memory 4241372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202642756 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.1202642756 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.2973088194
Short name T353
Test name
Test status
Simulation time 23044419497 ps
CPU time 400.54 seconds
Started Oct 15 01:31:11 PM UTC 24
Finished Oct 15 01:37:57 PM UTC 24
Peak memory 616316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973088194 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2973088194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload_invalid.3057809891
Short name T120
Test name
Test status
Simulation time 396259318 ps
CPU time 7.06 seconds
Started Oct 15 01:31:21 PM UTC 24
Finished Oct 15 01:31:30 PM UTC 24
Peak memory 231308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057809891 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload_invalid.3057809891 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.2241177383
Short name T311
Test name
Test status
Simulation time 219840414 ps
CPU time 5.93 seconds
Started Oct 15 01:31:03 PM UTC 24
Finished Oct 15 01:31:10 PM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241177383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2241177383 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.3899556195
Short name T469
Test name
Test status
Simulation time 507296413156 ps
CPU time 1194.96 seconds
Started Oct 15 01:32:49 PM UTC 24
Finished Oct 15 01:52:58 PM UTC 24
Peak memory 1284540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899556195 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3899556195 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.177868474
Short name T332
Test name
Test status
Simulation time 64758789 ps
CPU time 1.19 seconds
Started Oct 15 01:34:04 PM UTC 24
Finished Oct 15 01:34:06 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177868474 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.177868474 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.3626510692
Short name T351
Test name
Test status
Simulation time 23375795683 ps
CPU time 255.38 seconds
Started Oct 15 01:33:18 PM UTC 24
Finished Oct 15 01:37:37 PM UTC 24
Peak memory 341944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626510692 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3626510692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.1649651457
Short name T170
Test name
Test status
Simulation time 33254413079 ps
CPU time 601.4 seconds
Started Oct 15 01:33:15 PM UTC 24
Finished Oct 15 01:43:23 PM UTC 24
Peak memory 249716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649651457 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1649651457 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1332909730
Short name T333
Test name
Test status
Simulation time 1302288261 ps
CPU time 32.9 seconds
Started Oct 15 01:33:33 PM UTC 24
Finished Oct 15 01:34:08 PM UTC 24
Peak memory 235116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332909730 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1332909730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.2513525194
Short name T331
Test name
Test status
Simulation time 2366271442 ps
CPU time 26.39 seconds
Started Oct 15 01:33:35 PM UTC 24
Finished Oct 15 01:34:03 PM UTC 24
Peak memory 235488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513525194 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2513525194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.933921138
Short name T338
Test name
Test status
Simulation time 10622190845 ps
CPU time 111.52 seconds
Started Oct 15 01:33:20 PM UTC 24
Finished Oct 15 01:35:14 PM UTC 24
Peak memory 257920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933921138 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.933921138 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.74450845
Short name T359
Test name
Test status
Simulation time 3379176124 ps
CPU time 327.97 seconds
Started Oct 15 01:33:30 PM UTC 24
Finished Oct 15 01:39:03 PM UTC 24
Peak memory 350268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74450845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.74450845 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.3157434848
Short name T328
Test name
Test status
Simulation time 1302346598 ps
CPU time 2.76 seconds
Started Oct 15 01:33:30 PM UTC 24
Finished Oct 15 01:33:34 PM UTC 24
Peak memory 230704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157434848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3157434848 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.3644428627
Short name T330
Test name
Test status
Simulation time 493694332 ps
CPU time 1.87 seconds
Started Oct 15 01:33:40 PM UTC 24
Finished Oct 15 01:33:43 PM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644428627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3644428627 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.830557554
Short name T744
Test name
Test status
Simulation time 178326058325 ps
CPU time 3817.29 seconds
Started Oct 15 01:33:03 PM UTC 24
Finished Oct 15 02:37:20 PM UTC 24
Peak memory 4231224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830557554 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.830557554 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.4140907911
Short name T363
Test name
Test status
Simulation time 31145853026 ps
CPU time 364.47 seconds
Started Oct 15 01:33:06 PM UTC 24
Finished Oct 15 01:39:15 PM UTC 24
Peak memory 550780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140907911 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.4140907911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.3648902696
Short name T326
Test name
Test status
Simulation time 1757142469 ps
CPU time 28.45 seconds
Started Oct 15 01:32:59 PM UTC 24
Finished Oct 15 01:33:29 PM UTC 24
Peak memory 232956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648902696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3648902696 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.298203884
Short name T409
Test name
Test status
Simulation time 24239620619 ps
CPU time 727.15 seconds
Started Oct 15 01:33:45 PM UTC 24
Finished Oct 15 01:46:00 PM UTC 24
Peak memory 389376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298203884 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.298203884 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.1176296949
Short name T345
Test name
Test status
Simulation time 14653284 ps
CPU time 1.24 seconds
Started Oct 15 01:36:23 PM UTC 24
Finished Oct 15 01:36:25 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176296949 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1176296949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.2359871097
Short name T340
Test name
Test status
Simulation time 9281086756 ps
CPU time 54.37 seconds
Started Oct 15 01:34:44 PM UTC 24
Finished Oct 15 01:35:40 PM UTC 24
Peak memory 284664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359871097 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2359871097 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.3817835666
Short name T61
Test name
Test status
Simulation time 5242518763 ps
CPU time 297.36 seconds
Started Oct 15 01:34:38 PM UTC 24
Finished Oct 15 01:39:40 PM UTC 24
Peak memory 239596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817835666 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3817835666 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3709862578
Short name T346
Test name
Test status
Simulation time 1461725301 ps
CPU time 45.08 seconds
Started Oct 15 01:35:41 PM UTC 24
Finished Oct 15 01:36:28 PM UTC 24
Peak memory 233060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709862578 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3709862578 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.2711197636
Short name T344
Test name
Test status
Simulation time 2906882257 ps
CPU time 37.65 seconds
Started Oct 15 01:35:43 PM UTC 24
Finished Oct 15 01:36:22 PM UTC 24
Peak memory 230888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711197636 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2711197636 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.4213025710
Short name T366
Test name
Test status
Simulation time 21112118385 ps
CPU time 335.25 seconds
Started Oct 15 01:34:57 PM UTC 24
Finished Oct 15 01:40:37 PM UTC 24
Peak memory 518012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213025710 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.4213025710 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.1746118542
Short name T341
Test name
Test status
Simulation time 5092116735 ps
CPU time 19.16 seconds
Started Oct 15 01:35:22 PM UTC 24
Finished Oct 15 01:35:42 PM UTC 24
Peak memory 230888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746118542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1746118542 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.3661621103
Short name T343
Test name
Test status
Simulation time 164478975 ps
CPU time 1.71 seconds
Started Oct 15 01:36:04 PM UTC 24
Finished Oct 15 01:36:07 PM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661621103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3661621103 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.682153612
Short name T732
Test name
Test status
Simulation time 75691588204 ps
CPU time 3320.32 seconds
Started Oct 15 01:34:09 PM UTC 24
Finished Oct 15 02:30:05 PM UTC 24
Peak memory 3633016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682153612 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.682153612 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.2301447435
Short name T352
Test name
Test status
Simulation time 14905141022 ps
CPU time 202.9 seconds
Started Oct 15 01:34:21 PM UTC 24
Finished Oct 15 01:37:47 PM UTC 24
Peak memory 389100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301447435 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2301447435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload_invalid.3262010488
Short name T335
Test name
Test status
Simulation time 280074361 ps
CPU time 4.64 seconds
Started Oct 15 01:34:31 PM UTC 24
Finished Oct 15 01:34:37 PM UTC 24
Peak memory 231360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262010488 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload_invalid.3262010488 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.3572213607
Short name T336
Test name
Test status
Simulation time 1983745921 ps
CPU time 35.14 seconds
Started Oct 15 01:34:07 PM UTC 24
Finished Oct 15 01:34:43 PM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572213607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3572213607 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.1385944993
Short name T420
Test name
Test status
Simulation time 33701608683 ps
CPU time 691.46 seconds
Started Oct 15 01:36:07 PM UTC 24
Finished Oct 15 01:47:47 PM UTC 24
Peak memory 629184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385944993 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1385944993 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.3805196335
Short name T358
Test name
Test status
Simulation time 22072217 ps
CPU time 1.24 seconds
Started Oct 15 01:38:42 PM UTC 24
Finished Oct 15 01:38:44 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805196335 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3805196335 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.3449124990
Short name T379
Test name
Test status
Simulation time 23891521897 ps
CPU time 338.45 seconds
Started Oct 15 01:37:37 PM UTC 24
Finished Oct 15 01:43:20 PM UTC 24
Peak memory 510052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449124990 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3449124990 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.4039455455
Short name T396
Test name
Test status
Simulation time 22421947787 ps
CPU time 415.24 seconds
Started Oct 15 01:37:25 PM UTC 24
Finished Oct 15 01:44:25 PM UTC 24
Peak memory 252016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039455455 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.4039455455 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1825467880
Short name T356
Test name
Test status
Simulation time 404372446 ps
CPU time 26.23 seconds
Started Oct 15 01:38:10 PM UTC 24
Finished Oct 15 01:38:38 PM UTC 24
Peak memory 232944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825467880 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1825467880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.1857999829
Short name T357
Test name
Test status
Simulation time 285622217 ps
CPU time 25.62 seconds
Started Oct 15 01:38:14 PM UTC 24
Finished Oct 15 01:38:41 PM UTC 24
Peak memory 235180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857999829 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1857999829 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.276713875
Short name T391
Test name
Test status
Simulation time 82147571876 ps
CPU time 380.47 seconds
Started Oct 15 01:37:38 PM UTC 24
Finished Oct 15 01:44:03 PM UTC 24
Peak memory 497592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276713875 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.276713875 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.90228595
Short name T401
Test name
Test status
Simulation time 13502858447 ps
CPU time 422.29 seconds
Started Oct 15 01:37:48 PM UTC 24
Finished Oct 15 01:44:56 PM UTC 24
Peak memory 583664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90228595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.90228595 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.1005248493
Short name T354
Test name
Test status
Simulation time 3572226402 ps
CPU time 9.64 seconds
Started Oct 15 01:37:58 PM UTC 24
Finished Oct 15 01:38:09 PM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005248493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1005248493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.1683371860
Short name T361
Test name
Test status
Simulation time 7607253400 ps
CPU time 31.08 seconds
Started Oct 15 01:38:35 PM UTC 24
Finished Oct 15 01:39:08 PM UTC 24
Peak memory 252024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683371860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1683371860 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1977855787
Short name T483
Test name
Test status
Simulation time 330109236336 ps
CPU time 1048.75 seconds
Started Oct 15 01:36:28 PM UTC 24
Finished Oct 15 01:54:09 PM UTC 24
Peak memory 1623984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977855787 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.1977855787 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.531668070
Short name T368
Test name
Test status
Simulation time 2862657431 ps
CPU time 233.15 seconds
Started Oct 15 01:36:51 PM UTC 24
Finished Oct 15 01:40:48 PM UTC 24
Peak memory 329596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531668070 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.531668070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload_invalid.4289718977
Short name T349
Test name
Test status
Simulation time 495538222 ps
CPU time 4.86 seconds
Started Oct 15 01:37:18 PM UTC 24
Finished Oct 15 01:37:24 PM UTC 24
Peak memory 231312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289718977 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload_invalid.4289718977 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.2208286219
Short name T348
Test name
Test status
Simulation time 1583670433 ps
CPU time 48.78 seconds
Started Oct 15 01:36:26 PM UTC 24
Finished Oct 15 01:37:16 PM UTC 24
Peak memory 235248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208286219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2208286219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.617114919
Short name T538
Test name
Test status
Simulation time 149810229074 ps
CPU time 1267.88 seconds
Started Oct 15 01:38:39 PM UTC 24
Finished Oct 15 02:00:02 PM UTC 24
Peak memory 1085832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617114919 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.617114919 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.1926543537
Short name T370
Test name
Test status
Simulation time 122533600 ps
CPU time 1.14 seconds
Started Oct 15 01:41:11 PM UTC 24
Finished Oct 15 01:41:13 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926543537 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1926543537 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.2835442412
Short name T364
Test name
Test status
Simulation time 5856443867 ps
CPU time 45.18 seconds
Started Oct 15 01:39:10 PM UTC 24
Finished Oct 15 01:39:57 PM UTC 24
Peak memory 262120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835442412 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2835442412 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.569765321
Short name T385
Test name
Test status
Simulation time 34333538051 ps
CPU time 273.67 seconds
Started Oct 15 01:39:09 PM UTC 24
Finished Oct 15 01:43:47 PM UTC 24
Peak memory 241596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569765321 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.569765321 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.791576981
Short name T367
Test name
Test status
Simulation time 11507274828 ps
CPU time 37.17 seconds
Started Oct 15 01:40:04 PM UTC 24
Finished Oct 15 01:40:42 PM UTC 24
Peak memory 235316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791576981 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.791576981 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1063919493
Short name T371
Test name
Test status
Simulation time 1637723866 ps
CPU time 38.43 seconds
Started Oct 15 01:40:38 PM UTC 24
Finished Oct 15 01:41:18 PM UTC 24
Peak memory 245360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063919493 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1063919493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.3619531526
Short name T378
Test name
Test status
Simulation time 7232926349 ps
CPU time 239.17 seconds
Started Oct 15 01:39:15 PM UTC 24
Finished Oct 15 01:43:18 PM UTC 24
Peak memory 378756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619531526 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3619531526 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.992226331
Short name T389
Test name
Test status
Simulation time 6494844907 ps
CPU time 248.37 seconds
Started Oct 15 01:39:40 PM UTC 24
Finished Oct 15 01:43:52 PM UTC 24
Peak memory 348032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992226331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.992226331 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.1935426177
Short name T365
Test name
Test status
Simulation time 1143756722 ps
CPU time 4.12 seconds
Started Oct 15 01:39:58 PM UTC 24
Finished Oct 15 01:40:03 PM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935426177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1935426177 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.616924014
Short name T369
Test name
Test status
Simulation time 4890121612 ps
CPU time 26.37 seconds
Started Oct 15 01:40:43 PM UTC 24
Finished Oct 15 01:41:10 PM UTC 24
Peak memory 262260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616924014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.616924014 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.4018951871
Short name T546
Test name
Test status
Simulation time 76092342172 ps
CPU time 1364.71 seconds
Started Oct 15 01:38:54 PM UTC 24
Finished Oct 15 02:01:54 PM UTC 24
Peak memory 1990776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018951871 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.4018951871 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.2415976532
Short name T375
Test name
Test status
Simulation time 6438243542 ps
CPU time 162.5 seconds
Started Oct 15 01:39:04 PM UTC 24
Finished Oct 15 01:41:49 PM UTC 24
Peak memory 358324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415976532 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2415976532 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload_invalid.111210607
Short name T362
Test name
Test status
Simulation time 46649566 ps
CPU time 2.28 seconds
Started Oct 15 01:39:06 PM UTC 24
Finished Oct 15 01:39:09 PM UTC 24
Peak memory 231284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111210607 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload_invalid.111210607 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2558760864
Short name T360
Test name
Test status
Simulation time 6482573285 ps
CPU time 19.01 seconds
Started Oct 15 01:38:45 PM UTC 24
Finished Oct 15 01:39:05 PM UTC 24
Peak memory 231220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558760864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2558760864 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.3505577816
Short name T377
Test name
Test status
Simulation time 15248997139 ps
CPU time 133.57 seconds
Started Oct 15 01:40:49 PM UTC 24
Finished Oct 15 01:43:05 PM UTC 24
Peak memory 311552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505577816 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3505577816 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.3965791513
Short name T384
Test name
Test status
Simulation time 41469097 ps
CPU time 1.2 seconds
Started Oct 15 01:43:42 PM UTC 24
Finished Oct 15 01:43:44 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965791513 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3965791513 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.315878693
Short name T387
Test name
Test status
Simulation time 7732456066 ps
CPU time 117.81 seconds
Started Oct 15 01:41:50 PM UTC 24
Finished Oct 15 01:43:50 PM UTC 24
Peak memory 307120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315878693 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.315878693 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.2907511548
Short name T501
Test name
Test status
Simulation time 33080637232 ps
CPU time 827.23 seconds
Started Oct 15 01:41:38 PM UTC 24
Finished Oct 15 01:55:35 PM UTC 24
Peak memory 260016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907511548 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2907511548 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.2701176237
Short name T386
Test name
Test status
Simulation time 1099279103 ps
CPU time 25.28 seconds
Started Oct 15 01:43:21 PM UTC 24
Finished Oct 15 01:43:48 PM UTC 24
Peak memory 235140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701176237 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2701176237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2048573113
Short name T382
Test name
Test status
Simulation time 1696847772 ps
CPU time 14.88 seconds
Started Oct 15 01:43:25 PM UTC 24
Finished Oct 15 01:43:41 PM UTC 24
Peak memory 232732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048573113 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2048573113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1311796221
Short name T399
Test name
Test status
Simulation time 8808389822 ps
CPU time 153.89 seconds
Started Oct 15 01:42:07 PM UTC 24
Finished Oct 15 01:44:43 PM UTC 24
Peak memory 319356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311796221 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1311796221 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.2874348939
Short name T403
Test name
Test status
Simulation time 17398415727 ps
CPU time 110.82 seconds
Started Oct 15 01:43:06 PM UTC 24
Finished Oct 15 01:45:00 PM UTC 24
Peak memory 333744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874348939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2874348939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.860512827
Short name T380
Test name
Test status
Simulation time 1258741993 ps
CPU time 6.86 seconds
Started Oct 15 01:43:18 PM UTC 24
Finished Oct 15 01:43:27 PM UTC 24
Peak memory 230716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860512827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.860512827 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.3200880199
Short name T381
Test name
Test status
Simulation time 181656128 ps
CPU time 2 seconds
Started Oct 15 01:43:28 PM UTC 24
Finished Oct 15 01:43:31 PM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200880199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3200880199 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1549146159
Short name T702
Test name
Test status
Simulation time 121197978442 ps
CPU time 2599.01 seconds
Started Oct 15 01:41:18 PM UTC 24
Finished Oct 15 02:25:06 PM UTC 24
Peak memory 2942844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549146159 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1549146159 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.3529332297
Short name T428
Test name
Test status
Simulation time 34064226684 ps
CPU time 441.55 seconds
Started Oct 15 01:41:20 PM UTC 24
Finished Oct 15 01:48:48 PM UTC 24
Peak memory 608228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529332297 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3529332297 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload_invalid.616282496
Short name T374
Test name
Test status
Simulation time 80009749 ps
CPU time 4.68 seconds
Started Oct 15 01:41:32 PM UTC 24
Finished Oct 15 01:41:37 PM UTC 24
Peak memory 231364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616282496 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload_invalid.616282496 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.1625419515
Short name T376
Test name
Test status
Simulation time 2780003781 ps
CPU time 50.08 seconds
Started Oct 15 01:41:14 PM UTC 24
Finished Oct 15 01:42:06 PM UTC 24
Peak memory 235412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625419515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1625419515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.3171452735
Short name T402
Test name
Test status
Simulation time 16970536233 ps
CPU time 85.71 seconds
Started Oct 15 01:43:32 PM UTC 24
Finished Oct 15 01:44:59 PM UTC 24
Peak memory 348092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171452735 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3171452735 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.317803436
Short name T64
Test name
Test status
Simulation time 48227217 ps
CPU time 1.1 seconds
Started Oct 15 01:05:32 PM UTC 24
Finished Oct 15 01:05:34 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317803436 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.317803436 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.1367624167
Short name T198
Test name
Test status
Simulation time 6404078919 ps
CPU time 151.71 seconds
Started Oct 15 01:05:09 PM UTC 24
Finished Oct 15 01:07:44 PM UTC 24
Peak memory 337892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367624167 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1367624167 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.2476519590
Short name T24
Test name
Test status
Simulation time 5009363177 ps
CPU time 76.5 seconds
Started Oct 15 01:05:11 PM UTC 24
Finished Oct 15 01:06:30 PM UTC 24
Peak memory 294992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476519590 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2476519590 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.3465602020
Short name T98
Test name
Test status
Simulation time 282655108 ps
CPU time 10.66 seconds
Started Oct 15 01:04:43 PM UTC 24
Finished Oct 15 01:04:54 PM UTC 24
Peak memory 230916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465602020 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3465602020 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.437106019
Short name T92
Test name
Test status
Simulation time 502371461 ps
CPU time 33.27 seconds
Started Oct 15 01:05:18 PM UTC 24
Finished Oct 15 01:05:53 PM UTC 24
Peak memory 249460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437106019 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.437106019 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.478775380
Short name T91
Test name
Test status
Simulation time 2277037571 ps
CPU time 30.93 seconds
Started Oct 15 01:05:18 PM UTC 24
Finished Oct 15 01:05:51 PM UTC 24
Peak memory 228956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478775380 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.478775380 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3534651269
Short name T214
Test name
Test status
Simulation time 77007628861 ps
CPU time 363.38 seconds
Started Oct 15 01:05:11 PM UTC 24
Finished Oct 15 01:11:20 PM UTC 24
Peak memory 473008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534651269 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3534651269 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.1842306469
Short name T56
Test name
Test status
Simulation time 2955892475 ps
CPU time 4.64 seconds
Started Oct 15 01:05:17 PM UTC 24
Finished Oct 15 01:05:23 PM UTC 24
Peak memory 230836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842306469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1842306469 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.121006398
Short name T49
Test name
Test status
Simulation time 55683656 ps
CPU time 1.59 seconds
Started Oct 15 01:05:20 PM UTC 24
Finished Oct 15 01:05:23 PM UTC 24
Peak memory 229832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121006398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.121006398 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.249330651
Short name T267
Test name
Test status
Simulation time 11982612495 ps
CPU time 1112.3 seconds
Started Oct 15 01:04:39 PM UTC 24
Finished Oct 15 01:23:25 PM UTC 24
Peak memory 935800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249330651 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.249330651 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.908173358
Short name T86
Test name
Test status
Simulation time 8627003454 ps
CPU time 232.36 seconds
Started Oct 15 01:05:13 PM UTC 24
Finished Oct 15 01:09:08 PM UTC 24
Peak memory 399736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908173358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.908173358 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.1583038780
Short name T11
Test name
Test status
Simulation time 13696205092 ps
CPU time 51.19 seconds
Started Oct 15 01:05:29 PM UTC 24
Finished Oct 15 01:06:21 PM UTC 24
Peak memory 276004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583038780 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1583038780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.1859969061
Short name T35
Test name
Test status
Simulation time 18604549330 ps
CPU time 526.4 seconds
Started Oct 15 01:04:39 PM UTC 24
Finished Oct 15 01:13:33 PM UTC 24
Peak memory 599900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859969061 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1859969061 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload_invalid.1037668047
Short name T54
Test name
Test status
Simulation time 74423913 ps
CPU time 1.33 seconds
Started Oct 15 01:04:40 PM UTC 24
Finished Oct 15 01:04:43 PM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037668047 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload_invalid.1037668047 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.1885860641
Short name T190
Test name
Test status
Simulation time 957512142 ps
CPU time 47.79 seconds
Started Oct 15 01:04:37 PM UTC 24
Finished Oct 15 01:05:27 PM UTC 24
Peak memory 231048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885860641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1885860641 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.3164767539
Short name T59
Test name
Test status
Simulation time 20608691228 ps
CPU time 853.93 seconds
Started Oct 15 01:05:23 PM UTC 24
Finished Oct 15 01:19:47 PM UTC 24
Peak memory 475400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164767539 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3164767539 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3558888023
Short name T81
Test name
Test status
Simulation time 293624300 ps
CPU time 3.12 seconds
Started Oct 15 01:05:01 PM UTC 24
Finished Oct 15 01:05:05 PM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558888023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3558888023 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.2302034405
Short name T82
Test name
Test status
Simulation time 292146511 ps
CPU time 3.36 seconds
Started Oct 15 01:05:06 PM UTC 24
Finished Oct 15 01:05:11 PM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302034405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2302034405 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.2009271102
Short name T327
Test name
Test status
Simulation time 83841357144 ps
CPU time 1710.4 seconds
Started Oct 15 01:04:44 PM UTC 24
Finished Oct 15 01:33:33 PM UTC 24
Peak memory 1181464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009271102 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2009271102
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.1302273906
Short name T84
Test name
Test status
Simulation time 569238333 ps
CPU time 33.96 seconds
Started Oct 15 01:04:45 PM UTC 24
Finished Oct 15 01:05:20 PM UTC 24
Peak memory 230840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302273906 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1302273906
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1768627722
Short name T195
Test name
Test status
Simulation time 1511591110 ps
CPU time 40.34 seconds
Started Oct 15 01:04:49 PM UTC 24
Finished Oct 15 01:05:31 PM UTC 24
Peak memory 239340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768627722 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1768627722
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.4284827774
Short name T83
Test name
Test status
Simulation time 774448511 ps
CPU time 23.14 seconds
Started Oct 15 01:04:54 PM UTC 24
Finished Oct 15 01:05:18 PM UTC 24
Peak memory 230868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284827774 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.4284827774
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.133730774
Short name T186
Test name
Test status
Simulation time 8598383415 ps
CPU time 159.62 seconds
Started Oct 15 01:04:55 PM UTC 24
Finished Oct 15 01:07:37 PM UTC 24
Peak memory 288620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133730774 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.13373077
4 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.286282879
Short name T450
Test name
Test status
Simulation time 869479383483 ps
CPU time 2714.83 seconds
Started Oct 15 01:04:56 PM UTC 24
Finished Oct 15 01:50:41 PM UTC 24
Peak memory 3008412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286282879 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.28628287
9 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.3708234110
Short name T395
Test name
Test status
Simulation time 36916705 ps
CPU time 1.22 seconds
Started Oct 15 01:44:21 PM UTC 24
Finished Oct 15 01:44:23 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708234110 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3708234110 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.942077292
Short name T414
Test name
Test status
Simulation time 13061265966 ps
CPU time 173.2 seconds
Started Oct 15 01:43:54 PM UTC 24
Finished Oct 15 01:46:50 PM UTC 24
Peak memory 286644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942077292 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.942077292 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.1654730507
Short name T410
Test name
Test status
Simulation time 6001679406 ps
CPU time 128.51 seconds
Started Oct 15 01:43:50 PM UTC 24
Finished Oct 15 01:46:01 PM UTC 24
Peak memory 235392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654730507 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1654730507 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2911024674
Short name T443
Test name
Test status
Simulation time 33251464519 ps
CPU time 369.39 seconds
Started Oct 15 01:43:54 PM UTC 24
Finished Oct 15 01:50:08 PM UTC 24
Peak memory 540704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911024674 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2911024674 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.2914286597
Short name T433
Test name
Test status
Simulation time 30612034880 ps
CPU time 321.73 seconds
Started Oct 15 01:44:01 PM UTC 24
Finished Oct 15 01:49:27 PM UTC 24
Peak memory 452472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914286597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2914286597 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.1616664783
Short name T393
Test name
Test status
Simulation time 3979658321 ps
CPU time 5.9 seconds
Started Oct 15 01:44:05 PM UTC 24
Finished Oct 15 01:44:12 PM UTC 24
Peak memory 230940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616664783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1616664783 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.2598893959
Short name T397
Test name
Test status
Simulation time 3979353562 ps
CPU time 22.94 seconds
Started Oct 15 01:44:07 PM UTC 24
Finished Oct 15 01:44:31 PM UTC 24
Peak memory 251836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598893959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2598893959 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2715766929
Short name T400
Test name
Test status
Simulation time 1712628418 ps
CPU time 60.06 seconds
Started Oct 15 01:43:45 PM UTC 24
Finished Oct 15 01:44:47 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715766929 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2715766929 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.1640551233
Short name T425
Test name
Test status
Simulation time 3745077761 ps
CPU time 267.25 seconds
Started Oct 15 01:43:47 PM UTC 24
Finished Oct 15 01:48:18 PM UTC 24
Peak memory 360352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640551233 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1640551233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload_invalid.471061206
Short name T388
Test name
Test status
Simulation time 164413969 ps
CPU time 2.81 seconds
Started Oct 15 01:43:48 PM UTC 24
Finished Oct 15 01:43:52 PM UTC 24
Peak memory 231372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471061206 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload_invalid.471061206 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.2234432675
Short name T392
Test name
Test status
Simulation time 1290663071 ps
CPU time 22.46 seconds
Started Oct 15 01:43:42 PM UTC 24
Finished Oct 15 01:44:06 PM UTC 24
Peak memory 233080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234432675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2234432675 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.333263361
Short name T587
Test name
Test status
Simulation time 159294796384 ps
CPU time 1264.79 seconds
Started Oct 15 01:44:13 PM UTC 24
Finished Oct 15 02:05:31 PM UTC 24
Peak memory 1572920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333263361 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.333263361 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.261048523
Short name T407
Test name
Test status
Simulation time 31140223 ps
CPU time 1.25 seconds
Started Oct 15 01:45:23 PM UTC 24
Finished Oct 15 01:45:25 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261048523 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.261048523 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.986286042
Short name T411
Test name
Test status
Simulation time 9408290978 ps
CPU time 84.66 seconds
Started Oct 15 01:44:48 PM UTC 24
Finished Oct 15 01:46:14 PM UTC 24
Peak memory 311272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986286042 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.986286042 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.3184833002
Short name T465
Test name
Test status
Simulation time 34037914393 ps
CPU time 448.12 seconds
Started Oct 15 01:44:45 PM UTC 24
Finished Oct 15 01:52:18 PM UTC 24
Peak memory 249720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184833002 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3184833002 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.916392542
Short name T429
Test name
Test status
Simulation time 30889619220 ps
CPU time 254.67 seconds
Started Oct 15 01:44:57 PM UTC 24
Finished Oct 15 01:49:15 PM UTC 24
Peak memory 333940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916392542 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.916392542 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.1452386006
Short name T436
Test name
Test status
Simulation time 2687402613 ps
CPU time 277.73 seconds
Started Oct 15 01:45:00 PM UTC 24
Finished Oct 15 01:49:42 PM UTC 24
Peak memory 323444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452386006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1452386006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.2458108104
Short name T404
Test name
Test status
Simulation time 67749717 ps
CPU time 1.98 seconds
Started Oct 15 01:45:01 PM UTC 24
Finished Oct 15 01:45:04 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458108104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2458108104 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.3732222997
Short name T405
Test name
Test status
Simulation time 135383097 ps
CPU time 1.59 seconds
Started Oct 15 01:45:05 PM UTC 24
Finished Oct 15 01:45:08 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732222997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3732222997 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.319291391
Short name T734
Test name
Test status
Simulation time 365192855315 ps
CPU time 2788.35 seconds
Started Oct 15 01:44:26 PM UTC 24
Finished Oct 15 02:31:23 PM UTC 24
Peak memory 3573680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319291391 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.319291391 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.848687841
Short name T423
Test name
Test status
Simulation time 27798398333 ps
CPU time 209.17 seconds
Started Oct 15 01:44:32 PM UTC 24
Finished Oct 15 01:48:05 PM UTC 24
Peak memory 389020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848687841 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.848687841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.2136990232
Short name T398
Test name
Test status
Simulation time 1854745511 ps
CPU time 15.07 seconds
Started Oct 15 01:44:24 PM UTC 24
Finished Oct 15 01:44:40 PM UTC 24
Peak memory 233148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136990232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2136990232 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.1826972657
Short name T467
Test name
Test status
Simulation time 148982388488 ps
CPU time 444.19 seconds
Started Oct 15 01:45:08 PM UTC 24
Finished Oct 15 01:52:39 PM UTC 24
Peak memory 663848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826972657 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1826972657 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.3321384420
Short name T417
Test name
Test status
Simulation time 43551288 ps
CPU time 1.2 seconds
Started Oct 15 01:47:17 PM UTC 24
Finished Oct 15 01:47:19 PM UTC 24
Peak memory 214132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321384420 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3321384420 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.2096970545
Short name T419
Test name
Test status
Simulation time 1665055859 ps
CPU time 80.07 seconds
Started Oct 15 01:46:15 PM UTC 24
Finished Oct 15 01:47:37 PM UTC 24
Peak memory 253804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096970545 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2096970545 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.2119431507
Short name T457
Test name
Test status
Simulation time 17018656522 ps
CPU time 316.17 seconds
Started Oct 15 01:46:08 PM UTC 24
Finished Oct 15 01:51:29 PM UTC 24
Peak memory 243824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119431507 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2119431507 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1160734092
Short name T442
Test name
Test status
Simulation time 5254651664 ps
CPU time 226.61 seconds
Started Oct 15 01:46:17 PM UTC 24
Finished Oct 15 01:50:07 PM UTC 24
Peak memory 315456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160734092 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1160734092 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.253970886
Short name T416
Test name
Test status
Simulation time 8433804050 ps
CPU time 49.87 seconds
Started Oct 15 01:46:20 PM UTC 24
Finished Oct 15 01:47:12 PM UTC 24
Peak memory 266164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253970886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.253970886 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.11816115
Short name T415
Test name
Test status
Simulation time 1075404733 ps
CPU time 10.51 seconds
Started Oct 15 01:46:50 PM UTC 24
Finished Oct 15 01:47:02 PM UTC 24
Peak memory 230784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11816115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.11816115 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2046681262
Short name T471
Test name
Test status
Simulation time 4660136705 ps
CPU time 434.98 seconds
Started Oct 15 01:45:47 PM UTC 24
Finished Oct 15 01:53:07 PM UTC 24
Peak memory 503672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046681262 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2046681262 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.1233112862
Short name T424
Test name
Test status
Simulation time 17034924388 ps
CPU time 125.69 seconds
Started Oct 15 01:46:02 PM UTC 24
Finished Oct 15 01:48:10 PM UTC 24
Peak memory 305164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233112862 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1233112862 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload_invalid.3986752573
Short name T28
Test name
Test status
Simulation time 111845232 ps
CPU time 4.3 seconds
Started Oct 15 01:46:02 PM UTC 24
Finished Oct 15 01:46:07 PM UTC 24
Peak memory 231236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986752573 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload_invalid.3986752573 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.2546914953
Short name T408
Test name
Test status
Simulation time 1092728847 ps
CPU time 18.44 seconds
Started Oct 15 01:45:26 PM UTC 24
Finished Oct 15 01:45:46 PM UTC 24
Peak memory 231100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546914953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2546914953 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.1484016101
Short name T434
Test name
Test status
Simulation time 25144706436 ps
CPU time 143.11 seconds
Started Oct 15 01:47:13 PM UTC 24
Finished Oct 15 01:49:38 PM UTC 24
Peak memory 317760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484016101 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1484016101 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.1480370444
Short name T427
Test name
Test status
Simulation time 45224062 ps
CPU time 0.98 seconds
Started Oct 15 01:48:31 PM UTC 24
Finished Oct 15 01:48:33 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480370444 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1480370444 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.3306585840
Short name T452
Test name
Test status
Simulation time 8294709727 ps
CPU time 163.63 seconds
Started Oct 15 01:47:59 PM UTC 24
Finished Oct 15 01:50:46 PM UTC 24
Peak memory 354280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306585840 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3306585840 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.3282781234
Short name T458
Test name
Test status
Simulation time 13413333547 ps
CPU time 222.03 seconds
Started Oct 15 01:47:53 PM UTC 24
Finished Oct 15 01:51:39 PM UTC 24
Peak memory 239480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282781234 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3282781234 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.3109607210
Short name T481
Test name
Test status
Simulation time 11594214431 ps
CPU time 352.61 seconds
Started Oct 15 01:48:06 PM UTC 24
Finished Oct 15 01:54:04 PM UTC 24
Peak memory 520184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109607210 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3109607210 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.372276156
Short name T431
Test name
Test status
Simulation time 3538867019 ps
CPU time 68.36 seconds
Started Oct 15 01:48:10 PM UTC 24
Finished Oct 15 01:49:21 PM UTC 24
Peak memory 284544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372276156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.372276156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.688234898
Short name T426
Test name
Test status
Simulation time 76732105 ps
CPU time 1.81 seconds
Started Oct 15 01:48:19 PM UTC 24
Finished Oct 15 01:48:21 PM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688234898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.688234898 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.2445087331
Short name T73
Test name
Test status
Simulation time 151317019 ps
CPU time 2.12 seconds
Started Oct 15 01:48:23 PM UTC 24
Finished Oct 15 01:48:26 PM UTC 24
Peak memory 233016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445087331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2445087331 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2690080531
Short name T435
Test name
Test status
Simulation time 8245932585 ps
CPU time 121.18 seconds
Started Oct 15 01:47:37 PM UTC 24
Finished Oct 15 01:49:40 PM UTC 24
Peak memory 286636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690080531 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2690080531 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.1133054780
Short name T453
Test name
Test status
Simulation time 25732605457 ps
CPU time 191.38 seconds
Started Oct 15 01:47:38 PM UTC 24
Finished Oct 15 01:50:52 PM UTC 24
Peak memory 395128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133054780 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1133054780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload_invalid.2564043136
Short name T421
Test name
Test status
Simulation time 38328622 ps
CPU time 2.84 seconds
Started Oct 15 01:47:48 PM UTC 24
Finished Oct 15 01:47:52 PM UTC 24
Peak memory 231428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564043136 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload_invalid.2564043136 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.511708602
Short name T418
Test name
Test status
Simulation time 1159680060 ps
CPU time 15.6 seconds
Started Oct 15 01:47:20 PM UTC 24
Finished Oct 15 01:47:36 PM UTC 24
Peak memory 230916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511708602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.511708602 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.3021817041
Short name T487
Test name
Test status
Simulation time 20096406943 ps
CPU time 352.46 seconds
Started Oct 15 01:48:27 PM UTC 24
Finished Oct 15 01:54:24 PM UTC 24
Peak memory 411576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021817041 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3021817041 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.907115645
Short name T441
Test name
Test status
Simulation time 47247421 ps
CPU time 1.24 seconds
Started Oct 15 01:49:54 PM UTC 24
Finished Oct 15 01:49:56 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907115645 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.907115645 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.2590848820
Short name T447
Test name
Test status
Simulation time 4801721814 ps
CPU time 63.41 seconds
Started Oct 15 01:49:24 PM UTC 24
Finished Oct 15 01:50:30 PM UTC 24
Peak memory 276312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590848820 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2590848820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.100593586
Short name T524
Test name
Test status
Simulation time 60541139759 ps
CPU time 515.28 seconds
Started Oct 15 01:49:21 PM UTC 24
Finished Oct 15 01:58:03 PM UTC 24
Peak memory 254012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100593586 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.100593586 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.4161008212
Short name T438
Test name
Test status
Simulation time 621835725 ps
CPU time 24.31 seconds
Started Oct 15 01:49:28 PM UTC 24
Finished Oct 15 01:49:53 PM UTC 24
Peak memory 235376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161008212 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.4161008212 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.1272773759
Short name T493
Test name
Test status
Simulation time 50706312404 ps
CPU time 322.14 seconds
Started Oct 15 01:49:39 PM UTC 24
Finished Oct 15 01:55:05 PM UTC 24
Peak memory 583656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272773759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1272773759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.4177943737
Short name T439
Test name
Test status
Simulation time 4560429668 ps
CPU time 10.66 seconds
Started Oct 15 01:49:42 PM UTC 24
Finished Oct 15 01:49:54 PM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177943737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.4177943737 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.2704392981
Short name T437
Test name
Test status
Simulation time 439772509 ps
CPU time 2.07 seconds
Started Oct 15 01:49:43 PM UTC 24
Finished Oct 15 01:49:46 PM UTC 24
Peak memory 230804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704392981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2704392981 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3522087250
Short name T637
Test name
Test status
Simulation time 156878767105 ps
CPU time 1520.26 seconds
Started Oct 15 01:48:49 PM UTC 24
Finished Oct 15 02:14:27 PM UTC 24
Peak memory 1859508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522087250 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3522087250 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.1895739850
Short name T484
Test name
Test status
Simulation time 8778141686 ps
CPU time 291.01 seconds
Started Oct 15 01:49:16 PM UTC 24
Finished Oct 15 01:54:11 PM UTC 24
Peak memory 468992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895739850 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1895739850 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload_invalid.3428843520
Short name T432
Test name
Test status
Simulation time 66052211 ps
CPU time 4.38 seconds
Started Oct 15 01:49:18 PM UTC 24
Finished Oct 15 01:49:24 PM UTC 24
Peak memory 231424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428843520 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload_invalid.3428843520 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.4119172977
Short name T430
Test name
Test status
Simulation time 651938150 ps
CPU time 42.08 seconds
Started Oct 15 01:48:34 PM UTC 24
Finished Oct 15 01:49:18 PM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119172977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.4119172977 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.487201940
Short name T665
Test name
Test status
Simulation time 125620214688 ps
CPU time 1763.33 seconds
Started Oct 15 01:49:47 PM UTC 24
Finished Oct 15 02:19:28 PM UTC 24
Peak memory 1120644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487201940 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.487201940 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.1671545732
Short name T451
Test name
Test status
Simulation time 15712135 ps
CPU time 1.24 seconds
Started Oct 15 01:50:42 PM UTC 24
Finished Oct 15 01:50:44 PM UTC 24
Peak memory 214132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671545732 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1671545732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.2612949372
Short name T459
Test name
Test status
Simulation time 16149136614 ps
CPU time 99.43 seconds
Started Oct 15 01:50:11 PM UTC 24
Finished Oct 15 01:51:52 PM UTC 24
Peak memory 276476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612949372 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2612949372 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.4273016450
Short name T603
Test name
Test status
Simulation time 26617718161 ps
CPU time 1113.22 seconds
Started Oct 15 01:50:09 PM UTC 24
Finished Oct 15 02:08:55 PM UTC 24
Peak memory 262180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273016450 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.4273016450 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.1714917518
Short name T454
Test name
Test status
Simulation time 6104663862 ps
CPU time 51.38 seconds
Started Oct 15 01:50:14 PM UTC 24
Finished Oct 15 01:51:07 PM UTC 24
Peak memory 262204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714917518 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1714917518 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.2697406230
Short name T503
Test name
Test status
Simulation time 19480041351 ps
CPU time 336.33 seconds
Started Oct 15 01:50:23 PM UTC 24
Finished Oct 15 01:56:04 PM UTC 24
Peak memory 387000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697406230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2697406230 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.3149948742
Short name T448
Test name
Test status
Simulation time 106668226 ps
CPU time 2.1 seconds
Started Oct 15 01:50:31 PM UTC 24
Finished Oct 15 01:50:34 PM UTC 24
Peak memory 230820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149948742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3149948742 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.2545041158
Short name T449
Test name
Test status
Simulation time 97893152 ps
CPU time 2.27 seconds
Started Oct 15 01:50:35 PM UTC 24
Finished Oct 15 01:50:38 PM UTC 24
Peak memory 230896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545041158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2545041158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.663193486
Short name T763
Test name
Test status
Simulation time 526196086094 ps
CPU time 4773.07 seconds
Started Oct 15 01:49:56 PM UTC 24
Finished Oct 15 03:10:22 PM UTC 24
Peak memory 5099492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663193486 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.663193486 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.3808177411
Short name T461
Test name
Test status
Simulation time 1550358771 ps
CPU time 122.88 seconds
Started Oct 15 01:49:57 PM UTC 24
Finished Oct 15 01:52:03 PM UTC 24
Peak memory 280508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808177411 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3808177411 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload_invalid.4010108216
Short name T445
Test name
Test status
Simulation time 324750537 ps
CPU time 3.62 seconds
Started Oct 15 01:50:08 PM UTC 24
Finished Oct 15 01:50:13 PM UTC 24
Peak memory 231304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010108216 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload_invalid.4010108216 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.735381401
Short name T444
Test name
Test status
Simulation time 1011009131 ps
CPU time 14.63 seconds
Started Oct 15 01:49:54 PM UTC 24
Finished Oct 15 01:50:10 PM UTC 24
Peak memory 230916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735381401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.735381401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.4130203745
Short name T680
Test name
Test status
Simulation time 71713021974 ps
CPU time 1824.66 seconds
Started Oct 15 01:50:39 PM UTC 24
Finished Oct 15 02:21:24 PM UTC 24
Peak memory 1110248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130203745 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.4130203745 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.20420617
Short name T464
Test name
Test status
Simulation time 17434275 ps
CPU time 1.09 seconds
Started Oct 15 01:52:05 PM UTC 24
Finished Oct 15 01:52:08 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20420617 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.20420617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.3465803897
Short name T491
Test name
Test status
Simulation time 48695369939 ps
CPU time 197.63 seconds
Started Oct 15 01:51:24 PM UTC 24
Finished Oct 15 01:54:44 PM UTC 24
Peak memory 417692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465803897 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3465803897 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.1484852975
Short name T482
Test name
Test status
Simulation time 5082378459 ps
CPU time 171.76 seconds
Started Oct 15 01:51:12 PM UTC 24
Finished Oct 15 01:54:07 PM UTC 24
Peak memory 237492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484852975 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.1484852975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2648428366
Short name T460
Test name
Test status
Simulation time 1005640337 ps
CPU time 31.24 seconds
Started Oct 15 01:51:29 PM UTC 24
Finished Oct 15 01:52:02 PM UTC 24
Peak memory 247740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648428366 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2648428366 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.63553963
Short name T498
Test name
Test status
Simulation time 9072478172 ps
CPU time 210.9 seconds
Started Oct 15 01:51:40 PM UTC 24
Finished Oct 15 01:55:14 PM UTC 24
Peak memory 448568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63553963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.63553963 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.3387676228
Short name T463
Test name
Test status
Simulation time 1289874371 ps
CPU time 12.62 seconds
Started Oct 15 01:51:53 PM UTC 24
Finished Oct 15 01:52:07 PM UTC 24
Peak memory 230736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387676228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3387676228 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.4051608922
Short name T462
Test name
Test status
Simulation time 451806569 ps
CPU time 1.26 seconds
Started Oct 15 01:52:02 PM UTC 24
Finished Oct 15 01:52:05 PM UTC 24
Peak memory 229840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051608922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.4051608922 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.754696573
Short name T741
Test name
Test status
Simulation time 281593215597 ps
CPU time 2652.38 seconds
Started Oct 15 01:50:46 PM UTC 24
Finished Oct 15 02:35:28 PM UTC 24
Peak memory 3387252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754696573 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.754696573 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.3883974610
Short name T508
Test name
Test status
Simulation time 12720933290 ps
CPU time 318.13 seconds
Started Oct 15 01:50:54 PM UTC 24
Finished Oct 15 01:56:16 PM UTC 24
Peak memory 348056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883974610 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3883974610 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload_invalid.3268190100
Short name T455
Test name
Test status
Simulation time 175116154 ps
CPU time 2.39 seconds
Started Oct 15 01:51:08 PM UTC 24
Finished Oct 15 01:51:11 PM UTC 24
Peak memory 231132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268190100 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload_invalid.3268190100 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.4147943034
Short name T456
Test name
Test status
Simulation time 4206124622 ps
CPU time 35.93 seconds
Started Oct 15 01:50:45 PM UTC 24
Finished Oct 15 01:51:23 PM UTC 24
Peak memory 235260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147943034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.4147943034 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.2553747600
Short name T552
Test name
Test status
Simulation time 47796016009 ps
CPU time 628.54 seconds
Started Oct 15 01:52:03 PM UTC 24
Finished Oct 15 02:02:39 PM UTC 24
Peak memory 491388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553747600 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2553747600 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.129407259
Short name T474
Test name
Test status
Simulation time 45799744 ps
CPU time 1.26 seconds
Started Oct 15 01:53:12 PM UTC 24
Finished Oct 15 01:53:14 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129407259 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.129407259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.1108510688
Short name T494
Test name
Test status
Simulation time 6430922487 ps
CPU time 144.28 seconds
Started Oct 15 01:52:39 PM UTC 24
Finished Oct 15 01:55:06 PM UTC 24
Peak memory 358476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108510688 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1108510688 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.1567893205
Short name T476
Test name
Test status
Simulation time 565373768 ps
CPU time 61.81 seconds
Started Oct 15 01:52:31 PM UTC 24
Finished Oct 15 01:53:35 PM UTC 24
Peak memory 235312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567893205 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1567893205 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3799634889
Short name T500
Test name
Test status
Simulation time 82618518948 ps
CPU time 154.77 seconds
Started Oct 15 01:52:47 PM UTC 24
Finished Oct 15 01:55:25 PM UTC 24
Peak memory 319412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799634889 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3799634889 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.3518660992
Short name T515
Test name
Test status
Simulation time 3364598719 ps
CPU time 231.31 seconds
Started Oct 15 01:52:59 PM UTC 24
Finished Oct 15 01:56:54 PM UTC 24
Peak memory 354280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518660992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3518660992 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.1414950465
Short name T472
Test name
Test status
Simulation time 1315239368 ps
CPU time 3.78 seconds
Started Oct 15 01:53:04 PM UTC 24
Finished Oct 15 01:53:09 PM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414950465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1414950465 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.1770410022
Short name T473
Test name
Test status
Simulation time 59053290 ps
CPU time 2.01 seconds
Started Oct 15 01:53:08 PM UTC 24
Finished Oct 15 01:53:11 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770410022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1770410022 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.4235526120
Short name T622
Test name
Test status
Simulation time 146847820749 ps
CPU time 1159.31 seconds
Started Oct 15 01:52:09 PM UTC 24
Finished Oct 15 02:11:40 PM UTC 24
Peak memory 1810292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235526120 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.4235526120 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.61007976
Short name T468
Test name
Test status
Simulation time 1094410230 ps
CPU time 32.93 seconds
Started Oct 15 01:52:12 PM UTC 24
Finished Oct 15 01:52:46 PM UTC 24
Peak memory 247668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61007976 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.61007976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.1156963193
Short name T466
Test name
Test status
Simulation time 1710036326 ps
CPU time 21.03 seconds
Started Oct 15 01:52:08 PM UTC 24
Finished Oct 15 01:52:30 PM UTC 24
Peak memory 231028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156963193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1156963193 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.2665424441
Short name T475
Test name
Test status
Simulation time 210319499 ps
CPU time 13.1 seconds
Started Oct 15 01:53:10 PM UTC 24
Finished Oct 15 01:53:24 PM UTC 24
Peak memory 233028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665424441 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2665424441 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.1127373748
Short name T486
Test name
Test status
Simulation time 18294458 ps
CPU time 1.16 seconds
Started Oct 15 01:54:12 PM UTC 24
Finished Oct 15 01:54:14 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127373748 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1127373748 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.2333737672
Short name T490
Test name
Test status
Simulation time 3413677164 ps
CPU time 37.66 seconds
Started Oct 15 01:53:56 PM UTC 24
Finished Oct 15 01:54:35 PM UTC 24
Peak memory 253940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333737672 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2333737672 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.1437660158
Short name T592
Test name
Test status
Simulation time 79854350410 ps
CPU time 729.55 seconds
Started Oct 15 01:53:51 PM UTC 24
Finished Oct 15 02:06:09 PM UTC 24
Peak memory 262072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437660158 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1437660158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.3353436906
Short name T544
Test name
Test status
Simulation time 66956566310 ps
CPU time 433.03 seconds
Started Oct 15 01:53:59 PM UTC 24
Finished Oct 15 02:01:17 PM UTC 24
Peak memory 548712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353436906 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3353436906 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.646889719
Short name T534
Test name
Test status
Simulation time 25183531036 ps
CPU time 297.8 seconds
Started Oct 15 01:54:00 PM UTC 24
Finished Oct 15 01:59:02 PM UTC 24
Peak memory 464832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646889719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.646889719 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.3775178434
Short name T485
Test name
Test status
Simulation time 1473666198 ps
CPU time 6.78 seconds
Started Oct 15 01:54:05 PM UTC 24
Finished Oct 15 01:54:13 PM UTC 24
Peak memory 230868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775178434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3775178434 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.141468345
Short name T488
Test name
Test status
Simulation time 1266129593 ps
CPU time 19.44 seconds
Started Oct 15 01:54:08 PM UTC 24
Finished Oct 15 01:54:28 PM UTC 24
Peak memory 245752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141468345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.141468345 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.2622740918
Short name T499
Test name
Test status
Simulation time 4226096096 ps
CPU time 113.03 seconds
Started Oct 15 01:53:25 PM UTC 24
Finished Oct 15 01:55:20 PM UTC 24
Peak memory 288688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622740918 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.2622740918 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.1584543035
Short name T479
Test name
Test status
Simulation time 1927318566 ps
CPU time 19.52 seconds
Started Oct 15 01:53:35 PM UTC 24
Finished Oct 15 01:53:56 PM UTC 24
Peak memory 235388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584543035 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1584543035 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload_invalid.544236643
Short name T478
Test name
Test status
Simulation time 92185466 ps
CPU time 5.96 seconds
Started Oct 15 01:53:43 PM UTC 24
Finished Oct 15 01:53:50 PM UTC 24
Peak memory 236024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544236643 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload_invalid.544236643 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.845134743
Short name T477
Test name
Test status
Simulation time 403005375 ps
CPU time 26.44 seconds
Started Oct 15 01:53:15 PM UTC 24
Finished Oct 15 01:53:43 PM UTC 24
Peak memory 230892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845134743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.845134743 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.3618675385
Short name T532
Test name
Test status
Simulation time 16573341661 ps
CPU time 276.7 seconds
Started Oct 15 01:54:10 PM UTC 24
Finished Oct 15 01:58:50 PM UTC 24
Peak memory 504068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618675385 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3618675385 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.939843133
Short name T497
Test name
Test status
Simulation time 137536065 ps
CPU time 1.27 seconds
Started Oct 15 01:55:11 PM UTC 24
Finished Oct 15 01:55:14 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939843133 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.939843133 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.797812655
Short name T511
Test name
Test status
Simulation time 6166316024 ps
CPU time 114.8 seconds
Started Oct 15 01:54:37 PM UTC 24
Finished Oct 15 01:56:34 PM UTC 24
Peak memory 327728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797812655 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.797812655 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.643235567
Short name T537
Test name
Test status
Simulation time 10345988867 ps
CPU time 318.41 seconds
Started Oct 15 01:54:33 PM UTC 24
Finished Oct 15 01:59:56 PM UTC 24
Peak memory 241716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643235567 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.643235567 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.1987318415
Short name T527
Test name
Test status
Simulation time 11076004351 ps
CPU time 212.67 seconds
Started Oct 15 01:54:46 PM UTC 24
Finished Oct 15 01:58:22 PM UTC 24
Peak memory 319360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987318415 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1987318415 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.2459156687
Short name T548
Test name
Test status
Simulation time 84394507514 ps
CPU time 421.26 seconds
Started Oct 15 01:54:57 PM UTC 24
Finished Oct 15 02:02:03 PM UTC 24
Peak memory 604064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459156687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2459156687 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.3896743116
Short name T495
Test name
Test status
Simulation time 408620090 ps
CPU time 2.49 seconds
Started Oct 15 01:55:06 PM UTC 24
Finished Oct 15 01:55:10 PM UTC 24
Peak memory 230624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896743116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3896743116 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.11174967
Short name T496
Test name
Test status
Simulation time 195429974 ps
CPU time 1.79 seconds
Started Oct 15 01:55:07 PM UTC 24
Finished Oct 15 01:55:10 PM UTC 24
Peak memory 234624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11174967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.11174967 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.3689914804
Short name T759
Test name
Test status
Simulation time 109989945595 ps
CPU time 3520.34 seconds
Started Oct 15 01:54:15 PM UTC 24
Finished Oct 15 02:53:33 PM UTC 24
Peak memory 4036660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689914804 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.3689914804 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.4179457252
Short name T516
Test name
Test status
Simulation time 4079101345 ps
CPU time 154.36 seconds
Started Oct 15 01:54:25 PM UTC 24
Finished Oct 15 01:57:02 PM UTC 24
Peak memory 305076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179457252 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.4179457252 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload_invalid.1872307944
Short name T489
Test name
Test status
Simulation time 76304497 ps
CPU time 2 seconds
Started Oct 15 01:54:29 PM UTC 24
Finished Oct 15 01:54:33 PM UTC 24
Peak memory 230204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872307944 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload_invalid.1872307944 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.3098747476
Short name T502
Test name
Test status
Simulation time 16519899058 ps
CPU time 92.6 seconds
Started Oct 15 01:54:13 PM UTC 24
Finished Oct 15 01:55:48 PM UTC 24
Peak memory 235544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098747476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3098747476 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.2133223556
Short name T657
Test name
Test status
Simulation time 63743472472 ps
CPU time 1378.12 seconds
Started Oct 15 01:55:10 PM UTC 24
Finished Oct 15 02:18:24 PM UTC 24
Peak memory 668024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133223556 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2133223556 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.2834796435
Short name T65
Test name
Test status
Simulation time 18205417 ps
CPU time 1.31 seconds
Started Oct 15 01:07:38 PM UTC 24
Finished Oct 15 01:07:41 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834796435 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.2834796435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.2907555235
Short name T209
Test name
Test status
Simulation time 9141003735 ps
CPU time 243.63 seconds
Started Oct 15 01:06:35 PM UTC 24
Finished Oct 15 01:10:43 PM UTC 24
Peak memory 331644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907555235 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2907555235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3691509462
Short name T38
Test name
Test status
Simulation time 8408342924 ps
CPU time 182.32 seconds
Started Oct 15 01:06:37 PM UTC 24
Finished Oct 15 01:09:43 PM UTC 24
Peak memory 356216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691509462 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3691509462 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.1432640179
Short name T146
Test name
Test status
Simulation time 49532753825 ps
CPU time 333.49 seconds
Started Oct 15 01:05:51 PM UTC 24
Finished Oct 15 01:11:29 PM UTC 24
Peak memory 245620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432640179 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1432640179 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.107403645
Short name T139
Test name
Test status
Simulation time 386260003 ps
CPU time 13.91 seconds
Started Oct 15 01:06:57 PM UTC 24
Finished Oct 15 01:07:12 PM UTC 24
Peak memory 228856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107403645 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.107403645 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.2089347875
Short name T197
Test name
Test status
Simulation time 659843032 ps
CPU time 30.61 seconds
Started Oct 15 01:07:06 PM UTC 24
Finished Oct 15 01:07:38 PM UTC 24
Peak memory 235308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089347875 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2089347875 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.340268949
Short name T117
Test name
Test status
Simulation time 392432701 ps
CPU time 7.49 seconds
Started Oct 15 01:07:07 PM UTC 24
Finished Oct 15 01:07:16 PM UTC 24
Peak memory 231020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340268949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.340268949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3798257022
Short name T199
Test name
Test status
Simulation time 58534509711 ps
CPU time 107.28 seconds
Started Oct 15 01:06:41 PM UTC 24
Finished Oct 15 01:08:31 PM UTC 24
Peak memory 313204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798257022 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3798257022 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.4072594562
Short name T31
Test name
Test status
Simulation time 6521384198 ps
CPU time 88.39 seconds
Started Oct 15 01:06:44 PM UTC 24
Finished Oct 15 01:08:14 PM UTC 24
Peak memory 317308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072594562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.4072594562 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.2306204460
Short name T75
Test name
Test status
Simulation time 2357936409 ps
CPU time 4.04 seconds
Started Oct 15 01:06:51 PM UTC 24
Finished Oct 15 01:06:56 PM UTC 24
Peak memory 230844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306204460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2306204460 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.2492306750
Short name T50
Test name
Test status
Simulation time 74713400 ps
CPU time 1.82 seconds
Started Oct 15 01:07:13 PM UTC 24
Finished Oct 15 01:07:16 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492306750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2492306750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.1868496535
Short name T304
Test name
Test status
Simulation time 403734022721 ps
CPU time 1494.6 seconds
Started Oct 15 01:05:35 PM UTC 24
Finished Oct 15 01:30:47 PM UTC 24
Peak memory 1945512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868496535 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.1868496535 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.593243904
Short name T42
Test name
Test status
Simulation time 3819222113 ps
CPU time 100.62 seconds
Started Oct 15 01:06:43 PM UTC 24
Finished Oct 15 01:08:25 PM UTC 24
Peak memory 330040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593243904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.593243904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.1456467623
Short name T79
Test name
Test status
Simulation time 6126533187 ps
CPU time 100.27 seconds
Started Oct 15 01:07:22 PM UTC 24
Finished Oct 15 01:09:05 PM UTC 24
Peak memory 298528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456467623 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1456467623 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.3515720589
Short name T37
Test name
Test status
Simulation time 20277331378 ps
CPU time 173.97 seconds
Started Oct 15 01:05:44 PM UTC 24
Finished Oct 15 01:08:41 PM UTC 24
Peak memory 352176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515720589 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3515720589 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.3881599328
Short name T93
Test name
Test status
Simulation time 533899788 ps
CPU time 33.88 seconds
Started Oct 15 01:05:35 PM UTC 24
Finished Oct 15 01:06:10 PM UTC 24
Peak memory 231032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881599328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3881599328 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.3900367233
Short name T95
Test name
Test status
Simulation time 58349008 ps
CPU time 2.87 seconds
Started Oct 15 01:06:30 PM UTC 24
Finished Oct 15 01:06:34 PM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900367233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.3900367233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.4257778811
Short name T196
Test name
Test status
Simulation time 83396659 ps
CPU time 3.72 seconds
Started Oct 15 01:06:31 PM UTC 24
Finished Oct 15 01:06:36 PM UTC 24
Peak memory 231036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257778811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4257778811 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.2905974577
Short name T470
Test name
Test status
Simulation time 381748815808 ps
CPU time 2797.35 seconds
Started Oct 15 01:05:53 PM UTC 24
Finished Oct 15 01:53:03 PM UTC 24
Peak memory 3157788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905974577 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2905974577
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.4163970704
Short name T373
Test name
Test status
Simulation time 175049854845 ps
CPU time 2113.95 seconds
Started Oct 15 01:05:55 PM UTC 24
Finished Oct 15 01:41:31 PM UTC 24
Peak memory 3020696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163970704 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.4163970704
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.1934808774
Short name T306
Test name
Test status
Simulation time 42968298715 ps
CPU time 1468.06 seconds
Started Oct 15 01:06:08 PM UTC 24
Finished Oct 15 01:30:52 PM UTC 24
Peak memory 2279188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934808774 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1934808774
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3740643227
Short name T94
Test name
Test status
Simulation time 748114078 ps
CPU time 17.89 seconds
Started Oct 15 01:06:11 PM UTC 24
Finished Oct 15 01:06:30 PM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740643227 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3740643227
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.2220672589
Short name T440
Test name
Test status
Simulation time 1166473516486 ps
CPU time 2585.34 seconds
Started Oct 15 01:06:22 PM UTC 24
Finished Oct 15 01:49:55 PM UTC 24
Peak memory 3579692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220672589 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2220672
589 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.2720560895
Short name T187
Test name
Test status
Simulation time 6347958101 ps
CPU time 162.08 seconds
Started Oct 15 01:06:23 PM UTC 24
Finished Oct 15 01:09:08 PM UTC 24
Peak memory 360232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720560895 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2720560
895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.2094933719
Short name T510
Test name
Test status
Simulation time 25203196 ps
CPU time 1.23 seconds
Started Oct 15 01:56:17 PM UTC 24
Finished Oct 15 01:56:19 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094933719 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2094933719 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.1487322198
Short name T526
Test name
Test status
Simulation time 14136661338 ps
CPU time 149.56 seconds
Started Oct 15 01:55:49 PM UTC 24
Finished Oct 15 01:58:21 PM UTC 24
Peak memory 298976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487322198 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1487322198 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.3921236972
Short name T521
Test name
Test status
Simulation time 10799541728 ps
CPU time 135.59 seconds
Started Oct 15 01:55:36 PM UTC 24
Finished Oct 15 01:57:54 PM UTC 24
Peak memory 235440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921236972 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3921236972 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2160230386
Short name T542
Test name
Test status
Simulation time 51196302196 ps
CPU time 298.77 seconds
Started Oct 15 01:55:59 PM UTC 24
Finished Oct 15 02:01:03 PM UTC 24
Peak memory 468920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160230386 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2160230386 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.2060620692
Short name T560
Test name
Test status
Simulation time 127040773478 ps
CPU time 409 seconds
Started Oct 15 01:56:04 PM UTC 24
Finished Oct 15 02:02:59 PM UTC 24
Peak memory 499576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060620692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2060620692 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.453799071
Short name T509
Test name
Test status
Simulation time 375289594 ps
CPU time 4.68 seconds
Started Oct 15 01:56:12 PM UTC 24
Finished Oct 15 01:56:17 PM UTC 24
Peak memory 230768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453799071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.453799071 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.173720815
Short name T507
Test name
Test status
Simulation time 40951961 ps
CPU time 1.94 seconds
Started Oct 15 01:56:13 PM UTC 24
Finished Oct 15 01:56:16 PM UTC 24
Peak memory 229832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173720815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.173720815 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.2463869514
Short name T564
Test name
Test status
Simulation time 4463020072 ps
CPU time 512.53 seconds
Started Oct 15 01:55:16 PM UTC 24
Finished Oct 15 02:03:55 PM UTC 24
Peak memory 485296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463869514 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.2463869514 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.3285253808
Short name T554
Test name
Test status
Simulation time 81641990782 ps
CPU time 441.52 seconds
Started Oct 15 01:55:21 PM UTC 24
Finished Oct 15 02:02:48 PM UTC 24
Peak memory 614332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285253808 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3285253808 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.2206966538
Short name T506
Test name
Test status
Simulation time 4040110469 ps
CPU time 56.34 seconds
Started Oct 15 01:55:14 PM UTC 24
Finished Oct 15 01:56:12 PM UTC 24
Peak memory 231012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206966538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2206966538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.3181499680
Short name T512
Test name
Test status
Simulation time 444623121 ps
CPU time 16.07 seconds
Started Oct 15 01:56:17 PM UTC 24
Finished Oct 15 01:56:34 PM UTC 24
Peak memory 245256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181499680 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3181499680 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.174205739
Short name T520
Test name
Test status
Simulation time 35782468 ps
CPU time 1.2 seconds
Started Oct 15 01:57:10 PM UTC 24
Finished Oct 15 01:57:12 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174205739 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.174205739 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.3452977318
Short name T529
Test name
Test status
Simulation time 8659504386 ps
CPU time 122.71 seconds
Started Oct 15 01:56:41 PM UTC 24
Finished Oct 15 01:58:46 PM UTC 24
Peak memory 270256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452977318 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3452977318 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.1957518167
Short name T565
Test name
Test status
Simulation time 9338743880 ps
CPU time 431.17 seconds
Started Oct 15 01:56:39 PM UTC 24
Finished Oct 15 02:03:55 PM UTC 24
Peak memory 247784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957518167 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1957518167 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.2465682391
Short name T561
Test name
Test status
Simulation time 38845572532 ps
CPU time 385.92 seconds
Started Oct 15 01:56:42 PM UTC 24
Finished Oct 15 02:03:13 PM UTC 24
Peak memory 583792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465682391 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2465682391 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.3334971503
Short name T517
Test name
Test status
Simulation time 379298456 ps
CPU time 9.21 seconds
Started Oct 15 01:56:55 PM UTC 24
Finished Oct 15 01:57:05 PM UTC 24
Peak memory 232960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334971503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3334971503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.2547201660
Short name T518
Test name
Test status
Simulation time 141449579 ps
CPU time 2.42 seconds
Started Oct 15 01:57:03 PM UTC 24
Finished Oct 15 01:57:07 PM UTC 24
Peak memory 230492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547201660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2547201660 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.1559884609
Short name T519
Test name
Test status
Simulation time 48616139 ps
CPU time 1.78 seconds
Started Oct 15 01:57:06 PM UTC 24
Finished Oct 15 01:57:09 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559884609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1559884609 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.1939385386
Short name T748
Test name
Test status
Simulation time 25320790279 ps
CPU time 2578.84 seconds
Started Oct 15 01:56:20 PM UTC 24
Finished Oct 15 02:39:48 PM UTC 24
Peak memory 1781736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939385386 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.1939385386 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.196225507
Short name T528
Test name
Test status
Simulation time 19604423121 ps
CPU time 111.58 seconds
Started Oct 15 01:56:34 PM UTC 24
Finished Oct 15 01:58:28 PM UTC 24
Peak memory 286892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196225507 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.196225507 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload_invalid.3830915104
Short name T514
Test name
Test status
Simulation time 139831271 ps
CPU time 4.3 seconds
Started Oct 15 01:56:36 PM UTC 24
Finished Oct 15 01:56:41 PM UTC 24
Peak memory 233472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830915104 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload_invalid.3830915104 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.3554469770
Short name T513
Test name
Test status
Simulation time 320660420 ps
CPU time 18.55 seconds
Started Oct 15 01:56:18 PM UTC 24
Finished Oct 15 01:56:38 PM UTC 24
Peak memory 230908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554469770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3554469770 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.2846162752
Short name T522
Test name
Test status
Simulation time 2614856520 ps
CPU time 45.9 seconds
Started Oct 15 01:57:07 PM UTC 24
Finished Oct 15 01:57:55 PM UTC 24
Peak memory 245692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846162752 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2846162752 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.4026512262
Short name T533
Test name
Test status
Simulation time 20016164 ps
CPU time 1.27 seconds
Started Oct 15 01:58:51 PM UTC 24
Finished Oct 15 01:58:54 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026512262 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.4026512262 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.4145882702
Short name T569
Test name
Test status
Simulation time 150455300454 ps
CPU time 360.29 seconds
Started Oct 15 01:58:04 PM UTC 24
Finished Oct 15 02:04:09 PM UTC 24
Peak memory 507744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145882702 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.4145882702 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.1949599098
Short name T171
Test name
Test status
Simulation time 6026700486 ps
CPU time 723.87 seconds
Started Oct 15 01:58:04 PM UTC 24
Finished Oct 15 02:10:17 PM UTC 24
Peak memory 247724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949599098 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1949599098 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2491726039
Short name T556
Test name
Test status
Simulation time 35534040748 ps
CPU time 263.89 seconds
Started Oct 15 01:58:23 PM UTC 24
Finished Oct 15 02:02:51 PM UTC 24
Peak memory 386620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491726039 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2491726039 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.1591448435
Short name T545
Test name
Test status
Simulation time 9950770864 ps
CPU time 201.01 seconds
Started Oct 15 01:58:23 PM UTC 24
Finished Oct 15 02:01:47 PM UTC 24
Peak memory 327728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591448435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1591448435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.2743416219
Short name T530
Test name
Test status
Simulation time 1707212037 ps
CPU time 18.12 seconds
Started Oct 15 01:58:29 PM UTC 24
Finished Oct 15 01:58:48 PM UTC 24
Peak memory 230952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743416219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2743416219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.1911172340
Short name T531
Test name
Test status
Simulation time 48494450 ps
CPU time 2.07 seconds
Started Oct 15 01:58:47 PM UTC 24
Finished Oct 15 01:58:50 PM UTC 24
Peak memory 230776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911172340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1911172340 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.2792331375
Short name T750
Test name
Test status
Simulation time 92959153674 ps
CPU time 2553.58 seconds
Started Oct 15 01:57:55 PM UTC 24
Finished Oct 15 02:40:56 PM UTC 24
Peak memory 1865644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792331375 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.2792331375 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.3362188638
Short name T582
Test name
Test status
Simulation time 91677026828 ps
CPU time 432.95 seconds
Started Oct 15 01:57:56 PM UTC 24
Finished Oct 15 02:05:15 PM UTC 24
Peak memory 640888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362188638 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3362188638 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.4270107536
Short name T523
Test name
Test status
Simulation time 2798613723 ps
CPU time 44.1 seconds
Started Oct 15 01:57:13 PM UTC 24
Finished Oct 15 01:57:58 PM UTC 24
Peak memory 231044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270107536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.4270107536 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.2494098092
Short name T642
Test name
Test status
Simulation time 135737906342 ps
CPU time 1039.01 seconds
Started Oct 15 01:58:49 PM UTC 24
Finished Oct 15 02:16:20 PM UTC 24
Peak memory 1163136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494098092 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2494098092 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.4127623721
Short name T543
Test name
Test status
Simulation time 44207090 ps
CPU time 1.13 seconds
Started Oct 15 02:01:03 PM UTC 24
Finished Oct 15 02:01:06 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127623721 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.4127623721 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.2565978625
Short name T562
Test name
Test status
Simulation time 81169112171 ps
CPU time 224.9 seconds
Started Oct 15 01:59:56 PM UTC 24
Finished Oct 15 02:03:45 PM UTC 24
Peak memory 456600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565978625 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2565978625 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.130818268
Short name T632
Test name
Test status
Simulation time 27452167823 ps
CPU time 867.42 seconds
Started Oct 15 01:59:09 PM UTC 24
Finished Oct 15 02:13:48 PM UTC 24
Peak memory 264120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130818268 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.130818268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.764635368
Short name T573
Test name
Test status
Simulation time 16471419854 ps
CPU time 263.88 seconds
Started Oct 15 01:59:57 PM UTC 24
Finished Oct 15 02:04:25 PM UTC 24
Peak memory 479156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764635368 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.764635368 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.1263965538
Short name T597
Test name
Test status
Simulation time 12771412645 ps
CPU time 393.13 seconds
Started Oct 15 02:00:07 PM UTC 24
Finished Oct 15 02:06:45 PM UTC 24
Peak memory 587704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263965538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1263965538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.448377897
Short name T540
Test name
Test status
Simulation time 501443590 ps
CPU time 3.59 seconds
Started Oct 15 02:00:38 PM UTC 24
Finished Oct 15 02:00:43 PM UTC 24
Peak memory 230780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448377897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.448377897 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.321945828
Short name T541
Test name
Test status
Simulation time 108505405 ps
CPU time 1.82 seconds
Started Oct 15 02:00:44 PM UTC 24
Finished Oct 15 02:00:47 PM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321945828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.321945828 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.107676724
Short name T752
Test name
Test status
Simulation time 101195294136 ps
CPU time 2580.12 seconds
Started Oct 15 01:58:53 PM UTC 24
Finished Oct 15 02:42:21 PM UTC 24
Peak memory 1822700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107676724 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.107676724 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.3158550703
Short name T575
Test name
Test status
Simulation time 41999098222 ps
CPU time 334.94 seconds
Started Oct 15 01:58:55 PM UTC 24
Finished Oct 15 02:04:34 PM UTC 24
Peak memory 511896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158550703 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3158550703 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload_invalid.1172029521
Short name T535
Test name
Test status
Simulation time 59082141 ps
CPU time 4.17 seconds
Started Oct 15 01:59:03 PM UTC 24
Finished Oct 15 01:59:08 PM UTC 24
Peak memory 231364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172029521 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload_invalid.1172029521 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.1081327406
Short name T536
Test name
Test status
Simulation time 965993682 ps
CPU time 62.62 seconds
Started Oct 15 01:58:51 PM UTC 24
Finished Oct 15 01:59:56 PM UTC 24
Peak memory 235300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081327406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1081327406 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.1582946246
Short name T671
Test name
Test status
Simulation time 52780883509 ps
CPU time 1136.25 seconds
Started Oct 15 02:00:48 PM UTC 24
Finished Oct 15 02:19:57 PM UTC 24
Peak memory 868284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582946246 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1582946246 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.2818744853
Short name T557
Test name
Test status
Simulation time 45377665 ps
CPU time 1.24 seconds
Started Oct 15 02:02:48 PM UTC 24
Finished Oct 15 02:02:51 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818744853 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2818744853 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.1772962257
Short name T563
Test name
Test status
Simulation time 22161051292 ps
CPU time 103.2 seconds
Started Oct 15 02:02:05 PM UTC 24
Finished Oct 15 02:03:50 PM UTC 24
Peak memory 286648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772962257 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1772962257 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.2790651945
Short name T607
Test name
Test status
Simulation time 23381546625 ps
CPU time 439.6 seconds
Started Oct 15 02:01:59 PM UTC 24
Finished Oct 15 02:09:24 PM UTC 24
Peak memory 245624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790651945 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.2790651945 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2635058966
Short name T550
Test name
Test status
Simulation time 36502052 ps
CPU time 3.61 seconds
Started Oct 15 02:02:18 PM UTC 24
Finished Oct 15 02:02:22 PM UTC 24
Peak memory 228796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635058966 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2635058966 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.3504500063
Short name T551
Test name
Test status
Simulation time 677726384 ps
CPU time 12.67 seconds
Started Oct 15 02:02:24 PM UTC 24
Finished Oct 15 02:02:38 PM UTC 24
Peak memory 235572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504500063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3504500063 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.2362683995
Short name T555
Test name
Test status
Simulation time 1027118868 ps
CPU time 10.04 seconds
Started Oct 15 02:02:39 PM UTC 24
Finished Oct 15 02:02:50 PM UTC 24
Peak memory 230952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362683995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2362683995 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.3537918617
Short name T553
Test name
Test status
Simulation time 45286073 ps
CPU time 2.07 seconds
Started Oct 15 02:02:40 PM UTC 24
Finished Oct 15 02:02:43 PM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537918617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3537918617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.31010153
Short name T558
Test name
Test status
Simulation time 1956793477 ps
CPU time 92.14 seconds
Started Oct 15 02:01:18 PM UTC 24
Finished Oct 15 02:02:52 PM UTC 24
Peak memory 272244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31010153 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.31010153 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.3684111600
Short name T570
Test name
Test status
Simulation time 1713766587 ps
CPU time 139.29 seconds
Started Oct 15 02:01:48 PM UTC 24
Finished Oct 15 02:04:10 PM UTC 24
Peak memory 290684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684111600 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3684111600 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload_invalid.2990011698
Short name T547
Test name
Test status
Simulation time 139989890 ps
CPU time 2.87 seconds
Started Oct 15 02:01:54 PM UTC 24
Finished Oct 15 02:01:58 PM UTC 24
Peak memory 231280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990011698 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload_invalid.2990011698 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.2888049406
Short name T549
Test name
Test status
Simulation time 11265219887 ps
CPU time 68.41 seconds
Started Oct 15 02:01:07 PM UTC 24
Finished Oct 15 02:02:17 PM UTC 24
Peak memory 235484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888049406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2888049406 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.2509039545
Short name T576
Test name
Test status
Simulation time 5300749233 ps
CPU time 108.23 seconds
Started Oct 15 02:02:44 PM UTC 24
Finished Oct 15 02:04:35 PM UTC 24
Peak memory 280884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509039545 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2509039545 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.1271577404
Short name T568
Test name
Test status
Simulation time 45918075 ps
CPU time 1.23 seconds
Started Oct 15 02:03:59 PM UTC 24
Finished Oct 15 02:04:02 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271577404 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1271577404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.3314269543
Short name T577
Test name
Test status
Simulation time 9041993381 ps
CPU time 95.85 seconds
Started Oct 15 02:03:00 PM UTC 24
Finished Oct 15 02:04:38 PM UTC 24
Peak memory 301112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314269543 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3314269543 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.3062668227
Short name T654
Test name
Test status
Simulation time 27795224233 ps
CPU time 906.67 seconds
Started Oct 15 02:02:58 PM UTC 24
Finished Oct 15 02:18:15 PM UTC 24
Peak memory 264032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062668227 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3062668227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.2148311369
Short name T583
Test name
Test status
Simulation time 11308273103 ps
CPU time 123.84 seconds
Started Oct 15 02:03:14 PM UTC 24
Finished Oct 15 02:05:20 PM UTC 24
Peak memory 341988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148311369 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2148311369 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.2915476475
Short name T608
Test name
Test status
Simulation time 20881205289 ps
CPU time 339.34 seconds
Started Oct 15 02:03:46 PM UTC 24
Finished Oct 15 02:09:30 PM UTC 24
Peak memory 354276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915476475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2915476475 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.3359952508
Short name T566
Test name
Test status
Simulation time 442603453 ps
CPU time 5.18 seconds
Started Oct 15 02:03:51 PM UTC 24
Finished Oct 15 02:03:58 PM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359952508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3359952508 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.1157660501
Short name T567
Test name
Test status
Simulation time 59511166 ps
CPU time 3.16 seconds
Started Oct 15 02:03:56 PM UTC 24
Finished Oct 15 02:04:00 PM UTC 24
Peak memory 235180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157660501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1157660501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.3527913648
Short name T760
Test name
Test status
Simulation time 295878837718 ps
CPU time 3175.26 seconds
Started Oct 15 02:02:52 PM UTC 24
Finished Oct 15 02:56:22 PM UTC 24
Peak memory 3653684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527913648 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.3527913648 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.1473332976
Short name T596
Test name
Test status
Simulation time 6180585996 ps
CPU time 226.72 seconds
Started Oct 15 02:02:52 PM UTC 24
Finished Oct 15 02:06:42 PM UTC 24
Peak memory 339900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473332976 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1473332976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload_invalid.1880937835
Short name T559
Test name
Test status
Simulation time 109153267 ps
CPU time 3.31 seconds
Started Oct 15 02:02:53 PM UTC 24
Finished Oct 15 02:02:57 PM UTC 24
Peak memory 231340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880937835 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload_invalid.1880937835 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.3947088402
Short name T574
Test name
Test status
Simulation time 40784983928 ps
CPU time 98.15 seconds
Started Oct 15 02:02:51 PM UTC 24
Finished Oct 15 02:04:31 PM UTC 24
Peak memory 233128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947088402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3947088402 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.4103184713
Short name T649
Test name
Test status
Simulation time 109031140823 ps
CPU time 790.78 seconds
Started Oct 15 02:03:56 PM UTC 24
Finished Oct 15 02:17:16 PM UTC 24
Peak memory 1050660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103184713 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.4103184713 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.1226708032
Short name T580
Test name
Test status
Simulation time 21201341 ps
CPU time 1.29 seconds
Started Oct 15 02:04:40 PM UTC 24
Finished Oct 15 02:04:42 PM UTC 24
Peak memory 214132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226708032 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1226708032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.837561798
Short name T619
Test name
Test status
Simulation time 97326481366 ps
CPU time 420.61 seconds
Started Oct 15 02:04:24 PM UTC 24
Finished Oct 15 02:11:31 PM UTC 24
Peak memory 559004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837561798 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.837561798 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.3088024066
Short name T612
Test name
Test status
Simulation time 3268048921 ps
CPU time 327.32 seconds
Started Oct 15 02:04:17 PM UTC 24
Finished Oct 15 02:09:49 PM UTC 24
Peak memory 241728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088024066 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3088024066 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2390706507
Short name T599
Test name
Test status
Simulation time 27022285437 ps
CPU time 160.05 seconds
Started Oct 15 02:04:26 PM UTC 24
Finished Oct 15 02:07:09 PM UTC 24
Peak memory 341936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390706507 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2390706507 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.502469631
Short name T617
Test name
Test status
Simulation time 72926452569 ps
CPU time 400.65 seconds
Started Oct 15 02:04:32 PM UTC 24
Finished Oct 15 02:11:17 PM UTC 24
Peak memory 620440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502469631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.502469631 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.1855089072
Short name T579
Test name
Test status
Simulation time 204902098 ps
CPU time 3.03 seconds
Started Oct 15 02:04:36 PM UTC 24
Finished Oct 15 02:04:40 PM UTC 24
Peak memory 230708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855089072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1855089072 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.3965912034
Short name T578
Test name
Test status
Simulation time 194896351 ps
CPU time 1.92 seconds
Started Oct 15 02:04:36 PM UTC 24
Finished Oct 15 02:04:39 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965912034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3965912034 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.2521593860
Short name T675
Test name
Test status
Simulation time 138390306058 ps
CPU time 991.96 seconds
Started Oct 15 02:04:03 PM UTC 24
Finished Oct 15 02:20:45 PM UTC 24
Peak memory 1722428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521593860 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.2521593860 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.1659334529
Short name T572
Test name
Test status
Simulation time 163570728 ps
CPU time 11.27 seconds
Started Oct 15 02:04:11 PM UTC 24
Finished Oct 15 02:04:23 PM UTC 24
Peak memory 232604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659334529 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1659334529 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload_invalid.3609199288
Short name T571
Test name
Test status
Simulation time 1133807805 ps
CPU time 3.98 seconds
Started Oct 15 02:04:11 PM UTC 24
Finished Oct 15 02:04:16 PM UTC 24
Peak memory 231088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609199288 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload_invalid.3609199288 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.3579598139
Short name T581
Test name
Test status
Simulation time 3851707070 ps
CPU time 59.97 seconds
Started Oct 15 02:04:01 PM UTC 24
Finished Oct 15 02:05:03 PM UTC 24
Peak memory 231068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579598139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3579598139 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.1507497415
Short name T745
Test name
Test status
Simulation time 63139138178 ps
CPU time 1975.68 seconds
Started Oct 15 02:04:39 PM UTC 24
Finished Oct 15 02:37:57 PM UTC 24
Peak memory 2003236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507497415 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1507497415 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.2986034868
Short name T591
Test name
Test status
Simulation time 16142664 ps
CPU time 1.23 seconds
Started Oct 15 02:05:51 PM UTC 24
Finished Oct 15 02:05:53 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986034868 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2986034868 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.817323993
Short name T609
Test name
Test status
Simulation time 7847051199 ps
CPU time 251.11 seconds
Started Oct 15 02:05:21 PM UTC 24
Finished Oct 15 02:09:36 PM UTC 24
Peak memory 335928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817323993 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.817323993 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.498127296
Short name T590
Test name
Test status
Simulation time 318909468 ps
CPU time 27.83 seconds
Started Oct 15 02:05:21 PM UTC 24
Finished Oct 15 02:05:50 PM UTC 24
Peak memory 231164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498127296 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.498127296 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.1124998904
Short name T605
Test name
Test status
Simulation time 5699981459 ps
CPU time 223.78 seconds
Started Oct 15 02:05:23 PM UTC 24
Finished Oct 15 02:09:10 PM UTC 24
Peak memory 323508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124998904 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1124998904 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.2224406628
Short name T598
Test name
Test status
Simulation time 2822965870 ps
CPU time 95.95 seconds
Started Oct 15 02:05:29 PM UTC 24
Finished Oct 15 02:07:08 PM UTC 24
Peak memory 268284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224406628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2224406628 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.3396332063
Short name T588
Test name
Test status
Simulation time 422645174 ps
CPU time 2.03 seconds
Started Oct 15 02:05:33 PM UTC 24
Finished Oct 15 02:05:36 PM UTC 24
Peak memory 230688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396332063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3396332063 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.2023906662
Short name T589
Test name
Test status
Simulation time 56945390 ps
CPU time 2.01 seconds
Started Oct 15 02:05:37 PM UTC 24
Finished Oct 15 02:05:40 PM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023906662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2023906662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.301047270
Short name T735
Test name
Test status
Simulation time 54514423287 ps
CPU time 1593.81 seconds
Started Oct 15 02:04:43 PM UTC 24
Finished Oct 15 02:31:35 PM UTC 24
Peak memory 2082684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301047270 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.301047270 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.605249099
Short name T584
Test name
Test status
Simulation time 4667828031 ps
CPU time 14.6 seconds
Started Oct 15 02:05:05 PM UTC 24
Finished Oct 15 02:05:20 PM UTC 24
Peak memory 245428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605249099 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.605249099 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.1232406421
Short name T585
Test name
Test status
Simulation time 11993318380 ps
CPU time 39.3 seconds
Started Oct 15 02:04:41 PM UTC 24
Finished Oct 15 02:05:22 PM UTC 24
Peak memory 230980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232406421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1232406421 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.2016966865
Short name T753
Test name
Test status
Simulation time 814794397037 ps
CPU time 2203 seconds
Started Oct 15 02:05:41 PM UTC 24
Finished Oct 15 02:42:49 PM UTC 24
Peak memory 1229068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016966865 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2016966865 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.1541990482
Short name T601
Test name
Test status
Simulation time 76438940 ps
CPU time 0.96 seconds
Started Oct 15 02:08:16 PM UTC 24
Finished Oct 15 02:08:18 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541990482 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1541990482 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.1585138935
Short name T614
Test name
Test status
Simulation time 23214112770 ps
CPU time 248.76 seconds
Started Oct 15 02:06:28 PM UTC 24
Finished Oct 15 02:10:41 PM UTC 24
Peak memory 473008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585138935 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1585138935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.22788142
Short name T631
Test name
Test status
Simulation time 12429727967 ps
CPU time 422.35 seconds
Started Oct 15 02:06:28 PM UTC 24
Finished Oct 15 02:13:36 PM UTC 24
Peak memory 251800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22788142 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.22788142 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.263145629
Short name T602
Test name
Test status
Simulation time 14656543138 ps
CPU time 105.87 seconds
Started Oct 15 02:06:43 PM UTC 24
Finished Oct 15 02:08:31 PM UTC 24
Peak memory 262016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263145629 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.263145629 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.3917024641
Short name T616
Test name
Test status
Simulation time 17189560684 ps
CPU time 243.82 seconds
Started Oct 15 02:06:46 PM UTC 24
Finished Oct 15 02:10:54 PM UTC 24
Peak memory 323644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917024641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3917024641 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.2187729687
Short name T600
Test name
Test status
Simulation time 1997190982 ps
CPU time 9.89 seconds
Started Oct 15 02:07:09 PM UTC 24
Finished Oct 15 02:07:20 PM UTC 24
Peak memory 230704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187729687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2187729687 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.2365593909
Short name T71
Test name
Test status
Simulation time 1019448721 ps
CPU time 61.99 seconds
Started Oct 15 02:07:10 PM UTC 24
Finished Oct 15 02:08:14 PM UTC 24
Peak memory 257968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365593909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2365593909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.2222902491
Short name T656
Test name
Test status
Simulation time 18669341118 ps
CPU time 730.38 seconds
Started Oct 15 02:06:03 PM UTC 24
Finished Oct 15 02:18:23 PM UTC 24
Peak memory 1083512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222902491 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.2222902491 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.1314271222
Short name T595
Test name
Test status
Simulation time 1253571267 ps
CPU time 15.67 seconds
Started Oct 15 02:06:11 PM UTC 24
Finished Oct 15 02:06:27 PM UTC 24
Peak memory 235016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314271222 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1314271222 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload_invalid.1208952033
Short name T594
Test name
Test status
Simulation time 118615081 ps
CPU time 1.79 seconds
Started Oct 15 02:06:24 PM UTC 24
Finished Oct 15 02:06:27 PM UTC 24
Peak memory 230168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208952033 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload_invalid.1208952033 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.2110873625
Short name T593
Test name
Test status
Simulation time 1083284377 ps
CPU time 27.64 seconds
Started Oct 15 02:05:54 PM UTC 24
Finished Oct 15 02:06:23 PM UTC 24
Peak memory 230944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110873625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2110873625 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.4108436596
Short name T725
Test name
Test status
Simulation time 77599244030 ps
CPU time 1275.42 seconds
Started Oct 15 02:07:21 PM UTC 24
Finished Oct 15 02:28:51 PM UTC 24
Peak memory 870656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108436596 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.4108436596 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.3763721476
Short name T613
Test name
Test status
Simulation time 18320348 ps
CPU time 1.23 seconds
Started Oct 15 02:09:50 PM UTC 24
Finished Oct 15 02:09:52 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763721476 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3763721476 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.4251236543
Short name T627
Test name
Test status
Simulation time 27196579808 ps
CPU time 168.8 seconds
Started Oct 15 02:09:14 PM UTC 24
Finished Oct 15 02:12:05 PM UTC 24
Peak memory 372784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251236543 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.4251236543 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.427379715
Short name T723
Test name
Test status
Simulation time 108844588103 ps
CPU time 1112.35 seconds
Started Oct 15 02:09:11 PM UTC 24
Finished Oct 15 02:27:57 PM UTC 24
Peak memory 270264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427379715 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.427379715 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.2295102765
Short name T643
Test name
Test status
Simulation time 24437167437 ps
CPU time 414.27 seconds
Started Oct 15 02:09:25 PM UTC 24
Finished Oct 15 02:16:25 PM UTC 24
Peak memory 352240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295102765 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2295102765 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.598934121
Short name T618
Test name
Test status
Simulation time 15739310288 ps
CPU time 108.26 seconds
Started Oct 15 02:09:31 PM UTC 24
Finished Oct 15 02:11:22 PM UTC 24
Peak memory 343996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598934121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.598934121 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.604355076
Short name T610
Test name
Test status
Simulation time 984707906 ps
CPU time 4.91 seconds
Started Oct 15 02:09:36 PM UTC 24
Finished Oct 15 02:09:42 PM UTC 24
Peak memory 230804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604355076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.604355076 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.2392896834
Short name T611
Test name
Test status
Simulation time 48024442 ps
CPU time 1.67 seconds
Started Oct 15 02:09:43 PM UTC 24
Finished Oct 15 02:09:46 PM UTC 24
Peak memory 230012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392896834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2392896834 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.750985710
Short name T757
Test name
Test status
Simulation time 89118241029 ps
CPU time 2260.46 seconds
Started Oct 15 02:08:32 PM UTC 24
Finished Oct 15 02:46:38 PM UTC 24
Peak memory 1625980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750985710 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.750985710 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.876011284
Short name T626
Test name
Test status
Simulation time 7185606190 ps
CPU time 183.6 seconds
Started Oct 15 02:08:56 PM UTC 24
Finished Oct 15 02:12:03 PM UTC 24
Peak memory 294888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876011284 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.876011284 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload_invalid.4247501320
Short name T606
Test name
Test status
Simulation time 567909004 ps
CPU time 4.72 seconds
Started Oct 15 02:09:06 PM UTC 24
Finished Oct 15 02:09:12 PM UTC 24
Peak memory 231416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247501320 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload_invalid.4247501320 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.2826985172
Short name T604
Test name
Test status
Simulation time 3583539734 ps
CPU time 45.5 seconds
Started Oct 15 02:08:19 PM UTC 24
Finished Oct 15 02:09:06 PM UTC 24
Peak memory 231104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826985172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2826985172 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.159349273
Short name T697
Test name
Test status
Simulation time 107796696990 ps
CPU time 886.01 seconds
Started Oct 15 02:09:46 PM UTC 24
Finished Oct 15 02:24:43 PM UTC 24
Peak memory 1099704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159349273 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.159349273 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.391938480
Short name T206
Test name
Test status
Simulation time 16514664 ps
CPU time 1.26 seconds
Started Oct 15 01:09:50 PM UTC 24
Finished Oct 15 01:09:52 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391938480 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.391938480 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.2839040285
Short name T210
Test name
Test status
Simulation time 106394315324 ps
CPU time 115.11 seconds
Started Oct 15 01:08:47 PM UTC 24
Finished Oct 15 01:10:44 PM UTC 24
Peak memory 311352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839040285 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2839040285 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2513414142
Short name T191
Test name
Test status
Simulation time 22402800137 ps
CPU time 41.52 seconds
Started Oct 15 01:08:50 PM UTC 24
Finished Oct 15 01:09:33 PM UTC 24
Peak memory 257924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513414142 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2513414142 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.2324509562
Short name T147
Test name
Test status
Simulation time 26478600396 ps
CPU time 252.13 seconds
Started Oct 15 01:08:06 PM UTC 24
Finished Oct 15 01:12:21 PM UTC 24
Peak memory 245692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324509562 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2324509562 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.2167274880
Short name T204
Test name
Test status
Simulation time 2161803704 ps
CPU time 37.02 seconds
Started Oct 15 01:09:09 PM UTC 24
Finished Oct 15 01:09:48 PM UTC 24
Peak memory 230820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167274880 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2167274880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.3285096768
Short name T205
Test name
Test status
Simulation time 782941811 ps
CPU time 19.62 seconds
Started Oct 15 01:09:28 PM UTC 24
Finished Oct 15 01:09:49 PM UTC 24
Peak memory 235168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285096768 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3285096768 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.692950888
Short name T211
Test name
Test status
Simulation time 24831692595 ps
CPU time 78.58 seconds
Started Oct 15 01:09:33 PM UTC 24
Finished Oct 15 01:10:54 PM UTC 24
Peak memory 231148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692950888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.692950888 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.2270436825
Short name T207
Test name
Test status
Simulation time 2432240333 ps
CPU time 92.13 seconds
Started Oct 15 01:09:01 PM UTC 24
Finished Oct 15 01:10:35 PM UTC 24
Peak memory 268144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270436825 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.2270436825 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.3748572325
Short name T77
Test name
Test status
Simulation time 6139149333 ps
CPU time 16.78 seconds
Started Oct 15 01:09:09 PM UTC 24
Finished Oct 15 01:09:27 PM UTC 24
Peak memory 230540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748572325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3748572325 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1436875696
Short name T525
Test name
Test status
Simulation time 288540771621 ps
CPU time 2988.03 seconds
Started Oct 15 01:07:42 PM UTC 24
Finished Oct 15 01:58:03 PM UTC 24
Peak memory 3584084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436875696 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1436875696 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.4079838202
Short name T89
Test name
Test status
Simulation time 17202049986 ps
CPU time 358.7 seconds
Started Oct 15 01:09:03 PM UTC 24
Finished Oct 15 01:15:07 PM UTC 24
Peak memory 342400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079838202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.4079838202 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.1129124957
Short name T80
Test name
Test status
Simulation time 98471243842 ps
CPU time 80.85 seconds
Started Oct 15 01:09:49 PM UTC 24
Finished Oct 15 01:11:11 PM UTC 24
Peak memory 292320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129124957 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1129124957 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.1440850917
Short name T39
Test name
Test status
Simulation time 11670431188 ps
CPU time 176.01 seconds
Started Oct 15 01:07:45 PM UTC 24
Finished Oct 15 01:10:44 PM UTC 24
Peak memory 298876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440850917 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1440850917 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload_invalid.3114809353
Short name T76
Test name
Test status
Simulation time 617508403 ps
CPU time 5.79 seconds
Started Oct 15 01:08:02 PM UTC 24
Finished Oct 15 01:08:09 PM UTC 24
Peak memory 231472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114809353 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload_invalid.3114809353 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.447916978
Short name T193
Test name
Test status
Simulation time 975765122 ps
CPU time 63.44 seconds
Started Oct 15 01:07:39 PM UTC 24
Finished Oct 15 01:08:44 PM UTC 24
Peak memory 234992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447916978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.447916978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1700395330
Short name T200
Test name
Test status
Simulation time 42551894 ps
CPU time 3.35 seconds
Started Oct 15 01:08:41 PM UTC 24
Finished Oct 15 01:08:46 PM UTC 24
Peak memory 231040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700395330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1700395330 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.3413288344
Short name T201
Test name
Test status
Simulation time 383382370 ps
CPU time 3.03 seconds
Started Oct 15 01:08:45 PM UTC 24
Finished Oct 15 01:08:49 PM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413288344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3413288344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.3699027343
Short name T504
Test name
Test status
Simulation time 370447230923 ps
CPU time 2837.71 seconds
Started Oct 15 01:08:09 PM UTC 24
Finished Oct 15 01:55:58 PM UTC 24
Peak memory 3188504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699027343 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3699027343
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.465026754
Short name T329
Test name
Test status
Simulation time 40341013074 ps
CPU time 1507.81 seconds
Started Oct 15 01:08:15 PM UTC 24
Finished Oct 15 01:33:40 PM UTC 24
Peak memory 1095576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465026754 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.465026754 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.1529990581
Short name T299
Test name
Test status
Simulation time 138577757896 ps
CPU time 1195.77 seconds
Started Oct 15 01:08:26 PM UTC 24
Finished Oct 15 01:28:36 PM UTC 24
Peak memory 894744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529990581 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1529990581
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.4188113690
Short name T202
Test name
Test status
Simulation time 2202120037 ps
CPU time 26.54 seconds
Started Oct 15 01:08:32 PM UTC 24
Finished Oct 15 01:09:00 PM UTC 24
Peak memory 230960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188113690 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4188113690
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.184705969
Short name T221
Test name
Test status
Simulation time 10240897661 ps
CPU time 246.32 seconds
Started Oct 15 01:08:35 PM UTC 24
Finished Oct 15 01:12:46 PM UTC 24
Peak memory 442216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184705969 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.18470596
9 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.613255018
Short name T194
Test name
Test status
Simulation time 30923300586 ps
CPU time 385.22 seconds
Started Oct 15 01:08:41 PM UTC 24
Finished Oct 15 01:15:12 PM UTC 24
Peak memory 362268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613255018 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.61325501
8 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.3695856319
Short name T624
Test name
Test status
Simulation time 23230635 ps
CPU time 1.18 seconds
Started Oct 15 02:11:41 PM UTC 24
Finished Oct 15 02:11:43 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695856319 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3695856319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.2708846837
Short name T639
Test name
Test status
Simulation time 17816898538 ps
CPU time 258.93 seconds
Started Oct 15 02:11:00 PM UTC 24
Finished Oct 15 02:15:22 PM UTC 24
Peak memory 348088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708846837 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.2708846837 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.651071006
Short name T693
Test name
Test status
Simulation time 76714326228 ps
CPU time 777.13 seconds
Started Oct 15 02:10:55 PM UTC 24
Finished Oct 15 02:24:01 PM UTC 24
Peak memory 262076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651071006 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.651071006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.3607769948
Short name T650
Test name
Test status
Simulation time 49603396065 ps
CPU time 366.97 seconds
Started Oct 15 02:11:18 PM UTC 24
Finished Oct 15 02:17:30 PM UTC 24
Peak memory 489400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607769948 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3607769948 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.2137868553
Short name T620
Test name
Test status
Simulation time 662897117 ps
CPU time 11.65 seconds
Started Oct 15 02:11:22 PM UTC 24
Finished Oct 15 02:11:35 PM UTC 24
Peak memory 249716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137868553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2137868553 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.3559042251
Short name T623
Test name
Test status
Simulation time 3054586760 ps
CPU time 10.44 seconds
Started Oct 15 02:11:31 PM UTC 24
Finished Oct 15 02:11:43 PM UTC 24
Peak memory 230832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559042251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3559042251 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.466035171
Short name T621
Test name
Test status
Simulation time 84607565 ps
CPU time 1.85 seconds
Started Oct 15 02:11:36 PM UTC 24
Finished Oct 15 02:11:38 PM UTC 24
Peak memory 229972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466035171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.466035171 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.823450697
Short name T754
Test name
Test status
Simulation time 39079503869 ps
CPU time 1993.58 seconds
Started Oct 15 02:10:18 PM UTC 24
Finished Oct 15 02:43:55 PM UTC 24
Peak memory 1429364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823450697 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.823450697 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.2788698977
Short name T630
Test name
Test status
Simulation time 14157139092 ps
CPU time 126.08 seconds
Started Oct 15 02:10:42 PM UTC 24
Finished Oct 15 02:12:51 PM UTC 24
Peak memory 335804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788698977 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2788698977 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload_invalid.2207148504
Short name T29
Test name
Test status
Simulation time 205178353 ps
CPU time 4.14 seconds
Started Oct 15 02:10:53 PM UTC 24
Finished Oct 15 02:10:59 PM UTC 24
Peak memory 231304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207148504 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload_invalid.2207148504 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.3592574357
Short name T615
Test name
Test status
Simulation time 2844865511 ps
CPU time 58.26 seconds
Started Oct 15 02:09:53 PM UTC 24
Finished Oct 15 02:10:53 PM UTC 24
Peak memory 231012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592574357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3592574357 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.3800086528
Short name T743
Test name
Test status
Simulation time 45745239022 ps
CPU time 1427.4 seconds
Started Oct 15 02:11:40 PM UTC 24
Finished Oct 15 02:35:45 PM UTC 24
Peak memory 1315112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800086528 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3800086528 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.2435428109
Short name T635
Test name
Test status
Simulation time 47784835 ps
CPU time 1.2 seconds
Started Oct 15 02:14:00 PM UTC 24
Finished Oct 15 02:14:02 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435428109 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2435428109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.564660713
Short name T651
Test name
Test status
Simulation time 29855842210 ps
CPU time 287.01 seconds
Started Oct 15 02:12:45 PM UTC 24
Finished Oct 15 02:17:36 PM UTC 24
Peak memory 340000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564660713 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.564660713 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.4115048426
Short name T652
Test name
Test status
Simulation time 20622479572 ps
CPU time 339.01 seconds
Started Oct 15 02:12:06 PM UTC 24
Finished Oct 15 02:17:49 PM UTC 24
Peak memory 251832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115048426 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.4115048426 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.1472615628
Short name T641
Test name
Test status
Simulation time 39120985454 ps
CPU time 195.05 seconds
Started Oct 15 02:12:51 PM UTC 24
Finished Oct 15 02:16:09 PM UTC 24
Peak memory 421764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472615628 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1472615628 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.3314300089
Short name T640
Test name
Test status
Simulation time 1804457169 ps
CPU time 171.8 seconds
Started Oct 15 02:12:51 PM UTC 24
Finished Oct 15 02:15:46 PM UTC 24
Peak memory 300864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314300089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3314300089 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.877394261
Short name T634
Test name
Test status
Simulation time 3930058843 ps
CPU time 19.73 seconds
Started Oct 15 02:13:37 PM UTC 24
Finished Oct 15 02:13:58 PM UTC 24
Peak memory 230972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877394261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.877394261 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.2886869377
Short name T633
Test name
Test status
Simulation time 40938761 ps
CPU time 2.51 seconds
Started Oct 15 02:13:49 PM UTC 24
Finished Oct 15 02:13:53 PM UTC 24
Peak memory 230904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886869377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2886869377 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.4048778102
Short name T749
Test name
Test status
Simulation time 72757998339 ps
CPU time 1726.78 seconds
Started Oct 15 02:11:44 PM UTC 24
Finished Oct 15 02:40:51 PM UTC 24
Peak memory 1271676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048778102 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.4048778102 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.3639162900
Short name T662
Test name
Test status
Simulation time 18297682707 ps
CPU time 408.36 seconds
Started Oct 15 02:12:04 PM UTC 24
Finished Oct 15 02:18:57 PM UTC 24
Peak memory 391096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639162900 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3639162900 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.4225582965
Short name T625
Test name
Test status
Simulation time 254207045 ps
CPU time 16.19 seconds
Started Oct 15 02:11:44 PM UTC 24
Finished Oct 15 02:12:02 PM UTC 24
Peak memory 231040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225582965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.4225582965 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.682944128
Short name T638
Test name
Test status
Simulation time 12823534106 ps
CPU time 75.1 seconds
Started Oct 15 02:13:53 PM UTC 24
Finished Oct 15 02:15:10 PM UTC 24
Peak memory 287008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682944128 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.682944128 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.4136651708
Short name T647
Test name
Test status
Simulation time 20791415 ps
CPU time 1.12 seconds
Started Oct 15 02:17:01 PM UTC 24
Finished Oct 15 02:17:04 PM UTC 24
Peak memory 214132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136651708 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.4136651708 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.1257868360
Short name T646
Test name
Test status
Simulation time 64463197644 ps
CPU time 71.84 seconds
Started Oct 15 02:15:47 PM UTC 24
Finished Oct 15 02:17:01 PM UTC 24
Peak memory 294904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257868360 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1257868360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.2816701416
Short name T716
Test name
Test status
Simulation time 72685291270 ps
CPU time 683.41 seconds
Started Oct 15 02:15:23 PM UTC 24
Finished Oct 15 02:26:54 PM UTC 24
Peak memory 260208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816701416 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2816701416 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.27102028
Short name T667
Test name
Test status
Simulation time 6271699120 ps
CPU time 207.5 seconds
Started Oct 15 02:16:10 PM UTC 24
Finished Oct 15 02:19:41 PM UTC 24
Peak memory 376732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27102028 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.27102028 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.1604502843
Short name T684
Test name
Test status
Simulation time 42143227494 ps
CPU time 357.26 seconds
Started Oct 15 02:16:22 PM UTC 24
Finished Oct 15 02:22:24 PM UTC 24
Peak memory 522236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604502843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1604502843 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.3798820856
Short name T644
Test name
Test status
Simulation time 8198284400 ps
CPU time 10.28 seconds
Started Oct 15 02:16:26 PM UTC 24
Finished Oct 15 02:16:37 PM UTC 24
Peak memory 231028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798820856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3798820856 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.3367364616
Short name T645
Test name
Test status
Simulation time 34294264 ps
CPU time 1.83 seconds
Started Oct 15 02:16:38 PM UTC 24
Finished Oct 15 02:16:41 PM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367364616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3367364616 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.3613765571
Short name T765
Test name
Test status
Simulation time 91130618226 ps
CPU time 3875.96 seconds
Started Oct 15 02:14:24 PM UTC 24
Finished Oct 15 03:19:44 PM UTC 24
Peak memory 4272208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613765571 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.3613765571 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.4127688929
Short name T653
Test name
Test status
Simulation time 22395717527 ps
CPU time 220.86 seconds
Started Oct 15 02:14:28 PM UTC 24
Finished Oct 15 02:18:12 PM UTC 24
Peak memory 438332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127688929 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.4127688929 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.1610623588
Short name T636
Test name
Test status
Simulation time 679219972 ps
CPU time 19.51 seconds
Started Oct 15 02:14:03 PM UTC 24
Finished Oct 15 02:14:23 PM UTC 24
Peak memory 230964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610623588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1610623588 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.2934657459
Short name T663
Test name
Test status
Simulation time 1804124256 ps
CPU time 151.98 seconds
Started Oct 15 02:16:42 PM UTC 24
Finished Oct 15 02:19:17 PM UTC 24
Peak memory 315644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934657459 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2934657459 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.1860584700
Short name T658
Test name
Test status
Simulation time 97790241 ps
CPU time 1.22 seconds
Started Oct 15 02:18:24 PM UTC 24
Finished Oct 15 02:18:26 PM UTC 24
Peak memory 214096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860584700 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1860584700 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.3097135320
Short name T692
Test name
Test status
Simulation time 46356651201 ps
CPU time 356.69 seconds
Started Oct 15 02:17:48 PM UTC 24
Finished Oct 15 02:23:49 PM UTC 24
Peak memory 530272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097135320 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3097135320 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3293055323
Short name T673
Test name
Test status
Simulation time 3699174482 ps
CPU time 160.03 seconds
Started Oct 15 02:17:37 PM UTC 24
Finished Oct 15 02:20:20 PM UTC 24
Peak memory 235448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293055323 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3293055323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2773384915
Short name T664
Test name
Test status
Simulation time 3572601263 ps
CPU time 86.71 seconds
Started Oct 15 02:17:50 PM UTC 24
Finished Oct 15 02:19:18 PM UTC 24
Peak memory 292848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773384915 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2773384915 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.2493609306
Short name T698
Test name
Test status
Simulation time 57513699078 ps
CPU time 390.29 seconds
Started Oct 15 02:18:13 PM UTC 24
Finished Oct 15 02:24:48 PM UTC 24
Peak memory 587640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493609306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2493609306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.1341681316
Short name T659
Test name
Test status
Simulation time 1798446460 ps
CPU time 17.35 seconds
Started Oct 15 02:18:16 PM UTC 24
Finished Oct 15 02:18:35 PM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341681316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1341681316 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.1133096948
Short name T655
Test name
Test status
Simulation time 47815745 ps
CPU time 1.85 seconds
Started Oct 15 02:18:20 PM UTC 24
Finished Oct 15 02:18:22 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133096948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1133096948 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.3519710753
Short name T739
Test name
Test status
Simulation time 21029187875 ps
CPU time 959.26 seconds
Started Oct 15 02:17:12 PM UTC 24
Finished Oct 15 02:33:23 PM UTC 24
Peak memory 853944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519710753 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.3519710753 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.1276920061
Short name T691
Test name
Test status
Simulation time 31620719343 ps
CPU time 371.38 seconds
Started Oct 15 02:17:17 PM UTC 24
Finished Oct 15 02:23:33 PM UTC 24
Peak memory 581692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276920061 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1276920061 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.4011078331
Short name T648
Test name
Test status
Simulation time 310042160 ps
CPU time 4.7 seconds
Started Oct 15 02:17:05 PM UTC 24
Finished Oct 15 02:17:11 PM UTC 24
Peak memory 230948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011078331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.4011078331 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.664361898
Short name T761
Test name
Test status
Simulation time 138565317616 ps
CPU time 2356.92 seconds
Started Oct 15 02:18:24 PM UTC 24
Finished Oct 15 02:58:08 PM UTC 24
Peak memory 1188112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664361898 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.664361898 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.3983765547
Short name T668
Test name
Test status
Simulation time 77890283 ps
CPU time 1.25 seconds
Started Oct 15 02:19:42 PM UTC 24
Finished Oct 15 02:19:45 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983765547 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3983765547 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.356441690
Short name T686
Test name
Test status
Simulation time 23177563848 ps
CPU time 259.07 seconds
Started Oct 15 02:18:58 PM UTC 24
Finished Oct 15 02:23:21 PM UTC 24
Peak memory 311216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356441690 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.356441690 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.1251475640
Short name T740
Test name
Test status
Simulation time 40399383553 ps
CPU time 913.24 seconds
Started Oct 15 02:18:57 PM UTC 24
Finished Oct 15 02:34:21 PM UTC 24
Peak memory 262076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251475640 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1251475640 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.2498931895
Short name T681
Test name
Test status
Simulation time 18174402230 ps
CPU time 133.33 seconds
Started Oct 15 02:19:18 PM UTC 24
Finished Oct 15 02:21:34 PM UTC 24
Peak memory 341912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498931895 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2498931895 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.1968969140
Short name T676
Test name
Test status
Simulation time 3691286600 ps
CPU time 100.35 seconds
Started Oct 15 02:19:20 PM UTC 24
Finished Oct 15 02:21:02 PM UTC 24
Peak memory 278584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968969140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1968969140 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.2771262300
Short name T669
Test name
Test status
Simulation time 1625030994 ps
CPU time 15.04 seconds
Started Oct 15 02:19:30 PM UTC 24
Finished Oct 15 02:19:46 PM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771262300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2771262300 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.1178192831
Short name T74
Test name
Test status
Simulation time 95389088 ps
CPU time 1.72 seconds
Started Oct 15 02:19:39 PM UTC 24
Finished Oct 15 02:19:42 PM UTC 24
Peak memory 234624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178192831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1178192831 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.653758127
Short name T727
Test name
Test status
Simulation time 43526902682 ps
CPU time 623.84 seconds
Started Oct 15 02:18:27 PM UTC 24
Finished Oct 15 02:28:59 PM UTC 24
Peak memory 991152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653758127 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.653758127 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.1720177170
Short name T666
Test name
Test status
Simulation time 651350602 ps
CPU time 61.2 seconds
Started Oct 15 02:18:35 PM UTC 24
Finished Oct 15 02:19:38 PM UTC 24
Peak memory 251700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720177170 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.1720177170 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload_invalid.2003641512
Short name T661
Test name
Test status
Simulation time 477601045 ps
CPU time 6.09 seconds
Started Oct 15 02:18:49 PM UTC 24
Finished Oct 15 02:18:56 PM UTC 24
Peak memory 231400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003641512 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload_invalid.2003641512 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.1695250767
Short name T660
Test name
Test status
Simulation time 1219826249 ps
CPU time 20.71 seconds
Started Oct 15 02:18:26 PM UTC 24
Finished Oct 15 02:18:48 PM UTC 24
Peak memory 231108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695250767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1695250767 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.304871764
Short name T758
Test name
Test status
Simulation time 171701504169 ps
CPU time 1919.06 seconds
Started Oct 15 02:19:42 PM UTC 24
Finished Oct 15 02:52:03 PM UTC 24
Peak memory 1998760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304871764 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.304871764 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.1513225383
Short name T629
Test name
Test status
Simulation time 28872001 ps
CPU time 1.25 seconds
Started Oct 15 02:21:07 PM UTC 24
Finished Oct 15 02:21:09 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513225383 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1513225383 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.974255858
Short name T674
Test name
Test status
Simulation time 1116857942 ps
CPU time 20.97 seconds
Started Oct 15 02:20:22 PM UTC 24
Finished Oct 15 02:20:44 PM UTC 24
Peak memory 235432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974255858 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.974255858 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.3262329678
Short name T677
Test name
Test status
Simulation time 4955524053 ps
CPU time 47.13 seconds
Started Oct 15 02:20:15 PM UTC 24
Finished Oct 15 02:21:04 PM UTC 24
Peak memory 233024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262329678 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3262329678 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.2892545867
Short name T708
Test name
Test status
Simulation time 26800909802 ps
CPU time 300.99 seconds
Started Oct 15 02:20:45 PM UTC 24
Finished Oct 15 02:25:50 PM UTC 24
Peak memory 491496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892545867 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2892545867 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.3681718678
Short name T704
Test name
Test status
Simulation time 12671266836 ps
CPU time 291.96 seconds
Started Oct 15 02:20:46 PM UTC 24
Finished Oct 15 02:25:42 PM UTC 24
Peak memory 343992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681718678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3681718678 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.2701615097
Short name T679
Test name
Test status
Simulation time 830852364 ps
CPU time 8.44 seconds
Started Oct 15 02:20:59 PM UTC 24
Finished Oct 15 02:21:09 PM UTC 24
Peak memory 230920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701615097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2701615097 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.2353216805
Short name T678
Test name
Test status
Simulation time 181117291 ps
CPU time 1.59 seconds
Started Oct 15 02:21:03 PM UTC 24
Finished Oct 15 02:21:06 PM UTC 24
Peak memory 232176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353216805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2353216805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.3915357139
Short name T755
Test name
Test status
Simulation time 37906055541 ps
CPU time 1466.07 seconds
Started Oct 15 02:19:47 PM UTC 24
Finished Oct 15 02:44:30 PM UTC 24
Peak memory 1933300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915357139 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.3915357139 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.3576520142
Short name T672
Test name
Test status
Simulation time 4305645642 ps
CPU time 16.56 seconds
Started Oct 15 02:19:57 PM UTC 24
Finished Oct 15 02:20:15 PM UTC 24
Peak memory 251832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576520142 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3576520142 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.3434207286
Short name T670
Test name
Test status
Simulation time 2673988662 ps
CPU time 9.62 seconds
Started Oct 15 02:19:46 PM UTC 24
Finished Oct 15 02:19:56 PM UTC 24
Peak memory 231012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434207286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3434207286 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.3257829036
Short name T762
Test name
Test status
Simulation time 140401224703 ps
CPU time 2507.48 seconds
Started Oct 15 02:21:05 PM UTC 24
Finished Oct 15 03:03:21 PM UTC 24
Peak memory 1509880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257829036 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3257829036 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.1998614998
Short name T690
Test name
Test status
Simulation time 72423012 ps
CPU time 1.23 seconds
Started Oct 15 02:23:29 PM UTC 24
Finished Oct 15 02:23:32 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998614998 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1998614998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.3867127365
Short name T696
Test name
Test status
Simulation time 5372548600 ps
CPU time 152.31 seconds
Started Oct 15 02:22:01 PM UTC 24
Finished Oct 15 02:24:36 PM UTC 24
Peak memory 282488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867127365 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3867127365 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.1978569147
Short name T737
Test name
Test status
Simulation time 76809192594 ps
CPU time 655.79 seconds
Started Oct 15 02:21:43 PM UTC 24
Finished Oct 15 02:32:47 PM UTC 24
Peak memory 257972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978569147 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1978569147 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2495905909
Short name T685
Test name
Test status
Simulation time 71545471 ps
CPU time 4.05 seconds
Started Oct 15 02:22:25 PM UTC 24
Finished Oct 15 02:22:31 PM UTC 24
Peak memory 231112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495905909 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2495905909 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.3489024268
Short name T712
Test name
Test status
Simulation time 41806497803 ps
CPU time 220.87 seconds
Started Oct 15 02:22:32 PM UTC 24
Finished Oct 15 02:26:16 PM UTC 24
Peak memory 466872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489024268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3489024268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.1671236503
Short name T688
Test name
Test status
Simulation time 96386577 ps
CPU time 2.04 seconds
Started Oct 15 02:23:22 PM UTC 24
Finished Oct 15 02:23:25 PM UTC 24
Peak memory 230688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671236503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1671236503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.980091757
Short name T689
Test name
Test status
Simulation time 61469907 ps
CPU time 1.94 seconds
Started Oct 15 02:23:25 PM UTC 24
Finished Oct 15 02:23:28 PM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980091757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.980091757 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.732277901
Short name T751
Test name
Test status
Simulation time 24481309326 ps
CPU time 1221 seconds
Started Oct 15 02:21:10 PM UTC 24
Finished Oct 15 02:41:46 PM UTC 24
Peak memory 948124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732277901 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.732277901 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.2912769323
Short name T687
Test name
Test status
Simulation time 4864522543 ps
CPU time 116.26 seconds
Started Oct 15 02:21:25 PM UTC 24
Finished Oct 15 02:23:24 PM UTC 24
Peak memory 272384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912769323 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2912769323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload_invalid.3246642630
Short name T682
Test name
Test status
Simulation time 629093650 ps
CPU time 4.99 seconds
Started Oct 15 02:21:36 PM UTC 24
Finished Oct 15 02:21:42 PM UTC 24
Peak memory 233524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246642630 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload_invalid.3246642630 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.1952136523
Short name T683
Test name
Test status
Simulation time 7618133174 ps
CPU time 48.82 seconds
Started Oct 15 02:21:10 PM UTC 24
Finished Oct 15 02:22:00 PM UTC 24
Peak memory 230980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952136523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1952136523 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.2349367690
Short name T738
Test name
Test status
Simulation time 44546627116 ps
CPU time 554 seconds
Started Oct 15 02:23:26 PM UTC 24
Finished Oct 15 02:32:48 PM UTC 24
Peak memory 469312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349367690 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2349367690 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.4097318061
Short name T701
Test name
Test status
Simulation time 13037368 ps
CPU time 1.27 seconds
Started Oct 15 02:24:53 PM UTC 24
Finished Oct 15 02:24:55 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097318061 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.4097318061 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.2210425372
Short name T724
Test name
Test status
Simulation time 38110164539 ps
CPU time 225.59 seconds
Started Oct 15 02:24:32 PM UTC 24
Finished Oct 15 02:28:21 PM UTC 24
Peak memory 403508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210425372 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2210425372 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.4291828871
Short name T742
Test name
Test status
Simulation time 8033638528 ps
CPU time 681.36 seconds
Started Oct 15 02:24:10 PM UTC 24
Finished Oct 15 02:35:40 PM UTC 24
Peak memory 251824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291828871 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.4291828871 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.2211910116
Short name T720
Test name
Test status
Simulation time 39203984058 ps
CPU time 186.88 seconds
Started Oct 15 02:24:37 PM UTC 24
Finished Oct 15 02:27:47 PM UTC 24
Peak memory 378788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211910116 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2211910116 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.3473785311
Short name T722
Test name
Test status
Simulation time 35129798986 ps
CPU time 187.9 seconds
Started Oct 15 02:24:42 PM UTC 24
Finished Oct 15 02:27:53 PM UTC 24
Peak memory 421868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473785311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3473785311 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.2410529545
Short name T699
Test name
Test status
Simulation time 3390097608 ps
CPU time 5.62 seconds
Started Oct 15 02:24:43 PM UTC 24
Finished Oct 15 02:24:50 PM UTC 24
Peak memory 230864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410529545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2410529545 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.1338835896
Short name T700
Test name
Test status
Simulation time 51410833 ps
CPU time 1.58 seconds
Started Oct 15 02:24:50 PM UTC 24
Finished Oct 15 02:24:52 PM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338835896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1338835896 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.210574610
Short name T766
Test name
Test status
Simulation time 380135051223 ps
CPU time 3432.58 seconds
Started Oct 15 02:23:34 PM UTC 24
Finished Oct 15 03:21:29 PM UTC 24
Peak memory 3498004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210574610 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.210574610 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.935176552
Short name T733
Test name
Test status
Simulation time 53657725670 ps
CPU time 370.51 seconds
Started Oct 15 02:23:50 PM UTC 24
Finished Oct 15 02:30:06 PM UTC 24
Peak memory 382840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935176552 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.935176552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload_invalid.669917367
Short name T694
Test name
Test status
Simulation time 136348393 ps
CPU time 4.96 seconds
Started Oct 15 02:24:02 PM UTC 24
Finished Oct 15 02:24:08 PM UTC 24
Peak memory 231348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669917367 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload_invalid.669917367 +enable_masking=0 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.2617148124
Short name T695
Test name
Test status
Simulation time 821212592 ps
CPU time 56.08 seconds
Started Oct 15 02:23:33 PM UTC 24
Finished Oct 15 02:24:30 PM UTC 24
Peak memory 235200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617148124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2617148124 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.679586743
Short name T747
Test name
Test status
Simulation time 25960428651 ps
CPU time 838.15 seconds
Started Oct 15 02:24:51 PM UTC 24
Finished Oct 15 02:39:00 PM UTC 24
Peak memory 567608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679586743 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.679586743 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.3133153490
Short name T706
Test name
Test status
Simulation time 53471131 ps
CPU time 1.18 seconds
Started Oct 15 02:25:45 PM UTC 24
Finished Oct 15 02:25:48 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133153490 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3133153490 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.1455754325
Short name T719
Test name
Test status
Simulation time 3863936167 ps
CPU time 122.68 seconds
Started Oct 15 02:25:28 PM UTC 24
Finished Oct 15 02:27:33 PM UTC 24
Peak memory 284508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455754325 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1455754325 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.1596927238
Short name T717
Test name
Test status
Simulation time 5995375086 ps
CPU time 84.7 seconds
Started Oct 15 02:25:28 PM UTC 24
Finished Oct 15 02:26:55 PM UTC 24
Peak memory 235076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596927238 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.1596927238 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.1846159130
Short name T710
Test name
Test status
Simulation time 1925173103 ps
CPU time 18.01 seconds
Started Oct 15 02:25:31 PM UTC 24
Finished Oct 15 02:25:51 PM UTC 24
Peak memory 235564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846159130 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1846159130 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.1511862313
Short name T726
Test name
Test status
Simulation time 15663199349 ps
CPU time 194.29 seconds
Started Oct 15 02:25:38 PM UTC 24
Finished Oct 15 02:28:55 PM UTC 24
Peak memory 317356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511862313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1511862313 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.2104937583
Short name T709
Test name
Test status
Simulation time 1280011585 ps
CPU time 8.68 seconds
Started Oct 15 02:25:41 PM UTC 24
Finished Oct 15 02:25:51 PM UTC 24
Peak memory 230712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104937583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2104937583 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.714076215
Short name T707
Test name
Test status
Simulation time 361591266 ps
CPU time 5.09 seconds
Started Oct 15 02:25:43 PM UTC 24
Finished Oct 15 02:25:49 PM UTC 24
Peak memory 231168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714076215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.714076215 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.1468891073
Short name T764
Test name
Test status
Simulation time 285476269115 ps
CPU time 2953.44 seconds
Started Oct 15 02:25:06 PM UTC 24
Finished Oct 15 03:14:53 PM UTC 24
Peak memory 3420028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468891073 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.1468891073 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.2811759947
Short name T705
Test name
Test status
Simulation time 1106723074 ps
CPU time 33.52 seconds
Started Oct 15 02:25:12 PM UTC 24
Finished Oct 15 02:25:47 PM UTC 24
Peak memory 245620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811759947 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2811759947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload_invalid.3206234733
Short name T703
Test name
Test status
Simulation time 64522330 ps
CPU time 3.55 seconds
Started Oct 15 02:25:23 PM UTC 24
Finished Oct 15 02:25:27 PM UTC 24
Peak memory 231360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206234733 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload_invalid.3206234733 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.536286198
Short name T711
Test name
Test status
Simulation time 36766552158 ps
CPU time 68.46 seconds
Started Oct 15 02:24:56 PM UTC 24
Finished Oct 15 02:26:06 PM UTC 24
Peak memory 235384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536286198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.536286198 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.2174791490
Short name T718
Test name
Test status
Simulation time 3738913051 ps
CPU time 98.52 seconds
Started Oct 15 02:25:43 PM UTC 24
Finished Oct 15 02:27:24 PM UTC 24
Peak memory 286564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174791490 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2174791490 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.1350659364
Short name T713
Test name
Test status
Simulation time 57520911 ps
CPU time 1.24 seconds
Started Oct 15 02:26:15 PM UTC 24
Finished Oct 15 02:26:17 PM UTC 24
Peak memory 214124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350659364 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1350659364 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.1181985803
Short name T731
Test name
Test status
Simulation time 9546413235 ps
CPU time 228.89 seconds
Started Oct 15 02:25:52 PM UTC 24
Finished Oct 15 02:29:44 PM UTC 24
Peak memory 409448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181985803 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1181985803 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.3587470068
Short name T729
Test name
Test status
Simulation time 14409646353 ps
CPU time 214.93 seconds
Started Oct 15 02:25:52 PM UTC 24
Finished Oct 15 02:29:30 PM UTC 24
Peak memory 237408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587470068 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3587470068 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.232555206
Short name T728
Test name
Test status
Simulation time 37813097262 ps
CPU time 189.4 seconds
Started Oct 15 02:25:52 PM UTC 24
Finished Oct 15 02:29:04 PM UTC 24
Peak memory 362420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232555206 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.232555206 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.1521042146
Short name T730
Test name
Test status
Simulation time 12249307760 ps
CPU time 222.3 seconds
Started Oct 15 02:25:56 PM UTC 24
Finished Oct 15 02:29:42 PM UTC 24
Peak memory 339944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521042146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1521042146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.182146593
Short name T714
Test name
Test status
Simulation time 9035749659 ps
CPU time 13.15 seconds
Started Oct 15 02:26:07 PM UTC 24
Finished Oct 15 02:26:22 PM UTC 24
Peak memory 230972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182146593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.182146593 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.4061828732
Short name T72
Test name
Test status
Simulation time 139301063 ps
CPU time 2.16 seconds
Started Oct 15 02:26:10 PM UTC 24
Finished Oct 15 02:26:13 PM UTC 24
Peak memory 235220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061828732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.4061828732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.1236569574
Short name T756
Test name
Test status
Simulation time 23222669904 ps
CPU time 1223.57 seconds
Started Oct 15 02:25:48 PM UTC 24
Finished Oct 15 02:46:26 PM UTC 24
Peak memory 970612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236569574 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.1236569574 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.2788976908
Short name T736
Test name
Test status
Simulation time 19300179032 ps
CPU time 384.32 seconds
Started Oct 15 02:25:49 PM UTC 24
Finished Oct 15 02:32:19 PM UTC 24
Peak memory 395308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788976908 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2788976908 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.1076741647
Short name T715
Test name
Test status
Simulation time 2788386542 ps
CPU time 50.3 seconds
Started Oct 15 02:25:48 PM UTC 24
Finished Oct 15 02:26:40 PM UTC 24
Peak memory 231216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076741647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1076741647 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.1367149349
Short name T721
Test name
Test status
Simulation time 1991077302 ps
CPU time 93.06 seconds
Started Oct 15 02:26:14 PM UTC 24
Finished Oct 15 02:27:49 PM UTC 24
Peak memory 268208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367149349 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1367149349 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.996200295
Short name T217
Test name
Test status
Simulation time 41846224 ps
CPU time 1.15 seconds
Started Oct 15 01:11:29 PM UTC 24
Finished Oct 15 01:11:31 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996200295 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.996200295 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.1139410760
Short name T238
Test name
Test status
Simulation time 48747972573 ps
CPU time 377.01 seconds
Started Oct 15 01:10:41 PM UTC 24
Finished Oct 15 01:17:04 PM UTC 24
Peak memory 454712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139410760 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1139410760 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1497180654
Short name T224
Test name
Test status
Simulation time 12233513334 ps
CPU time 204.11 seconds
Started Oct 15 01:10:44 PM UTC 24
Finished Oct 15 01:14:11 PM UTC 24
Peak memory 436332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497180654 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1497180654 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.938037198
Short name T303
Test name
Test status
Simulation time 67530077824 ps
CPU time 1135.32 seconds
Started Oct 15 01:10:41 PM UTC 24
Finished Oct 15 01:29:50 PM UTC 24
Peak memory 272312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938037198 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.938037198 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.3902904151
Short name T216
Test name
Test status
Simulation time 687602660 ps
CPU time 16.14 seconds
Started Oct 15 01:11:10 PM UTC 24
Finished Oct 15 01:11:27 PM UTC 24
Peak memory 228736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902904151 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3902904151 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3910050487
Short name T215
Test name
Test status
Simulation time 485477357 ps
CPU time 12.3 seconds
Started Oct 15 01:11:12 PM UTC 24
Finished Oct 15 01:11:25 PM UTC 24
Peak memory 235092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910050487 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3910050487 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.2660739076
Short name T220
Test name
Test status
Simulation time 5734501560 ps
CPU time 43.16 seconds
Started Oct 15 01:11:21 PM UTC 24
Finished Oct 15 01:12:06 PM UTC 24
Peak memory 231216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660739076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2660739076 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.3729528315
Short name T229
Test name
Test status
Simulation time 12137772042 ps
CPU time 308.54 seconds
Started Oct 15 01:10:45 PM UTC 24
Finished Oct 15 01:15:58 PM UTC 24
Peak memory 335736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729528315 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.3729528315 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.62724530
Short name T213
Test name
Test status
Simulation time 1076368456 ps
CPU time 23.77 seconds
Started Oct 15 01:10:55 PM UTC 24
Finished Oct 15 01:11:20 PM UTC 24
Peak memory 262000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62724530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.62724530 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.3472696423
Short name T212
Test name
Test status
Simulation time 2404202941 ps
CPU time 7.28 seconds
Started Oct 15 01:11:01 PM UTC 24
Finished Oct 15 01:11:09 PM UTC 24
Peak memory 230820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472696423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3472696423 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.1794600016
Short name T46
Test name
Test status
Simulation time 162920596 ps
CPU time 1.72 seconds
Started Oct 15 01:11:21 PM UTC 24
Finished Oct 15 01:11:24 PM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794600016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1794600016 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.1431096711
Short name T406
Test name
Test status
Simulation time 57773903972 ps
CPU time 2080.91 seconds
Started Oct 15 01:10:20 PM UTC 24
Finished Oct 15 01:45:22 PM UTC 24
Peak memory 2830316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431096711 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.1431096711 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.3645174035
Short name T87
Test name
Test status
Simulation time 7656369922 ps
CPU time 142.8 seconds
Started Oct 15 01:10:45 PM UTC 24
Finished Oct 15 01:13:10 PM UTC 24
Peak memory 338368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645174035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3645174035 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.2408798936
Short name T208
Test name
Test status
Simulation time 2884891251 ps
CPU time 17.31 seconds
Started Oct 15 01:10:22 PM UTC 24
Finished Oct 15 01:10:41 PM UTC 24
Peak memory 241644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408798936 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2408798936 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload_invalid.3948740840
Short name T78
Test name
Test status
Simulation time 617011097 ps
CPU time 3.07 seconds
Started Oct 15 01:10:36 PM UTC 24
Finished Oct 15 01:10:41 PM UTC 24
Peak memory 231308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948740840 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload_invalid.3948740840 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.512314544
Short name T192
Test name
Test status
Simulation time 11892778875 ps
CPU time 65.07 seconds
Started Oct 15 01:09:53 PM UTC 24
Finished Oct 15 01:11:00 PM UTC 24
Peak memory 233140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512314544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.512314544 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.2850469171
Short name T149
Test name
Test status
Simulation time 67478921486 ps
CPU time 472.92 seconds
Started Oct 15 01:11:24 PM UTC 24
Finished Oct 15 01:19:23 PM UTC 24
Peak memory 712624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850469171 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2850469171 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.1772026921
Short name T227
Test name
Test status
Simulation time 37454219 ps
CPU time 1.07 seconds
Started Oct 15 01:14:54 PM UTC 24
Finished Oct 15 01:14:56 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772026921 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1772026921 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.1874727987
Short name T230
Test name
Test status
Simulation time 5333352615 ps
CPU time 250.96 seconds
Started Oct 15 01:12:07 PM UTC 24
Finished Oct 15 01:16:22 PM UTC 24
Peak memory 343920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874727987 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1874727987 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1139640332
Short name T232
Test name
Test status
Simulation time 30316378214 ps
CPU time 247.85 seconds
Started Oct 15 01:12:22 PM UTC 24
Finished Oct 15 01:16:34 PM UTC 24
Peak memory 325560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139640332 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1139640332 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.2135869897
Short name T58
Test name
Test status
Simulation time 13102279500 ps
CPU time 334.77 seconds
Started Oct 15 01:11:50 PM UTC 24
Finished Oct 15 01:17:29 PM UTC 24
Peak memory 241588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135869897 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2135869897 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.4128181053
Short name T223
Test name
Test status
Simulation time 327483499 ps
CPU time 25.45 seconds
Started Oct 15 01:13:34 PM UTC 24
Finished Oct 15 01:14:00 PM UTC 24
Peak memory 235312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128181053 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.4128181053 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.731572324
Short name T226
Test name
Test status
Simulation time 3563678836 ps
CPU time 37.83 seconds
Started Oct 15 01:13:52 PM UTC 24
Finished Oct 15 01:14:31 PM UTC 24
Peak memory 243176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731572324 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.731572324 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.152335137
Short name T168
Test name
Test status
Simulation time 18260818495 ps
CPU time 61.14 seconds
Started Oct 15 01:14:01 PM UTC 24
Finished Oct 15 01:15:04 PM UTC 24
Peak memory 231092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152335137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.152335137 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.72065546
Short name T233
Test name
Test status
Simulation time 4638271926 ps
CPU time 231.5 seconds
Started Oct 15 01:12:43 PM UTC 24
Finished Oct 15 01:16:38 PM UTC 24
Peak memory 329732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72065546 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.72065546 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.1339269960
Short name T158
Test name
Test status
Simulation time 27381544584 ps
CPU time 327.19 seconds
Started Oct 15 01:13:10 PM UTC 24
Finished Oct 15 01:18:42 PM UTC 24
Peak memory 509824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339269960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1339269960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.2844864760
Short name T222
Test name
Test status
Simulation time 3621148960 ps
CPU time 19.12 seconds
Started Oct 15 01:13:31 PM UTC 24
Finished Oct 15 01:13:51 PM UTC 24
Peak memory 230972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844864760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2844864760 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.3203398362
Short name T225
Test name
Test status
Simulation time 132038421 ps
CPU time 2.03 seconds
Started Oct 15 01:14:12 PM UTC 24
Finished Oct 15 01:14:15 PM UTC 24
Peak memory 233256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203398362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3203398362 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.2073837863
Short name T390
Test name
Test status
Simulation time 147021344759 ps
CPU time 1929.81 seconds
Started Oct 15 01:11:32 PM UTC 24
Finished Oct 15 01:44:00 PM UTC 24
Peak memory 2906036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073837863 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2073837863 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.3589186784
Short name T88
Test name
Test status
Simulation time 5128768882 ps
CPU time 125.86 seconds
Started Oct 15 01:12:46 PM UTC 24
Finished Oct 15 01:14:55 PM UTC 24
Peak memory 317688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589186784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3589186784 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.3450802407
Short name T219
Test name
Test status
Simulation time 329647922 ps
CPU time 4.59 seconds
Started Oct 15 01:11:40 PM UTC 24
Finished Oct 15 01:11:45 PM UTC 24
Peak memory 233016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450802407 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3450802407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload_invalid.1596983587
Short name T25
Test name
Test status
Simulation time 27731719 ps
CPU time 2.46 seconds
Started Oct 15 01:11:46 PM UTC 24
Finished Oct 15 01:11:49 PM UTC 24
Peak memory 231416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596983587 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload_invalid.1596983587 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.228445492
Short name T218
Test name
Test status
Simulation time 247550232 ps
CPU time 8.37 seconds
Started Oct 15 01:11:30 PM UTC 24
Finished Oct 15 01:11:39 PM UTC 24
Peak memory 231016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228445492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.228445492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.1718363501
Short name T255
Test name
Test status
Simulation time 11578142248 ps
CPU time 419.66 seconds
Started Oct 15 01:14:16 PM UTC 24
Finished Oct 15 01:21:21 PM UTC 24
Peak memory 438500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718363501 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1718363501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.4255959579
Short name T67
Test name
Test status
Simulation time 762979127 ps
CPU time 19.74 seconds
Started Oct 15 01:14:32 PM UTC 24
Finished Oct 15 01:14:53 PM UTC 24
Peak memory 245740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4255959579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_
with_rand_reset.4255959579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.3190684868
Short name T239
Test name
Test status
Simulation time 21467873 ps
CPU time 1.3 seconds
Started Oct 15 01:17:04 PM UTC 24
Finished Oct 15 01:17:07 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190684868 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3190684868 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.1592812360
Short name T240
Test name
Test status
Simulation time 17786178121 ps
CPU time 154.16 seconds
Started Oct 15 01:15:13 PM UTC 24
Finished Oct 15 01:17:50 PM UTC 24
Peak memory 331700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592812360 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1592812360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2635772210
Short name T231
Test name
Test status
Simulation time 1773626995 ps
CPU time 45.26 seconds
Started Oct 15 01:15:44 PM UTC 24
Finished Oct 15 01:16:31 PM UTC 24
Peak memory 247612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635772210 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2635772210 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.2557645876
Short name T266
Test name
Test status
Simulation time 12493254722 ps
CPU time 468.07 seconds
Started Oct 15 01:15:08 PM UTC 24
Finished Oct 15 01:23:01 PM UTC 24
Peak memory 251776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557645876 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2557645876 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.4039153032
Short name T235
Test name
Test status
Simulation time 924162927 ps
CPU time 18.82 seconds
Started Oct 15 01:16:35 PM UTC 24
Finished Oct 15 01:16:55 PM UTC 24
Peak memory 232960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039153032 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.4039153032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.3592314617
Short name T236
Test name
Test status
Simulation time 288565406 ps
CPU time 18.17 seconds
Started Oct 15 01:16:39 PM UTC 24
Finished Oct 15 01:16:58 PM UTC 24
Peak memory 235120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592314617 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3592314617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.3994768279
Short name T237
Test name
Test status
Simulation time 1792028924 ps
CPU time 18.33 seconds
Started Oct 15 01:16:44 PM UTC 24
Finished Oct 15 01:17:04 PM UTC 24
Peak memory 231000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994768279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3994768279 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.1762910091
Short name T253
Test name
Test status
Simulation time 42402444655 ps
CPU time 302.41 seconds
Started Oct 15 01:15:58 PM UTC 24
Finished Oct 15 01:21:05 PM UTC 24
Peak memory 311220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762910091 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1762910091 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.1071960805
Short name T43
Test name
Test status
Simulation time 9032384957 ps
CPU time 217.15 seconds
Started Oct 15 01:16:23 PM UTC 24
Finished Oct 15 01:20:03 PM UTC 24
Peak memory 317372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071960805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1071960805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.3047022719
Short name T234
Test name
Test status
Simulation time 9102305821 ps
CPU time 8.9 seconds
Started Oct 15 01:16:33 PM UTC 24
Finished Oct 15 01:16:43 PM UTC 24
Peak memory 230772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047022719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3047022719 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.821732074
Short name T47
Test name
Test status
Simulation time 38838128 ps
CPU time 2.02 seconds
Started Oct 15 01:16:56 PM UTC 24
Finished Oct 15 01:16:59 PM UTC 24
Peak memory 230876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821732074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.821732074 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.3558257493
Short name T586
Test name
Test status
Simulation time 96037186422 ps
CPU time 2999 seconds
Started Oct 15 01:14:58 PM UTC 24
Finished Oct 15 02:05:28 PM UTC 24
Peak memory 3573788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558257493 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.3558257493 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.4070909012
Short name T252
Test name
Test status
Simulation time 28095911977 ps
CPU time 248.6 seconds
Started Oct 15 01:16:21 PM UTC 24
Finished Oct 15 01:20:34 PM UTC 24
Peak memory 391492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070909012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.4070909012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.4145361796
Short name T36
Test name
Test status
Simulation time 13068259940 ps
CPU time 241.37 seconds
Started Oct 15 01:15:05 PM UTC 24
Finished Oct 15 01:19:09 PM UTC 24
Peak memory 337848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145361796 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.4145361796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.994257079
Short name T228
Test name
Test status
Simulation time 705005545 ps
CPU time 46.3 seconds
Started Oct 15 01:14:55 PM UTC 24
Finished Oct 15 01:15:43 PM UTC 24
Peak memory 230912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994257079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.994257079 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.2322360826
Short name T242
Test name
Test status
Simulation time 18236155101 ps
CPU time 93.53 seconds
Started Oct 15 01:16:59 PM UTC 24
Finished Oct 15 01:18:35 PM UTC 24
Peak memory 300924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322360826 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2322360826 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.232639880
Short name T249
Test name
Test status
Simulation time 85858631 ps
CPU time 1.36 seconds
Started Oct 15 01:19:24 PM UTC 24
Finished Oct 15 01:19:26 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232639880 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.232639880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.4141659009
Short name T243
Test name
Test status
Simulation time 1287906339 ps
CPU time 69.25 seconds
Started Oct 15 01:17:45 PM UTC 24
Finished Oct 15 01:18:56 PM UTC 24
Peak memory 255856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141659009 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.4141659009 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.4237049702
Short name T256
Test name
Test status
Simulation time 27020303911 ps
CPU time 207.63 seconds
Started Oct 15 01:17:51 PM UTC 24
Finished Oct 15 01:21:22 PM UTC 24
Peak memory 292920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237049702 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.4237049702 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.3158684634
Short name T307
Test name
Test status
Simulation time 15472145132 ps
CPU time 785.88 seconds
Started Oct 15 01:17:40 PM UTC 24
Finished Oct 15 01:30:55 PM UTC 24
Peak memory 257916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158684634 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3158684634 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.1658262464
Short name T245
Test name
Test status
Simulation time 179031368 ps
CPU time 4.6 seconds
Started Oct 15 01:19:01 PM UTC 24
Finished Oct 15 01:19:07 PM UTC 24
Peak memory 228776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658262464 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1658262464 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.473379736
Short name T247
Test name
Test status
Simulation time 1504879318 ps
CPU time 11.93 seconds
Started Oct 15 01:19:03 PM UTC 24
Finished Oct 15 01:19:17 PM UTC 24
Peak memory 235224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473379736 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.473379736 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.2545280040
Short name T248
Test name
Test status
Simulation time 5969890851 ps
CPU time 15.52 seconds
Started Oct 15 01:19:08 PM UTC 24
Finished Oct 15 01:19:24 PM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545280040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2545280040 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.554949414
Short name T251
Test name
Test status
Simulation time 2055733191 ps
CPU time 94.81 seconds
Started Oct 15 01:18:08 PM UTC 24
Finished Oct 15 01:19:45 PM UTC 24
Peak memory 255864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554949414 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.554949414 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.2802914210
Short name T279
Test name
Test status
Simulation time 25105619382 ps
CPU time 394.29 seconds
Started Oct 15 01:18:43 PM UTC 24
Finished Oct 15 01:25:23 PM UTC 24
Peak memory 538496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802914210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2802914210 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.3265278865
Short name T244
Test name
Test status
Simulation time 1791072698 ps
CPU time 5.45 seconds
Started Oct 15 01:18:56 PM UTC 24
Finished Oct 15 01:19:03 PM UTC 24
Peak memory 230720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265278865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3265278865 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.3902426609
Short name T246
Test name
Test status
Simulation time 25773293 ps
CPU time 1.99 seconds
Started Oct 15 01:19:11 PM UTC 24
Finished Oct 15 01:19:14 PM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902426609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3902426609 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.501789659
Short name T539
Test name
Test status
Simulation time 49712728593 ps
CPU time 2581.41 seconds
Started Oct 15 01:17:07 PM UTC 24
Finished Oct 15 02:00:37 PM UTC 24
Peak memory 1789824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501789659 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.501789659 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.1205923410
Short name T90
Test name
Test status
Simulation time 1680954675 ps
CPU time 23.6 seconds
Started Oct 15 01:18:35 PM UTC 24
Finished Oct 15 01:19:00 PM UTC 24
Peak memory 239864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205923410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1205923410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.3512670109
Short name T288
Test name
Test status
Simulation time 59059948874 ps
CPU time 519.99 seconds
Started Oct 15 01:17:31 PM UTC 24
Finished Oct 15 01:26:17 PM UTC 24
Peak memory 608232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512670109 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3512670109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload_invalid.2831681113
Short name T26
Test name
Test status
Simulation time 129800684 ps
CPU time 2.58 seconds
Started Oct 15 01:17:36 PM UTC 24
Finished Oct 15 01:17:39 PM UTC 24
Peak memory 231552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831681113 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload_invalid.2831681113 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.1901882434
Short name T241
Test name
Test status
Simulation time 8081670067 ps
CPU time 61.2 seconds
Started Oct 15 01:17:04 PM UTC 24
Finished Oct 15 01:18:07 PM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901882434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1901882434 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.2875146327
Short name T264
Test name
Test status
Simulation time 6147269467 ps
CPU time 162.13 seconds
Started Oct 15 01:19:15 PM UTC 24
Finished Oct 15 01:22:00 PM UTC 24
Peak memory 413568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875146327 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2875146327 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.406656319
Short name T262
Test name
Test status
Simulation time 55859799 ps
CPU time 1.24 seconds
Started Oct 15 01:21:44 PM UTC 24
Finished Oct 15 01:21:46 PM UTC 24
Peak memory 214064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406656319 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.406656319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.3820654059
Short name T278
Test name
Test status
Simulation time 10227069003 ps
CPU time 322.21 seconds
Started Oct 15 01:19:50 PM UTC 24
Finished Oct 15 01:25:17 PM UTC 24
Peak memory 340020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820654059 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3820654059 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.3585037460
Short name T271
Test name
Test status
Simulation time 4693819102 ps
CPU time 242.74 seconds
Started Oct 15 01:20:04 PM UTC 24
Finished Oct 15 01:24:10 PM UTC 24
Peak memory 321516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585037460 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3585037460 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.2046451055
Short name T189
Test name
Test status
Simulation time 34554568455 ps
CPU time 1092.27 seconds
Started Oct 15 01:19:48 PM UTC 24
Finished Oct 15 01:38:14 PM UTC 24
Peak memory 254064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046451055 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2046451055 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.3964458044
Short name T261
Test name
Test status
Simulation time 482443501 ps
CPU time 18.94 seconds
Started Oct 15 01:21:22 PM UTC 24
Finished Oct 15 01:21:42 PM UTC 24
Peak memory 230724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964458044 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3964458044 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.493385286
Short name T257
Test name
Test status
Simulation time 219420316 ps
CPU time 7.62 seconds
Started Oct 15 01:21:23 PM UTC 24
Finished Oct 15 01:21:32 PM UTC 24
Peak memory 230824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493385286 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.493385286 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.38139156
Short name T265
Test name
Test status
Simulation time 4437280296 ps
CPU time 38.97 seconds
Started Oct 15 01:21:33 PM UTC 24
Finished Oct 15 01:22:15 PM UTC 24
Peak memory 231140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38139156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.38139156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.3760496492
Short name T283
Test name
Test status
Simulation time 47048313896 ps
CPU time 301.33 seconds
Started Oct 15 01:20:35 PM UTC 24
Finished Oct 15 01:25:41 PM UTC 24
Peak memory 391160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760496492 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3760496492 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.2905925904
Short name T159
Test name
Test status
Simulation time 14433669357 ps
CPU time 501.06 seconds
Started Oct 15 01:21:12 PM UTC 24
Finished Oct 15 01:29:40 PM UTC 24
Peak memory 634804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905925904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2905925904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.3709702587
Short name T258
Test name
Test status
Simulation time 2190213877 ps
CPU time 12.06 seconds
Started Oct 15 01:21:21 PM UTC 24
Finished Oct 15 01:21:34 PM UTC 24
Peak memory 230784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709702587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3709702587 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.2444184034
Short name T260
Test name
Test status
Simulation time 104973112 ps
CPU time 1.83 seconds
Started Oct 15 01:21:35 PM UTC 24
Finished Oct 15 01:21:39 PM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444184034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2444184034 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.3797593966
Short name T254
Test name
Test status
Simulation time 3108368673 ps
CPU time 101.78 seconds
Started Oct 15 01:19:27 PM UTC 24
Finished Oct 15 01:21:11 PM UTC 24
Peak memory 364460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797593966 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.3797593966 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.2370153620
Short name T286
Test name
Test status
Simulation time 9462276862 ps
CPU time 276.2 seconds
Started Oct 15 01:21:06 PM UTC 24
Finished Oct 15 01:25:46 PM UTC 24
Peak memory 438620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370153620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2370153620 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.453499605
Short name T259
Test name
Test status
Simulation time 7831644615 ps
CPU time 124.26 seconds
Started Oct 15 01:19:30 PM UTC 24
Finished Oct 15 01:21:37 PM UTC 24
Peak memory 294844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453499605 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.453499605 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload_invalid.3360590143
Short name T118
Test name
Test status
Simulation time 194729059 ps
CPU time 2.62 seconds
Started Oct 15 01:19:46 PM UTC 24
Finished Oct 15 01:19:50 PM UTC 24
Peak memory 231472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360590143 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload_invalid.3360590143 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.1309048515
Short name T250
Test name
Test status
Simulation time 48437470 ps
CPU time 2.85 seconds
Started Oct 15 01:19:25 PM UTC 24
Finished Oct 15 01:19:29 PM UTC 24
Peak memory 230976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309048515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1309048515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.543788821
Short name T272
Test name
Test status
Simulation time 13253238626 ps
CPU time 170.78 seconds
Started Oct 15 01:21:37 PM UTC 24
Finished Oct 15 01:24:31 PM UTC 24
Peak memory 292768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543788821 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.543788821 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest
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