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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.78 95.77 90.51 100.00 66.94 93.67 98.84 96.72


Total test records in report: 1235
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T1062 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_shake_128.863359674 Feb 09 11:59:08 AM UTC 25 Feb 09 02:02:03 PM UTC 25 174773067237 ps
T1063 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.192425417 Feb 09 01:21:55 PM UTC 25 Feb 09 02:02:13 PM UTC 25 89707307767 ps
T1064 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_shake_128.2082107664 Feb 09 12:39:47 PM UTC 25 Feb 09 02:04:09 PM UTC 25 106942882641 ps
T1065 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_224.3911835227 Feb 09 01:22:57 PM UTC 25 Feb 09 02:05:01 PM UTC 25 103005705657 ps
T1066 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_shake_128.1714442503 Feb 09 12:44:51 PM UTC 25 Feb 09 02:06:08 PM UTC 25 104868307132 ps
T1067 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_shake_256.2715331452 Feb 09 12:09:18 PM UTC 25 Feb 09 02:06:22 PM UTC 25 935919717462 ps
T1068 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_256.1909054378 Feb 09 01:05:23 PM UTC 25 Feb 09 02:10:33 PM UTC 25 180747082416 ps
T1069 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_256.787451013 Feb 09 01:09:53 PM UTC 25 Feb 09 02:13:50 PM UTC 25 177237860359 ps
T1070 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_shake_128.876243054 Feb 09 12:13:38 PM UTC 25 Feb 09 02:14:00 PM UTC 25 1083112196270 ps
T1071 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_128.631510939 Feb 09 01:05:18 PM UTC 25 Feb 09 02:19:22 PM UTC 25 200047224263 ps
T1072 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_256.329821630 Feb 09 01:18:34 PM UTC 25 Feb 09 02:21:29 PM UTC 25 45674473751 ps
T1073 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_256.719059577 Feb 09 12:33:39 PM UTC 25 Feb 09 02:25:26 PM UTC 25 2107694608735 ps
T1074 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_256.1112201982 Feb 09 01:26:08 PM UTC 25 Feb 09 02:29:35 PM UTC 25 44019689413 ps
T1075 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_128.3118187103 Feb 09 12:33:29 PM UTC 25 Feb 09 02:37:58 PM UTC 25 267693501582 ps
T1076 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_shake_128.805820219 Feb 09 12:19:51 PM UTC 25 Feb 09 02:41:51 PM UTC 25 1594118041786 ps
T1077 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_128.4029078296 Feb 09 01:25:44 PM UTC 25 Feb 09 02:44:41 PM UTC 25 203255980024 ps
T1078 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_shake_256.947940392 Feb 09 12:58:44 PM UTC 25 Feb 09 02:54:28 PM UTC 25 1346000132111 ps
T1079 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_shake_128.4233991015 Feb 09 12:51:53 PM UTC 25 Feb 09 02:56:06 PM UTC 25 687877121054 ps
T1080 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_shake_128.2258594624 Feb 09 12:58:19 PM UTC 25 Feb 09 02:58:44 PM UTC 25 176919156776 ps
T1081 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_128.46937058 Feb 09 01:09:31 PM UTC 25 Feb 09 03:14:29 PM UTC 25 743880358880 ps
T1082 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_128.4246447566 Feb 09 01:17:44 PM UTC 25 Feb 09 03:33:52 PM UTC 25 1027571542953 ps
T93 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3211325849 Feb 09 08:33:12 AM UTC 25 Feb 09 08:33:14 AM UTC 25 76091139 ps
T1083 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.3397309368 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:15 AM UTC 25 10685917 ps
T110 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.403798949 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:15 AM UTC 25 21214866 ps
T94 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1059348719 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:16 AM UTC 25 48798406 ps
T95 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.971669017 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:16 AM UTC 25 105906728 ps
T130 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1519915415 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:16 AM UTC 25 130273384 ps
T54 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2444588677 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:16 AM UTC 25 103725250 ps
T55 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1418191993 Feb 09 08:33:35 AM UTC 25 Feb 09 08:33:38 AM UTC 25 372192408 ps
T96 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.208883230 Feb 09 08:33:12 AM UTC 25 Feb 09 08:33:17 AM UTC 25 439193364 ps
T97 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3594709193 Feb 09 08:33:14 AM UTC 25 Feb 09 08:33:17 AM UTC 25 65863450 ps
T1084 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2103014367 Feb 09 08:33:15 AM UTC 25 Feb 09 08:33:18 AM UTC 25 14821370 ps
T56 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3624128440 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:18 AM UTC 25 159261115 ps
T120 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3961655496 Feb 09 08:33:16 AM UTC 25 Feb 09 08:33:18 AM UTC 25 42078396 ps
T131 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2677004601 Feb 09 08:33:15 AM UTC 25 Feb 09 08:33:18 AM UTC 25 42086381 ps
T1085 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1644986929 Feb 09 08:33:14 AM UTC 25 Feb 09 08:33:18 AM UTC 25 310385982 ps
T98 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1989126766 Feb 09 08:33:14 AM UTC 25 Feb 09 08:33:18 AM UTC 25 57484977 ps
T107 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2809038683 Feb 09 08:33:14 AM UTC 25 Feb 09 08:33:19 AM UTC 25 70495839 ps
T139 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.3060579439 Feb 09 08:33:17 AM UTC 25 Feb 09 08:33:19 AM UTC 25 28236662 ps
T1086 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.1930598676 Feb 09 08:33:17 AM UTC 25 Feb 09 08:33:19 AM UTC 25 57451541 ps
T108 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1885522864 Feb 09 08:33:31 AM UTC 25 Feb 09 08:33:38 AM UTC 25 946141730 ps
T1087 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1352625727 Feb 09 08:33:17 AM UTC 25 Feb 09 08:33:20 AM UTC 25 26883221 ps
T100 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3601398465 Feb 09 08:33:18 AM UTC 25 Feb 09 08:33:21 AM UTC 25 79043993 ps
T111 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.862739222 Feb 09 08:33:15 AM UTC 25 Feb 09 08:33:21 AM UTC 25 128692796 ps
T1088 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.3873159181 Feb 09 08:33:19 AM UTC 25 Feb 09 08:33:21 AM UTC 25 19714954 ps
T153 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.417765880 Feb 09 08:33:19 AM UTC 25 Feb 09 08:33:22 AM UTC 25 14364767 ps
T109 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1251120672 Feb 09 08:33:15 AM UTC 25 Feb 09 08:33:23 AM UTC 25 112669088 ps
T124 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1110078796 Feb 09 08:33:18 AM UTC 25 Feb 09 08:33:23 AM UTC 25 85080016 ps
T99 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1661503835 Feb 09 08:33:19 AM UTC 25 Feb 09 08:33:23 AM UTC 25 70182084 ps
T140 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2478399021 Feb 09 08:33:14 AM UTC 25 Feb 09 08:33:23 AM UTC 25 540438043 ps
T123 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.3061033884 Feb 09 08:33:19 AM UTC 25 Feb 09 08:33:23 AM UTC 25 345258147 ps
T132 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.544008494 Feb 09 08:33:19 AM UTC 25 Feb 09 08:33:23 AM UTC 25 589998690 ps
T1089 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1790705931 Feb 09 08:33:20 AM UTC 25 Feb 09 08:33:23 AM UTC 25 96074222 ps
T141 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.3091133617 Feb 09 08:33:20 AM UTC 25 Feb 09 08:33:23 AM UTC 25 31870057 ps
T1090 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2685815852 Feb 09 08:33:17 AM UTC 25 Feb 09 08:33:23 AM UTC 25 3843464456 ps
T1091 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.1735209094 Feb 09 08:33:13 AM UTC 25 Feb 09 08:33:24 AM UTC 25 1024834023 ps
T128 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2229477483 Feb 09 08:33:19 AM UTC 25 Feb 09 08:33:25 AM UTC 25 126381759 ps
T101 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3413094703 Feb 09 08:33:22 AM UTC 25 Feb 09 08:33:25 AM UTC 25 45824945 ps
T1092 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3949561849 Feb 09 08:33:21 AM UTC 25 Feb 09 08:33:26 AM UTC 25 42035275 ps
T1093 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.4186529108 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:26 AM UTC 25 39655063 ps
T142 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2188967650 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:26 AM UTC 25 40502638 ps
T1094 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.352973754 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:26 AM UTC 25 38438581 ps
T1095 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.4182599102 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:26 AM UTC 25 63992971 ps
T133 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3112618902 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:27 AM UTC 25 63125746 ps
T121 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2244650704 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:27 AM UTC 25 298957632 ps
T102 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.813746213 Feb 09 08:33:32 AM UTC 25 Feb 09 08:33:35 AM UTC 25 45218348 ps
T127 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3710740984 Feb 09 08:33:22 AM UTC 25 Feb 09 08:33:27 AM UTC 25 94003433 ps
T103 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2835775463 Feb 09 08:33:22 AM UTC 25 Feb 09 08:33:27 AM UTC 25 65343684 ps
T1096 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2621877526 Feb 09 08:33:17 AM UTC 25 Feb 09 08:33:27 AM UTC 25 585868635 ps
T1097 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.587389046 Feb 09 08:33:25 AM UTC 25 Feb 09 08:33:28 AM UTC 25 24513460 ps
T1098 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1858555561 Feb 09 08:33:26 AM UTC 25 Feb 09 08:33:29 AM UTC 25 107960372 ps
T129 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.2558826412 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:29 AM UTC 25 263597611 ps
T122 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2158889849 Feb 09 08:33:26 AM UTC 25 Feb 09 08:33:29 AM UTC 25 106959286 ps
T1099 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.1769323936 Feb 09 08:33:27 AM UTC 25 Feb 09 08:33:30 AM UTC 25 35402891 ps
T154 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.1646186649 Feb 09 08:33:28 AM UTC 25 Feb 09 08:33:30 AM UTC 25 42172043 ps
T134 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.1457790292 Feb 09 08:33:27 AM UTC 25 Feb 09 08:33:30 AM UTC 25 192866281 ps
T143 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2876443873 Feb 09 08:33:28 AM UTC 25 Feb 09 08:33:30 AM UTC 25 34926716 ps
T1100 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2184019418 Feb 09 08:33:28 AM UTC 25 Feb 09 08:33:30 AM UTC 25 119046258 ps
T1101 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.4279614491 Feb 09 08:33:21 AM UTC 25 Feb 09 08:33:31 AM UTC 25 557806615 ps
T144 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1834824071 Feb 09 08:33:27 AM UTC 25 Feb 09 08:33:31 AM UTC 25 71687098 ps
T1102 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2480272576 Feb 09 08:33:20 AM UTC 25 Feb 09 08:33:31 AM UTC 25 522948879 ps
T161 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1449574135 Feb 09 08:33:27 AM UTC 25 Feb 09 08:33:32 AM UTC 25 120205377 ps
T117 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.161213955 Feb 09 08:33:27 AM UTC 25 Feb 09 08:33:32 AM UTC 25 269544600 ps
T1103 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3742505112 Feb 09 08:33:29 AM UTC 25 Feb 09 08:33:32 AM UTC 25 85473483 ps
T1104 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3121250960 Feb 09 08:33:30 AM UTC 25 Feb 09 08:33:32 AM UTC 25 54266666 ps
T1105 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.619050091 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:33 AM UTC 25 521574523 ps
T1106 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2033678707 Feb 09 08:33:29 AM UTC 25 Feb 09 08:33:33 AM UTC 25 354903535 ps
T155 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.4042421975 Feb 09 08:33:31 AM UTC 25 Feb 09 08:33:33 AM UTC 25 32953013 ps
T1107 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2663394568 Feb 09 08:33:24 AM UTC 25 Feb 09 08:33:33 AM UTC 25 142238025 ps
T1108 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.430958028 Feb 09 08:33:31 AM UTC 25 Feb 09 08:33:33 AM UTC 25 102187974 ps
T1109 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1599379507 Feb 09 08:33:31 AM UTC 25 Feb 09 08:33:35 AM UTC 25 199723392 ps
T112 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3994493886 Feb 09 08:33:30 AM UTC 25 Feb 09 08:33:34 AM UTC 25 50425184 ps
T1110 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3969872835 Feb 09 08:33:32 AM UTC 25 Feb 09 08:33:35 AM UTC 25 123316910 ps
T156 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.512868582 Feb 09 08:33:33 AM UTC 25 Feb 09 08:33:36 AM UTC 25 40928730 ps
T1111 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1191903669 Feb 09 08:33:31 AM UTC 25 Feb 09 08:33:36 AM UTC 25 336075528 ps
T1112 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.333942647 Feb 09 08:33:33 AM UTC 25 Feb 09 08:33:36 AM UTC 25 97324189 ps
T162 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1844863470 Feb 09 08:33:32 AM UTC 25 Feb 09 08:33:37 AM UTC 25 113841629 ps
T1113 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3394159537 Feb 09 08:33:35 AM UTC 25 Feb 09 08:33:37 AM UTC 25 15474527 ps
T1114 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.2672768903 Feb 09 08:33:28 AM UTC 25 Feb 09 08:33:37 AM UTC 25 134633884 ps
T115 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.315323686 Feb 09 08:33:32 AM UTC 25 Feb 09 08:33:37 AM UTC 25 46197750 ps
T1115 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2666770734 Feb 09 08:33:35 AM UTC 25 Feb 09 08:33:37 AM UTC 25 71262245 ps
T1116 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2896807511 Feb 09 08:33:35 AM UTC 25 Feb 09 08:33:37 AM UTC 25 196694625 ps
T1117 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.959072504 Feb 09 08:33:35 AM UTC 25 Feb 09 08:33:38 AM UTC 25 71275587 ps
T1118 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3035476797 Feb 09 08:33:28 AM UTC 25 Feb 09 08:33:38 AM UTC 25 843399506 ps
T1119 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3441569911 Feb 09 08:33:33 AM UTC 25 Feb 09 08:33:38 AM UTC 25 112973817 ps
T1120 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2801967859 Feb 09 08:33:33 AM UTC 25 Feb 09 08:33:38 AM UTC 25 428182779 ps
T1121 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1163561886 Feb 09 08:33:36 AM UTC 25 Feb 09 08:33:38 AM UTC 25 20698746 ps
T1122 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1578595765 Feb 09 08:33:36 AM UTC 25 Feb 09 08:33:39 AM UTC 25 273675612 ps
T1123 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.584229363 Feb 09 08:33:37 AM UTC 25 Feb 09 08:33:40 AM UTC 25 42587993 ps
T1124 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3159131186 Feb 09 08:33:36 AM UTC 25 Feb 09 08:33:40 AM UTC 25 427857765 ps
T116 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2109273056 Feb 09 08:33:37 AM UTC 25 Feb 09 08:33:40 AM UTC 25 59826273 ps
T1125 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3139427415 Feb 09 08:33:38 AM UTC 25 Feb 09 08:33:41 AM UTC 25 109993547 ps
T1126 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.4133013900 Feb 09 08:33:35 AM UTC 25 Feb 09 08:33:41 AM UTC 25 699932975 ps
T1127 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.746345005 Feb 09 08:33:38 AM UTC 25 Feb 09 08:33:41 AM UTC 25 130599077 ps
T1128 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2492527487 Feb 09 08:33:36 AM UTC 25 Feb 09 08:33:41 AM UTC 25 143586205 ps
T1129 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.448701302 Feb 09 08:33:38 AM UTC 25 Feb 09 08:33:42 AM UTC 25 81877906 ps
T1130 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3939285430 Feb 09 08:33:39 AM UTC 25 Feb 09 08:33:42 AM UTC 25 35358154 ps
T1131 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2694368815 Feb 09 08:33:38 AM UTC 25 Feb 09 08:33:42 AM UTC 25 138347038 ps
T1132 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2056065407 Feb 09 08:33:39 AM UTC 25 Feb 09 08:33:42 AM UTC 25 57855472 ps
T1133 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1285563696 Feb 09 08:33:38 AM UTC 25 Feb 09 08:33:42 AM UTC 25 36072825 ps
T113 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2490531895 Feb 09 08:33:38 AM UTC 25 Feb 09 08:33:42 AM UTC 25 32471895 ps
T1134 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1876237709 Feb 09 08:33:37 AM UTC 25 Feb 09 08:33:42 AM UTC 25 123566416 ps
T1135 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2155777969 Feb 09 08:33:40 AM UTC 25 Feb 09 08:33:42 AM UTC 25 90956506 ps
T1136 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2998038343 Feb 09 08:33:40 AM UTC 25 Feb 09 08:33:43 AM UTC 25 342101765 ps
T1137 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1257872417 Feb 09 08:33:41 AM UTC 25 Feb 09 08:33:43 AM UTC 25 23691491 ps
T1138 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1756556017 Feb 09 08:33:38 AM UTC 25 Feb 09 08:33:43 AM UTC 25 103491287 ps
T1139 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.547367405 Feb 09 08:33:41 AM UTC 25 Feb 09 08:33:44 AM UTC 25 118426734 ps
T1140 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1481831971 Feb 09 08:33:42 AM UTC 25 Feb 09 08:33:44 AM UTC 25 62117986 ps
T1141 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2103247195 Feb 09 08:33:40 AM UTC 25 Feb 09 08:33:44 AM UTC 25 89928727 ps
T167 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.695100431 Feb 09 08:33:41 AM UTC 25 Feb 09 08:33:45 AM UTC 25 474165643 ps
T114 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.4278530146 Feb 09 08:33:41 AM UTC 25 Feb 09 08:33:45 AM UTC 25 195768003 ps
T1142 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.207129604 Feb 09 08:33:42 AM UTC 25 Feb 09 08:33:45 AM UTC 25 37553641 ps
T1143 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1862390469 Feb 09 08:33:42 AM UTC 25 Feb 09 08:33:45 AM UTC 25 93409609 ps
T1144 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2446451996 Feb 09 08:33:42 AM UTC 25 Feb 09 08:33:46 AM UTC 25 83300125 ps
T1145 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2533481268 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:46 AM UTC 25 82565915 ps
T1146 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3612707381 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:46 AM UTC 25 33339367 ps
T1147 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2179478787 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:46 AM UTC 25 16870660 ps
T1148 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.359836686 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:47 AM UTC 25 174698558 ps
T1149 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2543457511 Feb 09 08:33:44 AM UTC 25 Feb 09 08:33:47 AM UTC 25 21576462 ps
T1150 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1318221805 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:47 AM UTC 25 456707381 ps
T1151 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1245639581 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:48 AM UTC 25 56961353 ps
T1152 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2404757535 Feb 09 08:33:46 AM UTC 25 Feb 09 08:33:48 AM UTC 25 72760235 ps
T1153 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1598210017 Feb 09 08:33:46 AM UTC 25 Feb 09 08:33:48 AM UTC 25 35241313 ps
T1154 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.438921373 Feb 09 08:33:44 AM UTC 25 Feb 09 08:33:49 AM UTC 25 189639852 ps
T1155 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.292492823 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:49 AM UTC 25 518545341 ps
T118 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2863679702 Feb 09 08:33:43 AM UTC 25 Feb 09 08:33:49 AM UTC 25 119295344 ps
T1156 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1623431556 Feb 09 08:33:46 AM UTC 25 Feb 09 08:33:49 AM UTC 25 380952197 ps
T1157 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3846544144 Feb 09 08:33:47 AM UTC 25 Feb 09 08:33:49 AM UTC 25 29102282 ps
T1158 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.753312884 Feb 09 08:33:47 AM UTC 25 Feb 09 08:33:50 AM UTC 25 27156041 ps
T1159 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2127383478 Feb 09 08:33:46 AM UTC 25 Feb 09 08:33:50 AM UTC 25 81700483 ps
T119 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2504386205 Feb 09 08:33:46 AM UTC 25 Feb 09 08:33:50 AM UTC 25 108798602 ps
T1160 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1736883382 Feb 09 08:33:46 AM UTC 25 Feb 09 08:33:50 AM UTC 25 222546915 ps
T165 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1327956178 Feb 09 08:33:44 AM UTC 25 Feb 09 08:33:50 AM UTC 25 116655763 ps
T1161 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3870590359 Feb 09 08:33:48 AM UTC 25 Feb 09 08:33:51 AM UTC 25 134964992 ps
T125 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1472361611 Feb 09 08:33:48 AM UTC 25 Feb 09 08:33:51 AM UTC 25 23582799 ps
T1162 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2982654275 Feb 09 08:33:47 AM UTC 25 Feb 09 08:33:51 AM UTC 25 37861288 ps
T126 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2305455171 Feb 09 08:33:44 AM UTC 25 Feb 09 08:33:51 AM UTC 25 218206198 ps
T1163 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.753260146 Feb 09 08:33:48 AM UTC 25 Feb 09 08:33:51 AM UTC 25 30221535 ps
T1164 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.844156016 Feb 09 08:33:49 AM UTC 25 Feb 09 08:33:51 AM UTC 25 39523493 ps
T1165 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1042147771 Feb 09 08:33:48 AM UTC 25 Feb 09 08:33:52 AM UTC 25 54412944 ps
T163 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1235275728 Feb 09 08:33:47 AM UTC 25 Feb 09 08:33:52 AM UTC 25 134185909 ps
T1166 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1966977830 Feb 09 08:33:49 AM UTC 25 Feb 09 08:33:52 AM UTC 25 13575181 ps
T1167 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2218182671 Feb 09 08:33:50 AM UTC 25 Feb 09 08:33:53 AM UTC 25 23049406 ps
T1168 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.365009747 Feb 09 08:33:51 AM UTC 25 Feb 09 08:33:53 AM UTC 25 38758742 ps
T1169 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.131043976 Feb 09 08:33:50 AM UTC 25 Feb 09 08:33:53 AM UTC 25 42816824 ps
T1170 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1558254439 Feb 09 08:33:51 AM UTC 25 Feb 09 08:33:54 AM UTC 25 51653617 ps
T1171 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.22543313 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:54 AM UTC 25 15150974 ps
T1172 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.198869592 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:54 AM UTC 25 21141869 ps
T1173 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2429523464 Feb 09 08:33:50 AM UTC 25 Feb 09 08:33:54 AM UTC 25 100071025 ps
T1174 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1476285691 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:54 AM UTC 25 66653644 ps
T1175 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2096225806 Feb 09 08:33:50 AM UTC 25 Feb 09 08:33:55 AM UTC 25 138716917 ps
T164 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.366215714 Feb 09 08:33:49 AM UTC 25 Feb 09 08:33:55 AM UTC 25 294931067 ps
T1176 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3171809081 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:55 AM UTC 25 192775379 ps
T1177 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.4118447410 Feb 09 08:33:53 AM UTC 25 Feb 09 08:33:56 AM UTC 25 259821003 ps
T1178 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3783878864 Feb 09 08:33:53 AM UTC 25 Feb 09 08:33:56 AM UTC 25 65553292 ps
T1179 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.512306761 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:56 AM UTC 25 329809638 ps
T1180 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.799216233 Feb 09 08:33:53 AM UTC 25 Feb 09 08:33:57 AM UTC 25 96003239 ps
T1181 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.994268227 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:57 AM UTC 25 455719528 ps
T1182 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3965606128 Feb 09 08:33:53 AM UTC 25 Feb 09 08:33:57 AM UTC 25 41611147 ps
T1183 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.301505569 Feb 09 08:33:54 AM UTC 25 Feb 09 08:33:57 AM UTC 25 362092455 ps
T1184 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3997917231 Feb 09 08:33:55 AM UTC 25 Feb 09 08:33:58 AM UTC 25 19906177 ps
T1185 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1266783982 Feb 09 08:33:55 AM UTC 25 Feb 09 08:33:58 AM UTC 25 17124995 ps
T1186 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3284561687 Feb 09 08:33:54 AM UTC 25 Feb 09 08:33:58 AM UTC 25 242839731 ps
T166 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2111720216 Feb 09 08:33:51 AM UTC 25 Feb 09 08:33:58 AM UTC 25 877293043 ps
T1187 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2335876790 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:58 AM UTC 25 140287876 ps
T1188 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3540016878 Feb 09 08:33:52 AM UTC 25 Feb 09 08:33:58 AM UTC 25 353617769 ps
T1189 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1945103169 Feb 09 08:33:55 AM UTC 25 Feb 09 08:33:59 AM UTC 25 243605953 ps
T1190 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3053330033 Feb 09 08:33:57 AM UTC 25 Feb 09 08:33:59 AM UTC 25 34617341 ps
T1191 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1275252847 Feb 09 08:33:55 AM UTC 25 Feb 09 08:33:59 AM UTC 25 29118335 ps
T1192 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.19130012 Feb 09 08:33:56 AM UTC 25 Feb 09 08:33:59 AM UTC 25 31452252 ps
T1193 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.930313621 Feb 09 08:33:56 AM UTC 25 Feb 09 08:34:00 AM UTC 25 68034950 ps
T1194 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2017001133 Feb 09 08:33:58 AM UTC 25 Feb 09 08:34:00 AM UTC 25 15765698 ps
T1195 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3015726411 Feb 09 08:33:58 AM UTC 25 Feb 09 08:34:01 AM UTC 25 113617589 ps
T1196 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3306955546 Feb 09 08:33:58 AM UTC 25 Feb 09 08:34:01 AM UTC 25 149099237 ps
T1197 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1274184679 Feb 09 08:33:59 AM UTC 25 Feb 09 08:34:01 AM UTC 25 35775368 ps
T1198 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2734881639 Feb 09 08:33:58 AM UTC 25 Feb 09 08:34:01 AM UTC 25 184043182 ps
T1199 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2366951582 Feb 09 08:33:55 AM UTC 25 Feb 09 08:34:02 AM UTC 25 260465430 ps
T1200 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.123124382 Feb 09 08:33:57 AM UTC 25 Feb 09 08:34:02 AM UTC 25 427126512 ps
T1201 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1144360526 Feb 09 08:33:58 AM UTC 25 Feb 09 08:34:02 AM UTC 25 453449606 ps
T1202 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.4212561411 Feb 09 08:33:59 AM UTC 25 Feb 09 08:34:02 AM UTC 25 82518590 ps
T1203 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2123484261 Feb 09 08:33:59 AM UTC 25 Feb 09 08:34:02 AM UTC 25 36896092 ps
T1204 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1516617378 Feb 09 08:34:00 AM UTC 25 Feb 09 08:34:02 AM UTC 25 43619477 ps
T1205 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2501202003 Feb 09 08:33:57 AM UTC 25 Feb 09 08:34:02 AM UTC 25 530946261 ps
T1206 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3384572188 Feb 09 08:34:00 AM UTC 25 Feb 09 08:34:02 AM UTC 25 15393795 ps
T1207 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1129840390 Feb 09 08:34:00 AM UTC 25 Feb 09 08:34:02 AM UTC 25 37945570 ps
T1208 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2108911602 Feb 09 08:34:00 AM UTC 25 Feb 09 08:34:03 AM UTC 25 15071260 ps
T1209 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4100916557 Feb 09 08:33:59 AM UTC 25 Feb 09 08:34:03 AM UTC 25 49474186 ps
T1210 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1036752520 Feb 09 08:34:01 AM UTC 25 Feb 09 08:34:04 AM UTC 25 193378716 ps
T1211 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3104504250 Feb 09 08:34:01 AM UTC 25 Feb 09 08:34:04 AM UTC 25 24759171 ps
T1212 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.941090617 Feb 09 08:34:02 AM UTC 25 Feb 09 08:34:04 AM UTC 25 48327854 ps
T168 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1595410800 Feb 09 08:33:59 AM UTC 25 Feb 09 08:34:04 AM UTC 25 189429797 ps
T1213 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.692853855 Feb 09 08:34:01 AM UTC 25 Feb 09 08:34:04 AM UTC 25 42775292 ps
T1214 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3461229856 Feb 09 08:34:01 AM UTC 25 Feb 09 08:34:04 AM UTC 25 19463284 ps
T1215 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2926254265 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 47985987 ps
T1216 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.196981918 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 24279012 ps
T1217 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3737656427 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 22712909 ps
T1218 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3131567350 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 17103957 ps
T1219 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.1809866359 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 48191750 ps
T1220 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1538400575 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 13844795 ps
T1221 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1091653836 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 15388864 ps
T1222 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.996618958 Feb 09 08:34:03 AM UTC 25 Feb 09 08:34:05 AM UTC 25 19091953 ps
T157 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1877180611 Feb 09 08:33:59 AM UTC 25 Feb 09 08:34:05 AM UTC 25 580045290 ps
T1223 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.838643102 Feb 09 08:34:04 AM UTC 25 Feb 09 08:34:06 AM UTC 25 22197897 ps
T1224 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.882791051 Feb 09 08:34:04 AM UTC 25 Feb 09 08:34:06 AM UTC 25 49567672 ps
T1225 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.961269376 Feb 09 08:34:04 AM UTC 25 Feb 09 08:34:06 AM UTC 25 24465869 ps
T1226 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2605907239 Feb 09 08:34:04 AM UTC 25 Feb 09 08:34:06 AM UTC 25 35783543 ps
T1227 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.959294612 Feb 09 08:34:04 AM UTC 25 Feb 09 08:34:07 AM UTC 25 45099638 ps
T1228 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.529790947 Feb 09 08:34:04 AM UTC 25 Feb 09 08:34:07 AM UTC 25 41029062 ps
T1229 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.4194581853 Feb 09 08:34:05 AM UTC 25 Feb 09 08:34:07 AM UTC 25 41235387 ps
T1230 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.458344589 Feb 09 08:34:05 AM UTC 25 Feb 09 08:34:08 AM UTC 25 47388572 ps
T1231 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2531393400 Feb 09 08:34:05 AM UTC 25 Feb 09 08:34:08 AM UTC 25 29911165 ps
T1232 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1633624493 Feb 09 08:34:05 AM UTC 25 Feb 09 08:34:08 AM UTC 25 14648446 ps
T1233 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.811054108 Feb 09 08:34:05 AM UTC 25 Feb 09 08:34:08 AM UTC 25 43898748 ps
T1234 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1689088108 Feb 09 08:34:06 AM UTC 25 Feb 09 08:34:09 AM UTC 25 44610688 ps
T1235 /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3635870513 Feb 09 08:34:06 AM UTC 25 Feb 09 08:34:09 AM UTC 25 16887411 ps

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.2500175244
Short name T4
Test name
Test status
Simulation time 689440233 ps
CPU time 26.07 seconds
Started Feb 09 08:34:23 AM UTC 25
Finished Feb 09 08:34:51 AM UTC 25
Peak memory 251924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500175244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2500175244 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2415975659
Short name T23
Test name
Test status
Simulation time 10377099030 ps
CPU time 279.36 seconds
Started Feb 09 08:34:09 AM UTC 25
Finished Feb 09 08:38:52 AM UTC 25
Peak memory 415816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415975659 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2415975659 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1885522864
Short name T108
Test name
Test status
Simulation time 946141730 ps
CPU time 5.63 seconds
Started Feb 09 08:33:31 AM UTC 25
Finished Feb 09 08:33:38 AM UTC 25
Peak memory 229092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885522864 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1885522864 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.1228195233
Short name T5
Test name
Test status
Simulation time 8465721172 ps
CPU time 77.1 seconds
Started Feb 09 08:34:49 AM UTC 25
Finished Feb 09 08:36:08 AM UTC 25
Peak memory 267328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228195233 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1228195233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.1853729659
Short name T26
Test name
Test status
Simulation time 5150738659 ps
CPU time 373.97 seconds
Started Feb 09 08:34:09 AM UTC 25
Finished Feb 09 08:40:28 AM UTC 25
Peak memory 405508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853729659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.kmac_error.1853729659 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.663268402
Short name T19
Test name
Test status
Simulation time 315949236 ps
CPU time 3.47 seconds
Started Feb 09 08:38:14 AM UTC 25
Finished Feb 09 08:38:18 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663268402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.663268402 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1989126766
Short name T98
Test name
Test status
Simulation time 57484977 ps
CPU time 2.92 seconds
Started Feb 09 08:33:14 AM UTC 25
Finished Feb 09 08:33:18 AM UTC 25
Peak memory 229984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989126766 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.1989126766 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.3847005824
Short name T42
Test name
Test status
Simulation time 2597167418 ps
CPU time 24.98 seconds
Started Feb 09 08:41:21 AM UTC 25
Finished Feb 09 08:41:48 AM UTC 25
Peak memory 251912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847005824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3847005824 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.862739222
Short name T111
Test name
Test status
Simulation time 128692796 ps
CPU time 4.54 seconds
Started Feb 09 08:33:15 AM UTC 25
Finished Feb 09 08:33:21 AM UTC 25
Peak memory 229568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862739222 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.862739222 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.417765880
Short name T153
Test name
Test status
Simulation time 14364767 ps
CPU time 1.22 seconds
Started Feb 09 08:33:19 AM UTC 25
Finished Feb 09 08:33:22 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417765880 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.417765880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.1633244633
Short name T9
Test name
Test status
Simulation time 150654978 ps
CPU time 2.67 seconds
Started Feb 09 11:08:12 AM UTC 25
Finished Feb 09 11:08:16 AM UTC 25
Peak memory 235320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633244633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1633244633 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.3024415172
Short name T76
Test name
Test status
Simulation time 84505970941 ps
CPU time 1207.54 seconds
Started Feb 09 08:34:33 AM UTC 25
Finished Feb 09 08:54:54 AM UTC 25
Peak memory 1024384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024415172 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3024415172 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.1879336888
Short name T17
Test name
Test status
Simulation time 823049849 ps
CPU time 51.89 seconds
Started Feb 09 08:34:52 AM UTC 25
Finished Feb 09 08:35:46 AM UTC 25
Peak memory 230724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879336888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.kmac_smoke.1879336888 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.1520424918
Short name T90
Test name
Test status
Simulation time 509960089 ps
CPU time 5.84 seconds
Started Feb 09 10:01:57 AM UTC 25
Finished Feb 09 10:02:04 AM UTC 25
Peak memory 232816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520424918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1520424918 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.208883230
Short name T96
Test name
Test status
Simulation time 439193364 ps
CPU time 4.07 seconds
Started Feb 09 08:33:12 AM UTC 25
Finished Feb 09 08:33:17 AM UTC 25
Peak memory 237068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208883230 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.208883230 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.54673003
Short name T48
Test name
Test status
Simulation time 4348480152 ps
CPU time 425.45 seconds
Started Feb 09 09:41:47 AM UTC 25
Finished Feb 09 09:48:58 AM UTC 25
Peak memory 245828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54673003 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.54673003 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.3710124414
Short name T18
Test name
Test status
Simulation time 64102371 ps
CPU time 1.26 seconds
Started Feb 09 08:34:52 AM UTC 25
Finished Feb 09 08:34:55 AM UTC 25
Peak memory 214468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710124414 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3710124414 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2677004601
Short name T131
Test name
Test status
Simulation time 42086381 ps
CPU time 1.49 seconds
Started Feb 09 08:33:15 AM UTC 25
Finished Feb 09 08:33:18 AM UTC 25
Peak memory 228792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677004601 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2677004601 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.3056344774
Short name T8
Test name
Test status
Simulation time 82524472 ps
CPU time 1.92 seconds
Started Feb 09 09:48:36 AM UTC 25
Finished Feb 09 09:48:40 AM UTC 25
Peak memory 229816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056344774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3056344774 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.4293457014
Short name T58
Test name
Test status
Simulation time 88171266 ps
CPU time 2.13 seconds
Started Feb 09 10:07:52 AM UTC 25
Finished Feb 09 10:07:56 AM UTC 25
Peak memory 230580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293457014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.4293457014 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2305455171
Short name T126
Test name
Test status
Simulation time 218206198 ps
CPU time 5.22 seconds
Started Feb 09 08:33:44 AM UTC 25
Finished Feb 09 08:33:51 AM UTC 25
Peak memory 229548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305455171 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2305455171 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.1777759818
Short name T28
Test name
Test status
Simulation time 3749702688 ps
CPU time 335.61 seconds
Started Feb 09 08:54:16 AM UTC 25
Finished Feb 09 08:59:56 AM UTC 25
Peak memory 358408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777759818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.kmac_error.1777759818 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1251120672
Short name T109
Test name
Test status
Simulation time 112669088 ps
CPU time 5.79 seconds
Started Feb 09 08:33:15 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251120672 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.1251120672 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.512868582
Short name T156
Test name
Test status
Simulation time 40928730 ps
CPU time 1.01 seconds
Started Feb 09 08:33:33 AM UTC 25
Finished Feb 09 08:33:36 AM UTC 25
Peak memory 218916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512868582 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.512868582 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_shake_128.2760487838
Short name T149
Test name
Test status
Simulation time 196614020953 ps
CPU time 5524.51 seconds
Started Feb 09 10:29:46 AM UTC 25
Finished Feb 09 12:02:49 PM UTC 25
Peak memory 2721724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760487838 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.2760487838 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.171878990
Short name T24
Test name
Test status
Simulation time 21851113603 ps
CPU time 66.14 seconds
Started Feb 09 08:38:19 AM UTC 25
Finished Feb 09 08:39:27 AM UTC 25
Peak memory 230860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171878990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.171878990 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.366215714
Short name T164
Test name
Test status
Simulation time 294931067 ps
CPU time 4.69 seconds
Started Feb 09 08:33:49 AM UTC 25
Finished Feb 09 08:33:55 AM UTC 25
Peak memory 219256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366215714 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.366215714 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1724704126
Short name T106
Test name
Test status
Simulation time 31769497418 ps
CPU time 343.22 seconds
Started Feb 09 08:36:32 AM UTC 25
Finished Feb 09 08:42:21 AM UTC 25
Peak memory 343916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724704126 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1724704126 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_shake_128.2994308971
Short name T150
Test name
Test status
Simulation time 108691610419 ps
CPU time 4925.79 seconds
Started Feb 09 11:04:26 AM UTC 25
Finished Feb 09 12:27:24 PM UTC 25
Peak memory 2719728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994308971 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2994308971 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.4278530146
Short name T114
Test name
Test status
Simulation time 195768003 ps
CPU time 3.14 seconds
Started Feb 09 08:33:41 AM UTC 25
Finished Feb 09 08:33:45 AM UTC 25
Peak memory 229680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278530146 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.4278530146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.4051358258
Short name T320
Test name
Test status
Simulation time 6775209360 ps
CPU time 191.63 seconds
Started Feb 09 09:25:48 AM UTC 25
Finished Feb 09 09:29:03 AM UTC 25
Peak memory 382980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051358258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.kmac_error.4051358258 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1595410800
Short name T168
Test name
Test status
Simulation time 189429797 ps
CPU time 3.59 seconds
Started Feb 09 08:33:59 AM UTC 25
Finished Feb 09 08:34:04 AM UTC 25
Peak memory 219232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595410800 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1595410800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.729992643
Short name T33
Test name
Test status
Simulation time 10958207849 ps
CPU time 330.81 seconds
Started Feb 09 08:34:09 AM UTC 25
Finished Feb 09 08:39:44 AM UTC 25
Peak memory 491912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729992643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.kmac_mubi.729992643 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.362684206
Short name T21
Test name
Test status
Simulation time 8687260544 ps
CPU time 114.14 seconds
Started Feb 09 08:34:09 AM UTC 25
Finished Feb 09 08:36:06 AM UTC 25
Peak memory 292932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362684206 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.362684206 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2478399021
Short name T140
Test name
Test status
Simulation time 540438043 ps
CPU time 7.3 seconds
Started Feb 09 08:33:14 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 219196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478399021 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2478399021 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.1735209094
Short name T1091
Test name
Test status
Simulation time 1024834023 ps
CPU time 9.17 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:24 AM UTC 25
Peak memory 219132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735209094 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1735209094 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1059348719
Short name T94
Test name
Test status
Simulation time 48798406 ps
CPU time 1.26 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:16 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059348719 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1059348719 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2809038683
Short name T107
Test name
Test status
Simulation time 70495839 ps
CPU time 3.39 seconds
Started Feb 09 08:33:14 AM UTC 25
Finished Feb 09 08:33:19 AM UTC 25
Peak memory 231548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2809038683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset
.2809038683 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.971669017
Short name T95
Test name
Test status
Simulation time 105906728 ps
CPU time 1.3 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:16 AM UTC 25
Peak memory 218800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971669017 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.971669017 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.403798949
Short name T110
Test name
Test status
Simulation time 21214866 ps
CPU time 1.17 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:15 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403798949 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.403798949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1519915415
Short name T130
Test name
Test status
Simulation time 130273384 ps
CPU time 1.79 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:16 AM UTC 25
Peak memory 228756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519915415 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1519915415 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.3397309368
Short name T1083
Test name
Test status
Simulation time 10685917 ps
CPU time 0.87 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:15 AM UTC 25
Peak memory 218820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397309368 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3397309368 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1644986929
Short name T1085
Test name
Test status
Simulation time 310385982 ps
CPU time 2.8 seconds
Started Feb 09 08:33:14 AM UTC 25
Finished Feb 09 08:33:18 AM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644986929 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1644986929 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3211325849
Short name T93
Test name
Test status
Simulation time 76091139 ps
CPU time 1.23 seconds
Started Feb 09 08:33:12 AM UTC 25
Finished Feb 09 08:33:14 AM UTC 25
Peak memory 229464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211325849 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.3211325849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2444588677
Short name T54
Test name
Test status
Simulation time 103725250 ps
CPU time 2.08 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:16 AM UTC 25
Peak memory 229616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444588677 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2444588677 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3624128440
Short name T56
Test name
Test status
Simulation time 159261115 ps
CPU time 3.56 seconds
Started Feb 09 08:33:13 AM UTC 25
Finished Feb 09 08:33:18 AM UTC 25
Peak memory 229412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624128440 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.3624128440 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2685815852
Short name T1090
Test name
Test status
Simulation time 3843464456 ps
CPU time 5.21 seconds
Started Feb 09 08:33:17 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 219196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685815852 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2685815852 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2621877526
Short name T1096
Test name
Test status
Simulation time 585868635 ps
CPU time 9.03 seconds
Started Feb 09 08:33:17 AM UTC 25
Finished Feb 09 08:33:27 AM UTC 25
Peak memory 218868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621877526 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2621877526 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.3060579439
Short name T139
Test name
Test status
Simulation time 28236662 ps
CPU time 1.49 seconds
Started Feb 09 08:33:17 AM UTC 25
Finished Feb 09 08:33:19 AM UTC 25
Peak memory 217824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060579439 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3060579439 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1110078796
Short name T124
Test name
Test status
Simulation time 85080016 ps
CPU time 3.52 seconds
Started Feb 09 08:33:18 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 231548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1110078796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset
.1110078796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.1930598676
Short name T1086
Test name
Test status
Simulation time 57451541 ps
CPU time 1.67 seconds
Started Feb 09 08:33:17 AM UTC 25
Finished Feb 09 08:33:19 AM UTC 25
Peak memory 227636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930598676 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1930598676 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3961655496
Short name T120
Test name
Test status
Simulation time 42078396 ps
CPU time 1.13 seconds
Started Feb 09 08:33:16 AM UTC 25
Finished Feb 09 08:33:18 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961655496 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3961655496 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2103014367
Short name T1084
Test name
Test status
Simulation time 14821370 ps
CPU time 1.11 seconds
Started Feb 09 08:33:15 AM UTC 25
Finished Feb 09 08:33:18 AM UTC 25
Peak memory 218852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103014367 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2103014367 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1352625727
Short name T1087
Test name
Test status
Simulation time 26883221 ps
CPU time 1.98 seconds
Started Feb 09 08:33:17 AM UTC 25
Finished Feb 09 08:33:20 AM UTC 25
Peak memory 228792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352625727 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1352625727 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3594709193
Short name T97
Test name
Test status
Simulation time 65863450 ps
CPU time 1.98 seconds
Started Feb 09 08:33:14 AM UTC 25
Finished Feb 09 08:33:17 AM UTC 25
Peak memory 228476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594709193 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.3594709193 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2446451996
Short name T1144
Test name
Test status
Simulation time 83300125 ps
CPU time 2.32 seconds
Started Feb 09 08:33:42 AM UTC 25
Finished Feb 09 08:33:46 AM UTC 25
Peak memory 231672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2446451996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_rese
t.2446451996 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1481831971
Short name T1140
Test name
Test status
Simulation time 62117986 ps
CPU time 1.21 seconds
Started Feb 09 08:33:42 AM UTC 25
Finished Feb 09 08:33:44 AM UTC 25
Peak memory 218844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481831971 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1481831971 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1257872417
Short name T1137
Test name
Test status
Simulation time 23691491 ps
CPU time 1.13 seconds
Started Feb 09 08:33:41 AM UTC 25
Finished Feb 09 08:33:43 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257872417 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1257872417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1862390469
Short name T1143
Test name
Test status
Simulation time 93409609 ps
CPU time 2.02 seconds
Started Feb 09 08:33:42 AM UTC 25
Finished Feb 09 08:33:45 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862390469 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1862390469 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2155777969
Short name T1135
Test name
Test status
Simulation time 90956506 ps
CPU time 1.55 seconds
Started Feb 09 08:33:40 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 228484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155777969 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.2155777969 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.547367405
Short name T1139
Test name
Test status
Simulation time 118426734 ps
CPU time 2.07 seconds
Started Feb 09 08:33:41 AM UTC 25
Finished Feb 09 08:33:44 AM UTC 25
Peak memory 229596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547367405 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.547367405 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.695100431
Short name T167
Test name
Test status
Simulation time 474165643 ps
CPU time 2.78 seconds
Started Feb 09 08:33:41 AM UTC 25
Finished Feb 09 08:33:45 AM UTC 25
Peak memory 229488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695100431 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.695100431 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1245639581
Short name T1151
Test name
Test status
Simulation time 56961353 ps
CPU time 2.91 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:48 AM UTC 25
Peak memory 236592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1245639581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_rese
t.1245639581 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3612707381
Short name T1146
Test name
Test status
Simulation time 33339367 ps
CPU time 1.14 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:46 AM UTC 25
Peak memory 228764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612707381 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3612707381 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2533481268
Short name T1145
Test name
Test status
Simulation time 82565915 ps
CPU time 1.2 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:46 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533481268 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2533481268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1318221805
Short name T1150
Test name
Test status
Simulation time 456707381 ps
CPU time 2.56 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:47 AM UTC 25
Peak memory 229440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318221805 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.1318221805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.207129604
Short name T1142
Test name
Test status
Simulation time 37553641 ps
CPU time 1.94 seconds
Started Feb 09 08:33:42 AM UTC 25
Finished Feb 09 08:33:45 AM UTC 25
Peak memory 228484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207129604 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.207129604 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.359836686
Short name T1148
Test name
Test status
Simulation time 174698558 ps
CPU time 2.27 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:47 AM UTC 25
Peak memory 229928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359836686 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.359836686 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2863679702
Short name T118
Test name
Test status
Simulation time 119295344 ps
CPU time 4.67 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:49 AM UTC 25
Peak memory 229600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863679702 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2863679702 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.292492823
Short name T1155
Test name
Test status
Simulation time 518545341 ps
CPU time 4.36 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:49 AM UTC 25
Peak memory 229432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292492823 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.292492823 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1623431556
Short name T1156
Test name
Test status
Simulation time 380952197 ps
CPU time 2.31 seconds
Started Feb 09 08:33:46 AM UTC 25
Finished Feb 09 08:33:49 AM UTC 25
Peak memory 231664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1623431556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_rese
t.1623431556 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2404757535
Short name T1152
Test name
Test status
Simulation time 72760235 ps
CPU time 1.43 seconds
Started Feb 09 08:33:46 AM UTC 25
Finished Feb 09 08:33:48 AM UTC 25
Peak memory 218844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404757535 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2404757535 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2543457511
Short name T1149
Test name
Test status
Simulation time 21576462 ps
CPU time 0.99 seconds
Started Feb 09 08:33:44 AM UTC 25
Finished Feb 09 08:33:47 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543457511 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2543457511 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1736883382
Short name T1160
Test name
Test status
Simulation time 222546915 ps
CPU time 3.37 seconds
Started Feb 09 08:33:46 AM UTC 25
Finished Feb 09 08:33:50 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736883382 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.1736883382 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2179478787
Short name T1147
Test name
Test status
Simulation time 16870660 ps
CPU time 1.5 seconds
Started Feb 09 08:33:43 AM UTC 25
Finished Feb 09 08:33:46 AM UTC 25
Peak memory 228544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179478787 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2179478787 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.438921373
Short name T1154
Test name
Test status
Simulation time 189639852 ps
CPU time 3 seconds
Started Feb 09 08:33:44 AM UTC 25
Finished Feb 09 08:33:49 AM UTC 25
Peak memory 229852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438921373 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.438921373 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1327956178
Short name T165
Test name
Test status
Simulation time 116655763 ps
CPU time 4.34 seconds
Started Feb 09 08:33:44 AM UTC 25
Finished Feb 09 08:33:50 AM UTC 25
Peak memory 229500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327956178 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1327956178 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1472361611
Short name T125
Test name
Test status
Simulation time 23582799 ps
CPU time 1.55 seconds
Started Feb 09 08:33:48 AM UTC 25
Finished Feb 09 08:33:51 AM UTC 25
Peak memory 228688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1472361611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_rese
t.1472361611 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.753312884
Short name T1158
Test name
Test status
Simulation time 27156041 ps
CPU time 1.49 seconds
Started Feb 09 08:33:47 AM UTC 25
Finished Feb 09 08:33:50 AM UTC 25
Peak memory 218796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753312884 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.753312884 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3846544144
Short name T1157
Test name
Test status
Simulation time 29102282 ps
CPU time 1.15 seconds
Started Feb 09 08:33:47 AM UTC 25
Finished Feb 09 08:33:49 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846544144 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3846544144 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2982654275
Short name T1162
Test name
Test status
Simulation time 37861288 ps
CPU time 2.85 seconds
Started Feb 09 08:33:47 AM UTC 25
Finished Feb 09 08:33:51 AM UTC 25
Peak memory 229416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982654275 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.2982654275 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1598210017
Short name T1153
Test name
Test status
Simulation time 35241313 ps
CPU time 1.54 seconds
Started Feb 09 08:33:46 AM UTC 25
Finished Feb 09 08:33:48 AM UTC 25
Peak memory 228700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598210017 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.1598210017 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2127383478
Short name T1159
Test name
Test status
Simulation time 81700483 ps
CPU time 2.84 seconds
Started Feb 09 08:33:46 AM UTC 25
Finished Feb 09 08:33:50 AM UTC 25
Peak memory 229748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127383478 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.2127383478 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2504386205
Short name T119
Test name
Test status
Simulation time 108798602 ps
CPU time 2.97 seconds
Started Feb 09 08:33:46 AM UTC 25
Finished Feb 09 08:33:50 AM UTC 25
Peak memory 236564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504386205 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2504386205 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1235275728
Short name T163
Test name
Test status
Simulation time 134185909 ps
CPU time 3.59 seconds
Started Feb 09 08:33:47 AM UTC 25
Finished Feb 09 08:33:52 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235275728 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1235275728 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.131043976
Short name T1169
Test name
Test status
Simulation time 42816824 ps
CPU time 1.73 seconds
Started Feb 09 08:33:50 AM UTC 25
Finished Feb 09 08:33:53 AM UTC 25
Peak memory 228728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
131043976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset
.131043976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1966977830
Short name T1166
Test name
Test status
Simulation time 13575181 ps
CPU time 1.37 seconds
Started Feb 09 08:33:49 AM UTC 25
Finished Feb 09 08:33:52 AM UTC 25
Peak memory 218844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966977830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1966977830 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.844156016
Short name T1164
Test name
Test status
Simulation time 39523493 ps
CPU time 0.82 seconds
Started Feb 09 08:33:49 AM UTC 25
Finished Feb 09 08:33:51 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844156016 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.844156016 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2429523464
Short name T1173
Test name
Test status
Simulation time 100071025 ps
CPU time 2.67 seconds
Started Feb 09 08:33:50 AM UTC 25
Finished Feb 09 08:33:54 AM UTC 25
Peak memory 229440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429523464 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.2429523464 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3870590359
Short name T1161
Test name
Test status
Simulation time 134964992 ps
CPU time 1.46 seconds
Started Feb 09 08:33:48 AM UTC 25
Finished Feb 09 08:33:51 AM UTC 25
Peak memory 228460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870590359 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3870590359 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.753260146
Short name T1163
Test name
Test status
Simulation time 30221535 ps
CPU time 1.75 seconds
Started Feb 09 08:33:48 AM UTC 25
Finished Feb 09 08:33:51 AM UTC 25
Peak memory 228536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753260146 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.753260146 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1042147771
Short name T1165
Test name
Test status
Simulation time 54412944 ps
CPU time 2.18 seconds
Started Feb 09 08:33:48 AM UTC 25
Finished Feb 09 08:33:52 AM UTC 25
Peak memory 229680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042147771 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1042147771 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.512306761
Short name T1179
Test name
Test status
Simulation time 329809638 ps
CPU time 3.29 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:56 AM UTC 25
Peak memory 231408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
512306761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset
.512306761 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.22543313
Short name T1171
Test name
Test status
Simulation time 15150974 ps
CPU time 1.18 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:54 AM UTC 25
Peak memory 218656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22543313 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.22543313 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.365009747
Short name T1168
Test name
Test status
Simulation time 38758742 ps
CPU time 1.07 seconds
Started Feb 09 08:33:51 AM UTC 25
Finished Feb 09 08:33:53 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365009747 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.365009747 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.994268227
Short name T1181
Test name
Test status
Simulation time 455719528 ps
CPU time 3.89 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:57 AM UTC 25
Peak memory 229440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994268227 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.994268227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2218182671
Short name T1167
Test name
Test status
Simulation time 23049406 ps
CPU time 0.95 seconds
Started Feb 09 08:33:50 AM UTC 25
Finished Feb 09 08:33:53 AM UTC 25
Peak memory 218500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218182671 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2218182671 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2096225806
Short name T1175
Test name
Test status
Simulation time 138716917 ps
CPU time 3.36 seconds
Started Feb 09 08:33:50 AM UTC 25
Finished Feb 09 08:33:55 AM UTC 25
Peak memory 229856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096225806 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.2096225806 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1558254439
Short name T1170
Test name
Test status
Simulation time 51653617 ps
CPU time 2.28 seconds
Started Feb 09 08:33:51 AM UTC 25
Finished Feb 09 08:33:54 AM UTC 25
Peak memory 229548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558254439 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1558254439 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2111720216
Short name T166
Test name
Test status
Simulation time 877293043 ps
CPU time 6.33 seconds
Started Feb 09 08:33:51 AM UTC 25
Finished Feb 09 08:33:58 AM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111720216 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2111720216 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3965606128
Short name T1182
Test name
Test status
Simulation time 41611147 ps
CPU time 2.44 seconds
Started Feb 09 08:33:53 AM UTC 25
Finished Feb 09 08:33:57 AM UTC 25
Peak memory 229496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3965606128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_rese
t.3965606128 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.4118447410
Short name T1177
Test name
Test status
Simulation time 259821003 ps
CPU time 1.6 seconds
Started Feb 09 08:33:53 AM UTC 25
Finished Feb 09 08:33:56 AM UTC 25
Peak memory 218796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118447410 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.4118447410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.198869592
Short name T1172
Test name
Test status
Simulation time 21141869 ps
CPU time 1.15 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:54 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198869592 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.198869592 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.799216233
Short name T1180
Test name
Test status
Simulation time 96003239 ps
CPU time 2.38 seconds
Started Feb 09 08:33:53 AM UTC 25
Finished Feb 09 08:33:57 AM UTC 25
Peak memory 229440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799216233 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.799216233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1476285691
Short name T1174
Test name
Test status
Simulation time 66653644 ps
CPU time 1.56 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:54 AM UTC 25
Peak memory 228676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476285691 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.1476285691 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3171809081
Short name T1176
Test name
Test status
Simulation time 192775379 ps
CPU time 2.39 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:55 AM UTC 25
Peak memory 229988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171809081 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.3171809081 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2335876790
Short name T1187
Test name
Test status
Simulation time 140287876 ps
CPU time 5.01 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:58 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335876790 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2335876790 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3540016878
Short name T1188
Test name
Test status
Simulation time 353617769 ps
CPU time 5.33 seconds
Started Feb 09 08:33:52 AM UTC 25
Finished Feb 09 08:33:58 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540016878 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3540016878 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1945103169
Short name T1189
Test name
Test status
Simulation time 243605953 ps
CPU time 1.92 seconds
Started Feb 09 08:33:55 AM UTC 25
Finished Feb 09 08:33:59 AM UTC 25
Peak memory 228784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1945103169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_rese
t.1945103169 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.1266783982
Short name T1185
Test name
Test status
Simulation time 17124995 ps
CPU time 1.32 seconds
Started Feb 09 08:33:55 AM UTC 25
Finished Feb 09 08:33:58 AM UTC 25
Peak memory 218804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266783982 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1266783982 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3997917231
Short name T1184
Test name
Test status
Simulation time 19906177 ps
CPU time 1.09 seconds
Started Feb 09 08:33:55 AM UTC 25
Finished Feb 09 08:33:58 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997917231 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3997917231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1275252847
Short name T1191
Test name
Test status
Simulation time 29118335 ps
CPU time 2.18 seconds
Started Feb 09 08:33:55 AM UTC 25
Finished Feb 09 08:33:59 AM UTC 25
Peak memory 229416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275252847 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.1275252847 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3783878864
Short name T1178
Test name
Test status
Simulation time 65553292 ps
CPU time 1.61 seconds
Started Feb 09 08:33:53 AM UTC 25
Finished Feb 09 08:33:56 AM UTC 25
Peak memory 228736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783878864 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.3783878864 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3284561687
Short name T1186
Test name
Test status
Simulation time 242839731 ps
CPU time 2.66 seconds
Started Feb 09 08:33:54 AM UTC 25
Finished Feb 09 08:33:58 AM UTC 25
Peak memory 229932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284561687 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.3284561687 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.301505569
Short name T1183
Test name
Test status
Simulation time 362092455 ps
CPU time 2.08 seconds
Started Feb 09 08:33:54 AM UTC 25
Finished Feb 09 08:33:57 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301505569 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.301505569 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2366951582
Short name T1199
Test name
Test status
Simulation time 260465430 ps
CPU time 5.19 seconds
Started Feb 09 08:33:55 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366951582 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2366951582 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2734881639
Short name T1198
Test name
Test status
Simulation time 184043182 ps
CPU time 1.99 seconds
Started Feb 09 08:33:58 AM UTC 25
Finished Feb 09 08:34:01 AM UTC 25
Peak memory 228784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2734881639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_rese
t.2734881639 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2017001133
Short name T1194
Test name
Test status
Simulation time 15765698 ps
CPU time 1.49 seconds
Started Feb 09 08:33:58 AM UTC 25
Finished Feb 09 08:34:00 AM UTC 25
Peak memory 218844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017001133 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2017001133 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3053330033
Short name T1190
Test name
Test status
Simulation time 34617341 ps
CPU time 0.8 seconds
Started Feb 09 08:33:57 AM UTC 25
Finished Feb 09 08:33:59 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053330033 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3053330033 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3306955546
Short name T1196
Test name
Test status
Simulation time 149099237 ps
CPU time 1.98 seconds
Started Feb 09 08:33:58 AM UTC 25
Finished Feb 09 08:34:01 AM UTC 25
Peak memory 228728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306955546 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.3306955546 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.19130012
Short name T1192
Test name
Test status
Simulation time 31452252 ps
CPU time 1.23 seconds
Started Feb 09 08:33:56 AM UTC 25
Finished Feb 09 08:33:59 AM UTC 25
Peak memory 228764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19130012 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.19130012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.930313621
Short name T1193
Test name
Test status
Simulation time 68034950 ps
CPU time 2.64 seconds
Started Feb 09 08:33:56 AM UTC 25
Finished Feb 09 08:34:00 AM UTC 25
Peak memory 236108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930313621 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.930313621 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2501202003
Short name T1205
Test name
Test status
Simulation time 530946261 ps
CPU time 4.44 seconds
Started Feb 09 08:33:57 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 229616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501202003 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2501202003 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.123124382
Short name T1200
Test name
Test status
Simulation time 427126512 ps
CPU time 3.94 seconds
Started Feb 09 08:33:57 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 229488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123124382 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.123124382 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4100916557
Short name T1209
Test name
Test status
Simulation time 49474186 ps
CPU time 2.6 seconds
Started Feb 09 08:33:59 AM UTC 25
Finished Feb 09 08:34:03 AM UTC 25
Peak memory 231544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4100916557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_rese
t.4100916557 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2123484261
Short name T1203
Test name
Test status
Simulation time 36896092 ps
CPU time 1.72 seconds
Started Feb 09 08:33:59 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 218796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123484261 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2123484261 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1274184679
Short name T1197
Test name
Test status
Simulation time 35775368 ps
CPU time 0.87 seconds
Started Feb 09 08:33:59 AM UTC 25
Finished Feb 09 08:34:01 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274184679 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1274184679 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.4212561411
Short name T1202
Test name
Test status
Simulation time 82518590 ps
CPU time 1.59 seconds
Started Feb 09 08:33:59 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 228768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212561411 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.4212561411 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3015726411
Short name T1195
Test name
Test status
Simulation time 113617589 ps
CPU time 1.69 seconds
Started Feb 09 08:33:58 AM UTC 25
Finished Feb 09 08:34:01 AM UTC 25
Peak memory 228468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015726411 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.3015726411 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1144360526
Short name T1201
Test name
Test status
Simulation time 453449606 ps
CPU time 2.78 seconds
Started Feb 09 08:33:58 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 229932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144360526 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.1144360526 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1877180611
Short name T157
Test name
Test status
Simulation time 580045290 ps
CPU time 4.97 seconds
Started Feb 09 08:33:59 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 229604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877180611 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1877180611 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.4279614491
Short name T1101
Test name
Test status
Simulation time 557806615 ps
CPU time 8.59 seconds
Started Feb 09 08:33:21 AM UTC 25
Finished Feb 09 08:33:31 AM UTC 25
Peak memory 219196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279614491 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.4279614491 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2480272576
Short name T1102
Test name
Test status
Simulation time 522948879 ps
CPU time 9.77 seconds
Started Feb 09 08:33:20 AM UTC 25
Finished Feb 09 08:33:31 AM UTC 25
Peak memory 219188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480272576 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2480272576 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.3091133617
Short name T141
Test name
Test status
Simulation time 31870057 ps
CPU time 1.7 seconds
Started Feb 09 08:33:20 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 218808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091133617 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3091133617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3710740984
Short name T127
Test name
Test status
Simulation time 94003433 ps
CPU time 3.2 seconds
Started Feb 09 08:33:22 AM UTC 25
Finished Feb 09 08:33:27 AM UTC 25
Peak memory 231612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3710740984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset
.3710740984 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1790705931
Short name T1089
Test name
Test status
Simulation time 96074222 ps
CPU time 1.63 seconds
Started Feb 09 08:33:20 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 218796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790705931 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1790705931 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.544008494
Short name T132
Test name
Test status
Simulation time 589998690 ps
CPU time 2.74 seconds
Started Feb 09 08:33:19 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 229552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544008494 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.544008494 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.3873159181
Short name T1088
Test name
Test status
Simulation time 19714954 ps
CPU time 1.08 seconds
Started Feb 09 08:33:19 AM UTC 25
Finished Feb 09 08:33:21 AM UTC 25
Peak memory 218852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873159181 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3873159181 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3949561849
Short name T1092
Test name
Test status
Simulation time 42035275 ps
CPU time 3.34 seconds
Started Feb 09 08:33:21 AM UTC 25
Finished Feb 09 08:33:26 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949561849 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3949561849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3601398465
Short name T100
Test name
Test status
Simulation time 79043993 ps
CPU time 1.57 seconds
Started Feb 09 08:33:18 AM UTC 25
Finished Feb 09 08:33:21 AM UTC 25
Peak memory 228672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601398465 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.3601398465 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1661503835
Short name T99
Test name
Test status
Simulation time 70182084 ps
CPU time 2.45 seconds
Started Feb 09 08:33:19 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 236540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661503835 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.1661503835 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.3061033884
Short name T123
Test name
Test status
Simulation time 345258147 ps
CPU time 2.61 seconds
Started Feb 09 08:33:19 AM UTC 25
Finished Feb 09 08:33:23 AM UTC 25
Peak memory 229532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061033884 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3061033884 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2229477483
Short name T128
Test name
Test status
Simulation time 126381759 ps
CPU time 4.29 seconds
Started Feb 09 08:33:19 AM UTC 25
Finished Feb 09 08:33:25 AM UTC 25
Peak memory 219196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229477483 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2229477483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.1516617378
Short name T1204
Test name
Test status
Simulation time 43619477 ps
CPU time 0.87 seconds
Started Feb 09 08:34:00 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516617378 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1516617378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3384572188
Short name T1206
Test name
Test status
Simulation time 15393795 ps
CPU time 1 seconds
Started Feb 09 08:34:00 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384572188 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3384572188 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.1129840390
Short name T1207
Test name
Test status
Simulation time 37945570 ps
CPU time 1 seconds
Started Feb 09 08:34:00 AM UTC 25
Finished Feb 09 08:34:02 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129840390 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1129840390 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2108911602
Short name T1208
Test name
Test status
Simulation time 15071260 ps
CPU time 1.16 seconds
Started Feb 09 08:34:00 AM UTC 25
Finished Feb 09 08:34:03 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108911602 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2108911602 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3104504250
Short name T1211
Test name
Test status
Simulation time 24759171 ps
CPU time 0.86 seconds
Started Feb 09 08:34:01 AM UTC 25
Finished Feb 09 08:34:04 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104504250 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3104504250 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1036752520
Short name T1210
Test name
Test status
Simulation time 193378716 ps
CPU time 0.92 seconds
Started Feb 09 08:34:01 AM UTC 25
Finished Feb 09 08:34:04 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036752520 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1036752520 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3461229856
Short name T1214
Test name
Test status
Simulation time 19463284 ps
CPU time 1.19 seconds
Started Feb 09 08:34:01 AM UTC 25
Finished Feb 09 08:34:04 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461229856 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3461229856 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.692853855
Short name T1213
Test name
Test status
Simulation time 42775292 ps
CPU time 1.14 seconds
Started Feb 09 08:34:01 AM UTC 25
Finished Feb 09 08:34:04 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692853855 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.692853855 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.941090617
Short name T1212
Test name
Test status
Simulation time 48327854 ps
CPU time 1.02 seconds
Started Feb 09 08:34:02 AM UTC 25
Finished Feb 09 08:34:04 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941090617 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.941090617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.196981918
Short name T1216
Test name
Test status
Simulation time 24279012 ps
CPU time 1.03 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196981918 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.196981918 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2663394568
Short name T1107
Test name
Test status
Simulation time 142238025 ps
CPU time 8.15 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:33 AM UTC 25
Peak memory 219132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663394568 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2663394568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.619050091
Short name T1105
Test name
Test status
Simulation time 521574523 ps
CPU time 7.68 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:33 AM UTC 25
Peak memory 219188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619050091 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.619050091 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.4182599102
Short name T1095
Test name
Test status
Simulation time 63992971 ps
CPU time 1.44 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:26 AM UTC 25
Peak memory 218808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182599102 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4182599102 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2158889849
Short name T122
Test name
Test status
Simulation time 106959286 ps
CPU time 2.02 seconds
Started Feb 09 08:33:26 AM UTC 25
Finished Feb 09 08:33:29 AM UTC 25
Peak memory 236656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2158889849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset
.2158889849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.352973754
Short name T1094
Test name
Test status
Simulation time 38438581 ps
CPU time 1.34 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:26 AM UTC 25
Peak memory 218840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352973754 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.352973754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2188967650
Short name T142
Test name
Test status
Simulation time 40502638 ps
CPU time 1.19 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:26 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188967650 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2188967650 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3112618902
Short name T133
Test name
Test status
Simulation time 63125746 ps
CPU time 1.85 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:27 AM UTC 25
Peak memory 228784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112618902 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3112618902 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.4186529108
Short name T1093
Test name
Test status
Simulation time 39655063 ps
CPU time 1.11 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:26 AM UTC 25
Peak memory 218852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186529108 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.4186529108 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.587389046
Short name T1097
Test name
Test status
Simulation time 24513460 ps
CPU time 2.04 seconds
Started Feb 09 08:33:25 AM UTC 25
Finished Feb 09 08:33:28 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587389046 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.587389046 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3413094703
Short name T101
Test name
Test status
Simulation time 45824945 ps
CPU time 1.64 seconds
Started Feb 09 08:33:22 AM UTC 25
Finished Feb 09 08:33:25 AM UTC 25
Peak memory 228472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413094703 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.3413094703 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2835775463
Short name T103
Test name
Test status
Simulation time 65343684 ps
CPU time 3.28 seconds
Started Feb 09 08:33:22 AM UTC 25
Finished Feb 09 08:33:27 AM UTC 25
Peak memory 229928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835775463 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.2835775463 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2244650704
Short name T121
Test name
Test status
Simulation time 298957632 ps
CPU time 1.86 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:27 AM UTC 25
Peak memory 228784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244650704 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2244650704 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.2558826412
Short name T129
Test name
Test status
Simulation time 263597611 ps
CPU time 3.87 seconds
Started Feb 09 08:33:24 AM UTC 25
Finished Feb 09 08:33:29 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558826412 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.2558826412 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3737656427
Short name T1217
Test name
Test status
Simulation time 22712909 ps
CPU time 1.05 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737656427 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3737656427 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1538400575
Short name T1220
Test name
Test status
Simulation time 13844795 ps
CPU time 1.16 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538400575 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1538400575 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.996618958
Short name T1222
Test name
Test status
Simulation time 19091953 ps
CPU time 1.2 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996618958 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.996618958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.1809866359
Short name T1219
Test name
Test status
Simulation time 48191750 ps
CPU time 1.04 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809866359 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1809866359 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2926254265
Short name T1215
Test name
Test status
Simulation time 47985987 ps
CPU time 0.7 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926254265 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2926254265 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1091653836
Short name T1221
Test name
Test status
Simulation time 15388864 ps
CPU time 1.03 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091653836 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1091653836 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.3131567350
Short name T1218
Test name
Test status
Simulation time 17103957 ps
CPU time 0.81 seconds
Started Feb 09 08:34:03 AM UTC 25
Finished Feb 09 08:34:05 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131567350 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3131567350 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.838643102
Short name T1223
Test name
Test status
Simulation time 22197897 ps
CPU time 0.9 seconds
Started Feb 09 08:34:04 AM UTC 25
Finished Feb 09 08:34:06 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838643102 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.838643102 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2605907239
Short name T1226
Test name
Test status
Simulation time 35783543 ps
CPU time 1.07 seconds
Started Feb 09 08:34:04 AM UTC 25
Finished Feb 09 08:34:06 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605907239 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2605907239 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.882791051
Short name T1224
Test name
Test status
Simulation time 49567672 ps
CPU time 0.89 seconds
Started Feb 09 08:34:04 AM UTC 25
Finished Feb 09 08:34:06 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882791051 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.882791051 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.2672768903
Short name T1114
Test name
Test status
Simulation time 134633884 ps
CPU time 7.75 seconds
Started Feb 09 08:33:28 AM UTC 25
Finished Feb 09 08:33:37 AM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672768903 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2672768903 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3035476797
Short name T1118
Test name
Test status
Simulation time 843399506 ps
CPU time 8.85 seconds
Started Feb 09 08:33:28 AM UTC 25
Finished Feb 09 08:33:38 AM UTC 25
Peak memory 219132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035476797 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3035476797 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2184019418
Short name T1100
Test name
Test status
Simulation time 119046258 ps
CPU time 1.62 seconds
Started Feb 09 08:33:28 AM UTC 25
Finished Feb 09 08:33:30 AM UTC 25
Peak memory 218808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184019418 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2184019418 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2033678707
Short name T1106
Test name
Test status
Simulation time 354903535 ps
CPU time 3.06 seconds
Started Feb 09 08:33:29 AM UTC 25
Finished Feb 09 08:33:33 AM UTC 25
Peak memory 236568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2033678707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset
.2033678707 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2876443873
Short name T143
Test name
Test status
Simulation time 34926716 ps
CPU time 1.17 seconds
Started Feb 09 08:33:28 AM UTC 25
Finished Feb 09 08:33:30 AM UTC 25
Peak memory 218804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876443873 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2876443873 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.1646186649
Short name T154
Test name
Test status
Simulation time 42172043 ps
CPU time 1.16 seconds
Started Feb 09 08:33:28 AM UTC 25
Finished Feb 09 08:33:30 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646186649 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1646186649 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.1457790292
Short name T134
Test name
Test status
Simulation time 192866281 ps
CPU time 1.35 seconds
Started Feb 09 08:33:27 AM UTC 25
Finished Feb 09 08:33:30 AM UTC 25
Peak memory 228792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457790292 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.1457790292 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.1769323936
Short name T1099
Test name
Test status
Simulation time 35402891 ps
CPU time 1.11 seconds
Started Feb 09 08:33:27 AM UTC 25
Finished Feb 09 08:33:30 AM UTC 25
Peak memory 218580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769323936 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmas
ked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1769323936 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3742505112
Short name T1103
Test name
Test status
Simulation time 85473483 ps
CPU time 2.08 seconds
Started Feb 09 08:33:29 AM UTC 25
Finished Feb 09 08:33:32 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742505112 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3742505112 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1858555561
Short name T1098
Test name
Test status
Simulation time 107960372 ps
CPU time 1.4 seconds
Started Feb 09 08:33:26 AM UTC 25
Finished Feb 09 08:33:29 AM UTC 25
Peak memory 218428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858555561 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.1858555561 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1834824071
Short name T144
Test name
Test status
Simulation time 71687098 ps
CPU time 2.59 seconds
Started Feb 09 08:33:27 AM UTC 25
Finished Feb 09 08:33:31 AM UTC 25
Peak memory 229760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834824071 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.1834824071 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.161213955
Short name T117
Test name
Test status
Simulation time 269544600 ps
CPU time 3.31 seconds
Started Feb 09 08:33:27 AM UTC 25
Finished Feb 09 08:33:32 AM UTC 25
Peak memory 229564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161213955 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.161213955 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1449574135
Short name T161
Test name
Test status
Simulation time 120205377 ps
CPU time 2.89 seconds
Started Feb 09 08:33:27 AM UTC 25
Finished Feb 09 08:33:32 AM UTC 25
Peak memory 229388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449574135 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.1449574135 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.529790947
Short name T1228
Test name
Test status
Simulation time 41029062 ps
CPU time 1.17 seconds
Started Feb 09 08:34:04 AM UTC 25
Finished Feb 09 08:34:07 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529790947 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.529790947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.959294612
Short name T1227
Test name
Test status
Simulation time 45099638 ps
CPU time 1.16 seconds
Started Feb 09 08:34:04 AM UTC 25
Finished Feb 09 08:34:07 AM UTC 25
Peak memory 218848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959294612 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.959294612 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.961269376
Short name T1225
Test name
Test status
Simulation time 24465869 ps
CPU time 0.83 seconds
Started Feb 09 08:34:04 AM UTC 25
Finished Feb 09 08:34:06 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961269376 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.961269376 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1633624493
Short name T1232
Test name
Test status
Simulation time 14648446 ps
CPU time 1.04 seconds
Started Feb 09 08:34:05 AM UTC 25
Finished Feb 09 08:34:08 AM UTC 25
Peak memory 218692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633624493 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1633624493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.458344589
Short name T1230
Test name
Test status
Simulation time 47388572 ps
CPU time 1.03 seconds
Started Feb 09 08:34:05 AM UTC 25
Finished Feb 09 08:34:08 AM UTC 25
Peak memory 218844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458344589 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.458344589 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.811054108
Short name T1233
Test name
Test status
Simulation time 43898748 ps
CPU time 1.02 seconds
Started Feb 09 08:34:05 AM UTC 25
Finished Feb 09 08:34:08 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811054108 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.811054108 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2531393400
Short name T1231
Test name
Test status
Simulation time 29911165 ps
CPU time 0.95 seconds
Started Feb 09 08:34:05 AM UTC 25
Finished Feb 09 08:34:08 AM UTC 25
Peak memory 218804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531393400 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2531393400 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.4194581853
Short name T1229
Test name
Test status
Simulation time 41235387 ps
CPU time 0.78 seconds
Started Feb 09 08:34:05 AM UTC 25
Finished Feb 09 08:34:07 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194581853 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.4194581853 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3635870513
Short name T1235
Test name
Test status
Simulation time 16887411 ps
CPU time 1.06 seconds
Started Feb 09 08:34:06 AM UTC 25
Finished Feb 09 08:34:09 AM UTC 25
Peak memory 218836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635870513 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3635870513 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1689088108
Short name T1234
Test name
Test status
Simulation time 44610688 ps
CPU time 1.05 seconds
Started Feb 09 08:34:06 AM UTC 25
Finished Feb 09 08:34:09 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689088108 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1689088108 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1191903669
Short name T1111
Test name
Test status
Simulation time 336075528 ps
CPU time 3.5 seconds
Started Feb 09 08:33:31 AM UTC 25
Finished Feb 09 08:33:36 AM UTC 25
Peak memory 236596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1191903669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset
.1191903669 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.430958028
Short name T1108
Test name
Test status
Simulation time 102187974 ps
CPU time 1.27 seconds
Started Feb 09 08:33:31 AM UTC 25
Finished Feb 09 08:33:33 AM UTC 25
Peak memory 228464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430958028 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.430958028 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.4042421975
Short name T155
Test name
Test status
Simulation time 32953013 ps
CPU time 1.17 seconds
Started Feb 09 08:33:31 AM UTC 25
Finished Feb 09 08:33:33 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042421975 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.4042421975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1599379507
Short name T1109
Test name
Test status
Simulation time 199723392 ps
CPU time 2.87 seconds
Started Feb 09 08:33:31 AM UTC 25
Finished Feb 09 08:33:35 AM UTC 25
Peak memory 229448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599379507 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1599379507 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3121250960
Short name T1104
Test name
Test status
Simulation time 54266666 ps
CPU time 1.38 seconds
Started Feb 09 08:33:30 AM UTC 25
Finished Feb 09 08:33:32 AM UTC 25
Peak memory 228676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121250960 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.3121250960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3994493886
Short name T112
Test name
Test status
Simulation time 50425184 ps
CPU time 2.82 seconds
Started Feb 09 08:33:30 AM UTC 25
Finished Feb 09 08:33:34 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994493886 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3994493886 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2801967859
Short name T1120
Test name
Test status
Simulation time 428182779 ps
CPU time 3.31 seconds
Started Feb 09 08:33:33 AM UTC 25
Finished Feb 09 08:33:38 AM UTC 25
Peak memory 231548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2801967859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset
.2801967859 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.333942647
Short name T1112
Test name
Test status
Simulation time 97324189 ps
CPU time 1.3 seconds
Started Feb 09 08:33:33 AM UTC 25
Finished Feb 09 08:33:36 AM UTC 25
Peak memory 218840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333942647 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.333942647 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3441569911
Short name T1119
Test name
Test status
Simulation time 112973817 ps
CPU time 3.17 seconds
Started Feb 09 08:33:33 AM UTC 25
Finished Feb 09 08:33:38 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441569911 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.3441569911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.813746213
Short name T102
Test name
Test status
Simulation time 45218348 ps
CPU time 1.82 seconds
Started Feb 09 08:33:32 AM UTC 25
Finished Feb 09 08:33:35 AM UTC 25
Peak memory 228604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813746213 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.813746213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3969872835
Short name T1110
Test name
Test status
Simulation time 123316910 ps
CPU time 1.91 seconds
Started Feb 09 08:33:32 AM UTC 25
Finished Feb 09 08:33:35 AM UTC 25
Peak memory 235756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969872835 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.3969872835 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.315323686
Short name T115
Test name
Test status
Simulation time 46197750 ps
CPU time 3.49 seconds
Started Feb 09 08:33:32 AM UTC 25
Finished Feb 09 08:33:37 AM UTC 25
Peak memory 229624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315323686 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.315323686 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.1844863470
Short name T162
Test name
Test status
Simulation time 113841629 ps
CPU time 2.97 seconds
Started Feb 09 08:33:32 AM UTC 25
Finished Feb 09 08:33:37 AM UTC 25
Peak memory 219172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844863470 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.1844863470 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3159131186
Short name T1124
Test name
Test status
Simulation time 427857765 ps
CPU time 2.55 seconds
Started Feb 09 08:33:36 AM UTC 25
Finished Feb 09 08:33:40 AM UTC 25
Peak memory 229500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3159131186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset
.3159131186 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2896807511
Short name T1116
Test name
Test status
Simulation time 196694625 ps
CPU time 1.52 seconds
Started Feb 09 08:33:35 AM UTC 25
Finished Feb 09 08:33:37 AM UTC 25
Peak memory 218844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896807511 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2896807511 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3394159537
Short name T1113
Test name
Test status
Simulation time 15474527 ps
CPU time 0.92 seconds
Started Feb 09 08:33:35 AM UTC 25
Finished Feb 09 08:33:37 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394159537 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3394159537 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1578595765
Short name T1122
Test name
Test status
Simulation time 273675612 ps
CPU time 2.03 seconds
Started Feb 09 08:33:36 AM UTC 25
Finished Feb 09 08:33:39 AM UTC 25
Peak memory 229500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578595765 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.1578595765 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2666770734
Short name T1115
Test name
Test status
Simulation time 71262245 ps
CPU time 1.59 seconds
Started Feb 09 08:33:35 AM UTC 25
Finished Feb 09 08:33:37 AM UTC 25
Peak memory 228728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666770734 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2666770734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.959072504
Short name T1117
Test name
Test status
Simulation time 71275587 ps
CPU time 1.98 seconds
Started Feb 09 08:33:35 AM UTC 25
Finished Feb 09 08:33:38 AM UTC 25
Peak memory 228536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959072504 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.959072504 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1418191993
Short name T55
Test name
Test status
Simulation time 372192408 ps
CPU time 2.26 seconds
Started Feb 09 08:33:35 AM UTC 25
Finished Feb 09 08:33:38 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418191993 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1418191993 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.4133013900
Short name T1126
Test name
Test status
Simulation time 699932975 ps
CPU time 4.74 seconds
Started Feb 09 08:33:35 AM UTC 25
Finished Feb 09 08:33:41 AM UTC 25
Peak memory 229432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133013900 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.4133013900 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.448701302
Short name T1129
Test name
Test status
Simulation time 81877906 ps
CPU time 2.12 seconds
Started Feb 09 08:33:38 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
448701302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.
448701302 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3139427415
Short name T1125
Test name
Test status
Simulation time 109993547 ps
CPU time 1.16 seconds
Started Feb 09 08:33:38 AM UTC 25
Finished Feb 09 08:33:41 AM UTC 25
Peak memory 218804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139427415 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3139427415 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.584229363
Short name T1123
Test name
Test status
Simulation time 42587993 ps
CPU time 1.01 seconds
Started Feb 09 08:33:37 AM UTC 25
Finished Feb 09 08:33:40 AM UTC 25
Peak memory 218916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584229363 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.584229363 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2694368815
Short name T1131
Test name
Test status
Simulation time 138347038 ps
CPU time 2.59 seconds
Started Feb 09 08:33:38 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 229492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694368815 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.2694368815 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1163561886
Short name T1121
Test name
Test status
Simulation time 20698746 ps
CPU time 1.19 seconds
Started Feb 09 08:33:36 AM UTC 25
Finished Feb 09 08:33:38 AM UTC 25
Peak memory 228540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163561886 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1163561886 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2492527487
Short name T1128
Test name
Test status
Simulation time 143586205 ps
CPU time 3.97 seconds
Started Feb 09 08:33:36 AM UTC 25
Finished Feb 09 08:33:41 AM UTC 25
Peak memory 237084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492527487 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.2492527487 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2109273056
Short name T116
Test name
Test status
Simulation time 59826273 ps
CPU time 1.73 seconds
Started Feb 09 08:33:37 AM UTC 25
Finished Feb 09 08:33:40 AM UTC 25
Peak memory 228788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109273056 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2109273056 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1876237709
Short name T1134
Test name
Test status
Simulation time 123566416 ps
CPU time 3.7 seconds
Started Feb 09 08:33:37 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876237709 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.1876237709 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2103247195
Short name T1141
Test name
Test status
Simulation time 89928727 ps
CPU time 3.56 seconds
Started Feb 09 08:33:40 AM UTC 25
Finished Feb 09 08:33:44 AM UTC 25
Peak memory 229500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2103247195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset
.2103247195 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2056065407
Short name T1132
Test name
Test status
Simulation time 57855472 ps
CPU time 1.23 seconds
Started Feb 09 08:33:39 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 218284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056065407 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2056065407 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3939285430
Short name T1130
Test name
Test status
Simulation time 35358154 ps
CPU time 1.08 seconds
Started Feb 09 08:33:39 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 218908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939285430 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3939285430 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2998038343
Short name T1136
Test name
Test status
Simulation time 342101765 ps
CPU time 2.08 seconds
Started Feb 09 08:33:40 AM UTC 25
Finished Feb 09 08:33:43 AM UTC 25
Peak memory 229264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998038343 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.2998038343 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.746345005
Short name T1127
Test name
Test status
Simulation time 130599077 ps
CPU time 1.39 seconds
Started Feb 09 08:33:38 AM UTC 25
Finished Feb 09 08:33:41 AM UTC 25
Peak memory 228540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746345005 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.746345005 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1285563696
Short name T1133
Test name
Test status
Simulation time 36072825 ps
CPU time 2.38 seconds
Started Feb 09 08:33:38 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 229984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285563696 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.1285563696 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.2490531895
Short name T113
Test name
Test status
Simulation time 32471895 ps
CPU time 2.29 seconds
Started Feb 09 08:33:38 AM UTC 25
Finished Feb 09 08:33:42 AM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490531895 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.2490531895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1756556017
Short name T1138
Test name
Test status
Simulation time 103491287 ps
CPU time 3.39 seconds
Started Feb 09 08:33:38 AM UTC 25
Finished Feb 09 08:33:43 AM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756556017 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1756556017 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.3913334498
Short name T22
Test name
Test status
Simulation time 62175453338 ps
CPU time 217.47 seconds
Started Feb 09 08:34:08 AM UTC 25
Finished Feb 09 08:37:49 AM UTC 25
Peak memory 466956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913334498 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3913334498 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.3109382324
Short name T135
Test name
Test status
Simulation time 13275986642 ps
CPU time 454.92 seconds
Started Feb 09 08:34:06 AM UTC 25
Finished Feb 09 08:41:48 AM UTC 25
Peak memory 249860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109382324 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3109382324 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.933848140
Short name T14
Test name
Test status
Simulation time 3109544520 ps
CPU time 46.52 seconds
Started Feb 09 08:34:10 AM UTC 25
Finished Feb 09 08:34:58 AM UTC 25
Peak memory 235368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933848140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.933848140 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.1750114721
Short name T12
Test name
Test status
Simulation time 1054565946 ps
CPU time 28.06 seconds
Started Feb 09 08:34:16 AM UTC 25
Finished Feb 09 08:34:46 AM UTC 25
Peak memory 235324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750114721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1750114721 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.1911559069
Short name T16
Test name
Test status
Simulation time 5689045714 ps
CPU time 83.02 seconds
Started Feb 09 08:34:16 AM UTC 25
Finished Feb 09 08:35:42 AM UTC 25
Peak memory 230780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911559069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1911559069 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.3099679390
Short name T3
Test name
Test status
Simulation time 1103666909 ps
CPU time 10.71 seconds
Started Feb 09 08:34:10 AM UTC 25
Finished Feb 09 08:34:22 AM UTC 25
Peak memory 230644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099679390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3099679390 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.705738219
Short name T308
Test name
Test status
Simulation time 78613735886 ps
CPU time 3104.97 seconds
Started Feb 09 08:34:06 AM UTC 25
Finished Feb 09 09:26:24 AM UTC 25
Peak memory 3741808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705738219 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.705738219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.1893481581
Short name T15
Test name
Test status
Simulation time 5433223397 ps
CPU time 77.33 seconds
Started Feb 09 08:34:06 AM UTC 25
Finished Feb 09 08:35:26 AM UTC 25
Peak memory 264192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893481581 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1893481581 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.2044709574
Short name T13
Test name
Test status
Simulation time 7740444521 ps
CPU time 42.17 seconds
Started Feb 09 08:34:06 AM UTC 25
Finished Feb 09 08:34:51 AM UTC 25
Peak memory 230852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044709574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.kmac_smoke.2044709574 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.4233694641
Short name T2
Test name
Test status
Simulation time 67992373 ps
CPU time 6.19 seconds
Started Feb 09 08:34:08 AM UTC 25
Finished Feb 09 08:34:15 AM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4233694641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.kmac_test_vectors_kmac.4233694641 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.267243836
Short name T1
Test name
Test status
Simulation time 66101481 ps
CPU time 5.72 seconds
Started Feb 09 08:34:08 AM UTC 25
Finished Feb 09 08:34:15 AM UTC 25
Peak memory 230868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=267243836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac_xof.267243836 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.4103814536
Short name T279
Test name
Test status
Simulation time 102739570357 ps
CPU time 2697.87 seconds
Started Feb 09 08:34:07 AM UTC 25
Finished Feb 09 09:19:33 AM UTC 25
Peak memory 3295172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103814536 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.4103814536 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.100372994
Short name T148
Test name
Test status
Simulation time 64268780043 ps
CPU time 2024.87 seconds
Started Feb 09 08:34:07 AM UTC 25
Finished Feb 09 09:08:12 AM UTC 25
Peak memory 2994124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100372994 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.100372994 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.2618574318
Short name T226
Test name
Test status
Simulation time 179094796260 ps
CPU time 1756.42 seconds
Started Feb 09 08:34:07 AM UTC 25
Finished Feb 09 09:03:43 AM UTC 25
Peak memory 2385912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618574318 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2618574318 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.2154129915
Short name T204
Test name
Test status
Simulation time 50980487498 ps
CPU time 1279.85 seconds
Started Feb 09 08:34:08 AM UTC 25
Finished Feb 09 08:55:42 AM UTC 25
Peak memory 1738804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154129915 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2154129915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.3842283178
Short name T473
Test name
Test status
Simulation time 447227960427 ps
CPU time 6537.74 seconds
Started Feb 09 08:34:08 AM UTC 25
Finished Feb 09 10:24:08 AM UTC 25
Peak memory 7751204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842283178 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3842283178 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.2460933914
Short name T417
Test name
Test status
Simulation time 573230418078 ps
CPU time 5500.05 seconds
Started Feb 09 08:34:08 AM UTC 25
Finished Feb 09 10:06:44 AM UTC 25
Peak memory 6324160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460933914 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2460933914 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.421069618
Short name T52
Test name
Test status
Simulation time 34658209 ps
CPU time 1.1 seconds
Started Feb 09 08:39:03 AM UTC 25
Finished Feb 09 08:39:05 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421069618 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.421069618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.4108686788
Short name T80
Test name
Test status
Simulation time 2583815195 ps
CPU time 195.83 seconds
Started Feb 09 08:36:32 AM UTC 25
Finished Feb 09 08:39:52 AM UTC 25
Peak memory 307088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108686788 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.4108686788 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.3014345201
Short name T84
Test name
Test status
Simulation time 8667121492 ps
CPU time 357.02 seconds
Started Feb 09 08:35:18 AM UTC 25
Finished Feb 09 08:41:20 AM UTC 25
Peak memory 243792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014345201 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3014345201 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.3347305892
Short name T73
Test name
Test status
Simulation time 858141772 ps
CPU time 31.56 seconds
Started Feb 09 08:38:14 AM UTC 25
Finished Feb 09 08:38:47 AM UTC 25
Peak memory 230548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347305892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3347305892 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.803457974
Short name T43
Test name
Test status
Simulation time 5484542958 ps
CPU time 48.64 seconds
Started Feb 09 08:38:19 AM UTC 25
Finished Feb 09 08:39:09 AM UTC 25
Peak memory 235312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803457974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.803457974 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.2447714577
Short name T50
Test name
Test status
Simulation time 52977667315 ps
CPU time 290.76 seconds
Started Feb 09 08:36:41 AM UTC 25
Finished Feb 09 08:41:36 AM UTC 25
Peak memory 424008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447714577 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2447714577 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.855780914
Short name T25
Test name
Test status
Simulation time 3206456703 ps
CPU time 26.74 seconds
Started Feb 09 08:37:49 AM UTC 25
Finished Feb 09 08:38:18 AM UTC 25
Peak memory 251908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855780914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.kmac_error.855780914 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.1549911592
Short name T6
Test name
Test status
Simulation time 52869638 ps
CPU time 1.65 seconds
Started Feb 09 08:38:43 AM UTC 25
Finished Feb 09 08:38:46 AM UTC 25
Peak memory 229888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549911592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1549911592 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.1593181303
Short name T250
Test name
Test status
Simulation time 305865005089 ps
CPU time 2323.74 seconds
Started Feb 09 08:34:55 AM UTC 25
Finished Feb 09 09:14:05 AM UTC 25
Peak memory 1550352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593181303 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.1593181303 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.233232833
Short name T34
Test name
Test status
Simulation time 4345442333 ps
CPU time 279.61 seconds
Started Feb 09 08:37:14 AM UTC 25
Finished Feb 09 08:41:58 AM UTC 25
Peak memory 346504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233232833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.kmac_mubi.233232833 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.3537966357
Short name T10
Test name
Test status
Simulation time 11691693366 ps
CPU time 80.72 seconds
Started Feb 09 08:38:53 AM UTC 25
Finished Feb 09 08:40:16 AM UTC 25
Peak memory 277560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537966357 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3537966357 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.1367135290
Short name T29
Test name
Test status
Simulation time 60959577714 ps
CPU time 460.91 seconds
Started Feb 09 08:34:59 AM UTC 25
Finished Feb 09 08:42:47 AM UTC 25
Peak memory 552972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367135290 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1367135290 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.3620609961
Short name T152
Test name
Test status
Simulation time 7370574954 ps
CPU time 667.06 seconds
Started Feb 09 08:38:47 AM UTC 25
Finished Feb 09 08:50:02 AM UTC 25
Peak memory 632848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620609961 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3620609961 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.812739000
Short name T71
Test name
Test status
Simulation time 244250696 ps
CPU time 6.03 seconds
Started Feb 09 08:36:09 AM UTC 25
Finished Feb 09 08:36:17 AM UTC 25
Peak memory 230784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=812739000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.kmac_test_vectors_kmac.812739000 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3165546601
Short name T72
Test name
Test status
Simulation time 237125970 ps
CPU time 6.03 seconds
Started Feb 09 08:36:18 AM UTC 25
Finished Feb 09 08:36:25 AM UTC 25
Peak memory 230876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3165546601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 1.kmac_test_vectors_kmac_xof.3165546601 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.1292566561
Short name T264
Test name
Test status
Simulation time 237256008137 ps
CPU time 2447.76 seconds
Started Feb 09 08:35:27 AM UTC 25
Finished Feb 09 09:16:42 AM UTC 25
Peak memory 3328000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292566561 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1292566561 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.4221893388
Short name T298
Test name
Test status
Simulation time 701426485351 ps
CPU time 2867.55 seconds
Started Feb 09 08:35:43 AM UTC 25
Finished Feb 09 09:24:01 AM UTC 25
Peak memory 3063740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221893388 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.4221893388 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.3546860568
Short name T211
Test name
Test status
Simulation time 14044804787 ps
CPU time 1232.26 seconds
Started Feb 09 08:35:47 AM UTC 25
Finished Feb 09 08:56:33 AM UTC 25
Peak memory 929724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546860568 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3546860568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.1777337967
Short name T210
Test name
Test status
Simulation time 34738488219 ps
CPU time 1218.44 seconds
Started Feb 09 08:35:55 AM UTC 25
Finished Feb 09 08:56:28 AM UTC 25
Peak memory 1738688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777337967 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1777337967 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.2449881654
Short name T527
Test name
Test status
Simulation time 490396940723 ps
CPU time 7426.53 seconds
Started Feb 09 08:36:00 AM UTC 25
Finished Feb 09 10:41:01 AM UTC 25
Peak memory 7626792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449881654 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2449881654 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.764051829
Short name T384
Test name
Test status
Simulation time 181732713947 ps
CPU time 4665.08 seconds
Started Feb 09 08:36:07 AM UTC 25
Finished Feb 09 09:54:43 AM UTC 25
Peak memory 2256832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764051829 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.764051829 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.2865918682
Short name T295
Test name
Test status
Simulation time 16820147 ps
CPU time 1.12 seconds
Started Feb 09 09:23:15 AM UTC 25
Finished Feb 09 09:23:18 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865918682 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2865918682 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.1178408502
Short name T303
Test name
Test status
Simulation time 13145576404 ps
CPU time 185.38 seconds
Started Feb 09 09:21:19 AM UTC 25
Finished Feb 09 09:24:28 AM UTC 25
Peak memory 344064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178408502 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1178408502 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.3433772915
Short name T321
Test name
Test status
Simulation time 18501050430 ps
CPU time 624.02 seconds
Started Feb 09 09:19:19 AM UTC 25
Finished Feb 09 09:29:51 AM UTC 25
Peak memory 258052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433772915 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3433772915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.3412148113
Short name T293
Test name
Test status
Simulation time 289950328 ps
CPU time 22.17 seconds
Started Feb 09 09:22:51 AM UTC 25
Finished Feb 09 09:23:14 AM UTC 25
Peak memory 235240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412148113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3412148113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.3587859007
Short name T291
Test name
Test status
Simulation time 1758128422 ps
CPU time 9.82 seconds
Started Feb 09 09:22:52 AM UTC 25
Finished Feb 09 09:23:03 AM UTC 25
Peak memory 235268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587859007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3587859007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.1263975006
Short name T297
Test name
Test status
Simulation time 4022437339 ps
CPU time 126.79 seconds
Started Feb 09 09:21:25 AM UTC 25
Finished Feb 09 09:23:34 AM UTC 25
Peak memory 276496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263975006 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1263975006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.1831490039
Short name T301
Test name
Test status
Simulation time 12805442368 ps
CPU time 110.07 seconds
Started Feb 09 09:22:21 AM UTC 25
Finished Feb 09 09:24:14 AM UTC 25
Peak memory 352312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831490039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.kmac_error.1831490039 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.888980319
Short name T289
Test name
Test status
Simulation time 2155560699 ps
CPU time 11.42 seconds
Started Feb 09 09:22:36 AM UTC 25
Finished Feb 09 09:22:49 AM UTC 25
Peak memory 230712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888980319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.888980319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.3070187214
Short name T294
Test name
Test status
Simulation time 457980760 ps
CPU time 1.86 seconds
Started Feb 09 09:23:14 AM UTC 25
Finished Feb 09 09:23:18 AM UTC 25
Peak memory 229868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070187214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3070187214 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.3393629218
Short name T410
Test name
Test status
Simulation time 49109561538 ps
CPU time 2649.94 seconds
Started Feb 09 09:19:08 AM UTC 25
Finished Feb 09 10:03:47 AM UTC 25
Peak memory 1757192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393629218 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.3393629218 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.2635575707
Short name T292
Test name
Test status
Simulation time 36237422262 ps
CPU time 231.88 seconds
Started Feb 09 09:19:10 AM UTC 25
Finished Feb 09 09:23:05 AM UTC 25
Peak memory 475288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635575707 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2635575707 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.1853935239
Short name T277
Test name
Test status
Simulation time 897902303 ps
CPU time 10.16 seconds
Started Feb 09 09:18:57 AM UTC 25
Finished Feb 09 09:19:09 AM UTC 25
Peak memory 230792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853935239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.kmac_smoke.1853935239 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.441931585
Short name T360
Test name
Test status
Simulation time 74112826735 ps
CPU time 1271.55 seconds
Started Feb 09 09:23:14 AM UTC 25
Finished Feb 09 09:44:42 AM UTC 25
Peak memory 1269836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441931585 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.441931585 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_kmac.527321414
Short name T285
Test name
Test status
Simulation time 226715046 ps
CPU time 5.67 seconds
Started Feb 09 09:21:11 AM UTC 25
Finished Feb 09 09:21:18 AM UTC 25
Peak memory 230784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=527321414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.kmac_test_vectors_kmac.527321414 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_kmac_xof.2951351652
Short name T286
Test name
Test status
Simulation time 3317057153 ps
CPU time 9.09 seconds
Started Feb 09 09:21:14 AM UTC 25
Finished Feb 09 09:21:24 AM UTC 25
Peak memory 230848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2951351652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 10.kmac_test_vectors_kmac_xof.2951351652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_224.51162909
Short name T421
Test name
Test status
Simulation time 264345560997 ps
CPU time 2836.63 seconds
Started Feb 09 09:19:24 AM UTC 25
Finished Feb 09 10:07:12 AM UTC 25
Peak memory 3309628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51162909 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.51162909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_256.3667747450
Short name T365
Test name
Test status
Simulation time 18512918111 ps
CPU time 1680.69 seconds
Started Feb 09 09:19:34 AM UTC 25
Finished Feb 09 09:47:53 AM UTC 25
Peak memory 1150952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667747450 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.3667747450 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_384.3724689979
Short name T372
Test name
Test status
Simulation time 46873206729 ps
CPU time 1780.69 seconds
Started Feb 09 09:19:42 AM UTC 25
Finished Feb 09 09:49:43 AM UTC 25
Peak memory 2402244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724689979 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.3724689979 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_512.3052518481
Short name T348
Test name
Test status
Simulation time 43058839233 ps
CPU time 1159.86 seconds
Started Feb 09 09:20:02 AM UTC 25
Finished Feb 09 09:39:36 AM UTC 25
Peak memory 1718208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052518481 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.3052518481 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_shake_128.1656978918
Short name T566
Test name
Test status
Simulation time 213642658287 ps
CPU time 5509.58 seconds
Started Feb 09 09:20:21 AM UTC 25
Finished Feb 09 10:53:09 AM UTC 25
Peak memory 2736052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656978918 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.1656978918 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/10.kmac_test_vectors_shake_256.1783942301
Short name T609
Test name
Test status
Simulation time 1047701069550 ps
CPU time 6329.77 seconds
Started Feb 09 09:20:43 AM UTC 25
Finished Feb 09 11:07:19 AM UTC 25
Peak memory 6440888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783942301 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.1783942301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.1356758287
Short name T313
Test name
Test status
Simulation time 29724161 ps
CPU time 1.15 seconds
Started Feb 09 09:26:55 AM UTC 25
Finished Feb 09 09:26:58 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356758287 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1356758287 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.1440144269
Short name T145
Test name
Test status
Simulation time 3769938223 ps
CPU time 194.93 seconds
Started Feb 09 09:24:45 AM UTC 25
Finished Feb 09 09:28:03 AM UTC 25
Peak memory 309252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440144269 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1440144269 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.338947114
Short name T329
Test name
Test status
Simulation time 36279864477 ps
CPU time 531.8 seconds
Started Feb 09 09:23:34 AM UTC 25
Finished Feb 09 09:32:33 AM UTC 25
Peak memory 258068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338947114 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.338947114 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2432191995
Short name T314
Test name
Test status
Simulation time 311593252 ps
CPU time 24.4 seconds
Started Feb 09 09:26:34 AM UTC 25
Finished Feb 09 09:27:00 AM UTC 25
Peak memory 232592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432191995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2432191995 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.3752630472
Short name T312
Test name
Test status
Simulation time 128698511 ps
CPU time 8.72 seconds
Started Feb 09 09:26:44 AM UTC 25
Finished Feb 09 09:26:54 AM UTC 25
Peak memory 228624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752630472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3752630472 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.1644710452
Short name T317
Test name
Test status
Simulation time 8659639408 ps
CPU time 158.82 seconds
Started Feb 09 09:25:34 AM UTC 25
Finished Feb 09 09:28:16 AM UTC 25
Peak memory 366660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644710452 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1644710452 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.463935549
Short name T309
Test name
Test status
Simulation time 8127483229 ps
CPU time 17.07 seconds
Started Feb 09 09:26:25 AM UTC 25
Finished Feb 09 09:26:43 AM UTC 25
Peak memory 230716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463935549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.463935549 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.951142121
Short name T311
Test name
Test status
Simulation time 67458188 ps
CPU time 2.01 seconds
Started Feb 09 09:26:50 AM UTC 25
Finished Feb 09 09:26:53 AM UTC 25
Peak memory 229756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951142121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.951142121 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.2379864639
Short name T336
Test name
Test status
Simulation time 29672407619 ps
CPU time 611.44 seconds
Started Feb 09 09:23:18 AM UTC 25
Finished Feb 09 09:33:38 AM UTC 25
Peak memory 653324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379864639 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.2379864639 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.1264552993
Short name T315
Test name
Test status
Simulation time 8963412197 ps
CPU time 237.23 seconds
Started Feb 09 09:23:18 AM UTC 25
Finished Feb 09 09:27:19 AM UTC 25
Peak memory 428056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264552993 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1264552993 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.1542736229
Short name T302
Test name
Test status
Simulation time 11003415767 ps
CPU time 57.56 seconds
Started Feb 09 09:23:15 AM UTC 25
Finished Feb 09 09:24:15 AM UTC 25
Peak memory 232836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542736229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.kmac_smoke.1542736229 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.1635414715
Short name T172
Test name
Test status
Simulation time 64762969828 ps
CPU time 1158 seconds
Started Feb 09 09:26:54 AM UTC 25
Finished Feb 09 09:46:25 AM UTC 25
Peak memory 590232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635414715 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1635414715 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_kmac.1396813250
Short name T304
Test name
Test status
Simulation time 271745564 ps
CPU time 5.79 seconds
Started Feb 09 09:24:28 AM UTC 25
Finished Feb 09 09:24:35 AM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1396813250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.kmac_test_vectors_kmac.1396813250 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_kmac_xof.4149478057
Short name T305
Test name
Test status
Simulation time 328118752 ps
CPU time 6.56 seconds
Started Feb 09 09:24:36 AM UTC 25
Finished Feb 09 09:24:44 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4149478057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.kmac_test_vectors_kmac_xof.4149478057 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_224.223249978
Short name T390
Test name
Test status
Simulation time 19376589634 ps
CPU time 1940.5 seconds
Started Feb 09 09:23:35 AM UTC 25
Finished Feb 09 09:56:18 AM UTC 25
Peak memory 1179560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223249978 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.223249978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_256.4125593663
Short name T436
Test name
Test status
Simulation time 79721615012 ps
CPU time 2801.07 seconds
Started Feb 09 09:24:03 AM UTC 25
Finished Feb 09 10:11:16 AM UTC 25
Peak memory 3082232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125593663 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.4125593663 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_384.902186259
Short name T389
Test name
Test status
Simulation time 279494929129 ps
CPU time 1862.09 seconds
Started Feb 09 09:24:08 AM UTC 25
Finished Feb 09 09:55:29 AM UTC 25
Peak memory 2391996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902186259 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.902186259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_512.729459156
Short name T357
Test name
Test status
Simulation time 230924241415 ps
CPU time 1131 seconds
Started Feb 09 09:24:08 AM UTC 25
Finished Feb 09 09:43:11 AM UTC 25
Peak memory 1720248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729459156 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.729459156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_shake_128.100157548
Short name T691
Test name
Test status
Simulation time 263577980508 ps
CPU time 7810.22 seconds
Started Feb 09 09:24:15 AM UTC 25
Finished Feb 09 11:35:44 AM UTC 25
Peak memory 7821348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100157548 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.100157548 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/11.kmac_test_vectors_shake_256.2975009266
Short name T606
Test name
Test status
Simulation time 607956957035 ps
CPU time 6017.16 seconds
Started Feb 09 09:24:16 AM UTC 25
Finished Feb 09 11:05:37 AM UTC 25
Peak memory 6455232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975009266 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2975009266 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.3986672128
Short name T332
Test name
Test status
Simulation time 16460478 ps
CPU time 1.23 seconds
Started Feb 09 09:32:42 AM UTC 25
Finished Feb 09 09:32:44 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986672128 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3986672128 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.3784493654
Short name T337
Test name
Test status
Simulation time 8171419550 ps
CPU time 231.58 seconds
Started Feb 09 09:30:33 AM UTC 25
Finished Feb 09 09:34:28 AM UTC 25
Peak memory 380932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784493654 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3784493654 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.3335557083
Short name T46
Test name
Test status
Simulation time 3599173303 ps
CPU time 158.15 seconds
Started Feb 09 09:27:33 AM UTC 25
Finished Feb 09 09:30:14 AM UTC 25
Peak memory 235528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335557083 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3335557083 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.3087517563
Short name T328
Test name
Test status
Simulation time 1423000186 ps
CPU time 47.83 seconds
Started Feb 09 09:31:32 AM UTC 25
Finished Feb 09 09:32:22 AM UTC 25
Peak memory 235272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087517563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3087517563 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1682653367
Short name T333
Test name
Test status
Simulation time 3298808232 ps
CPU time 22.68 seconds
Started Feb 09 09:32:22 AM UTC 25
Finished Feb 09 09:32:46 AM UTC 25
Peak memory 235336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682653367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1682653367 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2836317545
Short name T325
Test name
Test status
Simulation time 1174843700 ps
CPU time 32.29 seconds
Started Feb 09 09:30:43 AM UTC 25
Finished Feb 09 09:31:17 AM UTC 25
Peak memory 243632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836317545 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2836317545 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.1175359233
Short name T338
Test name
Test status
Simulation time 7630818073 ps
CPU time 303.69 seconds
Started Feb 09 09:31:18 AM UTC 25
Finished Feb 09 09:36:26 AM UTC 25
Peak memory 366592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175359233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.kmac_error.1175359233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.3045065109
Short name T327
Test name
Test status
Simulation time 535205861 ps
CPU time 2.91 seconds
Started Feb 09 09:31:27 AM UTC 25
Finished Feb 09 09:31:31 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045065109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3045065109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.3121408571
Short name T330
Test name
Test status
Simulation time 126513063 ps
CPU time 1.87 seconds
Started Feb 09 09:32:33 AM UTC 25
Finished Feb 09 09:32:37 AM UTC 25
Peak memory 229936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121408571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3121408571 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2686380514
Short name T391
Test name
Test status
Simulation time 186819167441 ps
CPU time 1739.75 seconds
Started Feb 09 09:27:00 AM UTC 25
Finished Feb 09 09:56:20 AM UTC 25
Peak memory 2166800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686380514 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2686380514 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.783830803
Short name T335
Test name
Test status
Simulation time 17993077123 ps
CPU time 370.13 seconds
Started Feb 09 09:27:20 AM UTC 25
Finished Feb 09 09:33:36 AM UTC 25
Peak memory 380948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783830803 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.783830803 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.2147388033
Short name T318
Test name
Test status
Simulation time 2889785724 ps
CPU time 77.41 seconds
Started Feb 09 09:26:58 AM UTC 25
Finished Feb 09 09:28:18 AM UTC 25
Peak memory 234884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147388033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.kmac_smoke.2147388033 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.2082599603
Short name T414
Test name
Test status
Simulation time 68895966309 ps
CPU time 1983.37 seconds
Started Feb 09 09:32:38 AM UTC 25
Finished Feb 09 10:06:03 AM UTC 25
Peak memory 766364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082599603 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2082599603 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_kmac.1513798496
Short name T322
Test name
Test status
Simulation time 246621606 ps
CPU time 7.2 seconds
Started Feb 09 09:30:15 AM UTC 25
Finished Feb 09 09:30:23 AM UTC 25
Peak memory 230804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1513798496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.kmac_test_vectors_kmac.1513798496 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_kmac_xof.462237975
Short name T323
Test name
Test status
Simulation time 511705084 ps
CPU time 7.02 seconds
Started Feb 09 09:30:24 AM UTC 25
Finished Feb 09 09:30:32 AM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=462237975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac_xof.462237975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_224.2514277759
Short name T453
Test name
Test status
Simulation time 96405916487 ps
CPU time 2731.6 seconds
Started Feb 09 09:28:05 AM UTC 25
Finished Feb 09 10:14:06 AM UTC 25
Peak memory 3221492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514277759 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.2514277759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_256.4061339918
Short name T416
Test name
Test status
Simulation time 251298729764 ps
CPU time 2275.28 seconds
Started Feb 09 09:28:17 AM UTC 25
Finished Feb 09 10:06:37 AM UTC 25
Peak memory 3026856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061339918 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.4061339918 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_384.3223882653
Short name T369
Test name
Test status
Simulation time 13642557963 ps
CPU time 1212.52 seconds
Started Feb 09 09:28:19 AM UTC 25
Finished Feb 09 09:48:45 AM UTC 25
Peak memory 931780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223882653 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.3223882653 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_512.1846233158
Short name T364
Test name
Test status
Simulation time 33049898224 ps
CPU time 1139.25 seconds
Started Feb 09 09:28:31 AM UTC 25
Finished Feb 09 09:47:43 AM UTC 25
Peak memory 1742844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846233158 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1846233158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_shake_128.881287323
Short name T545
Test name
Test status
Simulation time 50826445301 ps
CPU time 4537.95 seconds
Started Feb 09 09:29:03 AM UTC 25
Finished Feb 09 10:45:28 AM UTC 25
Peak memory 2701304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881287323 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.881287323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/12.kmac_test_vectors_shake_256.2715357878
Short name T501
Test name
Test status
Simulation time 272328733153 ps
CPU time 3620.13 seconds
Started Feb 09 09:29:52 AM UTC 25
Finished Feb 09 10:30:49 AM UTC 25
Peak memory 2252732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715357878 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2715357878 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.2024528566
Short name T352
Test name
Test status
Simulation time 12453313 ps
CPU time 1.19 seconds
Started Feb 09 09:39:48 AM UTC 25
Finished Feb 09 09:39:51 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024528566 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2024528566 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.4226434644
Short name T344
Test name
Test status
Simulation time 3303605236 ps
CPU time 19.2 seconds
Started Feb 09 09:37:53 AM UTC 25
Finished Feb 09 09:38:13 AM UTC 25
Peak memory 235528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226434644 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.4226434644 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.1885316950
Short name T375
Test name
Test status
Simulation time 64887732236 ps
CPU time 986.68 seconds
Started Feb 09 09:33:37 AM UTC 25
Finished Feb 09 09:50:15 AM UTC 25
Peak memory 268296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885316950 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1885316950 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2281997993
Short name T351
Test name
Test status
Simulation time 475260086 ps
CPU time 41.2 seconds
Started Feb 09 09:39:05 AM UTC 25
Finished Feb 09 09:39:48 AM UTC 25
Peak memory 245512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281997993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2281997993 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.56642922
Short name T354
Test name
Test status
Simulation time 3468561927 ps
CPU time 31.77 seconds
Started Feb 09 09:39:36 AM UTC 25
Finished Feb 09 09:40:10 AM UTC 25
Peak memory 235456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56642922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.56642922 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.2083174460
Short name T349
Test name
Test status
Simulation time 2347965381 ps
CPU time 84.3 seconds
Started Feb 09 09:38:15 AM UTC 25
Finished Feb 09 09:39:41 AM UTC 25
Peak memory 253936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083174460 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2083174460 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.172252914
Short name T347
Test name
Test status
Simulation time 1227296549 ps
CPU time 12.52 seconds
Started Feb 09 09:38:50 AM UTC 25
Finished Feb 09 09:39:04 AM UTC 25
Peak memory 230564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172252914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.172252914 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.2659085187
Short name T350
Test name
Test status
Simulation time 228702274 ps
CPU time 2.79 seconds
Started Feb 09 09:39:42 AM UTC 25
Finished Feb 09 09:39:46 AM UTC 25
Peak memory 232604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659085187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2659085187 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1947864367
Short name T395
Test name
Test status
Simulation time 14016566193 ps
CPU time 1520.16 seconds
Started Feb 09 09:32:48 AM UTC 25
Finished Feb 09 09:58:26 AM UTC 25
Peak memory 1103888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947864367 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.1947864367 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.3688482827
Short name T345
Test name
Test status
Simulation time 13386900321 ps
CPU time 334.53 seconds
Started Feb 09 09:33:05 AM UTC 25
Finished Feb 09 09:38:44 AM UTC 25
Peak memory 528400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688482827 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3688482827 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.935644849
Short name T334
Test name
Test status
Simulation time 5784054529 ps
CPU time 18 seconds
Started Feb 09 09:32:45 AM UTC 25
Finished Feb 09 09:33:04 AM UTC 25
Peak memory 230856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935644849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.kmac_smoke.935644849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.884424337
Short name T418
Test name
Test status
Simulation time 191370814448 ps
CPU time 1601.02 seconds
Started Feb 09 09:39:47 AM UTC 25
Finished Feb 09 10:06:46 AM UTC 25
Peak memory 1319320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884424337 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.884424337 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_kmac.3123668158
Short name T342
Test name
Test status
Simulation time 187780896 ps
CPU time 6.82 seconds
Started Feb 09 09:37:35 AM UTC 25
Finished Feb 09 09:37:44 AM UTC 25
Peak memory 230736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3123668158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.kmac_test_vectors_kmac.3123668158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_kmac_xof.3955282156
Short name T343
Test name
Test status
Simulation time 173546859 ps
CPU time 6.32 seconds
Started Feb 09 09:37:45 AM UTC 25
Finished Feb 09 09:37:52 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3955282156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.kmac_test_vectors_kmac_xof.3955282156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_224.1307334532
Short name T412
Test name
Test status
Simulation time 37682023862 ps
CPU time 1882.22 seconds
Started Feb 09 09:33:38 AM UTC 25
Finished Feb 09 10:05:21 AM UTC 25
Peak memory 1210284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307334532 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1307334532 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_256.2389129459
Short name T435
Test name
Test status
Simulation time 287798479425 ps
CPU time 2143.83 seconds
Started Feb 09 09:34:29 AM UTC 25
Finished Feb 09 10:10:36 AM UTC 25
Peak memory 3033020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389129459 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2389129459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_384.239654244
Short name T415
Test name
Test status
Simulation time 73297111727 ps
CPU time 1776.86 seconds
Started Feb 09 09:36:28 AM UTC 25
Finished Feb 09 10:06:24 AM UTC 25
Peak memory 2410424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239654244 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.239654244 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_512.1937448282
Short name T381
Test name
Test status
Simulation time 28459144211 ps
CPU time 1047.44 seconds
Started Feb 09 09:36:29 AM UTC 25
Finished Feb 09 09:54:09 AM UTC 25
Peak memory 704448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937448282 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.1937448282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_shake_128.2955314581
Short name T595
Test name
Test status
Simulation time 211714870930 ps
CPU time 5022.09 seconds
Started Feb 09 09:36:43 AM UTC 25
Finished Feb 09 11:01:18 AM UTC 25
Peak memory 2701236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955314581 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2955314581 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/13.kmac_test_vectors_shake_256.2297088371
Short name T636
Test name
Test status
Simulation time 146572914863 ps
CPU time 5868.38 seconds
Started Feb 09 09:36:57 AM UTC 25
Finished Feb 09 11:15:46 AM UTC 25
Peak memory 6485928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297088371 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2297088371 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.803569622
Short name T370
Test name
Test status
Simulation time 18056809 ps
CPU time 1.2 seconds
Started Feb 09 09:48:47 AM UTC 25
Finished Feb 09 09:48:49 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803569622 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.803569622 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.3674823610
Short name T377
Test name
Test status
Simulation time 3954510337 ps
CPU time 307.94 seconds
Started Feb 09 09:46:26 AM UTC 25
Finished Feb 09 09:51:38 AM UTC 25
Peak memory 339972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674823610 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3674823610 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.1276011702
Short name T367
Test name
Test status
Simulation time 2990790801 ps
CPU time 27.95 seconds
Started Feb 09 09:48:06 AM UTC 25
Finished Feb 09 09:48:36 AM UTC 25
Peak memory 235300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276011702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1276011702 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.389051878
Short name T368
Test name
Test status
Simulation time 5819945890 ps
CPU time 33.49 seconds
Started Feb 09 09:48:10 AM UTC 25
Finished Feb 09 09:48:45 AM UTC 25
Peak memory 232712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389051878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.389051878 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.4282698112
Short name T376
Test name
Test status
Simulation time 15919773806 ps
CPU time 275.44 seconds
Started Feb 09 09:46:34 AM UTC 25
Finished Feb 09 09:51:13 AM UTC 25
Peak memory 434244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282698112 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.4282698112 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.861989506
Short name T373
Test name
Test status
Simulation time 5729033575 ps
CPU time 128.84 seconds
Started Feb 09 09:47:44 AM UTC 25
Finished Feb 09 09:49:55 AM UTC 25
Peak memory 333896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861989506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.kmac_error.861989506 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.3513674350
Short name T366
Test name
Test status
Simulation time 2782907674 ps
CPU time 13.79 seconds
Started Feb 09 09:47:54 AM UTC 25
Finished Feb 09 09:48:09 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513674350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3513674350 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.151687755
Short name T517
Test name
Test status
Simulation time 80317277345 ps
CPU time 3391.3 seconds
Started Feb 09 09:40:07 AM UTC 25
Finished Feb 09 10:37:13 AM UTC 25
Peak memory 3887116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151687755 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.151687755 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.512708704
Short name T355
Test name
Test status
Simulation time 3233541192 ps
CPU time 93.51 seconds
Started Feb 09 09:40:11 AM UTC 25
Finished Feb 09 09:41:46 AM UTC 25
Peak memory 294960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512708704 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.512708704 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.3967366961
Short name T353
Test name
Test status
Simulation time 421641745 ps
CPU time 13.05 seconds
Started Feb 09 09:39:51 AM UTC 25
Finished Feb 09 09:40:06 AM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967366961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.kmac_smoke.3967366961 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.3687688332
Short name T394
Test name
Test status
Simulation time 48861128673 ps
CPU time 500.62 seconds
Started Feb 09 09:48:40 AM UTC 25
Finished Feb 09 09:57:07 AM UTC 25
Peak memory 546892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687688332 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3687688332 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_kmac.3958107927
Short name T362
Test name
Test status
Simulation time 265196997 ps
CPU time 7.41 seconds
Started Feb 09 09:46:15 AM UTC 25
Finished Feb 09 09:46:24 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3958107927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.kmac_test_vectors_kmac.3958107927 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_kmac_xof.1808338716
Short name T363
Test name
Test status
Simulation time 233009385 ps
CPU time 7.34 seconds
Started Feb 09 09:46:24 AM UTC 25
Finished Feb 09 09:46:33 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1808338716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.kmac_test_vectors_kmac_xof.1808338716 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_224.1813747065
Short name T446
Test name
Test status
Simulation time 29921111232 ps
CPU time 1797.67 seconds
Started Feb 09 09:41:52 AM UTC 25
Finished Feb 09 10:12:09 AM UTC 25
Peak memory 1210272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813747065 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.1813747065 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_256.1680145283
Short name T469
Test name
Test status
Simulation time 400948775340 ps
CPU time 2325.57 seconds
Started Feb 09 09:43:12 AM UTC 25
Finished Feb 09 10:22:23 AM UTC 25
Peak memory 3020864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680145283 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1680145283 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_384.2595771207
Short name T454
Test name
Test status
Simulation time 238433427583 ps
CPU time 1799.35 seconds
Started Feb 09 09:43:50 AM UTC 25
Finished Feb 09 10:14:09 AM UTC 25
Peak memory 2447296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595771207 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.2595771207 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_512.3069591249
Short name T430
Test name
Test status
Simulation time 92590587513 ps
CPU time 1479.14 seconds
Started Feb 09 09:44:25 AM UTC 25
Finished Feb 09 10:09:21 AM UTC 25
Peak memory 1714112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069591249 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.3069591249 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_shake_128.1078116426
Short name T619
Test name
Test status
Simulation time 105870782904 ps
CPU time 5155.04 seconds
Started Feb 09 09:44:43 AM UTC 25
Finished Feb 09 11:11:34 AM UTC 25
Peak memory 2705392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078116426 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.1078116426 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/14.kmac_test_vectors_shake_256.3253854891
Short name T666
Test name
Test status
Simulation time 2058172925274 ps
CPU time 5959.29 seconds
Started Feb 09 09:45:43 AM UTC 25
Finished Feb 09 11:26:04 AM UTC 25
Peak memory 6350848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253854891 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3253854891 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.2474110213
Short name T387
Test name
Test status
Simulation time 52029732 ps
CPU time 1.14 seconds
Started Feb 09 09:55:06 AM UTC 25
Finished Feb 09 09:55:08 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474110213 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2474110213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.2399558027
Short name T386
Test name
Test status
Simulation time 28323927200 ps
CPU time 186.42 seconds
Started Feb 09 09:51:55 AM UTC 25
Finished Feb 09 09:55:05 AM UTC 25
Peak memory 387056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399558027 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2399558027 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.2019904371
Short name T431
Test name
Test status
Simulation time 45081358166 ps
CPU time 1207.12 seconds
Started Feb 09 09:49:36 AM UTC 25
Finished Feb 09 10:09:58 AM UTC 25
Peak memory 270412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019904371 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2019904371 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.2979667975
Short name T385
Test name
Test status
Simulation time 403641181 ps
CPU time 11.1 seconds
Started Feb 09 09:54:36 AM UTC 25
Finished Feb 09 09:54:49 AM UTC 25
Peak memory 235272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979667975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2979667975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.3197390469
Short name T388
Test name
Test status
Simulation time 4015799059 ps
CPU time 40.37 seconds
Started Feb 09 09:54:44 AM UTC 25
Finished Feb 09 09:55:27 AM UTC 25
Peak memory 235332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197390469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3197390469 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.2785813953
Short name T400
Test name
Test status
Simulation time 74774737582 ps
CPU time 327.82 seconds
Started Feb 09 09:54:08 AM UTC 25
Finished Feb 09 09:59:40 AM UTC 25
Peak memory 495632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785813953 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2785813953 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.1834078834
Short name T393
Test name
Test status
Simulation time 62577440948 ps
CPU time 171.92 seconds
Started Feb 09 09:54:11 AM UTC 25
Finished Feb 09 09:57:06 AM UTC 25
Peak memory 376836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834078834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.kmac_error.1834078834 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.3689496401
Short name T383
Test name
Test status
Simulation time 5977363426 ps
CPU time 10.05 seconds
Started Feb 09 09:54:24 AM UTC 25
Finished Feb 09 09:54:35 AM UTC 25
Peak memory 232764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689496401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3689496401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.3322357937
Short name T40
Test name
Test status
Simulation time 97966095 ps
CPU time 1.83 seconds
Started Feb 09 09:54:49 AM UTC 25
Finished Feb 09 09:54:53 AM UTC 25
Peak memory 229816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322357937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3322357937 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.2478382949
Short name T546
Test name
Test status
Simulation time 105352735341 ps
CPU time 3373.45 seconds
Started Feb 09 09:48:50 AM UTC 25
Finished Feb 09 10:45:37 AM UTC 25
Peak memory 4157452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478382949 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.2478382949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.2913705122
Short name T396
Test name
Test status
Simulation time 65927096997 ps
CPU time 561.41 seconds
Started Feb 09 09:48:59 AM UTC 25
Finished Feb 09 09:58:28 AM UTC 25
Peak memory 614416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913705122 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2913705122 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.1228620151
Short name T374
Test name
Test status
Simulation time 11946251701 ps
CPU time 69.01 seconds
Started Feb 09 09:48:47 AM UTC 25
Finished Feb 09 09:49:57 AM UTC 25
Peak memory 235516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228620151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.kmac_smoke.1228620151 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.3490199027
Short name T455
Test name
Test status
Simulation time 49177008518 ps
CPU time 1298.12 seconds
Started Feb 09 09:54:53 AM UTC 25
Finished Feb 09 10:16:48 AM UTC 25
Peak memory 743880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490199027 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3490199027 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_kmac.1610285118
Short name T378
Test name
Test status
Simulation time 233654740 ps
CPU time 6.64 seconds
Started Feb 09 09:51:39 AM UTC 25
Finished Feb 09 09:51:47 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1610285118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.kmac_test_vectors_kmac.1610285118 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_kmac_xof.3996565384
Short name T379
Test name
Test status
Simulation time 129812060 ps
CPU time 5.2 seconds
Started Feb 09 09:51:48 AM UTC 25
Finished Feb 09 09:51:54 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3996565384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 15.kmac_test_vectors_kmac_xof.3996565384 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_224.1714347031
Short name T509
Test name
Test status
Simulation time 99924940777 ps
CPU time 2578.14 seconds
Started Feb 09 09:49:44 AM UTC 25
Finished Feb 09 10:33:09 AM UTC 25
Peak memory 3272708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714347031 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1714347031 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_256.1029091022
Short name T513
Test name
Test status
Simulation time 257416183666 ps
CPU time 2647.95 seconds
Started Feb 09 09:49:56 AM UTC 25
Finished Feb 09 10:34:34 AM UTC 25
Peak memory 3106808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029091022 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.1029091022 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_384.4133442924
Short name T433
Test name
Test status
Simulation time 27930150538 ps
CPU time 1201.34 seconds
Started Feb 09 09:49:58 AM UTC 25
Finished Feb 09 10:10:13 AM UTC 25
Peak memory 915456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133442924 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.4133442924 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_512.934837334
Short name T432
Test name
Test status
Simulation time 132503038343 ps
CPU time 1168.71 seconds
Started Feb 09 09:50:16 AM UTC 25
Finished Feb 09 10:09:58 AM UTC 25
Peak memory 1759168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934837334 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.934837334 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_shake_128.1578083140
Short name T713
Test name
Test status
Simulation time 501704400706 ps
CPU time 6817.45 seconds
Started Feb 09 09:51:01 AM UTC 25
Finished Feb 09 11:45:47 AM UTC 25
Peak memory 7778312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578083140 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1578083140 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/15.kmac_test_vectors_shake_256.1852276828
Short name T721
Test name
Test status
Simulation time 215976418718 ps
CPU time 6920.89 seconds
Started Feb 09 09:51:14 AM UTC 25
Finished Feb 09 11:47:47 AM UTC 25
Peak memory 6400032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852276828 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.1852276828 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.3083125075
Short name T406
Test name
Test status
Simulation time 29995019 ps
CPU time 1.21 seconds
Started Feb 09 10:02:07 AM UTC 25
Finished Feb 09 10:02:10 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083125075 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3083125075 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.1860203850
Short name T407
Test name
Test status
Simulation time 11242246742 ps
CPU time 217.11 seconds
Started Feb 09 09:58:52 AM UTC 25
Finished Feb 09 10:02:33 AM UTC 25
Peak memory 305156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860203850 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1860203850 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.898354971
Short name T422
Test name
Test status
Simulation time 56130555693 ps
CPU time 648.61 seconds
Started Feb 09 09:56:19 AM UTC 25
Finished Feb 09 10:07:16 AM UTC 25
Peak memory 253968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898354971 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.898354971 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2989318858
Short name T404
Test name
Test status
Simulation time 4476239597 ps
CPU time 56.99 seconds
Started Feb 09 10:00:58 AM UTC 25
Finished Feb 09 10:01:57 AM UTC 25
Peak memory 235332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989318858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2989318858 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.1798721985
Short name T405
Test name
Test status
Simulation time 816847239 ps
CPU time 22.32 seconds
Started Feb 09 10:01:43 AM UTC 25
Finished Feb 09 10:02:07 AM UTC 25
Peak memory 232592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798721985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1798721985 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.3784685186
Short name T411
Test name
Test status
Simulation time 28300742031 ps
CPU time 249.43 seconds
Started Feb 09 09:59:41 AM UTC 25
Finished Feb 09 10:03:55 AM UTC 25
Peak memory 335892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784685186 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3784685186 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.1764054756
Short name T409
Test name
Test status
Simulation time 25673781615 ps
CPU time 176.1 seconds
Started Feb 09 10:00:46 AM UTC 25
Finished Feb 09 10:03:45 AM UTC 25
Peak memory 397308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764054756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.kmac_error.1764054756 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.1034626430
Short name T402
Test name
Test status
Simulation time 962676554 ps
CPU time 3.05 seconds
Started Feb 09 10:00:53 AM UTC 25
Finished Feb 09 10:00:57 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034626430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1034626430 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.144396369
Short name T403
Test name
Test status
Simulation time 7458384426 ps
CPU time 368.81 seconds
Started Feb 09 09:55:28 AM UTC 25
Finished Feb 09 10:01:43 AM UTC 25
Peak memory 462856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144396369 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.144396369 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.1969332189
Short name T401
Test name
Test status
Simulation time 8836353842 ps
CPU time 316.8 seconds
Started Feb 09 09:55:30 AM UTC 25
Finished Feb 09 10:00:52 AM UTC 25
Peak memory 352332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969332189 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1969332189 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.3703313343
Short name T392
Test name
Test status
Simulation time 2772558415 ps
CPU time 81.06 seconds
Started Feb 09 09:55:10 AM UTC 25
Finished Feb 09 09:56:33 AM UTC 25
Peak memory 234884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703313343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.kmac_smoke.3703313343 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.798275125
Short name T428
Test name
Test status
Simulation time 77470580203 ps
CPU time 384.64 seconds
Started Feb 09 10:02:05 AM UTC 25
Finished Feb 09 10:08:35 AM UTC 25
Peak memory 358412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798275125 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.798275125 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_kmac.3804229552
Short name T398
Test name
Test status
Simulation time 698691884 ps
CPU time 6.64 seconds
Started Feb 09 09:58:33 AM UTC 25
Finished Feb 09 09:58:41 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3804229552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.kmac_test_vectors_kmac.3804229552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_kmac_xof.3060227673
Short name T399
Test name
Test status
Simulation time 248637816 ps
CPU time 7.76 seconds
Started Feb 09 09:58:42 AM UTC 25
Finished Feb 09 09:58:51 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3060227673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.kmac_test_vectors_kmac_xof.3060227673 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_224.1333856248
Short name T490
Test name
Test status
Simulation time 19750038126 ps
CPU time 1975.68 seconds
Started Feb 09 09:56:21 AM UTC 25
Finished Feb 09 10:29:40 AM UTC 25
Peak memory 1214468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333856248 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.1333856248 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_256.1963555338
Short name T488
Test name
Test status
Simulation time 18332155110 ps
CPU time 1908.58 seconds
Started Feb 09 09:56:34 AM UTC 25
Finished Feb 09 10:28:45 AM UTC 25
Peak memory 1151036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963555338 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1963555338 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_384.4109837097
Short name T507
Test name
Test status
Simulation time 263811252690 ps
CPU time 2107.93 seconds
Started Feb 09 09:57:06 AM UTC 25
Finished Feb 09 10:32:38 AM UTC 25
Peak memory 2396064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109837097 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.4109837097 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_512.1726807048
Short name T447
Test name
Test status
Simulation time 53153345933 ps
CPU time 891.64 seconds
Started Feb 09 09:57:08 AM UTC 25
Finished Feb 09 10:12:11 AM UTC 25
Peak memory 716776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726807048 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1726807048 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_shake_128.4260466931
Short name T746
Test name
Test status
Simulation time 178353535286 ps
CPU time 7120.93 seconds
Started Feb 09 09:58:27 AM UTC 25
Finished Feb 09 11:58:19 AM UTC 25
Peak memory 7905316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260466931 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.4260466931 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/16.kmac_test_vectors_shake_256.3969031506
Short name T700
Test name
Test status
Simulation time 225056882515 ps
CPU time 6058.2 seconds
Started Feb 09 09:58:29 AM UTC 25
Finished Feb 09 11:40:27 AM UTC 25
Peak memory 6395896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969031506 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.3969031506 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.773437016
Short name T426
Test name
Test status
Simulation time 49161944 ps
CPU time 1.18 seconds
Started Feb 09 10:07:56 AM UTC 25
Finished Feb 09 10:07:59 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773437016 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.773437016 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.2920494486
Short name T427
Test name
Test status
Simulation time 16409116398 ps
CPU time 102.21 seconds
Started Feb 09 10:06:47 AM UTC 25
Finished Feb 09 10:08:32 AM UTC 25
Peak memory 290804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920494486 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2920494486 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.1991626881
Short name T441
Test name
Test status
Simulation time 50386656436 ps
CPU time 477.38 seconds
Started Feb 09 10:03:46 AM UTC 25
Finished Feb 09 10:11:50 AM UTC 25
Peak memory 251916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991626881 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1991626881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1604230179
Short name T425
Test name
Test status
Simulation time 2129967040 ps
CPU time 34.64 seconds
Started Feb 09 10:07:17 AM UTC 25
Finished Feb 09 10:07:53 AM UTC 25
Peak memory 235272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604230179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1604230179 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.1896355223
Short name T424
Test name
Test status
Simulation time 3427530837 ps
CPU time 25.39 seconds
Started Feb 09 10:07:24 AM UTC 25
Finished Feb 09 10:07:51 AM UTC 25
Peak memory 235332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896355223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1896355223 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2135672012
Short name T434
Test name
Test status
Simulation time 32570157044 ps
CPU time 218.52 seconds
Started Feb 09 10:06:48 AM UTC 25
Finished Feb 09 10:10:30 AM UTC 25
Peak memory 360460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135672012 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2135672012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.718341126
Short name T438
Test name
Test status
Simulation time 3358301831 ps
CPU time 273.48 seconds
Started Feb 09 10:06:54 AM UTC 25
Finished Feb 09 10:11:31 AM UTC 25
Peak memory 346124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718341126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.kmac_error.718341126 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_key_error.1842507464
Short name T423
Test name
Test status
Simulation time 851758332 ps
CPU time 9.05 seconds
Started Feb 09 10:07:13 AM UTC 25
Finished Feb 09 10:07:23 AM UTC 25
Peak memory 230652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842507464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1842507464 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.2213542618
Short name T467
Test name
Test status
Simulation time 23897374214 ps
CPU time 1039.29 seconds
Started Feb 09 10:02:34 AM UTC 25
Finished Feb 09 10:20:05 AM UTC 25
Peak memory 919600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213542618 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.2213542618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.1112659811
Short name T413
Test name
Test status
Simulation time 1809100712 ps
CPU time 172.39 seconds
Started Feb 09 10:03:04 AM UTC 25
Finished Feb 09 10:05:59 AM UTC 25
Peak memory 292820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112659811 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1112659811 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.3352809041
Short name T408
Test name
Test status
Simulation time 2223514917 ps
CPU time 50.38 seconds
Started Feb 09 10:02:10 AM UTC 25
Finished Feb 09 10:03:03 AM UTC 25
Peak memory 230792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352809041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.kmac_smoke.3352809041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.3722603491
Short name T565
Test name
Test status
Simulation time 30014139270 ps
CPU time 2644.05 seconds
Started Feb 09 10:07:54 AM UTC 25
Finished Feb 09 10:52:28 AM UTC 25
Peak memory 772500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722603491 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3722603491 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_kmac.4094557231
Short name T419
Test name
Test status
Simulation time 880801684 ps
CPU time 7.08 seconds
Started Feb 09 10:06:38 AM UTC 25
Finished Feb 09 10:06:47 AM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4094557231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.kmac_test_vectors_kmac.4094557231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_kmac_xof.3546072604
Short name T420
Test name
Test status
Simulation time 1094024195 ps
CPU time 6.66 seconds
Started Feb 09 10:06:44 AM UTC 25
Finished Feb 09 10:06:53 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3546072604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 17.kmac_test_vectors_kmac_xof.3546072604 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_224.1470514888
Short name T559
Test name
Test status
Simulation time 95485092964 ps
CPU time 2755.24 seconds
Started Feb 09 10:03:47 AM UTC 25
Finished Feb 09 10:50:12 AM UTC 25
Peak memory 3198972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470514888 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1470514888 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_256.2133642730
Short name T564
Test name
Test status
Simulation time 190438800235 ps
CPU time 2816.71 seconds
Started Feb 09 10:03:55 AM UTC 25
Finished Feb 09 10:51:23 AM UTC 25
Peak memory 3067820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133642730 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.2133642730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_384.1143641832
Short name T479
Test name
Test status
Simulation time 56774429825 ps
CPU time 1276.51 seconds
Started Feb 09 10:05:23 AM UTC 25
Finished Feb 09 10:26:54 AM UTC 25
Peak memory 931780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143641832 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1143641832 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_512.3036827308
Short name T472
Test name
Test status
Simulation time 39622285911 ps
CPU time 1060.53 seconds
Started Feb 09 10:06:00 AM UTC 25
Finished Feb 09 10:23:54 AM UTC 25
Peak memory 712616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036827308 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.3036827308 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_shake_128.1014505580
Short name T678
Test name
Test status
Simulation time 204602777638 ps
CPU time 5152.51 seconds
Started Feb 09 10:06:04 AM UTC 25
Finished Feb 09 11:32:52 AM UTC 25
Peak memory 2725936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014505580 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.1014505580 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/17.kmac_test_vectors_shake_256.947200486
Short name T712
Test name
Test status
Simulation time 763436059311 ps
CPU time 5879.31 seconds
Started Feb 09 10:06:25 AM UTC 25
Finished Feb 09 11:45:24 AM UTC 25
Peak memory 6401980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947200486 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.947200486 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.1849372126
Short name T448
Test name
Test status
Simulation time 64557059 ps
CPU time 1.25 seconds
Started Feb 09 10:12:10 AM UTC 25
Finished Feb 09 10:12:13 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849372126 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1849372126 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.204319817
Short name T445
Test name
Test status
Simulation time 2820207583 ps
CPU time 34.9 seconds
Started Feb 09 10:11:32 AM UTC 25
Finished Feb 09 10:12:08 AM UTC 25
Peak memory 237580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204319817 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.204319817 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.2579142454
Short name T465
Test name
Test status
Simulation time 26051262102 ps
CPU time 623.94 seconds
Started Feb 09 10:08:52 AM UTC 25
Finished Feb 09 10:19:24 AM UTC 25
Peak memory 249936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579142454 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2579142454 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.818798235
Short name T449
Test name
Test status
Simulation time 237627220 ps
CPU time 21.86 seconds
Started Feb 09 10:11:59 AM UTC 25
Finished Feb 09 10:12:22 AM UTC 25
Peak memory 232596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818798235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.818798235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.3018365899
Short name T444
Test name
Test status
Simulation time 166527509 ps
CPU time 4.79 seconds
Started Feb 09 10:11:59 AM UTC 25
Finished Feb 09 10:12:05 AM UTC 25
Peak memory 228620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018365899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3018365899 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.3554954920
Short name T146
Test name
Test status
Simulation time 6347518888 ps
CPU time 274.57 seconds
Started Feb 09 10:11:35 AM UTC 25
Finished Feb 09 10:16:14 AM UTC 25
Peak memory 321600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554954920 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3554954920 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.1491179683
Short name T442
Test name
Test status
Simulation time 158220147 ps
CPU time 14.48 seconds
Started Feb 09 10:11:42 AM UTC 25
Finished Feb 09 10:11:58 AM UTC 25
Peak memory 247744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491179683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.kmac_error.1491179683 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.2804318033
Short name T443
Test name
Test status
Simulation time 651381799 ps
CPU time 7.25 seconds
Started Feb 09 10:11:50 AM UTC 25
Finished Feb 09 10:11:58 AM UTC 25
Peak memory 230588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804318033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2804318033 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.3235157837
Short name T91
Test name
Test status
Simulation time 190911332 ps
CPU time 2.73 seconds
Started Feb 09 10:12:06 AM UTC 25
Finished Feb 09 10:12:10 AM UTC 25
Peak memory 235152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235157837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3235157837 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.2186088981
Short name T604
Test name
Test status
Simulation time 435111113790 ps
CPU time 3320.13 seconds
Started Feb 09 10:08:32 AM UTC 25
Finished Feb 09 11:04:25 AM UTC 25
Peak memory 4284492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186088981 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.2186088981 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.3023430923
Short name T452
Test name
Test status
Simulation time 7694324214 ps
CPU time 295.24 seconds
Started Feb 09 10:08:37 AM UTC 25
Finished Feb 09 10:13:36 AM UTC 25
Peak memory 440344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023430923 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3023430923 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2419291537
Short name T429
Test name
Test status
Simulation time 6591216392 ps
CPU time 49.34 seconds
Started Feb 09 10:07:59 AM UTC 25
Finished Feb 09 10:08:50 AM UTC 25
Peak memory 230792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419291537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.kmac_smoke.2419291537 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.1884071782
Short name T471
Test name
Test status
Simulation time 7481690672 ps
CPU time 682.89 seconds
Started Feb 09 10:12:09 AM UTC 25
Finished Feb 09 10:23:41 AM UTC 25
Peak memory 551320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884071782 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1884071782 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_kmac.1257069711
Short name T437
Test name
Test status
Simulation time 384448959 ps
CPU time 5.01 seconds
Started Feb 09 10:11:17 AM UTC 25
Finished Feb 09 10:11:24 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1257069711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.kmac_test_vectors_kmac.1257069711 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_kmac_xof.3298711301
Short name T439
Test name
Test status
Simulation time 706169058 ps
CPU time 7.81 seconds
Started Feb 09 10:11:25 AM UTC 25
Finished Feb 09 10:11:34 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3298711301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.kmac_test_vectors_kmac_xof.3298711301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_224.680317680
Short name T516
Test name
Test status
Simulation time 38911271772 ps
CPU time 1635.95 seconds
Started Feb 09 10:09:23 AM UTC 25
Finished Feb 09 10:36:57 AM UTC 25
Peak memory 1198144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680317680 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.680317680 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_256.1412589191
Short name T587
Test name
Test status
Simulation time 93984764737 ps
CPU time 2947.19 seconds
Started Feb 09 10:09:59 AM UTC 25
Finished Feb 09 10:59:38 AM UTC 25
Peak memory 3092528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412589191 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1412589191 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_384.3108624409
Short name T493
Test name
Test status
Simulation time 14161881076 ps
CPU time 1178.79 seconds
Started Feb 09 10:09:59 AM UTC 25
Finished Feb 09 10:29:51 AM UTC 25
Peak memory 919488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108624409 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3108624409 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_512.3851248419
Short name T496
Test name
Test status
Simulation time 43857957273 ps
CPU time 1176.02 seconds
Started Feb 09 10:10:14 AM UTC 25
Finished Feb 09 10:30:04 AM UTC 25
Peak memory 1746880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851248419 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.3851248419 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_shake_128.806298576
Short name T803
Test name
Test status
Simulation time 171901202812 ps
CPU time 7309.11 seconds
Started Feb 09 10:10:31 AM UTC 25
Finished Feb 09 12:13:36 PM UTC 25
Peak memory 7852040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806298576 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.806298576 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/18.kmac_test_vectors_shake_256.532668949
Short name T780
Test name
Test status
Simulation time 614308495523 ps
CPU time 6921.54 seconds
Started Feb 09 10:10:36 AM UTC 25
Finished Feb 09 12:07:11 PM UTC 25
Peak memory 6510532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532668949 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.532668949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.1637812542
Short name T466
Test name
Test status
Simulation time 27895963 ps
CPU time 1.3 seconds
Started Feb 09 10:19:22 AM UTC 25
Finished Feb 09 10:19:24 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637812542 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1637812542 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.2076520534
Short name T459
Test name
Test status
Simulation time 4548147917 ps
CPU time 46.3 seconds
Started Feb 09 10:17:06 AM UTC 25
Finished Feb 09 10:17:54 AM UTC 25
Peak memory 266252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076520534 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2076520534 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.1782432922
Short name T460
Test name
Test status
Simulation time 4111942506 ps
CPU time 345.08 seconds
Started Feb 09 10:12:24 AM UTC 25
Finished Feb 09 10:18:13 AM UTC 25
Peak memory 245768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782432922 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1782432922 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.581690027
Short name T462
Test name
Test status
Simulation time 41242005 ps
CPU time 3.83 seconds
Started Feb 09 10:18:25 AM UTC 25
Finished Feb 09 10:18:30 AM UTC 25
Peak memory 230540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581690027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.581690027 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2880872264
Short name T464
Test name
Test status
Simulation time 480840213 ps
CPU time 40.77 seconds
Started Feb 09 10:18:32 AM UTC 25
Finished Feb 09 10:19:14 AM UTC 25
Peak memory 242832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880872264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2880872264 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.930778966
Short name T463
Test name
Test status
Simulation time 7133207249 ps
CPU time 75.59 seconds
Started Feb 09 10:17:51 AM UTC 25
Finished Feb 09 10:19:09 AM UTC 25
Peak memory 254032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930778966 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.930778966 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.488766676
Short name T474
Test name
Test status
Simulation time 51343709675 ps
CPU time 382.56 seconds
Started Feb 09 10:17:54 AM UTC 25
Finished Feb 09 10:24:22 AM UTC 25
Peak memory 569344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488766676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.kmac_error.488766676 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.1957937055
Short name T461
Test name
Test status
Simulation time 1645972930 ps
CPU time 8.63 seconds
Started Feb 09 10:18:14 AM UTC 25
Finished Feb 09 10:18:24 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957937055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1957937055 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.96850660
Short name T92
Test name
Test status
Simulation time 590889641 ps
CPU time 9.95 seconds
Started Feb 09 10:19:10 AM UTC 25
Finished Feb 09 10:19:21 AM UTC 25
Peak memory 240972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96850660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.96850660 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1841494150
Short name T499
Test name
Test status
Simulation time 36219259054 ps
CPU time 1080.23 seconds
Started Feb 09 10:12:11 AM UTC 25
Finished Feb 09 10:30:25 AM UTC 25
Peak memory 776180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841494150 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1841494150 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.3172726801
Short name T450
Test name
Test status
Simulation time 592707929 ps
CPU time 60.48 seconds
Started Feb 09 10:12:14 AM UTC 25
Finished Feb 09 10:13:16 AM UTC 25
Peak memory 249812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172726801 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3172726801 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.3244359232
Short name T451
Test name
Test status
Simulation time 2238472824 ps
CPU time 63.3 seconds
Started Feb 09 10:12:11 AM UTC 25
Finished Feb 09 10:13:17 AM UTC 25
Peak memory 235520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244359232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.kmac_smoke.3244359232 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.1377486814
Short name T489
Test name
Test status
Simulation time 28651999259 ps
CPU time 568.52 seconds
Started Feb 09 10:19:15 AM UTC 25
Finished Feb 09 10:28:50 AM UTC 25
Peak memory 403472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377486814 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1377486814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_kmac.3363192245
Short name T456
Test name
Test status
Simulation time 71131423 ps
CPU time 5.8 seconds
Started Feb 09 10:16:49 AM UTC 25
Finished Feb 09 10:16:56 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3363192245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.kmac_test_vectors_kmac.3363192245 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_kmac_xof.619009979
Short name T457
Test name
Test status
Simulation time 501601272 ps
CPU time 7.18 seconds
Started Feb 09 10:16:57 AM UTC 25
Finished Feb 09 10:17:05 AM UTC 25
Peak memory 230872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=619009979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac_xof.619009979 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_224.3381040383
Short name T534
Test name
Test status
Simulation time 212374522891 ps
CPU time 1780.46 seconds
Started Feb 09 10:13:17 AM UTC 25
Finished Feb 09 10:43:17 AM UTC 25
Peak memory 1226668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381040383 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3381040383 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_256.808601547
Short name T531
Test name
Test status
Simulation time 61056028137 ps
CPU time 1732.91 seconds
Started Feb 09 10:13:18 AM UTC 25
Finished Feb 09 10:42:31 AM UTC 25
Peak memory 1146812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808601547 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.808601547 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_384.2564680125
Short name T555
Test name
Test status
Simulation time 287280373739 ps
CPU time 2122.47 seconds
Started Feb 09 10:13:37 AM UTC 25
Finished Feb 09 10:49:22 AM UTC 25
Peak memory 2459576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564680125 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2564680125 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_512.1425530443
Short name T494
Test name
Test status
Simulation time 10632900853 ps
CPU time 934.51 seconds
Started Feb 09 10:14:07 AM UTC 25
Finished Feb 09 10:29:53 AM UTC 25
Peak memory 708604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425530443 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.1425530443 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_shake_128.98427851
Short name T844
Test name
Test status
Simulation time 357833491860 ps
CPU time 8045.42 seconds
Started Feb 09 10:14:10 AM UTC 25
Finished Feb 09 12:29:40 PM UTC 25
Peak memory 7852068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98427851 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.98427851 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/19.kmac_test_vectors_shake_256.1163475077
Short name T731
Test name
Test status
Simulation time 193697802496 ps
CPU time 5733.87 seconds
Started Feb 09 10:16:15 AM UTC 25
Finished Feb 09 11:52:47 AM UTC 25
Peak memory 6330300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163475077 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1163475077 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.3433139603
Short name T53
Test name
Test status
Simulation time 18018913 ps
CPU time 1.16 seconds
Started Feb 09 08:41:45 AM UTC 25
Finished Feb 09 08:41:48 AM UTC 25
Peak memory 214468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433139603 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3433139603 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.2919507040
Short name T169
Test name
Test status
Simulation time 3419505510 ps
CPU time 165.85 seconds
Started Feb 09 08:40:13 AM UTC 25
Finished Feb 09 08:43:02 AM UTC 25
Peak memory 294932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919507040 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2919507040 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.2995581773
Short name T105
Test name
Test status
Simulation time 19118994386 ps
CPU time 108.3 seconds
Started Feb 09 08:40:16 AM UTC 25
Finished Feb 09 08:42:06 AM UTC 25
Peak memory 311376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995581773 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2995581773 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.995221424
Short name T136
Test name
Test status
Simulation time 19826706386 ps
CPU time 243.42 seconds
Started Feb 09 08:39:11 AM UTC 25
Finished Feb 09 08:43:18 AM UTC 25
Peak memory 239632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995221424 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.995221424 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2695470397
Short name T83
Test name
Test status
Simulation time 266122587 ps
CPU time 3.15 seconds
Started Feb 09 08:40:58 AM UTC 25
Finished Feb 09 08:41:03 AM UTC 25
Peak memory 228496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695470397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2695470397 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.4208109641
Short name T85
Test name
Test status
Simulation time 1287622942 ps
CPU time 24.44 seconds
Started Feb 09 08:41:01 AM UTC 25
Finished Feb 09 08:41:27 AM UTC 25
Peak memory 228492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208109641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.4208109641 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.2246860015
Short name T51
Test name
Test status
Simulation time 6367721466 ps
CPU time 84.81 seconds
Started Feb 09 08:41:03 AM UTC 25
Finished Feb 09 08:42:31 AM UTC 25
Peak memory 230780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246860015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2246860015 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1322649222
Short name T104
Test name
Test status
Simulation time 14628242656 ps
CPU time 149.16 seconds
Started Feb 09 08:40:17 AM UTC 25
Finished Feb 09 08:42:49 AM UTC 25
Peak memory 284652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322649222 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1322649222 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.1448462857
Short name T49
Test name
Test status
Simulation time 4625396012 ps
CPU time 159.46 seconds
Started Feb 09 08:40:29 AM UTC 25
Finished Feb 09 08:43:12 AM UTC 25
Peak memory 311300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448462857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.kmac_error.1448462857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.1085576329
Short name T20
Test name
Test status
Simulation time 6109301635 ps
CPU time 4.13 seconds
Started Feb 09 08:40:56 AM UTC 25
Finished Feb 09 08:41:01 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085576329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1085576329 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.1268588445
Short name T181
Test name
Test status
Simulation time 5822273226 ps
CPU time 285.01 seconds
Started Feb 09 08:39:05 AM UTC 25
Finished Feb 09 08:43:55 AM UTC 25
Peak memory 415892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268588445 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.1268588445 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.1446591408
Short name T35
Test name
Test status
Simulation time 7347411551 ps
CPU time 109.65 seconds
Started Feb 09 08:40:17 AM UTC 25
Finished Feb 09 08:42:09 AM UTC 25
Peak memory 268676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446591408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.kmac_mubi.1446591408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.1704441236
Short name T11
Test name
Test status
Simulation time 15042934285 ps
CPU time 78.32 seconds
Started Feb 09 08:41:45 AM UTC 25
Finished Feb 09 08:43:06 AM UTC 25
Peak memory 267504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704441236 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1704441236 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.3972178554
Short name T31
Test name
Test status
Simulation time 60103750136 ps
CPU time 331.74 seconds
Started Feb 09 08:39:09 AM UTC 25
Finished Feb 09 08:44:46 AM UTC 25
Peak memory 514064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972178554 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3972178554 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.1162286135
Short name T86
Test name
Test status
Simulation time 108476013 ps
CPU time 8.37 seconds
Started Feb 09 08:39:04 AM UTC 25
Finished Feb 09 08:39:14 AM UTC 25
Peak memory 232768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162286135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.kmac_smoke.1162286135 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.1544243611
Short name T262
Test name
Test status
Simulation time 162771228095 ps
CPU time 2087.11 seconds
Started Feb 09 08:41:28 AM UTC 25
Finished Feb 09 09:16:39 AM UTC 25
Peak memory 1300888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544243611 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1544243611 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.373369780
Short name T81
Test name
Test status
Simulation time 256991432 ps
CPU time 6.08 seconds
Started Feb 09 08:40:04 AM UTC 25
Finished Feb 09 08:40:11 AM UTC 25
Peak memory 230848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=373369780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.kmac_test_vectors_kmac.373369780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.386061512
Short name T82
Test name
Test status
Simulation time 71445302 ps
CPU time 4.34 seconds
Started Feb 09 08:40:09 AM UTC 25
Finished Feb 09 08:40:15 AM UTC 25
Peak memory 230804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=386061512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac_xof.386061512 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.1401029394
Short name T238
Test name
Test status
Simulation time 20152434754 ps
CPU time 1796.87 seconds
Started Feb 09 08:39:15 AM UTC 25
Finished Feb 09 09:09:32 AM UTC 25
Peak memory 1241028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401029394 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1401029394 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3589801030
Short name T281
Test name
Test status
Simulation time 164562601934 ps
CPU time 2431.04 seconds
Started Feb 09 08:39:24 AM UTC 25
Finished Feb 09 09:20:20 AM UTC 25
Peak memory 2983872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589801030 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3589801030 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3823085148
Short name T251
Test name
Test status
Simulation time 183979106646 ps
CPU time 2065.92 seconds
Started Feb 09 08:39:28 AM UTC 25
Finished Feb 09 09:14:18 AM UTC 25
Peak memory 2357252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823085148 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3823085148 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.1768336354
Short name T200
Test name
Test status
Simulation time 37701512935 ps
CPU time 795.37 seconds
Started Feb 09 08:39:45 AM UTC 25
Finished Feb 09 08:53:09 AM UTC 25
Peak memory 681920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768336354 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1768336354 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.2553046036
Short name T549
Test name
Test status
Simulation time 1531613564291 ps
CPU time 7516.45 seconds
Started Feb 09 08:39:46 AM UTC 25
Finished Feb 09 10:46:22 AM UTC 25
Peak memory 7682136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553046036 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2553046036 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2442281833
Short name T371
Test name
Test status
Simulation time 44599518474 ps
CPU time 4137.78 seconds
Started Feb 09 08:39:53 AM UTC 25
Finished Feb 09 09:49:35 AM UTC 25
Peak memory 2262976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442281833 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2442281833 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.2587552723
Short name T484
Test name
Test status
Simulation time 16388632 ps
CPU time 1.17 seconds
Started Feb 09 10:27:24 AM UTC 25
Finished Feb 09 10:27:26 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587552723 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2587552723 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.4091610963
Short name T487
Test name
Test status
Simulation time 9783991931 ps
CPU time 184.45 seconds
Started Feb 09 10:25:33 AM UTC 25
Finished Feb 09 10:28:41 AM UTC 25
Peak memory 350332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091610963 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.4091610963 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.1913962949
Short name T476
Test name
Test status
Simulation time 4825120960 ps
CPU time 285.75 seconds
Started Feb 09 10:20:38 AM UTC 25
Finished Feb 09 10:25:29 AM UTC 25
Peak memory 239628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913962949 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1913962949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.4004386734
Short name T491
Test name
Test status
Simulation time 49663216529 ps
CPU time 243.55 seconds
Started Feb 09 10:25:37 AM UTC 25
Finished Feb 09 10:29:44 AM UTC 25
Peak memory 417844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004386734 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4004386734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.1547222112
Short name T486
Test name
Test status
Simulation time 1215328085 ps
CPU time 95.5 seconds
Started Feb 09 10:26:55 AM UTC 25
Finished Feb 09 10:28:33 AM UTC 25
Peak memory 284612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547222112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.kmac_error.1547222112 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.516362153
Short name T481
Test name
Test status
Simulation time 600782612 ps
CPU time 4.04 seconds
Started Feb 09 10:27:08 AM UTC 25
Finished Feb 09 10:27:13 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516362153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.516362153 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.3659542883
Short name T482
Test name
Test status
Simulation time 162452664 ps
CPU time 1.49 seconds
Started Feb 09 10:27:14 AM UTC 25
Finished Feb 09 10:27:17 AM UTC 25
Peak memory 229876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659542883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3659542883 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2155651780
Short name T524
Test name
Test status
Simulation time 11650808259 ps
CPU time 1192.19 seconds
Started Feb 09 10:19:25 AM UTC 25
Finished Feb 09 10:39:31 AM UTC 25
Peak memory 897032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155651780 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2155651780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.600617164
Short name T470
Test name
Test status
Simulation time 6792799467 ps
CPU time 147.76 seconds
Started Feb 09 10:20:05 AM UTC 25
Finished Feb 09 10:22:36 AM UTC 25
Peak memory 292876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600617164 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.600617164 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.4209211478
Short name T468
Test name
Test status
Simulation time 16439404266 ps
CPU time 70.36 seconds
Started Feb 09 10:19:25 AM UTC 25
Finished Feb 09 10:20:37 AM UTC 25
Peak memory 232844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209211478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.kmac_smoke.4209211478 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.3414796953
Short name T504
Test name
Test status
Simulation time 41121720582 ps
CPU time 213.25 seconds
Started Feb 09 10:27:17 AM UTC 25
Finished Feb 09 10:30:54 AM UTC 25
Peak memory 317460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414796953 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3414796953 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_kmac.4268522947
Short name T477
Test name
Test status
Simulation time 1075894219 ps
CPU time 6.99 seconds
Started Feb 09 10:25:24 AM UTC 25
Finished Feb 09 10:25:33 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4268522947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.kmac_test_vectors_kmac.4268522947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_kmac_xof.400840334
Short name T478
Test name
Test status
Simulation time 248971074 ps
CPU time 5.14 seconds
Started Feb 09 10:25:29 AM UTC 25
Finished Feb 09 10:25:36 AM UTC 25
Peak memory 230804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=400840334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac_xof.400840334 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_224.865832686
Short name T575
Test name
Test status
Simulation time 68339459145 ps
CPU time 1948.58 seconds
Started Feb 09 10:22:24 AM UTC 25
Finished Feb 09 10:55:15 AM UTC 25
Peak memory 1183680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865832686 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.865832686 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_256.188600619
Short name T589
Test name
Test status
Simulation time 98168857097 ps
CPU time 2256.8 seconds
Started Feb 09 10:22:37 AM UTC 25
Finished Feb 09 11:00:37 AM UTC 25
Peak memory 3129276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188600619 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.188600619 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_384.285686493
Short name T544
Test name
Test status
Simulation time 36690605711 ps
CPU time 1287.22 seconds
Started Feb 09 10:23:42 AM UTC 25
Finished Feb 09 10:45:24 AM UTC 25
Peak memory 927744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285686493 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.285686493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_512.1507641073
Short name T533
Test name
Test status
Simulation time 9914373875 ps
CPU time 1146.13 seconds
Started Feb 09 10:23:54 AM UTC 25
Finished Feb 09 10:43:14 AM UTC 25
Peak memory 737256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507641073 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1507641073 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_shake_128.70338032
Short name T714
Test name
Test status
Simulation time 193131827620 ps
CPU time 4883.93 seconds
Started Feb 09 10:24:10 AM UTC 25
Finished Feb 09 11:46:25 AM UTC 25
Peak memory 2664416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70338032 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.70338032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/20.kmac_test_vectors_shake_256.3939332587
Short name T816
Test name
Test status
Simulation time 451968221593 ps
CPU time 6682.33 seconds
Started Feb 09 10:24:23 AM UTC 25
Finished Feb 09 12:16:55 PM UTC 25
Peak memory 6432764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939332587 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3939332587 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.3976129121
Short name T503
Test name
Test status
Simulation time 65487375 ps
CPU time 1.2 seconds
Started Feb 09 10:30:51 AM UTC 25
Finished Feb 09 10:30:53 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976129121 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3976129121 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.2826589047
Short name T506
Test name
Test status
Simulation time 3552252896 ps
CPU time 88.26 seconds
Started Feb 09 10:30:04 AM UTC 25
Finished Feb 09 10:31:35 AM UTC 25
Peak memory 315448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826589047 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2826589047 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.1051998515
Short name T492
Test name
Test status
Simulation time 17444768419 ps
CPU time 60.95 seconds
Started Feb 09 10:28:42 AM UTC 25
Finished Feb 09 10:29:45 AM UTC 25
Peak memory 232848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051998515 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1051998515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.3511726474
Short name T511
Test name
Test status
Simulation time 25084176798 ps
CPU time 253.19 seconds
Started Feb 09 10:30:11 AM UTC 25
Finished Feb 09 10:34:28 AM UTC 25
Peak memory 319496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511726474 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3511726474 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.2519248451
Short name T518
Test name
Test status
Simulation time 56685737170 ps
CPU time 470.88 seconds
Started Feb 09 10:30:19 AM UTC 25
Finished Feb 09 10:38:16 AM UTC 25
Peak memory 620552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519248451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.kmac_error.2519248451 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.272761123
Short name T500
Test name
Test status
Simulation time 419999720 ps
CPU time 4.85 seconds
Started Feb 09 10:30:26 AM UTC 25
Finished Feb 09 10:30:33 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272761123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.272761123 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.346490408
Short name T502
Test name
Test status
Simulation time 2145583306 ps
CPU time 15.58 seconds
Started Feb 09 10:30:34 AM UTC 25
Finished Feb 09 10:30:51 AM UTC 25
Peak memory 245072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346490408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.346490408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3645422990
Short name T529
Test name
Test status
Simulation time 25327435509 ps
CPU time 837.89 seconds
Started Feb 09 10:27:56 AM UTC 25
Finished Feb 09 10:42:03 AM UTC 25
Peak memory 831500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645422990 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.3645422990 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.1544045222
Short name T498
Test name
Test status
Simulation time 11773176673 ps
CPU time 101.92 seconds
Started Feb 09 10:28:34 AM UTC 25
Finished Feb 09 10:30:19 AM UTC 25
Peak memory 290836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544045222 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1544045222 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.2774123396
Short name T485
Test name
Test status
Simulation time 1852479572 ps
CPU time 27.22 seconds
Started Feb 09 10:27:27 AM UTC 25
Finished Feb 09 10:27:55 AM UTC 25
Peak memory 230732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774123396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.kmac_smoke.2774123396 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.833172461
Short name T561
Test name
Test status
Simulation time 55372562592 ps
CPU time 1155.95 seconds
Started Feb 09 10:30:50 AM UTC 25
Finished Feb 09 10:50:20 AM UTC 25
Peak memory 907672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833172461 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.833172461 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_kmac.340672229
Short name T495
Test name
Test status
Simulation time 577511138 ps
CPU time 6.61 seconds
Started Feb 09 10:29:54 AM UTC 25
Finished Feb 09 10:30:02 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=340672229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.kmac_test_vectors_kmac.340672229 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_kmac_xof.2597056533
Short name T497
Test name
Test status
Simulation time 654476642 ps
CPU time 6.16 seconds
Started Feb 09 10:30:03 AM UTC 25
Finished Feb 09 10:30:11 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2597056533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 21.kmac_test_vectors_kmac_xof.2597056533 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_224.2437725149
Short name T635
Test name
Test status
Simulation time 118153241386 ps
CPU time 2777.77 seconds
Started Feb 09 10:28:46 AM UTC 25
Finished Feb 09 11:15:36 AM UTC 25
Peak memory 3252284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437725149 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2437725149 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_256.1962242310
Short name T652
Test name
Test status
Simulation time 207568812970 ps
CPU time 3037.72 seconds
Started Feb 09 10:28:51 AM UTC 25
Finished Feb 09 11:20:03 AM UTC 25
Peak memory 3063856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962242310 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.1962242310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_384.389592906
Short name T596
Test name
Test status
Simulation time 247193962476 ps
CPU time 1877.39 seconds
Started Feb 09 10:29:41 AM UTC 25
Finished Feb 09 11:01:19 AM UTC 25
Peak memory 2342964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389592906 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.389592906 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_512.3471431708
Short name T547
Test name
Test status
Simulation time 9945850627 ps
CPU time 954.51 seconds
Started Feb 09 10:29:45 AM UTC 25
Finished Feb 09 10:45:51 AM UTC 25
Peak memory 720812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471431708 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3471431708 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/21.kmac_test_vectors_shake_256.1508210779
Short name T820
Test name
Test status
Simulation time 1829282245946 ps
CPU time 6497.9 seconds
Started Feb 09 10:29:52 AM UTC 25
Finished Feb 09 12:19:20 PM UTC 25
Peak memory 6469568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508210779 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.1508210779 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.2582526607
Short name T522
Test name
Test status
Simulation time 27290660 ps
CPU time 0.97 seconds
Started Feb 09 10:38:38 AM UTC 25
Finished Feb 09 10:38:41 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582526607 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2582526607 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.1371447132
Short name T526
Test name
Test status
Simulation time 65726627467 ps
CPU time 309.04 seconds
Started Feb 09 10:34:51 AM UTC 25
Finished Feb 09 10:40:04 AM UTC 25
Peak memory 516108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371447132 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1371447132 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.2008133849
Short name T554
Test name
Test status
Simulation time 113024238942 ps
CPU time 1047.37 seconds
Started Feb 09 10:31:35 AM UTC 25
Finished Feb 09 10:49:15 AM UTC 25
Peak memory 266256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008133849 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2008133849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.2019845891
Short name T523
Test name
Test status
Simulation time 22294308352 ps
CPU time 138.15 seconds
Started Feb 09 10:36:58 AM UTC 25
Finished Feb 09 10:39:19 AM UTC 25
Peak memory 272396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019845891 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2019845891 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.2541447230
Short name T532
Test name
Test status
Simulation time 90907928868 ps
CPU time 351.39 seconds
Started Feb 09 10:37:14 AM UTC 25
Finished Feb 09 10:43:10 AM UTC 25
Peak memory 532464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541447230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.kmac_error.2541447230 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.838126836
Short name T519
Test name
Test status
Simulation time 1086503155 ps
CPU time 3.37 seconds
Started Feb 09 10:38:17 AM UTC 25
Finished Feb 09 10:38:22 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838126836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.838126836 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.115345329
Short name T520
Test name
Test status
Simulation time 55842370 ps
CPU time 2.19 seconds
Started Feb 09 10:38:22 AM UTC 25
Finished Feb 09 10:38:26 AM UTC 25
Peak memory 230656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115345329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.115345329 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.2919592612
Short name T585
Test name
Test status
Simulation time 16330877397 ps
CPU time 1655.53 seconds
Started Feb 09 10:30:55 AM UTC 25
Finished Feb 09 10:58:49 AM UTC 25
Peak memory 1224708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919592612 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.2919592612 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.3963044717
Short name T510
Test name
Test status
Simulation time 12418818666 ps
CPU time 187.34 seconds
Started Feb 09 10:30:58 AM UTC 25
Finished Feb 09 10:34:09 AM UTC 25
Peak memory 358600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963044717 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3963044717 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.2164821096
Short name T505
Test name
Test status
Simulation time 26737089 ps
CPU time 2.17 seconds
Started Feb 09 10:30:54 AM UTC 25
Finished Feb 09 10:30:57 AM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164821096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.kmac_smoke.2164821096 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.732015410
Short name T521
Test name
Test status
Simulation time 431812151 ps
CPU time 9.73 seconds
Started Feb 09 10:38:26 AM UTC 25
Finished Feb 09 10:38:37 AM UTC 25
Peak memory 234948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732015410 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.732015410 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_kmac.3039487800
Short name T514
Test name
Test status
Simulation time 619283639 ps
CPU time 5.52 seconds
Started Feb 09 10:34:35 AM UTC 25
Finished Feb 09 10:34:42 AM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3039487800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.kmac_test_vectors_kmac.3039487800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_kmac_xof.2387447379
Short name T515
Test name
Test status
Simulation time 236689288 ps
CPU time 5.68 seconds
Started Feb 09 10:34:43 AM UTC 25
Finished Feb 09 10:34:50 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2387447379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.kmac_test_vectors_kmac_xof.2387447379 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_224.1313312873
Short name T601
Test name
Test status
Simulation time 19224331492 ps
CPU time 1812.58 seconds
Started Feb 09 10:32:39 AM UTC 25
Finished Feb 09 11:03:12 AM UTC 25
Peak memory 1183684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313312873 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.1313312873 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_256.4188954282
Short name T626
Test name
Test status
Simulation time 254731861321 ps
CPU time 2457.22 seconds
Started Feb 09 10:32:46 AM UTC 25
Finished Feb 09 11:14:10 AM UTC 25
Peak memory 3069860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188954282 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.4188954282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_384.314959109
Short name T605
Test name
Test status
Simulation time 73094416768 ps
CPU time 1862.22 seconds
Started Feb 09 10:33:10 AM UTC 25
Finished Feb 09 11:04:32 AM UTC 25
Peak memory 2455488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314959109 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.314959109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_512.3061749212
Short name T584
Test name
Test status
Simulation time 35305925967 ps
CPU time 1438.41 seconds
Started Feb 09 10:34:10 AM UTC 25
Finished Feb 09 10:58:26 AM UTC 25
Peak memory 1781828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061749212 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.3061749212 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_shake_128.2875336077
Short name T838
Test name
Test status
Simulation time 708262760483 ps
CPU time 6616.95 seconds
Started Feb 09 10:34:30 AM UTC 25
Finished Feb 09 12:25:51 PM UTC 25
Peak memory 7749556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875336077 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.2875336077 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/22.kmac_test_vectors_shake_256.1667544829
Short name T767
Test name
Test status
Simulation time 619087868100 ps
CPU time 5357.33 seconds
Started Feb 09 10:34:34 AM UTC 25
Finished Feb 09 12:04:43 PM UTC 25
Peak memory 6584308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667544829 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1667544829 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/22.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.3357640129
Short name T541
Test name
Test status
Simulation time 23289820 ps
CPU time 1.31 seconds
Started Feb 09 10:44:45 AM UTC 25
Finished Feb 09 10:44:48 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357640129 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3357640129 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.2577473842
Short name T557
Test name
Test status
Simulation time 15903088345 ps
CPU time 395.79 seconds
Started Feb 09 10:43:19 AM UTC 25
Finished Feb 09 10:50:00 AM UTC 25
Peak memory 593928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577473842 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2577473842 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.3479322614
Short name T530
Test name
Test status
Simulation time 1040069626 ps
CPU time 128.78 seconds
Started Feb 09 10:39:54 AM UTC 25
Finished Feb 09 10:42:05 AM UTC 25
Peak memory 234816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479322614 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3479322614 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.1593764096
Short name T537
Test name
Test status
Simulation time 55655644 ps
CPU time 3.31 seconds
Started Feb 09 10:43:20 AM UTC 25
Finished Feb 09 10:43:24 AM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593764096 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1593764096 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.2691865217
Short name T551
Test name
Test status
Simulation time 5301988797 ps
CPU time 261.1 seconds
Started Feb 09 10:43:21 AM UTC 25
Finished Feb 09 10:47:46 AM UTC 25
Peak memory 333896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691865217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 23.kmac_error.2691865217 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.3830841803
Short name T538
Test name
Test status
Simulation time 216549719 ps
CPU time 2.79 seconds
Started Feb 09 10:43:25 AM UTC 25
Finished Feb 09 10:43:29 AM UTC 25
Peak memory 230708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830841803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.3830841803 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.755404963
Short name T539
Test name
Test status
Simulation time 48741438 ps
CPU time 1.85 seconds
Started Feb 09 10:43:30 AM UTC 25
Finished Feb 09 10:43:33 AM UTC 25
Peak memory 229760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755404963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.755404963 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1545660740
Short name T623
Test name
Test status
Simulation time 116097152871 ps
CPU time 2040.25 seconds
Started Feb 09 10:39:20 AM UTC 25
Finished Feb 09 11:13:42 AM UTC 25
Peak memory 1359888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545660740 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1545660740 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.19808376
Short name T542
Test name
Test status
Simulation time 13624009211 ps
CPU time 315.43 seconds
Started Feb 09 10:39:32 AM UTC 25
Finished Feb 09 10:44:52 AM UTC 25
Peak memory 346180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19808376 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.19808376 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.822687915
Short name T525
Test name
Test status
Simulation time 6154396113 ps
CPU time 69.51 seconds
Started Feb 09 10:38:41 AM UTC 25
Finished Feb 09 10:39:53 AM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822687915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.kmac_smoke.822687915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.3135803714
Short name T582
Test name
Test status
Simulation time 135612210932 ps
CPU time 804.17 seconds
Started Feb 09 10:43:34 AM UTC 25
Finished Feb 09 10:57:08 AM UTC 25
Peak memory 426368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135803714 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3135803714 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_kmac.3749580490
Short name T535
Test name
Test status
Simulation time 692735462 ps
CPU time 6.52 seconds
Started Feb 09 10:43:12 AM UTC 25
Finished Feb 09 10:43:19 AM UTC 25
Peak memory 230784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3749580490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.kmac_test_vectors_kmac.3749580490 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_kmac_xof.3385744004
Short name T536
Test name
Test status
Simulation time 65173370 ps
CPU time 3.78 seconds
Started Feb 09 10:43:15 AM UTC 25
Finished Feb 09 10:43:20 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3385744004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.kmac_test_vectors_kmac_xof.3385744004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_224.1412169343
Short name T645
Test name
Test status
Simulation time 19194769407 ps
CPU time 2268.9 seconds
Started Feb 09 10:40:05 AM UTC 25
Finished Feb 09 11:18:20 AM UTC 25
Peak memory 1232900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412169343 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.1412169343 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_256.344308851
Short name T662
Test name
Test status
Simulation time 189464838123 ps
CPU time 2637.45 seconds
Started Feb 09 10:41:02 AM UTC 25
Finished Feb 09 11:25:28 AM UTC 25
Peak memory 2983872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344308851 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.344308851 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_384.2019563769
Short name T627
Test name
Test status
Simulation time 152848345938 ps
CPU time 1985.08 seconds
Started Feb 09 10:41:02 AM UTC 25
Finished Feb 09 11:14:29 AM UTC 25
Peak memory 2408444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019563769 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2019563769 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_512.1978484816
Short name T580
Test name
Test status
Simulation time 18820113222 ps
CPU time 858.33 seconds
Started Feb 09 10:42:04 AM UTC 25
Finished Feb 09 10:56:33 AM UTC 25
Peak memory 706620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978484816 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1978484816 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_shake_128.1019567799
Short name T769
Test name
Test status
Simulation time 114958448656 ps
CPU time 4924.41 seconds
Started Feb 09 10:42:06 AM UTC 25
Finished Feb 09 12:05:03 PM UTC 25
Peak memory 2688948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019567799 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.1019567799 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/23.kmac_test_vectors_shake_256.3209376573
Short name T850
Test name
Test status
Simulation time 223499320678 ps
CPU time 6437.13 seconds
Started Feb 09 10:42:32 AM UTC 25
Finished Feb 09 12:30:56 PM UTC 25
Peak memory 6344800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209376573 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3209376573 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.3746452705
Short name T560
Test name
Test status
Simulation time 12800472 ps
CPU time 1.14 seconds
Started Feb 09 10:50:13 AM UTC 25
Finished Feb 09 10:50:16 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746452705 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3746452705 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.1566392867
Short name T567
Test name
Test status
Simulation time 12019970885 ps
CPU time 307.29 seconds
Started Feb 09 10:48:04 AM UTC 25
Finished Feb 09 10:53:16 AM UTC 25
Peak memory 497720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566392867 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1566392867 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.2063229163
Short name T550
Test name
Test status
Simulation time 815461018 ps
CPU time 86.54 seconds
Started Feb 09 10:45:24 AM UTC 25
Finished Feb 09 10:46:53 AM UTC 25
Peak memory 232788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063229163 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.2063229163 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1211546394
Short name T573
Test name
Test status
Simulation time 77569796611 ps
CPU time 340.48 seconds
Started Feb 09 10:49:15 AM UTC 25
Finished Feb 09 10:55:01 AM UTC 25
Peak memory 360592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211546394 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1211546394 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.3444064074
Short name T574
Test name
Test status
Simulation time 49590313040 ps
CPU time 335.39 seconds
Started Feb 09 10:49:24 AM UTC 25
Finished Feb 09 10:55:04 AM UTC 25
Peak memory 512008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444064074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.kmac_error.3444064074 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.2976901693
Short name T558
Test name
Test status
Simulation time 4949640807 ps
CPU time 8.78 seconds
Started Feb 09 10:50:01 AM UTC 25
Finished Feb 09 10:50:11 AM UTC 25
Peak memory 230844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976901693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2976901693 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.2099036718
Short name T57
Test name
Test status
Simulation time 1522189271 ps
CPU time 13.2 seconds
Started Feb 09 10:50:01 AM UTC 25
Finished Feb 09 10:50:15 AM UTC 25
Peak memory 249848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099036718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2099036718 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3242797429
Short name T708
Test name
Test status
Simulation time 277259250380 ps
CPU time 3452.17 seconds
Started Feb 09 10:44:53 AM UTC 25
Finished Feb 09 11:43:01 AM UTC 25
Peak memory 3950608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242797429 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3242797429 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.1013174264
Short name T556
Test name
Test status
Simulation time 3778670086 ps
CPU time 279.55 seconds
Started Feb 09 10:45:16 AM UTC 25
Finished Feb 09 10:50:00 AM UTC 25
Peak memory 366680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013174264 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1013174264 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.3305183814
Short name T543
Test name
Test status
Simulation time 5079769487 ps
CPU time 24.93 seconds
Started Feb 09 10:44:49 AM UTC 25
Finished Feb 09 10:45:16 AM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305183814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.kmac_smoke.3305183814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.251854524
Short name T622
Test name
Test status
Simulation time 153238983571 ps
CPU time 1381.75 seconds
Started Feb 09 10:50:12 AM UTC 25
Finished Feb 09 11:13:31 AM UTC 25
Peak memory 948628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251854524 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.251854524 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_kmac.1310538575
Short name T552
Test name
Test status
Simulation time 180767528 ps
CPU time 6.56 seconds
Started Feb 09 10:47:47 AM UTC 25
Finished Feb 09 10:47:55 AM UTC 25
Peak memory 230780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1310538575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.kmac_test_vectors_kmac.1310538575 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_kmac_xof.392320597
Short name T553
Test name
Test status
Simulation time 253492594 ps
CPU time 5.7 seconds
Started Feb 09 10:47:56 AM UTC 25
Finished Feb 09 10:48:03 AM UTC 25
Peak memory 230868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=392320597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac_xof.392320597 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_224.2127173745
Short name T657
Test name
Test status
Simulation time 66627025047 ps
CPU time 2277.8 seconds
Started Feb 09 10:45:29 AM UTC 25
Finished Feb 09 11:23:52 AM UTC 25
Peak memory 3198892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127173745 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2127173745 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_256.2957775868
Short name T618
Test name
Test status
Simulation time 17400954679 ps
CPU time 1529.82 seconds
Started Feb 09 10:45:39 AM UTC 25
Finished Feb 09 11:11:26 AM UTC 25
Peak memory 1126336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957775868 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.2957775868 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_384.2472365626
Short name T637
Test name
Test status
Simulation time 47670987031 ps
CPU time 1788.02 seconds
Started Feb 09 10:45:52 AM UTC 25
Finished Feb 09 11:16:00 AM UTC 25
Peak memory 2369540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472365626 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.2472365626 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_512.2135654201
Short name T610
Test name
Test status
Simulation time 171727589990 ps
CPU time 1296.53 seconds
Started Feb 09 10:46:02 AM UTC 25
Finished Feb 09 11:07:53 AM UTC 25
Peak memory 1691588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135654201 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2135654201 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_shake_128.1648515091
Short name T945
Test name
Test status
Simulation time 610867684147 ps
CPU time 8093.61 seconds
Started Feb 09 10:46:23 AM UTC 25
Finished Feb 09 01:02:45 PM UTC 25
Peak memory 7804964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648515091 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.1648515091 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/24.kmac_test_vectors_shake_256.2679920036
Short name T722
Test name
Test status
Simulation time 89288235384 ps
CPU time 3623.01 seconds
Started Feb 09 10:46:55 AM UTC 25
Finished Feb 09 11:47:54 AM UTC 25
Peak memory 2205684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679920036 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.2679920036 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.2853014262
Short name T578
Test name
Test status
Simulation time 71927305 ps
CPU time 1.17 seconds
Started Feb 09 10:55:31 AM UTC 25
Finished Feb 09 10:55:34 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853014262 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2853014262 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.1018367485
Short name T572
Test name
Test status
Simulation time 916142426 ps
CPU time 23.86 seconds
Started Feb 09 10:54:15 AM UTC 25
Finished Feb 09 10:54:41 AM UTC 25
Peak memory 235424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018367485 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1018367485 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.114756804
Short name T598
Test name
Test status
Simulation time 22140734111 ps
CPU time 677 seconds
Started Feb 09 10:50:23 AM UTC 25
Finished Feb 09 11:01:48 AM UTC 25
Peak memory 260108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114756804 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.114756804 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.1266310765
Short name T588
Test name
Test status
Simulation time 75714755868 ps
CPU time 348.41 seconds
Started Feb 09 10:54:41 AM UTC 25
Finished Feb 09 11:00:35 AM UTC 25
Peak memory 512004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266310765 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1266310765 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.2640906421
Short name T603
Test name
Test status
Simulation time 14444166762 ps
CPU time 518.6 seconds
Started Feb 09 10:55:01 AM UTC 25
Finished Feb 09 11:03:47 AM UTC 25
Peak memory 604172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640906421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 25.kmac_error.2640906421 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.2706941114
Short name T576
Test name
Test status
Simulation time 6227692300 ps
CPU time 11.24 seconds
Started Feb 09 10:55:05 AM UTC 25
Finished Feb 09 10:55:17 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706941114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2706941114 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.3415238297
Short name T577
Test name
Test status
Simulation time 2170528939 ps
CPU time 12.5 seconds
Started Feb 09 10:55:16 AM UTC 25
Finished Feb 09 10:55:30 AM UTC 25
Peak memory 232840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415238297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3415238297 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.838757017
Short name T665
Test name
Test status
Simulation time 41846152242 ps
CPU time 2103.22 seconds
Started Feb 09 10:50:16 AM UTC 25
Finished Feb 09 11:25:43 AM UTC 25
Peak memory 1450060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838757017 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.838757017 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.693611975
Short name T568
Test name
Test status
Simulation time 2660346772 ps
CPU time 184.25 seconds
Started Feb 09 10:50:20 AM UTC 25
Finished Feb 09 10:53:28 AM UTC 25
Peak memory 325640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693611975 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.693611975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.1440065447
Short name T563
Test name
Test status
Simulation time 2126306847 ps
CPU time 12.58 seconds
Started Feb 09 10:50:16 AM UTC 25
Finished Feb 09 10:50:30 AM UTC 25
Peak memory 230772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440065447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 25.kmac_smoke.1440065447 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.2075409060
Short name T617
Test name
Test status
Simulation time 33020855280 ps
CPU time 907.83 seconds
Started Feb 09 10:55:18 AM UTC 25
Finished Feb 09 11:10:37 AM UTC 25
Peak memory 825364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075409060 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2075409060 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_kmac.708625153
Short name T570
Test name
Test status
Simulation time 67047944 ps
CPU time 3.73 seconds
Started Feb 09 10:54:01 AM UTC 25
Finished Feb 09 10:54:06 AM UTC 25
Peak memory 230804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=708625153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.kmac_test_vectors_kmac.708625153 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_kmac_xof.152479206
Short name T571
Test name
Test status
Simulation time 70796351 ps
CPU time 5.44 seconds
Started Feb 09 10:54:07 AM UTC 25
Finished Feb 09 10:54:14 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=152479206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac_xof.152479206 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_224.2081341408
Short name T693
Test name
Test status
Simulation time 434461290974 ps
CPU time 2735.47 seconds
Started Feb 09 10:50:31 AM UTC 25
Finished Feb 09 11:36:36 AM UTC 25
Peak memory 3198916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081341408 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.2081341408 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_256.2309638730
Short name T677
Test name
Test status
Simulation time 128957193693 ps
CPU time 2400.1 seconds
Started Feb 09 10:51:24 AM UTC 25
Finished Feb 09 11:31:51 AM UTC 25
Peak memory 3106756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309638730 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.2309638730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_384.1815702663
Short name T656
Test name
Test status
Simulation time 71227879423 ps
CPU time 1832.81 seconds
Started Feb 09 10:52:29 AM UTC 25
Finished Feb 09 11:23:22 AM UTC 25
Peak memory 2414528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815702663 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.1815702663 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_512.3532790514
Short name T630
Test name
Test status
Simulation time 277548484816 ps
CPU time 1291.05 seconds
Started Feb 09 10:53:10 AM UTC 25
Finished Feb 09 11:14:56 AM UTC 25
Peak memory 1710136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532790514 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.3532790514 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_shake_128.185260041
Short name T787
Test name
Test status
Simulation time 106332764984 ps
CPU time 4560.36 seconds
Started Feb 09 10:53:17 AM UTC 25
Finished Feb 09 12:10:04 PM UTC 25
Peak memory 2717684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185260041 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.185260041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/25.kmac_test_vectors_shake_256.4255682205
Short name T779
Test name
Test status
Simulation time 432452047070 ps
CPU time 4365.05 seconds
Started Feb 09 10:53:28 AM UTC 25
Finished Feb 09 12:07:02 PM UTC 25
Peak memory 2234296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255682205 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.4255682205 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.3760110837
Short name T597
Test name
Test status
Simulation time 28541021 ps
CPU time 1.2 seconds
Started Feb 09 11:01:19 AM UTC 25
Finished Feb 09 11:01:22 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760110837 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3760110837 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.2721460823
Short name T158
Test name
Test status
Simulation time 12968202030 ps
CPU time 656.59 seconds
Started Feb 09 10:56:40 AM UTC 25
Finished Feb 09 11:07:45 AM UTC 25
Peak memory 249864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721460823 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2721460823 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2933878294
Short name T592
Test name
Test status
Simulation time 4799129818 ps
CPU time 20.2 seconds
Started Feb 09 11:00:46 AM UTC 25
Finished Feb 09 11:01:08 AM UTC 25
Peak memory 235532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933878294 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2933878294 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.407213885
Short name T600
Test name
Test status
Simulation time 3727576576 ps
CPU time 94.77 seconds
Started Feb 09 11:01:07 AM UTC 25
Finished Feb 09 11:02:44 AM UTC 25
Peak memory 333828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407213885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.kmac_error.407213885 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.2973035030
Short name T593
Test name
Test status
Simulation time 131128613 ps
CPU time 2.35 seconds
Started Feb 09 11:01:09 AM UTC 25
Finished Feb 09 11:01:13 AM UTC 25
Peak memory 230644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973035030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2973035030 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.3065943195
Short name T594
Test name
Test status
Simulation time 244671466 ps
CPU time 1.85 seconds
Started Feb 09 11:01:14 AM UTC 25
Finished Feb 09 11:01:17 AM UTC 25
Peak memory 234672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065943195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3065943195 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.1721804122
Short name T586
Test name
Test status
Simulation time 17532976157 ps
CPU time 181.97 seconds
Started Feb 09 10:55:44 AM UTC 25
Finished Feb 09 10:58:50 AM UTC 25
Peak memory 442372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721804122 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.1721804122 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.2039314976
Short name T583
Test name
Test status
Simulation time 2892840138 ps
CPU time 104.78 seconds
Started Feb 09 10:56:34 AM UTC 25
Finished Feb 09 10:58:21 AM UTC 25
Peak memory 282644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039314976 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2039314976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.3671855577
Short name T581
Test name
Test status
Simulation time 10722704986 ps
CPU time 62.8 seconds
Started Feb 09 10:55:34 AM UTC 25
Finished Feb 09 10:56:39 AM UTC 25
Peak memory 232840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671855577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.kmac_smoke.3671855577 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.3852070844
Short name T669
Test name
Test status
Simulation time 343210811457 ps
CPU time 1530.08 seconds
Started Feb 09 11:01:18 AM UTC 25
Finished Feb 09 11:27:06 AM UTC 25
Peak memory 1022492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852070844 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3852070844 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_kmac.2834331419
Short name T590
Test name
Test status
Simulation time 129110732 ps
CPU time 4.01 seconds
Started Feb 09 11:00:36 AM UTC 25
Finished Feb 09 11:00:41 AM UTC 25
Peak memory 230784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2834331419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.kmac_test_vectors_kmac.2834331419 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_kmac_xof.887191561
Short name T591
Test name
Test status
Simulation time 214305167 ps
CPU time 6.56 seconds
Started Feb 09 11:00:37 AM UTC 25
Finished Feb 09 11:00:46 AM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=887191561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac_xof.887191561 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_224.783712267
Short name T689
Test name
Test status
Simulation time 261489122353 ps
CPU time 2260.84 seconds
Started Feb 09 10:57:09 AM UTC 25
Finished Feb 09 11:35:14 AM UTC 25
Peak memory 3270584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783712267 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.783712267 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_256.1885354891
Short name T675
Test name
Test status
Simulation time 70556576606 ps
CPU time 1962.42 seconds
Started Feb 09 10:58:23 AM UTC 25
Finished Feb 09 11:31:29 AM UTC 25
Peak memory 1142788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885354891 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1885354891 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_384.422907261
Short name T674
Test name
Test status
Simulation time 98062513318 ps
CPU time 1857.45 seconds
Started Feb 09 10:58:27 AM UTC 25
Finished Feb 09 11:29:46 AM UTC 25
Peak memory 2414528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422907261 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.422907261 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_512.1939134367
Short name T641
Test name
Test status
Simulation time 271235026217 ps
CPU time 1095.43 seconds
Started Feb 09 10:58:50 AM UTC 25
Finished Feb 09 11:17:18 AM UTC 25
Peak memory 1734596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939134367 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1939134367 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_shake_128.2024621853
Short name T840
Test name
Test status
Simulation time 52541784394 ps
CPU time 5249.41 seconds
Started Feb 09 10:58:50 AM UTC 25
Finished Feb 09 12:27:17 PM UTC 25
Peak memory 2678708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024621853 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2024621853 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/26.kmac_test_vectors_shake_256.4062196158
Short name T784
Test name
Test status
Simulation time 179122245701 ps
CPU time 4087.63 seconds
Started Feb 09 10:59:40 AM UTC 25
Finished Feb 09 12:08:32 PM UTC 25
Peak memory 2213824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062196158 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.4062196158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.1321391520
Short name T613
Test name
Test status
Simulation time 16150244 ps
CPU time 1.26 seconds
Started Feb 09 11:08:20 AM UTC 25
Finished Feb 09 11:08:22 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321391520 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1321391520 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.2459880642
Short name T616
Test name
Test status
Simulation time 13736329403 ps
CPU time 269.88 seconds
Started Feb 09 11:05:55 AM UTC 25
Finished Feb 09 11:10:29 AM UTC 25
Peak memory 473084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459880642 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2459880642 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.3921128583
Short name T660
Test name
Test status
Simulation time 135651668907 ps
CPU time 1359.8 seconds
Started Feb 09 11:01:57 AM UTC 25
Finished Feb 09 11:24:52 AM UTC 25
Peak memory 272396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921128583 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3921128583 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.1458345772
Short name T614
Test name
Test status
Simulation time 3721727359 ps
CPU time 100.29 seconds
Started Feb 09 11:07:20 AM UTC 25
Finished Feb 09 11:09:03 AM UTC 25
Peak memory 296968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458345772 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1458345772 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.3740951024
Short name T612
Test name
Test status
Simulation time 1580224458 ps
CPU time 31.73 seconds
Started Feb 09 11:07:45 AM UTC 25
Finished Feb 09 11:08:19 AM UTC 25
Peak memory 266172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740951024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.kmac_error.3740951024 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.1910433813
Short name T611
Test name
Test status
Simulation time 3250938679 ps
CPU time 16.44 seconds
Started Feb 09 11:07:54 AM UTC 25
Finished Feb 09 11:08:12 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910433813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1910433813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.2334980087
Short name T620
Test name
Test status
Simulation time 27659916794 ps
CPU time 661.33 seconds
Started Feb 09 11:01:23 AM UTC 25
Finished Feb 09 11:12:32 AM UTC 25
Peak memory 1216520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334980087 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.2334980087 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.3212081404
Short name T602
Test name
Test status
Simulation time 3852543725 ps
CPU time 91.71 seconds
Started Feb 09 11:01:49 AM UTC 25
Finished Feb 09 11:03:23 AM UTC 25
Peak memory 264212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212081404 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3212081404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.1064553654
Short name T599
Test name
Test status
Simulation time 2736123585 ps
CPU time 34.41 seconds
Started Feb 09 11:01:20 AM UTC 25
Finished Feb 09 11:01:56 AM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064553654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.kmac_smoke.1064553654 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.2408104208
Short name T628
Test name
Test status
Simulation time 69983839830 ps
CPU time 371.51 seconds
Started Feb 09 11:08:18 AM UTC 25
Finished Feb 09 11:14:34 AM UTC 25
Peak memory 367136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408104208 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2408104208 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_kmac.2980061437
Short name T607
Test name
Test status
Simulation time 998645101 ps
CPU time 7.55 seconds
Started Feb 09 11:05:38 AM UTC 25
Finished Feb 09 11:05:47 AM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2980061437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.kmac_test_vectors_kmac.2980061437 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_kmac_xof.1204400125
Short name T608
Test name
Test status
Simulation time 180047914 ps
CPU time 5.2 seconds
Started Feb 09 11:05:48 AM UTC 25
Finished Feb 09 11:05:55 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1204400125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 27.kmac_test_vectors_kmac_xof.1204400125 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_224.4066318234
Short name T695
Test name
Test status
Simulation time 271393855431 ps
CPU time 2162.62 seconds
Started Feb 09 11:02:45 AM UTC 25
Finished Feb 09 11:39:11 AM UTC 25
Peak memory 3262400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066318234 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.4066318234 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_256.911658306
Short name T684
Test name
Test status
Simulation time 37791522782 ps
CPU time 1866 seconds
Started Feb 09 11:03:13 AM UTC 25
Finished Feb 09 11:34:40 AM UTC 25
Peak memory 1148852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911658306 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.911658306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_384.3001969243
Short name T658
Test name
Test status
Simulation time 147749452685 ps
CPU time 1233.73 seconds
Started Feb 09 11:03:24 AM UTC 25
Finished Feb 09 11:24:11 AM UTC 25
Peak memory 909308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001969243 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.3001969243 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_512.2272973322
Short name T646
Test name
Test status
Simulation time 19078750431 ps
CPU time 866.43 seconds
Started Feb 09 11:03:49 AM UTC 25
Finished Feb 09 11:18:26 AM UTC 25
Peak memory 690116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272973322 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2272973322 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/27.kmac_test_vectors_shake_256.3247073449
Short name T900
Test name
Test status
Simulation time 150235181622 ps
CPU time 6171.19 seconds
Started Feb 09 11:04:32 AM UTC 25
Finished Feb 09 12:48:31 PM UTC 25
Peak memory 6363076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247073449 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3247073449 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.1056241443
Short name T632
Test name
Test status
Simulation time 42441838 ps
CPU time 1.22 seconds
Started Feb 09 11:14:58 AM UTC 25
Finished Feb 09 11:15:01 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056241443 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1056241443 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.3454831768
Short name T634
Test name
Test status
Simulation time 12110892011 ps
CPU time 77.11 seconds
Started Feb 09 11:13:57 AM UTC 25
Finished Feb 09 11:15:16 AM UTC 25
Peak memory 280592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454831768 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3454831768 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.3938194497
Short name T659
Test name
Test status
Simulation time 8147796786 ps
CPU time 844.83 seconds
Started Feb 09 11:10:31 AM UTC 25
Finished Feb 09 11:24:46 AM UTC 25
Peak memory 251916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938194497 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3938194497 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.2367306000
Short name T642
Test name
Test status
Simulation time 13716598452 ps
CPU time 226.81 seconds
Started Feb 09 11:14:11 AM UTC 25
Finished Feb 09 11:18:01 AM UTC 25
Peak memory 335944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367306000 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2367306000 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.1084683623
Short name T633
Test name
Test status
Simulation time 366364080 ps
CPU time 35.66 seconds
Started Feb 09 11:14:30 AM UTC 25
Finished Feb 09 11:15:07 AM UTC 25
Peak memory 251848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084683623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.kmac_error.1084683623 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.898858203
Short name T629
Test name
Test status
Simulation time 3006768878 ps
CPU time 15.93 seconds
Started Feb 09 11:14:36 AM UTC 25
Finished Feb 09 11:14:53 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898858203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.898858203 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.864627965
Short name T631
Test name
Test status
Simulation time 206264552 ps
CPU time 2.16 seconds
Started Feb 09 11:14:54 AM UTC 25
Finished Feb 09 11:14:57 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864627965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.864627965 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.2894612039
Short name T790
Test name
Test status
Simulation time 522954470124 ps
CPU time 3634.33 seconds
Started Feb 09 11:09:03 AM UTC 25
Finished Feb 09 12:10:14 PM UTC 25
Peak memory 4108356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894612039 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.2894612039 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.3149777781
Short name T621
Test name
Test status
Simulation time 21225625828 ps
CPU time 203.26 seconds
Started Feb 09 11:09:09 AM UTC 25
Finished Feb 09 11:12:36 AM UTC 25
Peak memory 381008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149777781 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3149777781 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.487907895
Short name T615
Test name
Test status
Simulation time 3828349635 ps
CPU time 44.27 seconds
Started Feb 09 11:08:23 AM UTC 25
Finished Feb 09 11:09:09 AM UTC 25
Peak memory 230864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487907895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.kmac_smoke.487907895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.684081943
Short name T671
Test name
Test status
Simulation time 10644387244 ps
CPU time 726.46 seconds
Started Feb 09 11:14:57 AM UTC 25
Finished Feb 09 11:27:13 AM UTC 25
Peak memory 360952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684081943 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.684081943 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_kmac.1356203150
Short name T624
Test name
Test status
Simulation time 65104362 ps
CPU time 4.09 seconds
Started Feb 09 11:13:43 AM UTC 25
Finished Feb 09 11:13:48 AM UTC 25
Peak memory 230780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1356203150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.kmac_test_vectors_kmac.1356203150 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_kmac_xof.761282754
Short name T625
Test name
Test status
Simulation time 639381900 ps
CPU time 6.17 seconds
Started Feb 09 11:13:49 AM UTC 25
Finished Feb 09 11:13:57 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=761282754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac_xof.761282754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_224.3002619515
Short name T740
Test name
Test status
Simulation time 388697749555 ps
CPU time 2717.09 seconds
Started Feb 09 11:10:38 AM UTC 25
Finished Feb 09 11:56:25 AM UTC 25
Peak memory 3248068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002619515 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3002619515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_256.456008562
Short name T734
Test name
Test status
Simulation time 239180271220 ps
CPU time 2572.38 seconds
Started Feb 09 11:11:27 AM UTC 25
Finished Feb 09 11:54:50 AM UTC 25
Peak memory 3123256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456008562 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.456008562 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_384.631843779
Short name T682
Test name
Test status
Simulation time 13624018648 ps
CPU time 1350.52 seconds
Started Feb 09 11:11:36 AM UTC 25
Finished Feb 09 11:34:22 AM UTC 25
Peak memory 903100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631843779 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.631843779 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_512.3077003287
Short name T683
Test name
Test status
Simulation time 46184449877 ps
CPU time 1298.28 seconds
Started Feb 09 11:12:33 AM UTC 25
Finished Feb 09 11:34:26 AM UTC 25
Peak memory 1798144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077003287 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.3077003287 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_shake_128.2273616872
Short name T1025
Test name
Test status
Simulation time 1069846033412 ps
CPU time 8125.8 seconds
Started Feb 09 11:12:37 AM UTC 25
Finished Feb 09 01:29:27 PM UTC 25
Peak memory 7852044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273616872 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2273616872 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/28.kmac_test_vectors_shake_256.3932282148
Short name T942
Test name
Test status
Simulation time 982434906338 ps
CPU time 6459.23 seconds
Started Feb 09 11:13:32 AM UTC 25
Finished Feb 09 01:02:16 PM UTC 25
Peak memory 6400000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932282148 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.3932282148 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.2722585997
Short name T651
Test name
Test status
Simulation time 51804005 ps
CPU time 1.25 seconds
Started Feb 09 11:19:57 AM UTC 25
Finished Feb 09 11:20:00 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722585997 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2722585997 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.3903743351
Short name T655
Test name
Test status
Simulation time 5579707114 ps
CPU time 278.52 seconds
Started Feb 09 11:18:20 AM UTC 25
Finished Feb 09 11:23:03 AM UTC 25
Peak memory 331788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903743351 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.3903743351 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.3270418293
Short name T640
Test name
Test status
Simulation time 2418088210 ps
CPU time 50.53 seconds
Started Feb 09 11:15:37 AM UTC 25
Finished Feb 09 11:16:29 AM UTC 25
Peak memory 235536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270418293 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3270418293 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.3021065855
Short name T647
Test name
Test status
Simulation time 1852389002 ps
CPU time 10.02 seconds
Started Feb 09 11:18:21 AM UTC 25
Finished Feb 09 11:18:32 AM UTC 25
Peak memory 232844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021065855 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3021065855 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.3147383134
Short name T661
Test name
Test status
Simulation time 33808158263 ps
CPU time 413.42 seconds
Started Feb 09 11:18:26 AM UTC 25
Finished Feb 09 11:25:25 AM UTC 25
Peak memory 616452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147383134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 29.kmac_error.3147383134 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.304926514
Short name T648
Test name
Test status
Simulation time 1566072495 ps
CPU time 14.26 seconds
Started Feb 09 11:18:33 AM UTC 25
Finished Feb 09 11:18:49 AM UTC 25
Peak memory 230724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304926514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.304926514 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.911491007
Short name T649
Test name
Test status
Simulation time 4018473528 ps
CPU time 33.68 seconds
Started Feb 09 11:18:50 AM UTC 25
Finished Feb 09 11:19:25 AM UTC 25
Peak memory 262284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911491007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.911491007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.1032295808
Short name T827
Test name
Test status
Simulation time 463431387319 ps
CPU time 3919.81 seconds
Started Feb 09 11:15:07 AM UTC 25
Finished Feb 09 12:21:07 PM UTC 25
Peak memory 4505592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032295808 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.1032295808 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.2830019845
Short name T650
Test name
Test status
Simulation time 9672196676 ps
CPU time 273.86 seconds
Started Feb 09 11:15:18 AM UTC 25
Finished Feb 09 11:19:56 AM UTC 25
Peak memory 424012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830019845 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2830019845 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.425671234
Short name T639
Test name
Test status
Simulation time 13728807468 ps
CPU time 65.12 seconds
Started Feb 09 11:15:01 AM UTC 25
Finished Feb 09 11:16:08 AM UTC 25
Peak memory 234952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425671234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.kmac_smoke.425671234 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.1453827301
Short name T726
Test name
Test status
Simulation time 54506833691 ps
CPU time 1781.4 seconds
Started Feb 09 11:19:26 AM UTC 25
Finished Feb 09 11:49:26 AM UTC 25
Peak memory 1634320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453827301 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1453827301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_kmac.3247694016
Short name T643
Test name
Test status
Simulation time 71423800 ps
CPU time 5.88 seconds
Started Feb 09 11:18:03 AM UTC 25
Finished Feb 09 11:18:10 AM UTC 25
Peak memory 230804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3247694016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.kmac_test_vectors_kmac.3247694016 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_kmac_xof.4254314317
Short name T644
Test name
Test status
Simulation time 211769544 ps
CPU time 6.73 seconds
Started Feb 09 11:18:11 AM UTC 25
Finished Feb 09 11:18:19 AM UTC 25
Peak memory 230716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4254314317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 29.kmac_test_vectors_kmac_xof.4254314317 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_224.75764690
Short name T764
Test name
Test status
Simulation time 397152753185 ps
CPU time 2858.97 seconds
Started Feb 09 11:15:47 AM UTC 25
Finished Feb 09 12:03:57 PM UTC 25
Peak memory 3190788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75764690 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.75764690 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_256.3870942750
Short name T774
Test name
Test status
Simulation time 186393925846 ps
CPU time 2954.34 seconds
Started Feb 09 11:16:01 AM UTC 25
Finished Feb 09 12:05:49 PM UTC 25
Peak memory 3061692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870942750 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3870942750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_384.3112834552
Short name T697
Test name
Test status
Simulation time 71394757480 ps
CPU time 1400.88 seconds
Started Feb 09 11:16:08 AM UTC 25
Finished Feb 09 11:39:45 AM UTC 25
Peak memory 927680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112834552 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3112834552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_512.692107573
Short name T692
Test name
Test status
Simulation time 34797454520 ps
CPU time 1175.48 seconds
Started Feb 09 11:16:09 AM UTC 25
Finished Feb 09 11:35:59 AM UTC 25
Peak memory 1687608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692107573 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.692107573 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_shake_128.1331816431
Short name T889
Test name
Test status
Simulation time 87198091876 ps
CPU time 5153.57 seconds
Started Feb 09 11:16:30 AM UTC 25
Finished Feb 09 12:43:19 PM UTC 25
Peak memory 2689020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331816431 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1331816431 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/29.kmac_test_vectors_shake_256.2104331590
Short name T835
Test name
Test status
Simulation time 43105788987 ps
CPU time 4017.73 seconds
Started Feb 09 11:17:19 AM UTC 25
Finished Feb 09 12:25:00 PM UTC 25
Peak memory 2217920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104331590 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2104331590 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.2025446189
Short name T183
Test name
Test status
Simulation time 267877034 ps
CPU time 1.22 seconds
Started Feb 09 08:44:53 AM UTC 25
Finished Feb 09 08:44:55 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025446189 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.2025446189 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.232917511
Short name T189
Test name
Test status
Simulation time 19477460934 ps
CPU time 308.97 seconds
Started Feb 09 08:42:56 AM UTC 25
Finished Feb 09 08:48:10 AM UTC 25
Peak memory 340032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232917511 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.232917511 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3647792322
Short name T186
Test name
Test status
Simulation time 39946350145 ps
CPU time 226.88 seconds
Started Feb 09 08:42:56 AM UTC 25
Finished Feb 09 08:46:47 AM UTC 25
Peak memory 415884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647792322 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3647792322 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.3029805376
Short name T137
Test name
Test status
Simulation time 299400442361 ps
CPU time 816.59 seconds
Started Feb 09 08:41:59 AM UTC 25
Finished Feb 09 08:55:45 AM UTC 25
Peak memory 256008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029805376 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3029805376 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.4053420754
Short name T178
Test name
Test status
Simulation time 1227394578 ps
CPU time 23.08 seconds
Started Feb 09 08:43:20 AM UTC 25
Finished Feb 09 08:43:44 AM UTC 25
Peak memory 234708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053420754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.4053420754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.4135024763
Short name T179
Test name
Test status
Simulation time 618707602 ps
CPU time 25.06 seconds
Started Feb 09 08:43:23 AM UTC 25
Finished Feb 09 08:43:49 AM UTC 25
Peak memory 230540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135024763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4135024763 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2083619050
Short name T182
Test name
Test status
Simulation time 2148382615 ps
CPU time 34.31 seconds
Started Feb 09 08:43:45 AM UTC 25
Finished Feb 09 08:44:21 AM UTC 25
Peak memory 230864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083619050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2083619050 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.1343036178
Short name T170
Test name
Test status
Simulation time 35335295695 ps
CPU time 273.02 seconds
Started Feb 09 08:43:00 AM UTC 25
Finished Feb 09 08:47:38 AM UTC 25
Peak memory 401420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343036178 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.1343036178 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.2021623179
Short name T30
Test name
Test status
Simulation time 979374558 ps
CPU time 101.86 seconds
Started Feb 09 08:43:06 AM UTC 25
Finished Feb 09 08:44:51 AM UTC 25
Peak memory 284676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021623179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.kmac_error.2021623179 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.3843271449
Short name T62
Test name
Test status
Simulation time 2712040537 ps
CPU time 8.45 seconds
Started Feb 09 08:43:13 AM UTC 25
Finished Feb 09 08:43:22 AM UTC 25
Peak memory 230724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843271449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3843271449 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.100140356
Short name T180
Test name
Test status
Simulation time 61244827 ps
CPU time 2.66 seconds
Started Feb 09 08:43:50 AM UTC 25
Finished Feb 09 08:43:54 AM UTC 25
Peak memory 235464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100140356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.100140356 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.1005790359
Short name T282
Test name
Test status
Simulation time 81639412432 ps
CPU time 2307.09 seconds
Started Feb 09 08:41:48 AM UTC 25
Finished Feb 09 09:20:42 AM UTC 25
Peak memory 1560436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005790359 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.1005790359 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.4264763135
Short name T74
Test name
Test status
Simulation time 3345234462 ps
CPU time 237.71 seconds
Started Feb 09 08:43:02 AM UTC 25
Finished Feb 09 08:47:04 AM UTC 25
Peak memory 309640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264763135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.kmac_mubi.4264763135 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.967444776
Short name T69
Test name
Test status
Simulation time 21326990060 ps
CPU time 104.3 seconds
Started Feb 09 08:44:21 AM UTC 25
Finished Feb 09 08:46:08 AM UTC 25
Peak memory 298156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967444776 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.967444776 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.3235838282
Short name T184
Test name
Test status
Simulation time 7280959510 ps
CPU time 229.19 seconds
Started Feb 09 08:41:48 AM UTC 25
Finished Feb 09 08:45:41 AM UTC 25
Peak memory 436296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235838282 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3235838282 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.1585386094
Short name T171
Test name
Test status
Simulation time 6768889343 ps
CPU time 64.59 seconds
Started Feb 09 08:41:48 AM UTC 25
Finished Feb 09 08:42:55 AM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585386094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.kmac_smoke.1585386094 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.335191056
Short name T253
Test name
Test status
Simulation time 580700256251 ps
CPU time 1809.88 seconds
Started Feb 09 08:43:55 AM UTC 25
Finished Feb 09 09:14:24 AM UTC 25
Peak memory 1317276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335191056 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.335191056 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.4082161269
Short name T176
Test name
Test status
Simulation time 80190272 ps
CPU time 4.75 seconds
Started Feb 09 08:42:50 AM UTC 25
Finished Feb 09 08:42:56 AM UTC 25
Peak memory 230804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4082161269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.kmac_test_vectors_kmac.4082161269 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.3799594998
Short name T177
Test name
Test status
Simulation time 236912721 ps
CPU time 4.95 seconds
Started Feb 09 08:42:53 AM UTC 25
Finished Feb 09 08:42:59 AM UTC 25
Peak memory 230820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3799594998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.kmac_test_vectors_kmac_xof.3799594998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.2466527467
Short name T266
Test name
Test status
Simulation time 93322537254 ps
CPU time 2059.17 seconds
Started Feb 09 08:42:08 AM UTC 25
Finished Feb 09 09:16:51 AM UTC 25
Peak memory 1198016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466527467 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2466527467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3951014667
Short name T237
Test name
Test status
Simulation time 193503530405 ps
CPU time 1617.6 seconds
Started Feb 09 08:42:10 AM UTC 25
Finished Feb 09 09:09:24 AM UTC 25
Peak memory 1126324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951014667 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3951014667 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2387725618
Short name T261
Test name
Test status
Simulation time 153718523490 ps
CPU time 2025.34 seconds
Started Feb 09 08:42:22 AM UTC 25
Finished Feb 09 09:16:28 AM UTC 25
Peak memory 2418744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387725618 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2387725618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.2193016909
Short name T223
Test name
Test status
Simulation time 42971764925 ps
CPU time 1113.9 seconds
Started Feb 09 08:42:31 AM UTC 25
Finished Feb 09 09:01:17 AM UTC 25
Peak memory 1710008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193016909 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2193016909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1704090355
Short name T548
Test name
Test status
Simulation time 256245715252 ps
CPU time 7322.36 seconds
Started Feb 09 08:42:49 AM UTC 25
Finished Feb 09 10:46:01 AM UTC 25
Peak memory 7835636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704090355 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1704090355 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.3041151764
Short name T528
Test name
Test status
Simulation time 352514885414 ps
CPU time 7019.63 seconds
Started Feb 09 08:42:49 AM UTC 25
Finished Feb 09 10:41:01 AM UTC 25
Peak memory 6481864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041151764 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3041151764 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.1488372430
Short name T670
Test name
Test status
Simulation time 51813072 ps
CPU time 1.2 seconds
Started Feb 09 11:27:08 AM UTC 25
Finished Feb 09 11:27:10 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488372430 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1488372430 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.2762182640
Short name T673
Test name
Test status
Simulation time 23577362978 ps
CPU time 184.57 seconds
Started Feb 09 11:25:34 AM UTC 25
Finished Feb 09 11:28:42 AM UTC 25
Peak memory 346232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762182640 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2762182640 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.2011279021
Short name T159
Test name
Test status
Simulation time 19425095597 ps
CPU time 465.93 seconds
Started Feb 09 11:23:00 AM UTC 25
Finished Feb 09 11:30:53 AM UTC 25
Peak memory 245768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011279021 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2011279021 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.261854671
Short name T676
Test name
Test status
Simulation time 87304269781 ps
CPU time 352.67 seconds
Started Feb 09 11:25:39 AM UTC 25
Finished Feb 09 11:31:37 AM UTC 25
Peak memory 567316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261854671 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.261854671 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.2144744746
Short name T667
Test name
Test status
Simulation time 407825894 ps
CPU time 3.07 seconds
Started Feb 09 11:26:05 AM UTC 25
Finished Feb 09 11:26:09 AM UTC 25
Peak memory 230652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144744746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2144744746 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.1859426794
Short name T668
Test name
Test status
Simulation time 60091723 ps
CPU time 1.69 seconds
Started Feb 09 11:26:10 AM UTC 25
Finished Feb 09 11:26:13 AM UTC 25
Peak memory 231860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859426794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1859426794 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.944076009
Short name T758
Test name
Test status
Simulation time 47758248240 ps
CPU time 2521.75 seconds
Started Feb 09 11:20:04 AM UTC 25
Finished Feb 09 12:02:34 PM UTC 25
Peak memory 1687572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944076009 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.944076009 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.2290757070
Short name T654
Test name
Test status
Simulation time 6722449879 ps
CPU time 167.65 seconds
Started Feb 09 11:20:09 AM UTC 25
Finished Feb 09 11:22:59 AM UTC 25
Peak memory 286868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290757070 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2290757070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.1422513877
Short name T653
Test name
Test status
Simulation time 1200633307 ps
CPU time 6.44 seconds
Started Feb 09 11:20:00 AM UTC 25
Finished Feb 09 11:20:08 AM UTC 25
Peak memory 230736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422513877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.kmac_smoke.1422513877 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.2773923905
Short name T688
Test name
Test status
Simulation time 25586426432 ps
CPU time 530.82 seconds
Started Feb 09 11:26:14 AM UTC 25
Finished Feb 09 11:35:12 AM UTC 25
Peak memory 289176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773923905 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2773923905 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_kmac.3359437219
Short name T663
Test name
Test status
Simulation time 523102222 ps
CPU time 6 seconds
Started Feb 09 11:25:26 AM UTC 25
Finished Feb 09 11:25:33 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3359437219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.kmac_test_vectors_kmac.3359437219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_kmac_xof.31204480
Short name T664
Test name
Test status
Simulation time 831365366 ps
CPU time 8.13 seconds
Started Feb 09 11:25:29 AM UTC 25
Finished Feb 09 11:25:39 AM UTC 25
Peak memory 230880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=31204480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 30.kmac_test_vectors_kmac_xof.31204480 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_224.199496273
Short name T776
Test name
Test status
Simulation time 129893685876 ps
CPU time 2570.03 seconds
Started Feb 09 11:23:03 AM UTC 25
Finished Feb 09 12:06:22 PM UTC 25
Peak memory 3184632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199496273 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.199496273 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_256.60329624
Short name T773
Test name
Test status
Simulation time 472117068509 ps
CPU time 2515.46 seconds
Started Feb 09 11:23:23 AM UTC 25
Finished Feb 09 12:05:46 PM UTC 25
Peak memory 3078080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60329624 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.60329624 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_384.658242437
Short name T743
Test name
Test status
Simulation time 529053418318 ps
CPU time 1950.73 seconds
Started Feb 09 11:23:53 AM UTC 25
Finished Feb 09 11:56:47 AM UTC 25
Peak memory 2357244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658242437 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.658242437 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_512.3690301133
Short name T711
Test name
Test status
Simulation time 97282604981 ps
CPU time 1255.09 seconds
Started Feb 09 11:24:12 AM UTC 25
Finished Feb 09 11:45:21 AM UTC 25
Peak memory 1730492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690301133 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.3690301133 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_shake_128.4286030932
Short name T1035
Test name
Test status
Simulation time 225655874264 ps
CPU time 7621.24 seconds
Started Feb 09 11:24:47 AM UTC 25
Finished Feb 09 01:33:06 PM UTC 25
Peak memory 7876648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286030932 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.4286030932 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/30.kmac_test_vectors_shake_256.3706327895
Short name T986
Test name
Test status
Simulation time 1671923563015 ps
CPU time 6573.15 seconds
Started Feb 09 11:24:54 AM UTC 25
Finished Feb 09 01:15:34 PM UTC 25
Peak memory 6442944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706327895 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3706327895 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.659826636
Short name T687
Test name
Test status
Simulation time 14581736 ps
CPU time 1.03 seconds
Started Feb 09 11:34:46 AM UTC 25
Finished Feb 09 11:34:49 AM UTC 25
Peak memory 214468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659826636 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.659826636 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.3117094395
Short name T702
Test name
Test status
Simulation time 15541239977 ps
CPU time 465.22 seconds
Started Feb 09 11:33:01 AM UTC 25
Finished Feb 09 11:40:54 AM UTC 25
Peak memory 526344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117094395 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3117094395 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.2627943044
Short name T720
Test name
Test status
Simulation time 58355391188 ps
CPU time 1124.38 seconds
Started Feb 09 11:28:43 AM UTC 25
Finished Feb 09 11:47:41 AM UTC 25
Peak memory 266248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627943044 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2627943044 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.3712234230
Short name T696
Test name
Test status
Simulation time 14016289106 ps
CPU time 382.59 seconds
Started Feb 09 11:33:02 AM UTC 25
Finished Feb 09 11:39:31 AM UTC 25
Peak memory 446476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712234230 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3712234230 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.622676639
Short name T694
Test name
Test status
Simulation time 34492742136 ps
CPU time 206.89 seconds
Started Feb 09 11:34:23 AM UTC 25
Finished Feb 09 11:37:53 AM UTC 25
Peak memory 419844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622676639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.kmac_error.622676639 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.135088610
Short name T685
Test name
Test status
Simulation time 1364930516 ps
CPU time 11.43 seconds
Started Feb 09 11:34:27 AM UTC 25
Finished Feb 09 11:34:40 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135088610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.135088610 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.4214483837
Short name T686
Test name
Test status
Simulation time 126416810 ps
CPU time 2.04 seconds
Started Feb 09 11:34:40 AM UTC 25
Finished Feb 09 11:34:44 AM UTC 25
Peak memory 230656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214483837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.4214483837 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2087701089
Short name T744
Test name
Test status
Simulation time 103515740182 ps
CPU time 1760.24 seconds
Started Feb 09 11:27:14 AM UTC 25
Finished Feb 09 11:56:54 AM UTC 25
Peak memory 1228812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087701089 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2087701089 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.637391881
Short name T679
Test name
Test status
Simulation time 7280742522 ps
CPU time 274.68 seconds
Started Feb 09 11:28:13 AM UTC 25
Finished Feb 09 11:32:52 AM UTC 25
Peak memory 342004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637391881 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.637391881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.2871768060
Short name T672
Test name
Test status
Simulation time 4362961371 ps
CPU time 60 seconds
Started Feb 09 11:27:11 AM UTC 25
Finished Feb 09 11:28:13 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871768060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.kmac_smoke.2871768060 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.1539211316
Short name T705
Test name
Test status
Simulation time 4135223104 ps
CPU time 457.27 seconds
Started Feb 09 11:34:40 AM UTC 25
Finished Feb 09 11:42:25 AM UTC 25
Peak memory 280660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539211316 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1539211316 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_kmac.3169868662
Short name T680
Test name
Test status
Simulation time 239604378 ps
CPU time 5.55 seconds
Started Feb 09 11:32:53 AM UTC 25
Finished Feb 09 11:33:00 AM UTC 25
Peak memory 230656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3169868662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.kmac_test_vectors_kmac.3169868662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_kmac_xof.3843952474
Short name T681
Test name
Test status
Simulation time 330355451 ps
CPU time 6.33 seconds
Started Feb 09 11:32:53 AM UTC 25
Finished Feb 09 11:33:01 AM UTC 25
Peak memory 230672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3843952474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 31.kmac_test_vectors_kmac_xof.3843952474 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_224.2407591720
Short name T811
Test name
Test status
Simulation time 698320733294 ps
CPU time 2731.93 seconds
Started Feb 09 11:29:41 AM UTC 25
Finished Feb 09 12:15:40 PM UTC 25
Peak memory 3264452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407591720 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.2407591720 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_256.2152503140
Short name T747
Test name
Test status
Simulation time 17866992320 ps
CPU time 1710.33 seconds
Started Feb 09 11:29:47 AM UTC 25
Finished Feb 09 11:58:37 AM UTC 25
Peak memory 1157052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152503140 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2152503140 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_384.2981821729
Short name T730
Test name
Test status
Simulation time 28587250244 ps
CPU time 1277.04 seconds
Started Feb 09 11:30:54 AM UTC 25
Finished Feb 09 11:52:25 AM UTC 25
Peak memory 937920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981821729 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2981821729 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_512.1555127485
Short name T728
Test name
Test status
Simulation time 68413240472 ps
CPU time 1140.53 seconds
Started Feb 09 11:31:30 AM UTC 25
Finished Feb 09 11:50:44 AM UTC 25
Peak memory 1712116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555127485 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1555127485 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_shake_128.4291586133
Short name T901
Test name
Test status
Simulation time 169263426121 ps
CPU time 4616.92 seconds
Started Feb 09 11:31:38 AM UTC 25
Finished Feb 09 12:49:23 PM UTC 25
Peak memory 2701248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291586133 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.4291586133 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/31.kmac_test_vectors_shake_256.3621619820
Short name T1032
Test name
Test status
Simulation time 228970198771 ps
CPU time 7071.86 seconds
Started Feb 09 11:31:52 AM UTC 25
Finished Feb 09 01:30:59 PM UTC 25
Peak memory 6363072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621619820 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3621619820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.2084845923
Short name T706
Test name
Test status
Simulation time 39420369 ps
CPU time 1.15 seconds
Started Feb 09 11:42:26 AM UTC 25
Finished Feb 09 11:42:28 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084845923 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2084845923 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.786464221
Short name T701
Test name
Test status
Simulation time 7016741110 ps
CPU time 48.86 seconds
Started Feb 09 11:40:01 AM UTC 25
Finished Feb 09 11:40:52 AM UTC 25
Peak memory 260220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786464221 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.786464221 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.681740594
Short name T716
Test name
Test status
Simulation time 48275029522 ps
CPU time 664.89 seconds
Started Feb 09 11:35:21 AM UTC 25
Finished Feb 09 11:46:35 AM UTC 25
Peak memory 247824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681740594 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.681740594 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.1124194768
Short name T715
Test name
Test status
Simulation time 15974548192 ps
CPU time 353.02 seconds
Started Feb 09 11:40:29 AM UTC 25
Finished Feb 09 11:46:27 AM UTC 25
Peak memory 526400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124194768 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1124194768 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.1845889585
Short name T719
Test name
Test status
Simulation time 36420308777 ps
CPU time 366.3 seconds
Started Feb 09 11:40:53 AM UTC 25
Finished Feb 09 11:47:05 AM UTC 25
Peak memory 477184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845889585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.kmac_error.1845889585 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.2817793091
Short name T703
Test name
Test status
Simulation time 3434067817 ps
CPU time 3.49 seconds
Started Feb 09 11:40:54 AM UTC 25
Finished Feb 09 11:40:59 AM UTC 25
Peak memory 230716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817793091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2817793091 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.209034404
Short name T704
Test name
Test status
Simulation time 677401616 ps
CPU time 2.34 seconds
Started Feb 09 11:40:59 AM UTC 25
Finished Feb 09 11:41:03 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209034404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.209034404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.160672309
Short name T783
Test name
Test status
Simulation time 934413048512 ps
CPU time 1910.11 seconds
Started Feb 09 11:35:13 AM UTC 25
Finished Feb 09 12:07:24 PM UTC 25
Peak memory 2441236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160672309 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.160672309 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.615794224
Short name T707
Test name
Test status
Simulation time 47348768913 ps
CPU time 437.78 seconds
Started Feb 09 11:35:15 AM UTC 25
Finished Feb 09 11:42:39 AM UTC 25
Peak memory 546832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615794224 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.615794224 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.3313137047
Short name T690
Test name
Test status
Simulation time 3790596507 ps
CPU time 29.33 seconds
Started Feb 09 11:34:50 AM UTC 25
Finished Feb 09 11:35:21 AM UTC 25
Peak memory 230792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313137047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.kmac_smoke.3313137047 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.1852579070
Short name T801
Test name
Test status
Simulation time 69817857014 ps
CPU time 1875.64 seconds
Started Feb 09 11:41:04 AM UTC 25
Finished Feb 09 12:12:40 PM UTC 25
Peak memory 1196488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852579070 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1852579070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_kmac.1632385315
Short name T698
Test name
Test status
Simulation time 122720335 ps
CPU time 5.34 seconds
Started Feb 09 11:39:46 AM UTC 25
Finished Feb 09 11:39:52 AM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1632385315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.kmac_test_vectors_kmac.1632385315 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_kmac_xof.3941385938
Short name T699
Test name
Test status
Simulation time 648516193 ps
CPU time 6.09 seconds
Started Feb 09 11:39:53 AM UTC 25
Finished Feb 09 11:40:00 AM UTC 25
Peak memory 230716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3941385938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 32.kmac_test_vectors_kmac_xof.3941385938 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_224.3189446928
Short name T802
Test name
Test status
Simulation time 356764172522 ps
CPU time 2205.4 seconds
Started Feb 09 11:35:45 AM UTC 25
Finished Feb 09 12:12:53 PM UTC 25
Peak memory 3209216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189446928 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.3189446928 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_256.2187655725
Short name T809
Test name
Test status
Simulation time 74958017958 ps
CPU time 2337.64 seconds
Started Feb 09 11:35:59 AM UTC 25
Finished Feb 09 12:15:22 PM UTC 25
Peak memory 3010560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187655725 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2187655725 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_384.3289945951
Short name T749
Test name
Test status
Simulation time 45501860902 ps
CPU time 1335.9 seconds
Started Feb 09 11:36:36 AM UTC 25
Finished Feb 09 11:59:08 AM UTC 25
Peak memory 933868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289945951 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3289945951 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_512.3288749413
Short name T748
Test name
Test status
Simulation time 313801856387 ps
CPU time 1247.42 seconds
Started Feb 09 11:37:55 AM UTC 25
Finished Feb 09 11:58:56 AM UTC 25
Peak memory 1679300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288749413 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3288749413 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_shake_128.3284747703
Short name T1037
Test name
Test status
Simulation time 182415187808 ps
CPU time 6858.35 seconds
Started Feb 09 11:39:11 AM UTC 25
Finished Feb 09 01:34:39 PM UTC 25
Peak memory 8013860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284747703 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3284747703 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/32.kmac_test_vectors_shake_256.1497213378
Short name T983
Test name
Test status
Simulation time 145081301080 ps
CPU time 5611.14 seconds
Started Feb 09 11:39:32 AM UTC 25
Finished Feb 09 01:14:00 PM UTC 25
Peak memory 6410172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497213378 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1497213378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.776011792
Short name T724
Test name
Test status
Simulation time 24547472 ps
CPU time 1.18 seconds
Started Feb 09 11:48:03 AM UTC 25
Finished Feb 09 11:48:06 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776011792 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.776011792 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.1442317890
Short name T729
Test name
Test status
Simulation time 17731577262 ps
CPU time 249.82 seconds
Started Feb 09 11:46:52 AM UTC 25
Finished Feb 09 11:51:07 AM UTC 25
Peak memory 313352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442317890 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1442317890 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.3690059529
Short name T761
Test name
Test status
Simulation time 124250275238 ps
CPU time 1202.25 seconds
Started Feb 09 11:43:08 AM UTC 25
Finished Feb 09 12:03:24 PM UTC 25
Peak memory 272388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690059529 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3690059529 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.2313202786
Short name T727
Test name
Test status
Simulation time 16366495391 ps
CPU time 179.31 seconds
Started Feb 09 11:47:06 AM UTC 25
Finished Feb 09 11:50:08 AM UTC 25
Peak memory 356368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313202786 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2313202786 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.1691618796
Short name T736
Test name
Test status
Simulation time 13696320887 ps
CPU time 433.47 seconds
Started Feb 09 11:47:43 AM UTC 25
Finished Feb 09 11:55:03 AM UTC 25
Peak memory 548860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691618796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.kmac_error.1691618796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.2376786965
Short name T723
Test name
Test status
Simulation time 1406705533 ps
CPU time 13.45 seconds
Started Feb 09 11:47:47 AM UTC 25
Finished Feb 09 11:48:02 AM UTC 25
Peak memory 232708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376786965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2376786965 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.1592755754
Short name T87
Test name
Test status
Simulation time 63638673 ps
CPU time 2.05 seconds
Started Feb 09 11:47:56 AM UTC 25
Finished Feb 09 11:47:59 AM UTC 25
Peak memory 230768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592755754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1592755754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.2467813550
Short name T756
Test name
Test status
Simulation time 305410435901 ps
CPU time 1157.84 seconds
Started Feb 09 11:42:41 AM UTC 25
Finished Feb 09 12:02:12 PM UTC 25
Peak memory 1353744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467813550 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.2467813550 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.3206851930
Short name T710
Test name
Test status
Simulation time 4730832297 ps
CPU time 42.16 seconds
Started Feb 09 11:43:02 AM UTC 25
Finished Feb 09 11:43:46 AM UTC 25
Peak memory 256020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206851930 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3206851930 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.3382945098
Short name T709
Test name
Test status
Simulation time 5263181434 ps
CPU time 36.53 seconds
Started Feb 09 11:42:29 AM UTC 25
Finished Feb 09 11:43:07 AM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382945098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.kmac_smoke.3382945098 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.462630146
Short name T857
Test name
Test status
Simulation time 105219890803 ps
CPU time 2698.98 seconds
Started Feb 09 11:48:00 AM UTC 25
Finished Feb 09 12:33:28 PM UTC 25
Peak memory 2021940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462630146 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.462630146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_kmac.347709264
Short name T717
Test name
Test status
Simulation time 185204121 ps
CPU time 6.74 seconds
Started Feb 09 11:46:36 AM UTC 25
Finished Feb 09 11:46:44 AM UTC 25
Peak memory 230868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=347709264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.kmac_test_vectors_kmac.347709264 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_kmac_xof.1409422169
Short name T718
Test name
Test status
Simulation time 63129888 ps
CPU time 5.36 seconds
Started Feb 09 11:46:45 AM UTC 25
Finished Feb 09 11:46:52 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1409422169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 33.kmac_test_vectors_kmac_xof.1409422169 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_224.1879630050
Short name T808
Test name
Test status
Simulation time 28177135672 ps
CPU time 1858.43 seconds
Started Feb 09 11:43:48 AM UTC 25
Finished Feb 09 12:15:07 PM UTC 25
Peak memory 1210284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879630050 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1879630050 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_256.2122096162
Short name T800
Test name
Test status
Simulation time 36660673084 ps
CPU time 1580.62 seconds
Started Feb 09 11:45:22 AM UTC 25
Finished Feb 09 12:12:00 PM UTC 25
Peak memory 1163260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122096162 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2122096162 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_384.623531167
Short name T817
Test name
Test status
Simulation time 275213744867 ps
CPU time 1908.22 seconds
Started Feb 09 11:45:25 AM UTC 25
Finished Feb 09 12:17:34 PM UTC 25
Peak memory 2353148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623531167 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.623531167 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_512.3372079754
Short name T762
Test name
Test status
Simulation time 130155921904 ps
CPU time 1052.32 seconds
Started Feb 09 11:45:49 AM UTC 25
Finished Feb 09 12:03:33 PM UTC 25
Peak memory 1730556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372079754 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3372079754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_shake_128.3203041172
Short name T953
Test name
Test status
Simulation time 104860676613 ps
CPU time 4687.88 seconds
Started Feb 09 11:46:27 AM UTC 25
Finished Feb 09 01:05:23 PM UTC 25
Peak memory 2738164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203041172 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3203041172 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/33.kmac_test_vectors_shake_256.2949053547
Short name T1045
Test name
Test status
Simulation time 796389434887 ps
CPU time 6873.82 seconds
Started Feb 09 11:46:28 AM UTC 25
Finished Feb 09 01:42:15 PM UTC 25
Peak memory 6537360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949053547 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2949053547 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.3128219348
Short name T742
Test name
Test status
Simulation time 12157892 ps
CPU time 1.17 seconds
Started Feb 09 11:56:29 AM UTC 25
Finished Feb 09 11:56:31 AM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128219348 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3128219348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.3790928405
Short name T733
Test name
Test status
Simulation time 13827398295 ps
CPU time 189.01 seconds
Started Feb 09 11:50:09 AM UTC 25
Finished Feb 09 11:53:22 AM UTC 25
Peak memory 235536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790928405 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3790928405 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.3913658552
Short name T739
Test name
Test status
Simulation time 6486217790 ps
CPU time 71.91 seconds
Started Feb 09 11:55:09 AM UTC 25
Finished Feb 09 11:56:23 AM UTC 25
Peak memory 247792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913658552 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3913658552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.3436005040
Short name T751
Test name
Test status
Simulation time 8321564916 ps
CPU time 317.3 seconds
Started Feb 09 11:55:33 AM UTC 25
Finished Feb 09 12:00:55 PM UTC 25
Peak memory 466948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436005040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.kmac_error.3436005040 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.2518120594
Short name T741
Test name
Test status
Simulation time 2189172320 ps
CPU time 6.05 seconds
Started Feb 09 11:56:22 AM UTC 25
Finished Feb 09 11:56:29 AM UTC 25
Peak memory 230652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518120594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2518120594 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.199899367
Short name T88
Test name
Test status
Simulation time 144094288 ps
CPU time 1.86 seconds
Started Feb 09 11:56:24 AM UTC 25
Finished Feb 09 11:56:27 AM UTC 25
Peak memory 229760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199899367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.199899367 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3223208970
Short name T732
Test name
Test status
Simulation time 2491267838 ps
CPU time 258.03 seconds
Started Feb 09 11:48:56 AM UTC 25
Finished Feb 09 11:53:18 AM UTC 25
Peak memory 378900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223208970 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3223208970 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.931814554
Short name T738
Test name
Test status
Simulation time 8752241329 ps
CPU time 408.24 seconds
Started Feb 09 11:49:27 AM UTC 25
Finished Feb 09 11:56:21 AM UTC 25
Peak memory 382984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931814554 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.931814554 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.2106935848
Short name T725
Test name
Test status
Simulation time 1629763493 ps
CPU time 46.45 seconds
Started Feb 09 11:48:06 AM UTC 25
Finished Feb 09 11:48:55 AM UTC 25
Peak memory 230852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106935848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.kmac_smoke.2106935848 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.3714056002
Short name T750
Test name
Test status
Simulation time 3386592533 ps
CPU time 222.13 seconds
Started Feb 09 11:56:26 AM UTC 25
Finished Feb 09 12:00:11 PM UTC 25
Peak memory 285052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714056002 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3714056002 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_kmac.4080776615
Short name T735
Test name
Test status
Simulation time 671692102 ps
CPU time 7.05 seconds
Started Feb 09 11:54:51 AM UTC 25
Finished Feb 09 11:54:59 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4080776615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.kmac_test_vectors_kmac.4080776615 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_kmac_xof.2924266859
Short name T737
Test name
Test status
Simulation time 867885409 ps
CPU time 7.48 seconds
Started Feb 09 11:55:00 AM UTC 25
Finished Feb 09 11:55:09 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2924266859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 34.kmac_test_vectors_kmac_xof.2924266859 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_224.3508615635
Short name T878
Test name
Test status
Simulation time 182618350030 ps
CPU time 2954.93 seconds
Started Feb 09 11:50:45 AM UTC 25
Finished Feb 09 12:40:32 PM UTC 25
Peak memory 3379140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508615635 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3508615635 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_256.3872145100
Short name T826
Test name
Test status
Simulation time 18545483275 ps
CPU time 1743.7 seconds
Started Feb 09 11:51:08 AM UTC 25
Finished Feb 09 12:20:31 PM UTC 25
Peak memory 1165248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872145100 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.3872145100 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_384.4036940418
Short name T822
Test name
Test status
Simulation time 63763913388 ps
CPU time 1639.06 seconds
Started Feb 09 11:52:26 AM UTC 25
Finished Feb 09 12:20:02 PM UTC 25
Peak memory 2418624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036940418 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.4036940418 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_512.2519430975
Short name T786
Test name
Test status
Simulation time 62796789968 ps
CPU time 975.21 seconds
Started Feb 09 11:52:49 AM UTC 25
Finished Feb 09 12:09:16 PM UTC 25
Peak memory 706492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519430975 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.2519430975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_shake_128.998495730
Short name T1053
Test name
Test status
Simulation time 718805711735 ps
CPU time 7014.86 seconds
Started Feb 09 11:53:19 AM UTC 25
Finished Feb 09 01:51:26 PM UTC 25
Peak memory 7891036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998495730 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.998495730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/34.kmac_test_vectors_shake_256.4048550566
Short name T1014
Test name
Test status
Simulation time 187077974554 ps
CPU time 5543.43 seconds
Started Feb 09 11:53:23 AM UTC 25
Finished Feb 09 01:26:41 PM UTC 25
Peak memory 6375336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048550566 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.4048550566 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.2916401424
Short name T759
Test name
Test status
Simulation time 48179460 ps
CPU time 1.18 seconds
Started Feb 09 12:02:50 PM UTC 25
Finished Feb 09 12:02:53 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916401424 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2916401424 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.1264299327
Short name T754
Test name
Test status
Simulation time 1528177272 ps
CPU time 40.83 seconds
Started Feb 09 12:01:14 PM UTC 25
Finished Feb 09 12:01:56 PM UTC 25
Peak memory 241672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264299327 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1264299327 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.1458875893
Short name T765
Test name
Test status
Simulation time 34914000441 ps
CPU time 430.13 seconds
Started Feb 09 11:56:56 AM UTC 25
Finished Feb 09 12:04:12 PM UTC 25
Peak memory 245772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458875893 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1458875893 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.2566665231
Short name T772
Test name
Test status
Simulation time 18187199398 ps
CPU time 206.53 seconds
Started Feb 09 12:01:58 PM UTC 25
Finished Feb 09 12:05:28 PM UTC 25
Peak memory 294924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566665231 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2566665231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.3080541722
Short name T768
Test name
Test status
Simulation time 26392893561 ps
CPU time 168.06 seconds
Started Feb 09 12:02:11 PM UTC 25
Finished Feb 09 12:05:02 PM UTC 25
Peak memory 342016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080541722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.kmac_error.3080541722 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.2474217328
Short name T757
Test name
Test status
Simulation time 7582077793 ps
CPU time 9.45 seconds
Started Feb 09 12:02:13 PM UTC 25
Finished Feb 09 12:02:24 PM UTC 25
Peak memory 230716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474217328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2474217328 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.3465064455
Short name T760
Test name
Test status
Simulation time 1841867302 ps
CPU time 26.63 seconds
Started Feb 09 12:02:25 PM UTC 25
Finished Feb 09 12:02:53 PM UTC 25
Peak memory 251816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465064455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3465064455 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.188129151
Short name T874
Test name
Test status
Simulation time 94634086786 ps
CPU time 2525.69 seconds
Started Feb 09 11:56:32 AM UTC 25
Finished Feb 09 12:39:07 PM UTC 25
Peak memory 1708044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188129151 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.188129151 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.1065557978
Short name T755
Test name
Test status
Simulation time 209776507282 ps
CPU time 316.84 seconds
Started Feb 09 11:56:48 AM UTC 25
Finished Feb 09 12:02:10 PM UTC 25
Peak memory 454672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065557978 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1065557978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.2470330567
Short name T745
Test name
Test status
Simulation time 1111855576 ps
CPU time 35.41 seconds
Started Feb 09 11:56:30 AM UTC 25
Finished Feb 09 11:57:07 AM UTC 25
Peak memory 232772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470330567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.kmac_smoke.2470330567 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.2144395204
Short name T810
Test name
Test status
Simulation time 17544787930 ps
CPU time 769.59 seconds
Started Feb 09 12:02:35 PM UTC 25
Finished Feb 09 12:15:35 PM UTC 25
Peak memory 692628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144395204 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2144395204 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_kmac.827000774
Short name T752
Test name
Test status
Simulation time 245037589 ps
CPU time 5.76 seconds
Started Feb 09 12:00:56 PM UTC 25
Finished Feb 09 12:01:03 PM UTC 25
Peak memory 230784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=827000774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.kmac_test_vectors_kmac.827000774 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_kmac_xof.604918270
Short name T753
Test name
Test status
Simulation time 339088659 ps
CPU time 6.64 seconds
Started Feb 09 12:01:04 PM UTC 25
Finished Feb 09 12:01:12 PM UTC 25
Peak memory 230812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=604918270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac_xof.604918270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_224.1699824111
Short name T903
Test name
Test status
Simulation time 97573516097 ps
CPU time 3124.26 seconds
Started Feb 09 11:57:08 AM UTC 25
Finished Feb 09 12:49:47 PM UTC 25
Peak memory 3260356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699824111 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.1699824111 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_256.728994073
Short name T839
Test name
Test status
Simulation time 99786245785 ps
CPU time 1703.92 seconds
Started Feb 09 11:58:21 AM UTC 25
Finished Feb 09 12:27:04 PM UTC 25
Peak memory 1097728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728994073 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.728994073 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_384.2421955200
Short name T853
Test name
Test status
Simulation time 291674483426 ps
CPU time 1979.35 seconds
Started Feb 09 11:58:38 AM UTC 25
Finished Feb 09 12:31:59 PM UTC 25
Peak memory 2394108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421955200 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.2421955200 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_512.3826363220
Short name T818
Test name
Test status
Simulation time 88714167763 ps
CPU time 1166.62 seconds
Started Feb 09 11:58:57 AM UTC 25
Finished Feb 09 12:18:37 PM UTC 25
Peak memory 1746884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826363220 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.3826363220 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_shake_128.863359674
Short name T1062
Test name
Test status
Simulation time 174773067237 ps
CPU time 7297.96 seconds
Started Feb 09 11:59:08 AM UTC 25
Finished Feb 09 02:02:03 PM UTC 25
Peak memory 7819296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863359674 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.863359674 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/35.kmac_test_vectors_shake_256.2096428509
Short name T957
Test name
Test status
Simulation time 333224017910 ps
CPU time 3933 seconds
Started Feb 09 12:00:15 PM UTC 25
Finished Feb 09 01:06:29 PM UTC 25
Peak memory 2236340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096428509 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.2096428509 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.2754474797
Short name T777
Test name
Test status
Simulation time 113959831 ps
CPU time 1.23 seconds
Started Feb 09 12:06:22 PM UTC 25
Finished Feb 09 12:06:25 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754474797 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2754474797 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.2952965422
Short name T785
Test name
Test status
Simulation time 14968813371 ps
CPU time 219.74 seconds
Started Feb 09 12:05:23 PM UTC 25
Finished Feb 09 12:09:06 PM UTC 25
Peak memory 366596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952965422 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2952965422 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.2882328551
Short name T823
Test name
Test status
Simulation time 180013022923 ps
CPU time 982.84 seconds
Started Feb 09 12:03:33 PM UTC 25
Finished Feb 09 12:20:07 PM UTC 25
Peak memory 274444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882328551 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2882328551 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.3079703310
Short name T795
Test name
Test status
Simulation time 10178464918 ps
CPU time 345.74 seconds
Started Feb 09 12:05:29 PM UTC 25
Finished Feb 09 12:11:20 PM UTC 25
Peak memory 456720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079703310 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3079703310 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.2171896451
Short name T788
Test name
Test status
Simulation time 21324340331 ps
CPU time 262.88 seconds
Started Feb 09 12:05:47 PM UTC 25
Finished Feb 09 12:10:14 PM UTC 25
Peak memory 448508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171896451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.kmac_error.2171896451 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.89043110
Short name T775
Test name
Test status
Simulation time 1317036759 ps
CPU time 12.06 seconds
Started Feb 09 12:05:50 PM UTC 25
Finished Feb 09 12:06:03 PM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89043110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.kmac_key_error.89043110 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.671580071
Short name T41
Test name
Test status
Simulation time 35446655 ps
CPU time 1.88 seconds
Started Feb 09 12:06:04 PM UTC 25
Finished Feb 09 12:06:07 PM UTC 25
Peak memory 231976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671580071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.671580071 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3825954493
Short name T893
Test name
Test status
Simulation time 106226135929 ps
CPU time 2471.81 seconds
Started Feb 09 12:02:54 PM UTC 25
Finished Feb 09 12:44:32 PM UTC 25
Peak memory 1855500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825954493 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3825954493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.3055077697
Short name T766
Test name
Test status
Simulation time 2644973721 ps
CPU time 63.77 seconds
Started Feb 09 12:03:25 PM UTC 25
Finished Feb 09 12:04:31 PM UTC 25
Peak memory 251984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055077697 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3055077697 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.2982409582
Short name T763
Test name
Test status
Simulation time 8955397789 ps
CPU time 53.35 seconds
Started Feb 09 12:02:54 PM UTC 25
Finished Feb 09 12:03:49 PM UTC 25
Peak memory 230792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982409582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.kmac_smoke.2982409582 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.4187717098
Short name T782
Test name
Test status
Simulation time 4813776900 ps
CPU time 73.16 seconds
Started Feb 09 12:06:08 PM UTC 25
Finished Feb 09 12:07:24 PM UTC 25
Peak memory 268308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187717098 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.4187717098 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_kmac.1330423493
Short name T770
Test name
Test status
Simulation time 379916086 ps
CPU time 7.59 seconds
Started Feb 09 12:05:03 PM UTC 25
Finished Feb 09 12:05:12 PM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1330423493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.kmac_test_vectors_kmac.1330423493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_kmac_xof.3267805056
Short name T771
Test name
Test status
Simulation time 917350308 ps
CPU time 8.06 seconds
Started Feb 09 12:05:13 PM UTC 25
Finished Feb 09 12:05:22 PM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3267805056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 36.kmac_test_vectors_kmac_xof.3267805056 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_224.4243693308
Short name T921
Test name
Test status
Simulation time 442244129812 ps
CPU time 3040.74 seconds
Started Feb 09 12:03:50 PM UTC 25
Finished Feb 09 12:55:03 PM UTC 25
Peak memory 3248184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243693308 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.4243693308 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_256.3458771153
Short name T875
Test name
Test status
Simulation time 81025878090 ps
CPU time 2100.86 seconds
Started Feb 09 12:03:58 PM UTC 25
Finished Feb 09 12:39:21 PM UTC 25
Peak memory 3053572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458771153 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.3458771153 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_384.2966209079
Short name T882
Test name
Test status
Simulation time 63720923796 ps
CPU time 2175.48 seconds
Started Feb 09 12:04:13 PM UTC 25
Finished Feb 09 12:40:54 PM UTC 25
Peak memory 2392060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966209079 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2966209079 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_512.2768763706
Short name T847
Test name
Test status
Simulation time 221406993047 ps
CPU time 1548.32 seconds
Started Feb 09 12:04:32 PM UTC 25
Finished Feb 09 12:30:38 PM UTC 25
Peak memory 1734568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768763706 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.2768763706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_shake_128.2584870617
Short name T1022
Test name
Test status
Simulation time 52204067897 ps
CPU time 4943.54 seconds
Started Feb 09 12:04:45 PM UTC 25
Finished Feb 09 01:28:00 PM UTC 25
Peak memory 2723824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584870617 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.2584870617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/36.kmac_test_vectors_shake_256.3843833897
Short name T1061
Test name
Test status
Simulation time 441069696309 ps
CPU time 6925.81 seconds
Started Feb 09 12:05:03 PM UTC 25
Finished Feb 09 02:01:42 PM UTC 25
Peak memory 6406076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843833897 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3843833897 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.3844485982
Short name T796
Test name
Test status
Simulation time 40719853 ps
CPU time 1.2 seconds
Started Feb 09 12:11:21 PM UTC 25
Finished Feb 09 12:11:24 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844485982 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3844485982 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.1202930792
Short name T792
Test name
Test status
Simulation time 7345266915 ps
CPU time 20.42 seconds
Started Feb 09 12:10:16 PM UTC 25
Finished Feb 09 12:10:38 PM UTC 25
Peak memory 237656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202930792 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1202930792 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.3691980971
Short name T160
Test name
Test status
Simulation time 28041063941 ps
CPU time 304.04 seconds
Started Feb 09 12:07:13 PM UTC 25
Finished Feb 09 12:12:21 PM UTC 25
Peak memory 239604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691980971 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3691980971 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.3020508848
Short name T797
Test name
Test status
Simulation time 3447986069 ps
CPU time 80.53 seconds
Started Feb 09 12:10:16 PM UTC 25
Finished Feb 09 12:11:38 PM UTC 25
Peak memory 278532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020508848 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3020508848 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.3272987019
Short name T804
Test name
Test status
Simulation time 26542016382 ps
CPU time 240.93 seconds
Started Feb 09 12:10:25 PM UTC 25
Finished Feb 09 12:14:30 PM UTC 25
Peak memory 395328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272987019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.kmac_error.3272987019 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.3981949785
Short name T793
Test name
Test status
Simulation time 3199652096 ps
CPU time 6.61 seconds
Started Feb 09 12:10:38 PM UTC 25
Finished Feb 09 12:10:46 PM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981949785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3981949785 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.50330306
Short name T794
Test name
Test status
Simulation time 92730553 ps
CPU time 1.84 seconds
Started Feb 09 12:10:48 PM UTC 25
Finished Feb 09 12:10:51 PM UTC 25
Peak memory 231780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50330306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.50330306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.3193805906
Short name T781
Test name
Test status
Simulation time 528693664 ps
CPU time 22.51 seconds
Started Feb 09 12:06:52 PM UTC 25
Finished Feb 09 12:07:16 PM UTC 25
Peak memory 251844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193805906 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.3193805906 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.4109826529
Short name T799
Test name
Test status
Simulation time 60970026003 ps
CPU time 286.06 seconds
Started Feb 09 12:07:03 PM UTC 25
Finished Feb 09 12:11:53 PM UTC 25
Peak memory 510104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109826529 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.4109826529 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.4049645106
Short name T778
Test name
Test status
Simulation time 4063291592 ps
CPU time 23.48 seconds
Started Feb 09 12:06:26 PM UTC 25
Finished Feb 09 12:06:51 PM UTC 25
Peak memory 230864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049645106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.kmac_smoke.4049645106 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.282066016
Short name T858
Test name
Test status
Simulation time 20005091495 ps
CPU time 1351.59 seconds
Started Feb 09 12:10:52 PM UTC 25
Finished Feb 09 12:33:38 PM UTC 25
Peak memory 819680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282066016 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.282066016 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_kmac.817468162
Short name T789
Test name
Test status
Simulation time 1001124404 ps
CPU time 7.59 seconds
Started Feb 09 12:10:05 PM UTC 25
Finished Feb 09 12:10:14 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=817468162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.kmac_test_vectors_kmac.817468162 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_kmac_xof.756023817
Short name T791
Test name
Test status
Simulation time 251137671 ps
CPU time 6.76 seconds
Started Feb 09 12:10:16 PM UTC 25
Finished Feb 09 12:10:24 PM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=756023817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac_xof.756023817 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_224.739157742
Short name T915
Test name
Test status
Simulation time 575225830510 ps
CPU time 2703.27 seconds
Started Feb 09 12:07:17 PM UTC 25
Finished Feb 09 12:52:47 PM UTC 25
Peak memory 3270652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739157742 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.739157742 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_256.4113703107
Short name T892
Test name
Test status
Simulation time 468401723852 ps
CPU time 2197.2 seconds
Started Feb 09 12:07:24 PM UTC 25
Finished Feb 09 12:44:25 PM UTC 25
Peak memory 3055612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113703107 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.4113703107 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_384.1889182058
Short name T883
Test name
Test status
Simulation time 696899783834 ps
CPU time 2060.04 seconds
Started Feb 09 12:07:24 PM UTC 25
Finished Feb 09 12:42:07 PM UTC 25
Peak memory 2387964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889182058 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.1889182058 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_512.3559557120
Short name T836
Test name
Test status
Simulation time 10187736828 ps
CPU time 988.62 seconds
Started Feb 09 12:08:33 PM UTC 25
Finished Feb 09 12:25:13 PM UTC 25
Peak memory 729004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559557120 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3559557120 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_shake_128.4230465080
Short name T1002
Test name
Test status
Simulation time 50681177092 ps
CPU time 4344.92 seconds
Started Feb 09 12:09:07 PM UTC 25
Finished Feb 09 01:22:18 PM UTC 25
Peak memory 2693236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230465080 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.4230465080 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/37.kmac_test_vectors_shake_256.2715331452
Short name T1067
Test name
Test status
Simulation time 935919717462 ps
CPU time 6950.71 seconds
Started Feb 09 12:09:18 PM UTC 25
Finished Feb 09 02:06:22 PM UTC 25
Peak memory 6369380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715331452 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2715331452 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.1428037964
Short name T813
Test name
Test status
Simulation time 155580244 ps
CPU time 1.23 seconds
Started Feb 09 12:15:46 PM UTC 25
Finished Feb 09 12:15:48 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428037964 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1428037964 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.45613395
Short name T812
Test name
Test status
Simulation time 977175235 ps
CPU time 34.74 seconds
Started Feb 09 12:15:04 PM UTC 25
Finished Feb 09 12:15:40 PM UTC 25
Peak memory 249860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45613395 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.45613395 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.3286169528
Short name T855
Test name
Test status
Simulation time 66798778105 ps
CPU time 1207.42 seconds
Started Feb 09 12:11:54 PM UTC 25
Finished Feb 09 12:32:15 PM UTC 25
Peak memory 268360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286169528 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3286169528 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.234020450
Short name T819
Test name
Test status
Simulation time 19747259935 ps
CPU time 235.7 seconds
Started Feb 09 12:15:07 PM UTC 25
Finished Feb 09 12:19:07 PM UTC 25
Peak memory 362512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234020450 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.234020450 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.2865626109
Short name T821
Test name
Test status
Simulation time 52541530463 ps
CPU time 263.13 seconds
Started Feb 09 12:15:23 PM UTC 25
Finished Feb 09 12:19:49 PM UTC 25
Peak memory 358404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865626109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.kmac_error.2865626109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.3624130007
Short name T814
Test name
Test status
Simulation time 2261266709 ps
CPU time 12.31 seconds
Started Feb 09 12:15:36 PM UTC 25
Finished Feb 09 12:15:50 PM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624130007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3624130007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.4023077321
Short name T59
Test name
Test status
Simulation time 60255480 ps
CPU time 2.1 seconds
Started Feb 09 12:15:41 PM UTC 25
Finished Feb 09 12:15:45 PM UTC 25
Peak memory 235368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023077321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.4023077321 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.525987999
Short name T965
Test name
Test status
Simulation time 315914947756 ps
CPU time 3313.37 seconds
Started Feb 09 12:11:40 PM UTC 25
Finished Feb 09 01:07:28 PM UTC 25
Peak memory 3903548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525987999 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.525987999 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.2702424438
Short name T805
Test name
Test status
Simulation time 11369968616 ps
CPU time 182.98 seconds
Started Feb 09 12:11:40 PM UTC 25
Finished Feb 09 12:14:46 PM UTC 25
Peak memory 366604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702424438 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2702424438 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.1345918801
Short name T798
Test name
Test status
Simulation time 852394107 ps
CPU time 13.55 seconds
Started Feb 09 12:11:24 PM UTC 25
Finished Feb 09 12:11:39 PM UTC 25
Peak memory 230788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345918801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.kmac_smoke.1345918801 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.1102840730
Short name T856
Test name
Test status
Simulation time 167152079372 ps
CPU time 1033.16 seconds
Started Feb 09 12:15:41 PM UTC 25
Finished Feb 09 12:33:06 PM UTC 25
Peak memory 1099856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102840730 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1102840730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_kmac.1516648550
Short name T806
Test name
Test status
Simulation time 67337200 ps
CPU time 5.56 seconds
Started Feb 09 12:14:47 PM UTC 25
Finished Feb 09 12:14:53 PM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1516648550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.kmac_test_vectors_kmac.1516648550 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_kmac_xof.1707759348
Short name T807
Test name
Test status
Simulation time 1243481849 ps
CPU time 7.26 seconds
Started Feb 09 12:14:55 PM UTC 25
Finished Feb 09 12:15:03 PM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1707759348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 38.kmac_test_vectors_kmac_xof.1707759348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_224.4102658260
Short name T890
Test name
Test status
Simulation time 37802514110 ps
CPU time 1874.71 seconds
Started Feb 09 12:12:01 PM UTC 25
Finished Feb 09 12:43:37 PM UTC 25
Peak memory 1163256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102658260 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.4102658260 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_256.2728601530
Short name T891
Test name
Test status
Simulation time 36329650793 ps
CPU time 1869.64 seconds
Started Feb 09 12:12:23 PM UTC 25
Finished Feb 09 12:43:54 PM UTC 25
Peak memory 1153016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728601530 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.2728601530 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_384.1358307358
Short name T870
Test name
Test status
Simulation time 97951806272 ps
CPU time 1489.59 seconds
Started Feb 09 12:12:41 PM UTC 25
Finished Feb 09 12:37:48 PM UTC 25
Peak memory 935988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358307358 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1358307358 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_512.1514131493
Short name T843
Test name
Test status
Simulation time 67171181723 ps
CPU time 952.32 seconds
Started Feb 09 12:12:54 PM UTC 25
Finished Feb 09 12:28:58 PM UTC 25
Peak memory 704444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514131493 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.1514131493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_shake_128.876243054
Short name T1070
Test name
Test status
Simulation time 1083112196270 ps
CPU time 7150.77 seconds
Started Feb 09 12:13:38 PM UTC 25
Finished Feb 09 02:14:00 PM UTC 25
Peak memory 7923800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876243054 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.876243054 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/38.kmac_test_vectors_shake_256.1042145603
Short name T1023
Test name
Test status
Simulation time 175376553320 ps
CPU time 4376.02 seconds
Started Feb 09 12:14:31 PM UTC 25
Finished Feb 09 01:28:13 PM UTC 25
Peak memory 2269116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042145603 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1042145603 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.490105450
Short name T831
Test name
Test status
Simulation time 18555451 ps
CPU time 1.29 seconds
Started Feb 09 12:23:48 PM UTC 25
Finished Feb 09 12:23:50 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490105450 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.490105450 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.1234861004
Short name T832
Test name
Test status
Simulation time 135263266232 ps
CPU time 202.99 seconds
Started Feb 09 12:20:27 PM UTC 25
Finished Feb 09 12:23:53 PM UTC 25
Peak memory 405512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234861004 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1234861004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.394481146
Short name T833
Test name
Test status
Simulation time 4459302239 ps
CPU time 438.38 seconds
Started Feb 09 12:16:56 PM UTC 25
Finished Feb 09 12:24:21 PM UTC 25
Peak memory 243728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394481146 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.394481146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.2124445107
Short name T830
Test name
Test status
Simulation time 75761193417 ps
CPU time 191.76 seconds
Started Feb 09 12:20:32 PM UTC 25
Finished Feb 09 12:23:47 PM UTC 25
Peak memory 352240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124445107 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2124445107 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.1067332891
Short name T837
Test name
Test status
Simulation time 31665258335 ps
CPU time 252.64 seconds
Started Feb 09 12:21:08 PM UTC 25
Finished Feb 09 12:25:25 PM UTC 25
Peak memory 448584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067332891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.kmac_error.1067332891 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.2304287278
Short name T829
Test name
Test status
Simulation time 1379077621 ps
CPU time 13 seconds
Started Feb 09 12:23:09 PM UTC 25
Finished Feb 09 12:23:23 PM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304287278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2304287278 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.3740835112
Short name T89
Test name
Test status
Simulation time 121274671 ps
CPU time 2.2 seconds
Started Feb 09 12:23:24 PM UTC 25
Finished Feb 09 12:23:28 PM UTC 25
Peak memory 235320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740835112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3740835112 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.55716574
Short name T888
Test name
Test status
Simulation time 122055751461 ps
CPU time 1620.64 seconds
Started Feb 09 12:15:51 PM UTC 25
Finished Feb 09 12:43:11 PM UTC 25
Peak memory 1882128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55716574 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.55716574 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.1176051532
Short name T828
Test name
Test status
Simulation time 58230842632 ps
CPU time 398.16 seconds
Started Feb 09 12:16:23 PM UTC 25
Finished Feb 09 12:23:07 PM UTC 25
Peak memory 514068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176051532 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1176051532 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.3149539543
Short name T815
Test name
Test status
Simulation time 2847956092 ps
CPU time 31.9 seconds
Started Feb 09 12:15:49 PM UTC 25
Finished Feb 09 12:16:22 PM UTC 25
Peak memory 232904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149539543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.kmac_smoke.3149539543 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.3353578992
Short name T908
Test name
Test status
Simulation time 631632589563 ps
CPU time 1612.9 seconds
Started Feb 09 12:23:28 PM UTC 25
Finished Feb 09 12:50:39 PM UTC 25
Peak memory 1348000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353578992 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3353578992 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_kmac.1578521584
Short name T824
Test name
Test status
Simulation time 1063574534 ps
CPU time 8.18 seconds
Started Feb 09 12:20:08 PM UTC 25
Finished Feb 09 12:20:18 PM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1578521584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.kmac_test_vectors_kmac.1578521584 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_kmac_xof.353891095
Short name T825
Test name
Test status
Simulation time 257200265 ps
CPU time 5.1 seconds
Started Feb 09 12:20:19 PM UTC 25
Finished Feb 09 12:20:26 PM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=353891095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac_xof.353891095 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_224.3609500390
Short name T899
Test name
Test status
Simulation time 133522459897 ps
CPU time 1757.99 seconds
Started Feb 09 12:17:35 PM UTC 25
Finished Feb 09 12:47:13 PM UTC 25
Peak memory 1200132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609500390 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.3609500390 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_256.329866793
Short name T929
Test name
Test status
Simulation time 474594422546 ps
CPU time 2292.5 seconds
Started Feb 09 12:18:38 PM UTC 25
Finished Feb 09 12:57:15 PM UTC 25
Peak memory 3096508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329866793 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.329866793 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_384.1773289156
Short name T873
Test name
Test status
Simulation time 28903083991 ps
CPU time 1179.92 seconds
Started Feb 09 12:19:08 PM UTC 25
Finished Feb 09 12:39:01 PM UTC 25
Peak memory 948164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773289156 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1773289156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_512.2664714180
Short name T867
Test name
Test status
Simulation time 38386200409 ps
CPU time 1046.03 seconds
Started Feb 09 12:19:21 PM UTC 25
Finished Feb 09 12:37:00 PM UTC 25
Peak memory 718852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664714180 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2664714180 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_shake_128.805820219
Short name T1076
Test name
Test status
Simulation time 1594118041786 ps
CPU time 8435.55 seconds
Started Feb 09 12:19:51 PM UTC 25
Finished Feb 09 02:41:51 PM UTC 25
Peak memory 7804964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805820219 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.805820219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/39.kmac_test_vectors_shake_256.1893030363
Short name T1050
Test name
Test status
Simulation time 580500933583 ps
CPU time 5303.25 seconds
Started Feb 09 12:20:03 PM UTC 25
Finished Feb 09 01:49:19 PM UTC 25
Peak memory 6410292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893030363 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1893030363 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.4149164751
Short name T190
Test name
Test status
Simulation time 19166250 ps
CPU time 1.21 seconds
Started Feb 09 08:48:10 AM UTC 25
Finished Feb 09 08:48:13 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149164751 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.4149164751 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.3008683551
Short name T195
Test name
Test status
Simulation time 14416561020 ps
CPU time 183.53 seconds
Started Feb 09 08:46:55 AM UTC 25
Finished Feb 09 08:50:03 AM UTC 25
Peak memory 288728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008683551 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3008683551 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.3197459155
Short name T196
Test name
Test status
Simulation time 59320649739 ps
CPU time 212.75 seconds
Started Feb 09 08:46:55 AM UTC 25
Finished Feb 09 08:50:32 AM UTC 25
Peak memory 403544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197459155 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3197459155 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.3646482064
Short name T138
Test name
Test status
Simulation time 358090317686 ps
CPU time 1122.13 seconds
Started Feb 09 08:45:18 AM UTC 25
Finished Feb 09 09:04:14 AM UTC 25
Peak memory 268300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646482064 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3646482064 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.2870312240
Short name T188
Test name
Test status
Simulation time 570580636 ps
CPU time 21.41 seconds
Started Feb 09 08:47:07 AM UTC 25
Finished Feb 09 08:47:30 AM UTC 25
Peak memory 235276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870312240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2870312240 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.601546403
Short name T191
Test name
Test status
Simulation time 10347544603 ps
CPU time 45.82 seconds
Started Feb 09 08:47:31 AM UTC 25
Finished Feb 09 08:48:18 AM UTC 25
Peak memory 235312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601546403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.601546403 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.603206948
Short name T192
Test name
Test status
Simulation time 8560179087 ps
CPU time 58.15 seconds
Started Feb 09 08:47:31 AM UTC 25
Finished Feb 09 08:48:31 AM UTC 25
Peak memory 230788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603206948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.603206948 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3961205346
Short name T194
Test name
Test status
Simulation time 5912854057 ps
CPU time 134.34 seconds
Started Feb 09 08:46:55 AM UTC 25
Finished Feb 09 08:49:13 AM UTC 25
Peak memory 276440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961205346 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3961205346 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.1756531344
Short name T27
Test name
Test status
Simulation time 19056833944 ps
CPU time 318.61 seconds
Started Feb 09 08:47:06 AM UTC 25
Finished Feb 09 08:52:29 AM UTC 25
Peak memory 350208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756531344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.kmac_error.1756531344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.2075091855
Short name T63
Test name
Test status
Simulation time 8767555768 ps
CPU time 17.9 seconds
Started Feb 09 08:47:06 AM UTC 25
Finished Feb 09 08:47:25 AM UTC 25
Peak memory 230776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075091855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2075091855 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.3095244974
Short name T61
Test name
Test status
Simulation time 56610580 ps
CPU time 2.12 seconds
Started Feb 09 08:47:31 AM UTC 25
Finished Feb 09 08:47:34 AM UTC 25
Peak memory 230604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095244974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3095244974 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.3589243182
Short name T288
Test name
Test status
Simulation time 25086246607 ps
CPU time 2239.58 seconds
Started Feb 09 08:44:53 AM UTC 25
Finished Feb 09 09:22:36 AM UTC 25
Peak memory 1722384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589243182 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.3589243182 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.1208869369
Short name T75
Test name
Test status
Simulation time 7542757562 ps
CPU time 67.96 seconds
Started Feb 09 08:46:55 AM UTC 25
Finished Feb 09 08:48:06 AM UTC 25
Peak memory 262536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208869369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.kmac_mubi.1208869369 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.100523414
Short name T70
Test name
Test status
Simulation time 6602543979 ps
CPU time 33.29 seconds
Started Feb 09 08:48:07 AM UTC 25
Finished Feb 09 08:48:42 AM UTC 25
Peak memory 265304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100523414 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.100523414 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.2757133978
Short name T32
Test name
Test status
Simulation time 71112287943 ps
CPU time 367.2 seconds
Started Feb 09 08:44:56 AM UTC 25
Finished Feb 09 08:51:08 AM UTC 25
Peak memory 528392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757133978 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2757133978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.3276534611
Short name T174
Test name
Test status
Simulation time 10365474253 ps
CPU time 64.17 seconds
Started Feb 09 08:44:53 AM UTC 25
Finished Feb 09 08:45:59 AM UTC 25
Peak memory 234932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276534611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.kmac_smoke.3276534611 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.3010012039
Short name T44
Test name
Test status
Simulation time 146380627176 ps
CPU time 619.75 seconds
Started Feb 09 08:47:35 AM UTC 25
Finished Feb 09 08:58:03 AM UTC 25
Peak memory 326052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010012039 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3010012039 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.2528525309
Short name T185
Test name
Test status
Simulation time 68841954 ps
CPU time 5.27 seconds
Started Feb 09 08:46:33 AM UTC 25
Finished Feb 09 08:46:40 AM UTC 25
Peak memory 230724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2528525309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.kmac_test_vectors_kmac.2528525309 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.3680259802
Short name T187
Test name
Test status
Simulation time 281807393 ps
CPU time 5.26 seconds
Started Feb 09 08:46:40 AM UTC 25
Finished Feb 09 08:46:47 AM UTC 25
Peak memory 230820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3680259802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 4.kmac_test_vectors_kmac_xof.3680259802 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.552355800
Short name T246
Test name
Test status
Simulation time 36792517573 ps
CPU time 1574.73 seconds
Started Feb 09 08:45:18 AM UTC 25
Finished Feb 09 09:11:50 AM UTC 25
Peak memory 1179660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552355800 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.552355800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.1255580964
Short name T307
Test name
Test status
Simulation time 79666614215 ps
CPU time 2397.54 seconds
Started Feb 09 08:45:23 AM UTC 25
Finished Feb 09 09:25:47 AM UTC 25
Peak memory 3051520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255580964 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1255580964 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3989333944
Short name T284
Test name
Test status
Simulation time 148150911147 ps
CPU time 2107.19 seconds
Started Feb 09 08:45:42 AM UTC 25
Finished Feb 09 09:21:13 AM UTC 25
Peak memory 2437024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989333944 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3989333944 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.768145813
Short name T221
Test name
Test status
Simulation time 10800214648 ps
CPU time 846.03 seconds
Started Feb 09 08:46:00 AM UTC 25
Finished Feb 09 09:00:16 AM UTC 25
Peak memory 702404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768145813 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.768145813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.1754037970
Short name T569
Test name
Test status
Simulation time 1021223040163 ps
CPU time 7591.67 seconds
Started Feb 09 08:46:09 AM UTC 25
Finished Feb 09 10:53:59 AM UTC 25
Peak memory 7811100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754037970 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1754037970 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2933593874
Short name T382
Test name
Test status
Simulation time 171196669175 ps
CPU time 4028.9 seconds
Started Feb 09 08:46:30 AM UTC 25
Finished Feb 09 09:54:23 AM UTC 25
Peak memory 2199488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933593874 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2933593874 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.2299001054
Short name T849
Test name
Test status
Simulation time 16888193 ps
CPU time 1.17 seconds
Started Feb 09 12:30:40 PM UTC 25
Finished Feb 09 12:30:43 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299001054 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2299001054 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.1980850302
Short name T863
Test name
Test status
Simulation time 63226946560 ps
CPU time 434.88 seconds
Started Feb 09 12:27:43 PM UTC 25
Finished Feb 09 12:35:04 PM UTC 25
Peak memory 518144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980850302 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1980850302 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.3305557722
Short name T845
Test name
Test status
Simulation time 9189947221 ps
CPU time 317.87 seconds
Started Feb 09 12:24:55 PM UTC 25
Finished Feb 09 12:30:17 PM UTC 25
Peak memory 241676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305557722 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3305557722 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.602582653
Short name T859
Test name
Test status
Simulation time 8315062462 ps
CPU time 307.8 seconds
Started Feb 09 12:29:00 PM UTC 25
Finished Feb 09 12:34:12 PM UTC 25
Peak memory 337940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602582653 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.602582653 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.1957926907
Short name T864
Test name
Test status
Simulation time 4042428775 ps
CPU time 343 seconds
Started Feb 09 12:29:41 PM UTC 25
Finished Feb 09 12:35:29 PM UTC 25
Peak memory 370688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957926907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 40.kmac_error.1957926907 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.825767455
Short name T846
Test name
Test status
Simulation time 3112070299 ps
CPU time 16.32 seconds
Started Feb 09 12:30:18 PM UTC 25
Finished Feb 09 12:30:36 PM UTC 25
Peak memory 230636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825767455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.825767455 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.3546457086
Short name T848
Test name
Test status
Simulation time 41077403 ps
CPU time 1.58 seconds
Started Feb 09 12:30:37 PM UTC 25
Finished Feb 09 12:30:40 PM UTC 25
Peak memory 229876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546457086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3546457086 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.3225121093
Short name T928
Test name
Test status
Simulation time 51720880107 ps
CPU time 1974.07 seconds
Started Feb 09 12:23:54 PM UTC 25
Finished Feb 09 12:57:10 PM UTC 25
Peak memory 2553864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225121093 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.3225121093 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.2006392090
Short name T852
Test name
Test status
Simulation time 55562339870 ps
CPU time 432.02 seconds
Started Feb 09 12:24:21 PM UTC 25
Finished Feb 09 12:31:39 PM UTC 25
Peak memory 509960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006392090 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2006392090 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.1818978272
Short name T834
Test name
Test status
Simulation time 929147060 ps
CPU time 60.88 seconds
Started Feb 09 12:23:51 PM UTC 25
Finished Feb 09 12:24:53 PM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818978272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 40.kmac_smoke.1818978272 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.727340757
Short name T943
Test name
Test status
Simulation time 72924459355 ps
CPU time 1876.13 seconds
Started Feb 09 12:30:39 PM UTC 25
Finished Feb 09 01:02:18 PM UTC 25
Peak memory 786448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727340757 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.727340757 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_kmac.1763152144
Short name T841
Test name
Test status
Simulation time 427835836 ps
CPU time 7.18 seconds
Started Feb 09 12:27:25 PM UTC 25
Finished Feb 09 12:27:33 PM UTC 25
Peak memory 230712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1763152144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.kmac_test_vectors_kmac.1763152144 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_kmac_xof.3901314101
Short name T842
Test name
Test status
Simulation time 316495361 ps
CPU time 7.32 seconds
Started Feb 09 12:27:34 PM UTC 25
Finished Feb 09 12:27:42 PM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3901314101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.kmac_test_vectors_kmac_xof.3901314101 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_224.1440826475
Short name T980
Test name
Test status
Simulation time 100347702917 ps
CPU time 2877.76 seconds
Started Feb 09 12:25:01 PM UTC 25
Finished Feb 09 01:13:31 PM UTC 25
Peak memory 3217404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440826475 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.1440826475 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_256.2658498536
Short name T967
Test name
Test status
Simulation time 323048842821 ps
CPU time 2511.61 seconds
Started Feb 09 12:25:14 PM UTC 25
Finished Feb 09 01:07:32 PM UTC 25
Peak memory 3119040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658498536 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2658498536 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_384.2788670600
Short name T917
Test name
Test status
Simulation time 232751523295 ps
CPU time 1632.24 seconds
Started Feb 09 12:25:26 PM UTC 25
Finished Feb 09 12:52:55 PM UTC 25
Peak memory 2385856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788670600 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2788670600 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_512.4288612109
Short name T876
Test name
Test status
Simulation time 9875914395 ps
CPU time 823.51 seconds
Started Feb 09 12:25:52 PM UTC 25
Finished Feb 09 12:39:45 PM UTC 25
Peak memory 710596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288612109 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.4288612109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_shake_128.2820756935
Short name T1055
Test name
Test status
Simulation time 105170606837 ps
CPU time 5028.57 seconds
Started Feb 09 12:27:06 PM UTC 25
Finished Feb 09 01:51:49 PM UTC 25
Peak memory 2682928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820756935 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2820756935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/40.kmac_test_vectors_shake_256.3665081883
Short name T1048
Test name
Test status
Simulation time 256742103525 ps
CPU time 4637.18 seconds
Started Feb 09 12:27:18 PM UTC 25
Finished Feb 09 01:45:27 PM UTC 25
Peak memory 2258876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665081883 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3665081883 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.2947965459
Short name T868
Test name
Test status
Simulation time 89652630 ps
CPU time 1.27 seconds
Started Feb 09 12:37:02 PM UTC 25
Finished Feb 09 12:37:04 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947965459 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2947965459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.1777455448
Short name T871
Test name
Test status
Simulation time 17914879804 ps
CPU time 209.07 seconds
Started Feb 09 12:34:29 PM UTC 25
Finished Feb 09 12:38:01 PM UTC 25
Peak memory 428040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777455448 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1777455448 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.3936822769
Short name T862
Test name
Test status
Simulation time 1483781143 ps
CPU time 171.9 seconds
Started Feb 09 12:31:41 PM UTC 25
Finished Feb 09 12:34:36 PM UTC 25
Peak memory 235184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936822769 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3936822769 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.2794308704
Short name T880
Test name
Test status
Simulation time 57126697664 ps
CPU time 363.85 seconds
Started Feb 09 12:34:37 PM UTC 25
Finished Feb 09 12:40:46 PM UTC 25
Peak memory 456720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794308704 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2794308704 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.3776526538
Short name T877
Test name
Test status
Simulation time 3432298199 ps
CPU time 305.69 seconds
Started Feb 09 12:35:05 PM UTC 25
Finished Feb 09 12:40:15 PM UTC 25
Peak memory 352320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776526538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.kmac_error.3776526538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.3569638852
Short name T865
Test name
Test status
Simulation time 1403476139 ps
CPU time 13.57 seconds
Started Feb 09 12:35:30 PM UTC 25
Finished Feb 09 12:35:45 PM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569638852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3569638852 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.1388638271
Short name T866
Test name
Test status
Simulation time 89007525 ps
CPU time 2.63 seconds
Started Feb 09 12:35:46 PM UTC 25
Finished Feb 09 12:35:50 PM UTC 25
Peak memory 230788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388638271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1388638271 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.495243679
Short name T935
Test name
Test status
Simulation time 530269165710 ps
CPU time 1700.43 seconds
Started Feb 09 12:30:57 PM UTC 25
Finished Feb 09 12:59:35 PM UTC 25
Peak memory 2486416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495243679 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.495243679 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.462423622
Short name T854
Test name
Test status
Simulation time 3261547052 ps
CPU time 68.87 seconds
Started Feb 09 12:31:02 PM UTC 25
Finished Feb 09 12:32:13 PM UTC 25
Peak memory 256076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462423622 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.462423622 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.3510250857
Short name T851
Test name
Test status
Simulation time 2404758633 ps
CPU time 16.55 seconds
Started Feb 09 12:30:44 PM UTC 25
Finished Feb 09 12:31:02 PM UTC 25
Peak memory 230916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510250857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.kmac_smoke.3510250857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.4254647246
Short name T869
Test name
Test status
Simulation time 3961999288 ps
CPU time 96.33 seconds
Started Feb 09 12:35:51 PM UTC 25
Finished Feb 09 12:37:30 PM UTC 25
Peak memory 299028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254647246 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.4254647246 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_kmac.4215305563
Short name T860
Test name
Test status
Simulation time 975558857 ps
CPU time 7.41 seconds
Started Feb 09 12:34:13 PM UTC 25
Finished Feb 09 12:34:22 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4215305563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.kmac_test_vectors_kmac.4215305563 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_kmac_xof.447541358
Short name T861
Test name
Test status
Simulation time 323198082 ps
CPU time 4.34 seconds
Started Feb 09 12:34:22 PM UTC 25
Finished Feb 09 12:34:28 PM UTC 25
Peak memory 230748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=447541358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac_xof.447541358 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_224.698051636
Short name T975
Test name
Test status
Simulation time 67221813380 ps
CPU time 2393.58 seconds
Started Feb 09 12:32:00 PM UTC 25
Finished Feb 09 01:12:19 PM UTC 25
Peak memory 3225528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698051636 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.698051636 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_256.2293796314
Short name T930
Test name
Test status
Simulation time 69974609054 ps
CPU time 1509.15 seconds
Started Feb 09 12:32:15 PM UTC 25
Finished Feb 09 12:57:40 PM UTC 25
Peak memory 1134592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293796314 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.2293796314 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_384.2504844655
Short name T919
Test name
Test status
Simulation time 27291642186 ps
CPU time 1294.56 seconds
Started Feb 09 12:32:16 PM UTC 25
Finished Feb 09 12:54:05 PM UTC 25
Peak memory 931900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504844655 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2504844655 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_512.3812917266
Short name T931
Test name
Test status
Simulation time 42564147063 ps
CPU time 1474.69 seconds
Started Feb 09 12:33:07 PM UTC 25
Finished Feb 09 12:58:00 PM UTC 25
Peak memory 1714172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812917266 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3812917266 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_128.3118187103
Short name T1075
Test name
Test status
Simulation time 267693501582 ps
CPU time 7397.79 seconds
Started Feb 09 12:33:29 PM UTC 25
Finished Feb 09 02:37:58 PM UTC 25
Peak memory 7872444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118187103 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3118187103 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_256.719059577
Short name T1073
Test name
Test status
Simulation time 2107694608735 ps
CPU time 6638.4 seconds
Started Feb 09 12:33:39 PM UTC 25
Finished Feb 09 02:25:26 PM UTC 25
Peak memory 6526912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719059577 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.719059577 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.725724327
Short name T886
Test name
Test status
Simulation time 35745116 ps
CPU time 1.15 seconds
Started Feb 09 12:42:31 PM UTC 25
Finished Feb 09 12:42:33 PM UTC 25
Peak memory 214468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725724327 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.725724327 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.3456925097
Short name T896
Test name
Test status
Simulation time 13377384470 ps
CPU time 302.45 seconds
Started Feb 09 12:40:47 PM UTC 25
Finished Feb 09 12:45:54 PM UTC 25
Peak memory 321544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456925097 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3456925097 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.3514375247
Short name T914
Test name
Test status
Simulation time 109241966434 ps
CPU time 866.06 seconds
Started Feb 09 12:38:02 PM UTC 25
Finished Feb 09 12:52:38 PM UTC 25
Peak memory 264180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514375247 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3514375247 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.3192194769
Short name T894
Test name
Test status
Simulation time 27140992751 ps
CPU time 234.23 seconds
Started Feb 09 12:40:52 PM UTC 25
Finished Feb 09 12:44:50 PM UTC 25
Peak memory 372808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192194769 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3192194769 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.1377956678
Short name T885
Test name
Test status
Simulation time 2309689768 ps
CPU time 92.46 seconds
Started Feb 09 12:40:55 PM UTC 25
Finished Feb 09 12:42:30 PM UTC 25
Peak memory 301060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377956678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.kmac_error.1377956678 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.321034213
Short name T884
Test name
Test status
Simulation time 2366402277 ps
CPU time 11.44 seconds
Started Feb 09 12:42:08 PM UTC 25
Finished Feb 09 12:42:21 PM UTC 25
Peak memory 230624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321034213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.321034213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.416127889
Short name T60
Test name
Test status
Simulation time 118827497 ps
CPU time 1.94 seconds
Started Feb 09 12:42:22 PM UTC 25
Finished Feb 09 12:42:25 PM UTC 25
Peak memory 234764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416127889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.416127889 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1201090774
Short name T963
Test name
Test status
Simulation time 55120504662 ps
CPU time 1740.77 seconds
Started Feb 09 12:37:30 PM UTC 25
Finished Feb 09 01:06:50 PM UTC 25
Peak memory 2342924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201090774 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1201090774 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.3223656943
Short name T895
Test name
Test status
Simulation time 42219779890 ps
CPU time 422.68 seconds
Started Feb 09 12:37:50 PM UTC 25
Finished Feb 09 12:44:58 PM UTC 25
Peak memory 397328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223656943 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3223656943 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.4167001215
Short name T872
Test name
Test status
Simulation time 11539762029 ps
CPU time 86.71 seconds
Started Feb 09 12:37:05 PM UTC 25
Finished Feb 09 12:38:34 PM UTC 25
Peak memory 234892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167001215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.kmac_smoke.4167001215 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.168378074
Short name T911
Test name
Test status
Simulation time 63705773965 ps
CPU time 507.41 seconds
Started Feb 09 12:42:27 PM UTC 25
Finished Feb 09 12:51:01 PM UTC 25
Peak memory 377248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168378074 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.168378074 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_kmac.1550412791
Short name T879
Test name
Test status
Simulation time 245079886 ps
CPU time 5.78 seconds
Started Feb 09 12:40:33 PM UTC 25
Finished Feb 09 12:40:40 PM UTC 25
Peak memory 230872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1550412791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.kmac_test_vectors_kmac.1550412791 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_kmac_xof.1877940245
Short name T881
Test name
Test status
Simulation time 992646235 ps
CPU time 8.42 seconds
Started Feb 09 12:40:42 PM UTC 25
Finished Feb 09 12:40:51 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1877940245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 42.kmac_test_vectors_kmac_xof.1877940245 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_224.4243416639
Short name T989
Test name
Test status
Simulation time 97272669103 ps
CPU time 2323.57 seconds
Started Feb 09 12:38:35 PM UTC 25
Finished Feb 09 01:17:42 PM UTC 25
Peak memory 3254212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243416639 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.4243416639 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_256.2947467902
Short name T952
Test name
Test status
Simulation time 18466515541 ps
CPU time 1562.84 seconds
Started Feb 09 12:39:02 PM UTC 25
Finished Feb 09 01:05:22 PM UTC 25
Peak memory 1159232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947467902 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.2947467902 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_384.1518278969
Short name T956
Test name
Test status
Simulation time 29118833256 ps
CPU time 1576.15 seconds
Started Feb 09 12:39:08 PM UTC 25
Finished Feb 09 01:05:43 PM UTC 25
Peak memory 954304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518278969 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.1518278969 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_512.3900682598
Short name T933
Test name
Test status
Simulation time 96538397774 ps
CPU time 1149.24 seconds
Started Feb 09 12:39:21 PM UTC 25
Finished Feb 09 12:58:43 PM UTC 25
Peak memory 1716284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900682598 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3900682598 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_shake_128.2082107664
Short name T1064
Test name
Test status
Simulation time 106942882641 ps
CPU time 5008.85 seconds
Started Feb 09 12:39:47 PM UTC 25
Finished Feb 09 02:04:09 PM UTC 25
Peak memory 2734068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082107664 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.2082107664 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/42.kmac_test_vectors_shake_256.3266334077
Short name T1042
Test name
Test status
Simulation time 54280382435 ps
CPU time 3618.1 seconds
Started Feb 09 12:40:17 PM UTC 25
Finished Feb 09 01:41:14 PM UTC 25
Peak memory 2242492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266334077 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.3266334077 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.3236834418
Short name T905
Test name
Test status
Simulation time 47093403 ps
CPU time 1.2 seconds
Started Feb 09 12:49:49 PM UTC 25
Finished Feb 09 12:49:51 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236834418 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3236834418 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.1470991905
Short name T906
Test name
Test status
Simulation time 36203815929 ps
CPU time 213.95 seconds
Started Feb 09 12:46:15 PM UTC 25
Finished Feb 09 12:49:52 PM UTC 25
Peak memory 446536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470991905 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1470991905 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.1068813623
Short name T926
Test name
Test status
Simulation time 29270877640 ps
CPU time 766.57 seconds
Started Feb 09 12:43:21 PM UTC 25
Finished Feb 09 12:56:17 PM UTC 25
Peak memory 253964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068813623 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1068813623 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2513720136
Short name T913
Test name
Test status
Simulation time 12539657447 ps
CPU time 274.27 seconds
Started Feb 09 12:47:13 PM UTC 25
Finished Feb 09 12:51:52 PM UTC 25
Peak memory 331856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513720136 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2513720136 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.932669937
Short name T912
Test name
Test status
Simulation time 23674153596 ps
CPU time 192.46 seconds
Started Feb 09 12:48:33 PM UTC 25
Finished Feb 09 12:51:49 PM UTC 25
Peak memory 403460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932669937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.kmac_error.932669937 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.2720737976
Short name T902
Test name
Test status
Simulation time 7136218951 ps
CPU time 18.13 seconds
Started Feb 09 12:49:24 PM UTC 25
Finished Feb 09 12:49:43 PM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720737976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2720737976 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.2358694908
Short name T904
Test name
Test status
Simulation time 153606466 ps
CPU time 1.81 seconds
Started Feb 09 12:49:44 PM UTC 25
Finished Feb 09 12:49:48 PM UTC 25
Peak memory 229876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358694908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2358694908 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.1025282048
Short name T939
Test name
Test status
Simulation time 125913502324 ps
CPU time 1082.23 seconds
Started Feb 09 12:43:03 PM UTC 25
Finished Feb 09 01:01:17 PM UTC 25
Peak memory 1662960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025282048 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.1025282048 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.2309167306
Short name T909
Test name
Test status
Simulation time 28016218902 ps
CPU time 444.78 seconds
Started Feb 09 12:43:12 PM UTC 25
Finished Feb 09 12:50:42 PM UTC 25
Peak memory 606228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309167306 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2309167306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.3655489355
Short name T887
Test name
Test status
Simulation time 2334965928 ps
CPU time 26.59 seconds
Started Feb 09 12:42:34 PM UTC 25
Finished Feb 09 12:43:02 PM UTC 25
Peak memory 230904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655489355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 43.kmac_smoke.3655489355 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.4287183035
Short name T948
Test name
Test status
Simulation time 35016229491 ps
CPU time 845.15 seconds
Started Feb 09 12:49:49 PM UTC 25
Finished Feb 09 01:04:04 PM UTC 25
Peak memory 874880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287183035 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4287183035 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_kmac.1155658081
Short name T897
Test name
Test status
Simulation time 1003465770 ps
CPU time 7.86 seconds
Started Feb 09 12:45:56 PM UTC 25
Finished Feb 09 12:46:05 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1155658081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.kmac_test_vectors_kmac.1155658081 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_kmac_xof.356301530
Short name T898
Test name
Test status
Simulation time 236812462 ps
CPU time 7.38 seconds
Started Feb 09 12:46:06 PM UTC 25
Finished Feb 09 12:46:14 PM UTC 25
Peak memory 230812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=356301530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac_xof.356301530 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_224.2677704483
Short name T1001
Test name
Test status
Simulation time 130065068076 ps
CPU time 2276.14 seconds
Started Feb 09 12:43:38 PM UTC 25
Finished Feb 09 01:22:00 PM UTC 25
Peak memory 3184580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677704483 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.2677704483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_256.2923972881
Short name T1008
Test name
Test status
Simulation time 93844813599 ps
CPU time 2481.59 seconds
Started Feb 09 12:43:55 PM UTC 25
Finished Feb 09 01:25:43 PM UTC 25
Peak memory 3022852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923972881 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2923972881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_384.2479888738
Short name T991
Test name
Test status
Simulation time 74214441523 ps
CPU time 2114.92 seconds
Started Feb 09 12:44:26 PM UTC 25
Finished Feb 09 01:20:05 PM UTC 25
Peak memory 2441152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479888738 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2479888738 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_512.2936562437
Short name T938
Test name
Test status
Simulation time 73367571576 ps
CPU time 969.78 seconds
Started Feb 09 12:44:32 PM UTC 25
Finished Feb 09 01:00:53 PM UTC 25
Peak memory 714692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936562437 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.2936562437 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_shake_128.1714442503
Short name T1066
Test name
Test status
Simulation time 104868307132 ps
CPU time 4825.93 seconds
Started Feb 09 12:44:51 PM UTC 25
Finished Feb 09 02:06:08 PM UTC 25
Peak memory 2672632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714442503 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.1714442503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/43.kmac_test_vectors_shake_256.3227149253
Short name T1056
Test name
Test status
Simulation time 179895511538 ps
CPU time 3979.18 seconds
Started Feb 09 12:44:59 PM UTC 25
Finished Feb 09 01:52:00 PM UTC 25
Peak memory 2228152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227149253 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3227149253 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.547931647
Short name T924
Test name
Test status
Simulation time 20617460 ps
CPU time 1.18 seconds
Started Feb 09 12:55:09 PM UTC 25
Finished Feb 09 12:55:11 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547931647 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.547931647 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.387320169
Short name T920
Test name
Test status
Simulation time 3961664438 ps
CPU time 107.02 seconds
Started Feb 09 12:52:56 PM UTC 25
Finished Feb 09 12:54:46 PM UTC 25
Peak memory 303112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387320169 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.387320169 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.3621281790
Short name T960
Test name
Test status
Simulation time 90682901893 ps
CPU time 952.79 seconds
Started Feb 09 12:50:40 PM UTC 25
Finished Feb 09 01:06:44 PM UTC 25
Peak memory 264200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621281790 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3621281790 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.178049847
Short name T934
Test name
Test status
Simulation time 26053156220 ps
CPU time 381.4 seconds
Started Feb 09 12:53:03 PM UTC 25
Finished Feb 09 12:59:30 PM UTC 25
Peak memory 473104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178049847 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.178049847 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.3885097118
Short name T932
Test name
Test status
Simulation time 3027841285 ps
CPU time 248.47 seconds
Started Feb 09 12:54:06 PM UTC 25
Finished Feb 09 12:58:18 PM UTC 25
Peak memory 340024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885097118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.kmac_error.3885097118 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.2910945635
Short name T922
Test name
Test status
Simulation time 1773136123 ps
CPU time 17.88 seconds
Started Feb 09 12:54:46 PM UTC 25
Finished Feb 09 12:55:05 PM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910945635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2910945635 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.1830147826
Short name T923
Test name
Test status
Simulation time 92982420 ps
CPU time 2.08 seconds
Started Feb 09 12:55:04 PM UTC 25
Finished Feb 09 12:55:08 PM UTC 25
Peak memory 235284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830147826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1830147826 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.1707461529
Short name T907
Test name
Test status
Simulation time 5352006148 ps
CPU time 37.13 seconds
Started Feb 09 12:49:53 PM UTC 25
Finished Feb 09 12:50:32 PM UTC 25
Peak memory 274440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707461529 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.1707461529 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.2768203292
Short name T927
Test name
Test status
Simulation time 12606578158 ps
CPU time 353.17 seconds
Started Feb 09 12:50:33 PM UTC 25
Finished Feb 09 12:56:31 PM UTC 25
Peak memory 520212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768203292 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2768203292 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.2285391384
Short name T910
Test name
Test status
Simulation time 936576795 ps
CPU time 59.39 seconds
Started Feb 09 12:49:52 PM UTC 25
Finished Feb 09 12:50:53 PM UTC 25
Peak memory 230724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285391384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.kmac_smoke.2285391384 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.379976294
Short name T987
Test name
Test status
Simulation time 172364434786 ps
CPU time 1240.97 seconds
Started Feb 09 12:55:07 PM UTC 25
Finished Feb 09 01:16:03 PM UTC 25
Peak memory 1186200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379976294 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.379976294 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_kmac.1988368562
Short name T916
Test name
Test status
Simulation time 132550556 ps
CPU time 5.56 seconds
Started Feb 09 12:52:48 PM UTC 25
Finished Feb 09 12:52:54 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1988368562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.kmac_test_vectors_kmac.1988368562 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_kmac_xof.3677931394
Short name T918
Test name
Test status
Simulation time 638761970 ps
CPU time 6.28 seconds
Started Feb 09 12:52:55 PM UTC 25
Finished Feb 09 12:53:02 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3677931394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 44.kmac_test_vectors_kmac_xof.3677931394 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_224.3468853490
Short name T1043
Test name
Test status
Simulation time 290320518159 ps
CPU time 3049.58 seconds
Started Feb 09 12:50:43 PM UTC 25
Finished Feb 09 01:42:07 PM UTC 25
Peak memory 3201088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468853490 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.3468853490 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_256.3865131757
Short name T1024
Test name
Test status
Simulation time 63943913953 ps
CPU time 2233.1 seconds
Started Feb 09 12:50:55 PM UTC 25
Finished Feb 09 01:28:33 PM UTC 25
Peak memory 3047396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865131757 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.3865131757 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_384.3010750682
Short name T976
Test name
Test status
Simulation time 13923195687 ps
CPU time 1291.41 seconds
Started Feb 09 12:51:02 PM UTC 25
Finished Feb 09 01:12:48 PM UTC 25
Peak memory 931776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010750682 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3010750682 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_512.1371252559
Short name T985
Test name
Test status
Simulation time 69486313906 ps
CPU time 1354.27 seconds
Started Feb 09 12:51:51 PM UTC 25
Finished Feb 09 01:14:40 PM UTC 25
Peak memory 1736700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371252559 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1371252559 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_shake_128.4233991015
Short name T1079
Test name
Test status
Simulation time 687877121054 ps
CPU time 7375.35 seconds
Started Feb 09 12:51:53 PM UTC 25
Finished Feb 09 02:56:06 PM UTC 25
Peak memory 7862312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233991015 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.4233991015 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/44.kmac_test_vectors_shake_256.2912157278
Short name T1058
Test name
Test status
Simulation time 139835152212 ps
CPU time 3768.56 seconds
Started Feb 09 12:52:39 PM UTC 25
Finished Feb 09 01:56:07 PM UTC 25
Peak memory 2240572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912157278 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2912157278 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.204770629
Short name T944
Test name
Test status
Simulation time 29529720 ps
CPU time 1.2 seconds
Started Feb 09 01:02:17 PM UTC 25
Finished Feb 09 01:02:20 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204770629 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.204770629 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.2268108209
Short name T951
Test name
Test status
Simulation time 48368766818 ps
CPU time 332.37 seconds
Started Feb 09 12:59:39 PM UTC 25
Finished Feb 09 01:05:16 PM UTC 25
Peak memory 471048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268108209 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2268108209 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.2790335060
Short name T972
Test name
Test status
Simulation time 48670552875 ps
CPU time 844.71 seconds
Started Feb 09 12:56:32 PM UTC 25
Finished Feb 09 01:10:47 PM UTC 25
Peak memory 260108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790335060 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2790335060 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.2063287853
Short name T950
Test name
Test status
Simulation time 51503725299 ps
CPU time 266.51 seconds
Started Feb 09 12:59:45 PM UTC 25
Finished Feb 09 01:04:16 PM UTC 25
Peak memory 464912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063287853 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2063287853 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.2133173427
Short name T958
Test name
Test status
Simulation time 21910392780 ps
CPU time 338.67 seconds
Started Feb 09 01:00:54 PM UTC 25
Finished Feb 09 01:06:38 PM UTC 25
Peak memory 444416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133173427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 45.kmac_error.2133173427 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.3064225284
Short name T940
Test name
Test status
Simulation time 1897274203 ps
CPU time 6.18 seconds
Started Feb 09 01:01:18 PM UTC 25
Finished Feb 09 01:01:26 PM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064225284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3064225284 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.2186356972
Short name T941
Test name
Test status
Simulation time 169893540 ps
CPU time 2.22 seconds
Started Feb 09 01:01:27 PM UTC 25
Finished Feb 09 01:01:30 PM UTC 25
Peak memory 235260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186356972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2186356972 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.227370934
Short name T1034
Test name
Test status
Simulation time 418118916555 ps
CPU time 2180.23 seconds
Started Feb 09 12:55:23 PM UTC 25
Finished Feb 09 01:32:05 PM UTC 25
Peak memory 2971668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227370934 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.227370934 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.3954095987
Short name T946
Test name
Test status
Simulation time 17415802539 ps
CPU time 380.98 seconds
Started Feb 09 12:56:19 PM UTC 25
Finished Feb 09 01:02:45 PM UTC 25
Peak memory 612372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954095987 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3954095987 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.1033978600
Short name T925
Test name
Test status
Simulation time 303423264 ps
CPU time 7.67 seconds
Started Feb 09 12:55:12 PM UTC 25
Finished Feb 09 12:55:21 PM UTC 25
Peak memory 230856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033978600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 45.kmac_smoke.1033978600 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.1474318260
Short name T1027
Test name
Test status
Simulation time 232451166658 ps
CPU time 1676.37 seconds
Started Feb 09 01:01:31 PM UTC 25
Finished Feb 09 01:29:46 PM UTC 25
Peak memory 1221008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474318260 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1474318260 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_kmac.88270938
Short name T936
Test name
Test status
Simulation time 125062841 ps
CPU time 5.1 seconds
Started Feb 09 12:59:32 PM UTC 25
Finished Feb 09 12:59:38 PM UTC 25
Peak memory 230748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=88270938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 45.kmac_test_vectors_kmac.88270938 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_kmac_xof.3533972841
Short name T937
Test name
Test status
Simulation time 246945473 ps
CPU time 6.77 seconds
Started Feb 09 12:59:37 PM UTC 25
Finished Feb 09 12:59:45 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3533972841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 45.kmac_test_vectors_kmac_xof.3533972841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_sha3_224.2703412232
Short name T1009
Test name
Test status
Simulation time 19063272319 ps
CPU time 1718.17 seconds
Started Feb 09 12:57:12 PM UTC 25
Finished Feb 09 01:26:08 PM UTC 25
Peak memory 1222596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703412232 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2703412232 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_sha3_256.3026649616
Short name T1033
Test name
Test status
Simulation time 226808827544 ps
CPU time 2009.7 seconds
Started Feb 09 12:57:16 PM UTC 25
Finished Feb 09 01:31:08 PM UTC 25
Peak memory 1175552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026649616 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3026649616 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_sha3_384.3563052613
Short name T1028
Test name
Test status
Simulation time 75667761479 ps
CPU time 1919.31 seconds
Started Feb 09 12:57:41 PM UTC 25
Finished Feb 09 01:30:01 PM UTC 25
Peak memory 2441132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563052613 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.3563052613 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_sha3_512.562654458
Short name T1007
Test name
Test status
Simulation time 600322402592 ps
CPU time 1638.58 seconds
Started Feb 09 12:58:00 PM UTC 25
Finished Feb 09 01:25:37 PM UTC 25
Peak memory 1708032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562654458 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.562654458 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_shake_128.2258594624
Short name T1080
Test name
Test status
Simulation time 176919156776 ps
CPU time 7151.28 seconds
Started Feb 09 12:58:19 PM UTC 25
Finished Feb 09 02:58:44 PM UTC 25
Peak memory 7833816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258594624 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.2258594624 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/45.kmac_test_vectors_shake_256.947940392
Short name T1078
Test name
Test status
Simulation time 1346000132111 ps
CPU time 6871.27 seconds
Started Feb 09 12:58:44 PM UTC 25
Finished Feb 09 02:54:28 PM UTC 25
Peak memory 6373316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947940392 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.947940392 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.3686866575
Short name T962
Test name
Test status
Simulation time 48456125 ps
CPU time 1.16 seconds
Started Feb 09 01:06:48 PM UTC 25
Finished Feb 09 01:06:50 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686866575 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3686866575 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.2195735417
Short name T964
Test name
Test status
Simulation time 4487965937 ps
CPU time 78.56 seconds
Started Feb 09 01:05:41 PM UTC 25
Finished Feb 09 01:07:02 PM UTC 25
Peak memory 282624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195735417 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2195735417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.877528530
Short name T1005
Test name
Test status
Simulation time 51098556465 ps
CPU time 1271.51 seconds
Started Feb 09 01:02:47 PM UTC 25
Finished Feb 09 01:24:14 PM UTC 25
Peak memory 272468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877528530 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.877528530 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.3301270871
Short name T966
Test name
Test status
Simulation time 3487707133 ps
CPU time 104.54 seconds
Started Feb 09 01:05:45 PM UTC 25
Finished Feb 09 01:07:31 PM UTC 25
Peak memory 278536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301270871 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3301270871 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.806707161
Short name T971
Test name
Test status
Simulation time 11651567433 ps
CPU time 198.16 seconds
Started Feb 09 01:06:30 PM UTC 25
Finished Feb 09 01:09:52 PM UTC 25
Peak memory 325636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806707161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.kmac_error.806707161 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.1675986306
Short name T959
Test name
Test status
Simulation time 336231874 ps
CPU time 2.39 seconds
Started Feb 09 01:06:39 PM UTC 25
Finished Feb 09 01:06:42 PM UTC 25
Peak memory 232772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675986306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1675986306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.1985545524
Short name T961
Test name
Test status
Simulation time 178639955 ps
CPU time 1.99 seconds
Started Feb 09 01:06:43 PM UTC 25
Finished Feb 09 01:06:46 PM UTC 25
Peak memory 229936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985545524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1985545524 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.3045720872
Short name T977
Test name
Test status
Simulation time 20499734732 ps
CPU time 642.05 seconds
Started Feb 09 01:02:21 PM UTC 25
Finished Feb 09 01:13:11 PM UTC 25
Peak memory 985080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045720872 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.3045720872 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.1748670070
Short name T949
Test name
Test status
Simulation time 5555280690 ps
CPU time 86.39 seconds
Started Feb 09 01:02:46 PM UTC 25
Finished Feb 09 01:04:14 PM UTC 25
Peak memory 288824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748670070 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1748670070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.254310841
Short name T947
Test name
Test status
Simulation time 4332506832 ps
CPU time 28.79 seconds
Started Feb 09 01:02:19 PM UTC 25
Finished Feb 09 01:02:49 PM UTC 25
Peak memory 230772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254310841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.kmac_smoke.254310841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.4048767604
Short name T1015
Test name
Test status
Simulation time 52286125824 ps
CPU time 1182.13 seconds
Started Feb 09 01:06:45 PM UTC 25
Finished Feb 09 01:26:42 PM UTC 25
Peak memory 1186200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048767604 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.4048767604 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_kmac.519749658
Short name T954
Test name
Test status
Simulation time 242949719 ps
CPU time 7.46 seconds
Started Feb 09 01:05:25 PM UTC 25
Finished Feb 09 01:05:33 PM UTC 25
Peak memory 230740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=519749658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.kmac_test_vectors_kmac.519749658 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_kmac_xof.3405573467
Short name T955
Test name
Test status
Simulation time 122414172 ps
CPU time 5.33 seconds
Started Feb 09 01:05:34 PM UTC 25
Finished Feb 09 01:05:40 PM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3405573467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 46.kmac_test_vectors_kmac_xof.3405573467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_224.317913351
Short name T1059
Test name
Test status
Simulation time 100829451282 ps
CPU time 3166.44 seconds
Started Feb 09 01:02:50 PM UTC 25
Finished Feb 09 01:56:12 PM UTC 25
Peak memory 3266492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317913351 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.317913351 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_256.3162751043
Short name T1049
Test name
Test status
Simulation time 164596467003 ps
CPU time 2665 seconds
Started Feb 09 01:04:06 PM UTC 25
Finished Feb 09 01:49:01 PM UTC 25
Peak memory 3053504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162751043 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3162751043 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_384.1755372840
Short name T1020
Test name
Test status
Simulation time 26375918286 ps
CPU time 1388 seconds
Started Feb 09 01:04:15 PM UTC 25
Finished Feb 09 01:27:39 PM UTC 25
Peak memory 937924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755372840 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.1755372840 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_512.2091790732
Short name T995
Test name
Test status
Simulation time 47790970065 ps
CPU time 1012.98 seconds
Started Feb 09 01:04:17 PM UTC 25
Finished Feb 09 01:21:22 PM UTC 25
Peak memory 1730496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091790732 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2091790732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_128.631510939
Short name T1071
Test name
Test status
Simulation time 200047224263 ps
CPU time 4398.34 seconds
Started Feb 09 01:05:18 PM UTC 25
Finished Feb 09 02:19:22 PM UTC 25
Peak memory 2652100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631510939 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.631510939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_256.1909054378
Short name T1068
Test name
Test status
Simulation time 180747082416 ps
CPU time 3869.06 seconds
Started Feb 09 01:05:23 PM UTC 25
Finished Feb 09 02:10:33 PM UTC 25
Peak memory 2242496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909054378 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1909054378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.4179034298
Short name T981
Test name
Test status
Simulation time 40828802 ps
CPU time 1.16 seconds
Started Feb 09 01:13:32 PM UTC 25
Finished Feb 09 01:13:35 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179034298 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.4179034298 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.3849354857
Short name T982
Test name
Test status
Simulation time 26858805991 ps
CPU time 153.26 seconds
Started Feb 09 01:11:04 PM UTC 25
Finished Feb 09 01:13:40 PM UTC 25
Peak memory 352244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849354857 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3849354857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.3196521823
Short name T997
Test name
Test status
Simulation time 24067173650 ps
CPU time 850.17 seconds
Started Feb 09 01:07:29 PM UTC 25
Finished Feb 09 01:21:50 PM UTC 25
Peak memory 262148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196521823 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3196521823 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1756159220
Short name T990
Test name
Test status
Simulation time 16363163343 ps
CPU time 366.25 seconds
Started Feb 09 01:12:21 PM UTC 25
Finished Feb 09 01:18:32 PM UTC 25
Peak memory 489472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756159220 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1756159220 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.2520104631
Short name T988
Test name
Test status
Simulation time 6007527659 ps
CPU time 207.86 seconds
Started Feb 09 01:12:49 PM UTC 25
Finished Feb 09 01:16:21 PM UTC 25
Peak memory 399360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520104631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.kmac_error.2520104631 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.3288610651
Short name T978
Test name
Test status
Simulation time 2784564806 ps
CPU time 6.9 seconds
Started Feb 09 01:13:12 PM UTC 25
Finished Feb 09 01:13:20 PM UTC 25
Peak memory 230724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288610651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3288610651 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.3515711170
Short name T979
Test name
Test status
Simulation time 136274221 ps
CPU time 2.08 seconds
Started Feb 09 01:13:22 PM UTC 25
Finished Feb 09 01:13:25 PM UTC 25
Peak memory 230588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515711170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3515711170 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.1848932867
Short name T969
Test name
Test status
Simulation time 17022603599 ps
CPU time 150.23 seconds
Started Feb 09 01:06:51 PM UTC 25
Finished Feb 09 01:09:24 PM UTC 25
Peak memory 360452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848932867 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.1848932867 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.2893259935
Short name T970
Test name
Test status
Simulation time 2090405856 ps
CPU time 143.27 seconds
Started Feb 09 01:07:03 PM UTC 25
Finished Feb 09 01:09:29 PM UTC 25
Peak memory 298956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893259935 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2893259935 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.2326328718
Short name T968
Test name
Test status
Simulation time 15395943274 ps
CPU time 87.89 seconds
Started Feb 09 01:06:51 PM UTC 25
Finished Feb 09 01:08:21 PM UTC 25
Peak memory 234888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326328718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.kmac_smoke.2326328718 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.1299053466
Short name T1018
Test name
Test status
Simulation time 13276870118 ps
CPU time 834.29 seconds
Started Feb 09 01:13:26 PM UTC 25
Finished Feb 09 01:27:30 PM UTC 25
Peak memory 638996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299053466 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1299053466 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_kmac.536796348
Short name T973
Test name
Test status
Simulation time 268203705 ps
CPU time 5.68 seconds
Started Feb 09 01:10:49 PM UTC 25
Finished Feb 09 01:10:55 PM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=536796348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.kmac_test_vectors_kmac.536796348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_kmac_xof.3065194185
Short name T974
Test name
Test status
Simulation time 473811081 ps
CPU time 5.13 seconds
Started Feb 09 01:10:57 PM UTC 25
Finished Feb 09 01:11:03 PM UTC 25
Peak memory 230792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3065194185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.kmac_test_vectors_kmac_xof.3065194185 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_224.1560690808
Short name T1041
Test name
Test status
Simulation time 19259090273 ps
CPU time 1876.44 seconds
Started Feb 09 01:07:32 PM UTC 25
Finished Feb 09 01:39:09 PM UTC 25
Peak memory 1198020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560690808 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.1560690808 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_256.2661690341
Short name T1054
Test name
Test status
Simulation time 247546779676 ps
CPU time 2623.6 seconds
Started Feb 09 01:07:33 PM UTC 25
Finished Feb 09 01:51:47 PM UTC 25
Peak memory 3108800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661690341 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2661690341 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_384.3639490395
Short name T1039
Test name
Test status
Simulation time 192000786612 ps
CPU time 1616.48 seconds
Started Feb 09 01:08:22 PM UTC 25
Finished Feb 09 01:35:36 PM UTC 25
Peak memory 2363396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639490395 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.3639490395 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_512.2640725771
Short name T1011
Test name
Test status
Simulation time 38371875464 ps
CPU time 1001.35 seconds
Started Feb 09 01:09:25 PM UTC 25
Finished Feb 09 01:26:19 PM UTC 25
Peak memory 692164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640725771 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2640725771 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_128.46937058
Short name T1081
Test name
Test status
Simulation time 743880358880 ps
CPU time 7423.13 seconds
Started Feb 09 01:09:31 PM UTC 25
Finished Feb 09 03:14:29 PM UTC 25
Peak memory 7815200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46937058 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.46937058 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_256.787451013
Short name T1069
Test name
Test status
Simulation time 177237860359 ps
CPU time 3796.47 seconds
Started Feb 09 01:09:53 PM UTC 25
Finished Feb 09 02:13:50 PM UTC 25
Peak memory 2183164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787451013 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.787451013 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.1392225126
Short name T1000
Test name
Test status
Simulation time 49556139 ps
CPU time 1.19 seconds
Started Feb 09 01:21:57 PM UTC 25
Finished Feb 09 01:21:59 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392225126 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1392225126 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.2607751065
Short name T1003
Test name
Test status
Simulation time 1780787283 ps
CPU time 144.12 seconds
Started Feb 09 01:20:22 PM UTC 25
Finished Feb 09 01:22:49 PM UTC 25
Peak memory 282568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607751065 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2607751065 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.739961399
Short name T1036
Test name
Test status
Simulation time 34193933647 ps
CPU time 1164.64 seconds
Started Feb 09 01:14:18 PM UTC 25
Finished Feb 09 01:33:56 PM UTC 25
Peak memory 268364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739961399 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.739961399 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.2366061341
Short name T1006
Test name
Test status
Simulation time 104108093746 ps
CPU time 219.97 seconds
Started Feb 09 01:21:01 PM UTC 25
Finished Feb 09 01:24:44 PM UTC 25
Peak memory 424016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366061341 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2366061341 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.3945144185
Short name T996
Test name
Test status
Simulation time 4020195637 ps
CPU time 24.17 seconds
Started Feb 09 01:21:23 PM UTC 25
Finished Feb 09 01:21:48 PM UTC 25
Peak memory 245764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945144185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.kmac_error.3945144185 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.1247463363
Short name T999
Test name
Test status
Simulation time 509748358 ps
CPU time 5.38 seconds
Started Feb 09 01:21:49 PM UTC 25
Finished Feb 09 01:21:55 PM UTC 25
Peak memory 230592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247463363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1247463363 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.1357227805
Short name T998
Test name
Test status
Simulation time 147623254 ps
CPU time 1.69 seconds
Started Feb 09 01:21:51 PM UTC 25
Finished Feb 09 01:21:54 PM UTC 25
Peak memory 234492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357227805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1357227805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.1432223092
Short name T1051
Test name
Test status
Simulation time 51999338281 ps
CPU time 2162.49 seconds
Started Feb 09 01:13:41 PM UTC 25
Finished Feb 09 01:50:06 PM UTC 25
Peak memory 1665040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432223092 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.1432223092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.908015732
Short name T994
Test name
Test status
Simulation time 33389936978 ps
CPU time 413.51 seconds
Started Feb 09 01:14:01 PM UTC 25
Finished Feb 09 01:21:00 PM UTC 25
Peak memory 391244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908015732 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.908015732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.1120705585
Short name T984
Test name
Test status
Simulation time 4211645216 ps
CPU time 39.46 seconds
Started Feb 09 01:13:36 PM UTC 25
Finished Feb 09 01:14:17 PM UTC 25
Peak memory 232908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120705585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.kmac_smoke.1120705585 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.192425417
Short name T1063
Test name
Test status
Simulation time 89707307767 ps
CPU time 2392.85 seconds
Started Feb 09 01:21:55 PM UTC 25
Finished Feb 09 02:02:13 PM UTC 25
Peak memory 1679800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192425417 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.192425417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_kmac.749325618
Short name T992
Test name
Test status
Simulation time 701226905 ps
CPU time 6.03 seconds
Started Feb 09 01:20:06 PM UTC 25
Finished Feb 09 01:20:14 PM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=749325618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.kmac_test_vectors_kmac.749325618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_kmac_xof.1895138226
Short name T993
Test name
Test status
Simulation time 122026022 ps
CPU time 5.26 seconds
Started Feb 09 01:20:14 PM UTC 25
Finished Feb 09 01:20:21 PM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1895138226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 48.kmac_test_vectors_kmac_xof.1895138226 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_224.3222076004
Short name T1047
Test name
Test status
Simulation time 36521100604 ps
CPU time 1775.76 seconds
Started Feb 09 01:14:42 PM UTC 25
Finished Feb 09 01:44:37 PM UTC 25
Peak memory 1171384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222076004 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3222076004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_256.2242521820
Short name T1046
Test name
Test status
Simulation time 118035332587 ps
CPU time 1720.92 seconds
Started Feb 09 01:15:36 PM UTC 25
Finished Feb 09 01:44:37 PM UTC 25
Peak memory 1146872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242521820 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2242521820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_384.4074482145
Short name T1044
Test name
Test status
Simulation time 112184870674 ps
CPU time 1552.36 seconds
Started Feb 09 01:16:04 PM UTC 25
Finished Feb 09 01:42:15 PM UTC 25
Peak memory 921540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074482145 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.4074482145 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_512.1023992773
Short name T1029
Test name
Test status
Simulation time 10201490145 ps
CPU time 812.77 seconds
Started Feb 09 01:16:21 PM UTC 25
Finished Feb 09 01:30:03 PM UTC 25
Peak memory 710592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023992773 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1023992773 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_128.4246447566
Short name T1082
Test name
Test status
Simulation time 1027571542953 ps
CPU time 8084.95 seconds
Started Feb 09 01:17:44 PM UTC 25
Finished Feb 09 03:33:52 PM UTC 25
Peak memory 7850020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246447566 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.4246447566 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_256.329821630
Short name T1072
Test name
Test status
Simulation time 45674473751 ps
CPU time 3735.78 seconds
Started Feb 09 01:18:34 PM UTC 25
Finished Feb 09 02:21:29 PM UTC 25
Peak memory 2273220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329821630 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.329821630 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.1385153339
Short name T1019
Test name
Test status
Simulation time 16636546 ps
CPU time 1.19 seconds
Started Feb 09 01:27:31 PM UTC 25
Finished Feb 09 01:27:34 PM UTC 25
Peak memory 214352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385153339 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1385153339 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.2581656194
Short name T1026
Test name
Test status
Simulation time 5215986100 ps
CPU time 187.63 seconds
Started Feb 09 01:26:26 PM UTC 25
Finished Feb 09 01:29:37 PM UTC 25
Peak memory 290880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581656194 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2581656194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.1008033792
Short name T1030
Test name
Test status
Simulation time 9065203290 ps
CPU time 464.2 seconds
Started Feb 09 01:22:50 PM UTC 25
Finished Feb 09 01:30:41 PM UTC 25
Peak memory 245772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008033792 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1008033792 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.3432443509
Short name T1021
Test name
Test status
Simulation time 3526150240 ps
CPU time 74.91 seconds
Started Feb 09 01:26:28 PM UTC 25
Finished Feb 09 01:27:44 PM UTC 25
Peak memory 258120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432443509 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3432443509 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.2898796780
Short name T1031
Test name
Test status
Simulation time 2603512308 ps
CPU time 240.56 seconds
Started Feb 09 01:26:42 PM UTC 25
Finished Feb 09 01:30:47 PM UTC 25
Peak memory 327680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898796780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 49.kmac_error.2898796780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.3708647192
Short name T1016
Test name
Test status
Simulation time 2758835668 ps
CPU time 12.32 seconds
Started Feb 09 01:26:43 PM UTC 25
Finished Feb 09 01:26:57 PM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708647192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3708647192 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.3824031192
Short name T1017
Test name
Test status
Simulation time 148093978 ps
CPU time 1.84 seconds
Started Feb 09 01:26:58 PM UTC 25
Finished Feb 09 01:27:01 PM UTC 25
Peak memory 229816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824031192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3824031192 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3616997529
Short name T1052
Test name
Test status
Simulation time 36196021154 ps
CPU time 1744.14 seconds
Started Feb 09 01:22:01 PM UTC 25
Finished Feb 09 01:51:24 PM UTC 25
Peak memory 1378312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616997529 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.3616997529 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.3085563241
Short name T1010
Test name
Test status
Simulation time 174375677303 ps
CPU time 234.61 seconds
Started Feb 09 01:22:19 PM UTC 25
Finished Feb 09 01:26:17 PM UTC 25
Peak memory 401496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085563241 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3085563241 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.1014638168
Short name T1004
Test name
Test status
Simulation time 3486956612 ps
CPU time 54.91 seconds
Started Feb 09 01:22:00 PM UTC 25
Finished Feb 09 01:22:56 PM UTC 25
Peak memory 235392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014638168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 49.kmac_smoke.1014638168 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.4082014907
Short name T1038
Test name
Test status
Simulation time 16464861295 ps
CPU time 497.94 seconds
Started Feb 09 01:27:02 PM UTC 25
Finished Feb 09 01:35:27 PM UTC 25
Peak memory 764276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082014907 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.4082014907 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_kmac.1749481129
Short name T1012
Test name
Test status
Simulation time 171896960 ps
CPU time 6.26 seconds
Started Feb 09 01:26:18 PM UTC 25
Finished Feb 09 01:26:25 PM UTC 25
Peak memory 230716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1749481129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.kmac_test_vectors_kmac.1749481129 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_kmac_xof.3146470348
Short name T1013
Test name
Test status
Simulation time 3260356414 ps
CPU time 5.41 seconds
Started Feb 09 01:26:20 PM UTC 25
Finished Feb 09 01:26:27 PM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3146470348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 49.kmac_test_vectors_kmac_xof.3146470348 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_224.3911835227
Short name T1065
Test name
Test status
Simulation time 103005705657 ps
CPU time 2497.92 seconds
Started Feb 09 01:22:57 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 3237944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911835227 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3911835227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_256.389903483
Short name T1057
Test name
Test status
Simulation time 18369080258 ps
CPU time 1733.25 seconds
Started Feb 09 01:24:15 PM UTC 25
Finished Feb 09 01:53:28 PM UTC 25
Peak memory 1142840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389903483 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.389903483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_384.1087125015
Short name T1060
Test name
Test status
Simulation time 303637294186 ps
CPU time 2163.16 seconds
Started Feb 09 01:24:45 PM UTC 25
Finished Feb 09 02:01:12 PM UTC 25
Peak memory 2490308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087125015 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.1087125015 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_512.1603307572
Short name T1040
Test name
Test status
Simulation time 19029116138 ps
CPU time 774.79 seconds
Started Feb 09 01:25:39 PM UTC 25
Finished Feb 09 01:38:43 PM UTC 25
Peak memory 700412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603307572 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1603307572 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_128.4029078296
Short name T1077
Test name
Test status
Simulation time 203255980024 ps
CPU time 4687.21 seconds
Started Feb 09 01:25:44 PM UTC 25
Finished Feb 09 02:44:41 PM UTC 25
Peak memory 2703340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029078296 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.4029078296 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_256.1112201982
Short name T1074
Test name
Test status
Simulation time 44019689413 ps
CPU time 3767.29 seconds
Started Feb 09 01:26:08 PM UTC 25
Finished Feb 09 02:29:35 PM UTC 25
Peak memory 2226108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112201982 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.1112201982 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.568087655
Short name T205
Test name
Test status
Simulation time 11464766 ps
CPU time 1.14 seconds
Started Feb 09 08:55:43 AM UTC 25
Finished Feb 09 08:55:45 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568087655 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.568087655 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.2055020227
Short name T213
Test name
Test status
Simulation time 51416510379 ps
CPU time 328.65 seconds
Started Feb 09 08:51:27 AM UTC 25
Finished Feb 09 08:57:01 AM UTC 25
Peak memory 446480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055020227 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2055020227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1143167986
Short name T207
Test name
Test status
Simulation time 7838222085 ps
CPU time 206.26 seconds
Started Feb 09 08:52:30 AM UTC 25
Finished Feb 09 08:56:00 AM UTC 25
Peak memory 385024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143167986 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1143167986 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.537298747
Short name T199
Test name
Test status
Simulation time 41489856521 ps
CPU time 248.24 seconds
Started Feb 09 08:48:40 AM UTC 25
Finished Feb 09 08:52:52 AM UTC 25
Peak memory 237588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537298747 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.537298747 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.530809237
Short name T203
Test name
Test status
Simulation time 1620448073 ps
CPU time 29.95 seconds
Started Feb 09 08:54:41 AM UTC 25
Finished Feb 09 08:55:12 AM UTC 25
Peak memory 235332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530809237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.530809237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.807512010
Short name T202
Test name
Test status
Simulation time 681186482 ps
CPU time 10.14 seconds
Started Feb 09 08:54:56 AM UTC 25
Finished Feb 09 08:55:07 AM UTC 25
Peak memory 230608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807512010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.807512010 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.2336731332
Short name T209
Test name
Test status
Simulation time 19011409263 ps
CPU time 54.98 seconds
Started Feb 09 08:55:08 AM UTC 25
Finished Feb 09 08:56:05 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336731332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2336731332 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.1179035232
Short name T208
Test name
Test status
Simulation time 7042029916 ps
CPU time 185.19 seconds
Started Feb 09 08:52:52 AM UTC 25
Finished Feb 09 08:56:01 AM UTC 25
Peak memory 358412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179035232 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1179035232 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.3168538915
Short name T64
Test name
Test status
Simulation time 6251061070 ps
CPU time 12.92 seconds
Started Feb 09 08:54:25 AM UTC 25
Finished Feb 09 08:54:40 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168538915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3168538915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.3113887920
Short name T38
Test name
Test status
Simulation time 72791767 ps
CPU time 1.64 seconds
Started Feb 09 08:55:13 AM UTC 25
Finished Feb 09 08:55:16 AM UTC 25
Peak memory 229768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113887920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3113887920 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.2026005768
Short name T259
Test name
Test status
Simulation time 211163515877 ps
CPU time 1644.57 seconds
Started Feb 09 08:48:19 AM UTC 25
Finished Feb 09 09:16:01 AM UTC 25
Peak memory 2377796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026005768 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.2026005768 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.4154565778
Short name T77
Test name
Test status
Simulation time 2814215980 ps
CPU time 215.22 seconds
Started Feb 09 08:53:11 AM UTC 25
Finished Feb 09 08:56:49 AM UTC 25
Peak memory 309772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154565778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.kmac_mubi.4154565778 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.1466787618
Short name T201
Test name
Test status
Simulation time 13168934785 ps
CPU time 338.54 seconds
Started Feb 09 08:48:32 AM UTC 25
Finished Feb 09 08:54:15 AM UTC 25
Peak memory 350220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466787618 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1466787618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.1242730016
Short name T193
Test name
Test status
Simulation time 2355509357 ps
CPU time 23.91 seconds
Started Feb 09 08:48:13 AM UTC 25
Finished Feb 09 08:48:39 AM UTC 25
Peak memory 230788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242730016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.kmac_smoke.1242730016 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.304096077
Short name T151
Test name
Test status
Simulation time 2583393630 ps
CPU time 41.84 seconds
Started Feb 09 08:55:17 AM UTC 25
Finished Feb 09 08:56:01 AM UTC 25
Peak memory 239628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304096077 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.304096077 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_kmac.2855385491
Short name T197
Test name
Test status
Simulation time 715437197 ps
CPU time 6.72 seconds
Started Feb 09 08:51:09 AM UTC 25
Finished Feb 09 08:51:17 AM UTC 25
Peak memory 230812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2855385491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.kmac_test_vectors_kmac.2855385491 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_kmac_xof.3409025688
Short name T198
Test name
Test status
Simulation time 845356236 ps
CPU time 5.87 seconds
Started Feb 09 08:51:18 AM UTC 25
Finished Feb 09 08:51:26 AM UTC 25
Peak memory 230812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3409025688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 5.kmac_test_vectors_kmac_xof.3409025688 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_224.1022950644
Short name T270
Test name
Test status
Simulation time 37002656654 ps
CPU time 1759.11 seconds
Started Feb 09 08:48:43 AM UTC 25
Finished Feb 09 09:18:21 AM UTC 25
Peak memory 1187780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022950644 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.1022950644 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_256.1645286055
Short name T306
Test name
Test status
Simulation time 61279164020 ps
CPU time 2156.27 seconds
Started Feb 09 08:49:14 AM UTC 25
Finished Feb 09 09:25:33 AM UTC 25
Peak memory 3049404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645286055 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1645286055 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_384.3861946327
Short name T245
Test name
Test status
Simulation time 13306850799 ps
CPU time 1289.1 seconds
Started Feb 09 08:50:03 AM UTC 25
Finished Feb 09 09:11:47 AM UTC 25
Peak memory 911272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861946327 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3861946327 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_512.3173389419
Short name T247
Test name
Test status
Simulation time 35159449544 ps
CPU time 1298.24 seconds
Started Feb 09 08:50:04 AM UTC 25
Finished Feb 09 09:11:57 AM UTC 25
Peak memory 1793988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173389419 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.3173389419 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_shake_128.2995613647
Short name T579
Test name
Test status
Simulation time 1078255039565 ps
CPU time 7443.1 seconds
Started Feb 09 08:50:28 AM UTC 25
Finished Feb 09 10:55:43 AM UTC 25
Peak memory 7925852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995613647 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.2995613647 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/5.kmac_test_vectors_shake_256.1045047979
Short name T512
Test name
Test status
Simulation time 603721850837 ps
CPU time 6176.41 seconds
Started Feb 09 08:50:33 AM UTC 25
Finished Feb 09 10:34:33 AM UTC 25
Peak memory 6393860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045047979 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.1045047979 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.2151113865
Short name T220
Test name
Test status
Simulation time 48086093 ps
CPU time 1.09 seconds
Started Feb 09 08:59:58 AM UTC 25
Finished Feb 09 09:00:00 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151113865 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2151113865 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.101856634
Short name T222
Test name
Test status
Simulation time 7689278884 ps
CPU time 219.58 seconds
Started Feb 09 08:57:02 AM UTC 25
Finished Feb 09 09:00:45 AM UTC 25
Peak memory 376832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101856634 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.101856634 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.4051813548
Short name T224
Test name
Test status
Simulation time 11688985922 ps
CPU time 293.35 seconds
Started Feb 09 08:57:06 AM UTC 25
Finished Feb 09 09:02:04 AM UTC 25
Peak memory 348176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051813548 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.4051813548 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.2472633579
Short name T241
Test name
Test status
Simulation time 18358848625 ps
CPU time 839.46 seconds
Started Feb 09 08:55:54 AM UTC 25
Finished Feb 09 09:10:04 AM UTC 25
Peak memory 260172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472633579 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2472633579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.3927855417
Short name T216
Test name
Test status
Simulation time 1844772844 ps
CPU time 24.82 seconds
Started Feb 09 08:58:59 AM UTC 25
Finished Feb 09 08:59:26 AM UTC 25
Peak memory 235272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927855417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3927855417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.1882520805
Short name T218
Test name
Test status
Simulation time 1163797526 ps
CPU time 20.49 seconds
Started Feb 09 08:59:23 AM UTC 25
Finished Feb 09 08:59:45 AM UTC 25
Peak memory 230668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882520805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1882520805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.1442400650
Short name T217
Test name
Test status
Simulation time 2106477564 ps
CPU time 8.64 seconds
Started Feb 09 08:59:26 AM UTC 25
Finished Feb 09 08:59:36 AM UTC 25
Peak memory 230736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442400650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1442400650 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3270060814
Short name T225
Test name
Test status
Simulation time 46900697610 ps
CPU time 351.2 seconds
Started Feb 09 08:57:32 AM UTC 25
Finished Feb 09 09:03:28 AM UTC 25
Peak memory 471052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270060814 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3270060814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.4140024667
Short name T147
Test name
Test status
Simulation time 9825765877 ps
CPU time 292.92 seconds
Started Feb 09 08:58:04 AM UTC 25
Finished Feb 09 09:03:01 AM UTC 25
Peak memory 497736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140024667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.kmac_error.4140024667 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.3475365959
Short name T65
Test name
Test status
Simulation time 1981861398 ps
CPU time 16.15 seconds
Started Feb 09 08:58:41 AM UTC 25
Finished Feb 09 08:58:59 AM UTC 25
Peak memory 230596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475365959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3475365959 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.1008620813
Short name T219
Test name
Test status
Simulation time 415870735 ps
CPU time 12.83 seconds
Started Feb 09 08:59:38 AM UTC 25
Finished Feb 09 08:59:52 AM UTC 25
Peak memory 245084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008620813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1008620813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.3879689814
Short name T271
Test name
Test status
Simulation time 44815905742 ps
CPU time 1356.24 seconds
Started Feb 09 08:55:46 AM UTC 25
Finished Feb 09 09:18:38 AM UTC 25
Peak memory 999260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879689814 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.3879689814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.3683194892
Short name T78
Test name
Test status
Simulation time 28326030990 ps
CPU time 381.05 seconds
Started Feb 09 08:57:35 AM UTC 25
Finished Feb 09 09:04:01 AM UTC 25
Peak memory 545212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683194892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.kmac_mubi.3683194892 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.1141997211
Short name T215
Test name
Test status
Simulation time 3977290767 ps
CPU time 208.7 seconds
Started Feb 09 08:55:50 AM UTC 25
Finished Feb 09 08:59:22 AM UTC 25
Peak memory 301072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141997211 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1141997211 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.2296940404
Short name T206
Test name
Test status
Simulation time 265279993 ps
CPU time 5.69 seconds
Started Feb 09 08:55:46 AM UTC 25
Finished Feb 09 08:55:53 AM UTC 25
Peak memory 232696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296940404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.kmac_smoke.2296940404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.199174708
Short name T331
Test name
Test status
Simulation time 97329009866 ps
CPU time 1953.65 seconds
Started Feb 09 08:59:47 AM UTC 25
Finished Feb 09 09:32:41 AM UTC 25
Peak memory 1055148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199174708 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.199174708 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_kmac.2178941194
Short name T212
Test name
Test status
Simulation time 177471318 ps
CPU time 6.19 seconds
Started Feb 09 08:56:51 AM UTC 25
Finished Feb 09 08:56:58 AM UTC 25
Peak memory 230744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2178941194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.kmac_test_vectors_kmac.2178941194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_kmac_xof.323500941
Short name T214
Test name
Test status
Simulation time 65246634 ps
CPU time 5.49 seconds
Started Feb 09 08:56:59 AM UTC 25
Finished Feb 09 08:57:05 AM UTC 25
Peak memory 230808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=323500941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac_xof.323500941 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_224.2626362212
Short name T380
Test name
Test status
Simulation time 346389204962 ps
CPU time 3446.57 seconds
Started Feb 09 08:56:01 AM UTC 25
Finished Feb 09 09:54:06 AM UTC 25
Peak memory 3248124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626362212 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2626362212 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_256.2971771001
Short name T361
Test name
Test status
Simulation time 93224911275 ps
CPU time 2948.41 seconds
Started Feb 09 08:56:01 AM UTC 25
Finished Feb 09 09:45:43 AM UTC 25
Peak memory 2971560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971771001 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2971771001 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_384.2949147357
Short name T287
Test name
Test status
Simulation time 495596356441 ps
CPU time 1562.59 seconds
Started Feb 09 08:56:01 AM UTC 25
Finished Feb 09 09:22:20 AM UTC 25
Peak memory 2351096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949147357 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.2949147357 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_512.1954938611
Short name T283
Test name
Test status
Simulation time 48587606856 ps
CPU time 1486.64 seconds
Started Feb 09 08:56:05 AM UTC 25
Finished Feb 09 09:21:10 AM UTC 25
Peak memory 1712064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954938611 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.1954938611 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_shake_128.244516461
Short name T458
Test name
Test status
Simulation time 106074294985 ps
CPU time 4830.15 seconds
Started Feb 09 08:56:29 AM UTC 25
Finished Feb 09 10:17:50 AM UTC 25
Peak memory 2711488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244516461 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.244516461 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/6.kmac_test_vectors_shake_256.519622015
Short name T562
Test name
Test status
Simulation time 248609959632 ps
CPU time 6757.56 seconds
Started Feb 09 08:56:34 AM UTC 25
Finished Feb 09 10:50:22 AM UTC 25
Peak memory 6490048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519622015 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.519622015 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.2907667379
Short name T235
Test name
Test status
Simulation time 57962879 ps
CPU time 1.19 seconds
Started Feb 09 09:08:55 AM UTC 25
Finished Feb 09 09:08:58 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907667379 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2907667379 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.1751309501
Short name T233
Test name
Test status
Simulation time 115918383265 ps
CPU time 285.36 seconds
Started Feb 09 09:04:01 AM UTC 25
Finished Feb 09 09:08:50 AM UTC 25
Peak memory 438284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751309501 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1751309501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.465255170
Short name T229
Test name
Test status
Simulation time 149532828 ps
CPU time 5.76 seconds
Started Feb 09 09:04:02 AM UTC 25
Finished Feb 09 09:04:09 AM UTC 25
Peak memory 234840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465255170 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.465255170 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.2179601339
Short name T230
Test name
Test status
Simulation time 17647760268 ps
CPU time 294.55 seconds
Started Feb 09 09:00:50 AM UTC 25
Finished Feb 09 09:05:49 AM UTC 25
Peak memory 241680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179601339 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2179601339 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.3242415199
Short name T231
Test name
Test status
Simulation time 497797185 ps
CPU time 33.2 seconds
Started Feb 09 09:07:37 AM UTC 25
Finished Feb 09 09:08:12 AM UTC 25
Peak memory 235340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242415199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3242415199 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.2325559161
Short name T232
Test name
Test status
Simulation time 772857469 ps
CPU time 29 seconds
Started Feb 09 09:08:12 AM UTC 25
Finished Feb 09 09:08:42 AM UTC 25
Peak memory 235236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325559161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2325559161 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.239549220
Short name T234
Test name
Test status
Simulation time 14715958872 ps
CPU time 40.09 seconds
Started Feb 09 09:08:13 AM UTC 25
Finished Feb 09 09:08:55 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239549220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.239549220 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.795346447
Short name T240
Test name
Test status
Simulation time 13305985459 ps
CPU time 329.68 seconds
Started Feb 09 09:04:10 AM UTC 25
Finished Feb 09 09:09:44 AM UTC 25
Peak memory 338000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795346447 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.795346447 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.344546915
Short name T36
Test name
Test status
Simulation time 1486390937 ps
CPU time 150.09 seconds
Started Feb 09 09:05:50 AM UTC 25
Finished Feb 09 09:08:23 AM UTC 25
Peak memory 294860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344546915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.kmac_error.344546915 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.1281180960
Short name T66
Test name
Test status
Simulation time 330760199 ps
CPU time 3.71 seconds
Started Feb 09 09:07:31 AM UTC 25
Finished Feb 09 09:07:36 AM UTC 25
Peak memory 230652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281180960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1281180960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.49026926
Short name T236
Test name
Test status
Simulation time 4172733810 ps
CPU time 32.93 seconds
Started Feb 09 09:08:24 AM UTC 25
Finished Feb 09 09:08:59 AM UTC 25
Peak memory 262148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49026926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.49026926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.368638958
Short name T319
Test name
Test status
Simulation time 15555469049 ps
CPU time 1674.15 seconds
Started Feb 09 09:00:17 AM UTC 25
Finished Feb 09 09:28:30 AM UTC 25
Peak memory 1216596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368638958 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.368638958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.4281553435
Short name T79
Test name
Test status
Simulation time 6795487576 ps
CPU time 191.6 seconds
Started Feb 09 09:04:15 AM UTC 25
Finished Feb 09 09:07:30 AM UTC 25
Peak memory 369024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281553435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.kmac_mubi.4281553435 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.3558104602
Short name T239
Test name
Test status
Simulation time 78629652157 ps
CPU time 521.39 seconds
Started Feb 09 09:00:49 AM UTC 25
Finished Feb 09 09:09:38 AM UTC 25
Peak memory 624652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558104602 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3558104602 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.29787213
Short name T173
Test name
Test status
Simulation time 7119015293 ps
CPU time 79.24 seconds
Started Feb 09 09:00:01 AM UTC 25
Finished Feb 09 09:01:35 AM UTC 25
Peak memory 235512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29787213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.kmac_smoke.29787213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.2387803389
Short name T45
Test name
Test status
Simulation time 27863994213 ps
CPU time 1057.66 seconds
Started Feb 09 09:08:43 AM UTC 25
Finished Feb 09 09:26:33 AM UTC 25
Peak memory 677880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387803389 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2387803389 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_kmac.2464647239
Short name T227
Test name
Test status
Simulation time 338661487 ps
CPU time 6.84 seconds
Started Feb 09 09:03:44 AM UTC 25
Finished Feb 09 09:03:52 AM UTC 25
Peak memory 230812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2464647239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.kmac_test_vectors_kmac.2464647239 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_kmac_xof.3164058229
Short name T228
Test name
Test status
Simulation time 764653997 ps
CPU time 6.23 seconds
Started Feb 09 09:03:53 AM UTC 25
Finished Feb 09 09:04:00 AM UTC 25
Peak memory 230820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3164058229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 7.kmac_test_vectors_kmac_xof.3164058229 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_224.3785358998
Short name T326
Test name
Test status
Simulation time 38802127312 ps
CPU time 1789.46 seconds
Started Feb 09 09:01:18 AM UTC 25
Finished Feb 09 09:31:27 AM UTC 25
Peak memory 1220676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785358998 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.3785358998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_256.2488699732
Short name T358
Test name
Test status
Simulation time 169742502927 ps
CPU time 2507.01 seconds
Started Feb 09 09:01:36 AM UTC 25
Finished Feb 09 09:43:49 AM UTC 25
Peak memory 3156020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488699732 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2488699732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_384.3944539377
Short name T299
Test name
Test status
Simulation time 13830086522 ps
CPU time 1306.94 seconds
Started Feb 09 09:02:05 AM UTC 25
Finished Feb 09 09:24:07 AM UTC 25
Peak memory 907204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944539377 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.3944539377 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_512.1758503501
Short name T300
Test name
Test status
Simulation time 33008602067 ps
CPU time 1250.22 seconds
Started Feb 09 09:03:02 AM UTC 25
Finished Feb 09 09:24:07 AM UTC 25
Peak memory 1755068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758503501 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1758503501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_shake_128.861305104
Short name T475
Test name
Test status
Simulation time 50881951856 ps
CPU time 4861.97 seconds
Started Feb 09 09:03:29 AM UTC 25
Finished Feb 09 10:25:23 AM UTC 25
Peak memory 2709488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861305104 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.861305104 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/7.kmac_test_vectors_shake_256.55933116
Short name T540
Test name
Test status
Simulation time 631205633921 ps
CPU time 6005.95 seconds
Started Feb 09 09:03:38 AM UTC 25
Finished Feb 09 10:44:44 AM UTC 25
Peak memory 6465468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55933116 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.55933116 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.1368277257
Short name T255
Test name
Test status
Simulation time 78171446 ps
CPU time 1.44 seconds
Started Feb 09 09:14:30 AM UTC 25
Finished Feb 09 09:14:33 AM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368277257 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1368277257 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.1636999736
Short name T258
Test name
Test status
Simulation time 11306908891 ps
CPU time 295.09 seconds
Started Feb 09 09:10:58 AM UTC 25
Finished Feb 09 09:15:58 AM UTC 25
Peak memory 346136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636999736 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1636999736 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2497680503
Short name T248
Test name
Test status
Simulation time 1461305614 ps
CPU time 46.29 seconds
Started Feb 09 09:11:48 AM UTC 25
Finished Feb 09 09:12:36 AM UTC 25
Peak memory 264148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497680503 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2497680503 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.1718512155
Short name T242
Test name
Test status
Simulation time 18018342376 ps
CPU time 40.73 seconds
Started Feb 09 09:09:33 AM UTC 25
Finished Feb 09 09:10:15 AM UTC 25
Peak memory 235328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718512155 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_u
nmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1718512155 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.662847412
Short name T252
Test name
Test status
Simulation time 1133300503 ps
CPU time 32.06 seconds
Started Feb 09 09:13:45 AM UTC 25
Finished Feb 09 09:14:19 AM UTC 25
Peak memory 247560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662847412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.662847412 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.3856120065
Short name T256
Test name
Test status
Simulation time 1645655921 ps
CPU time 31.45 seconds
Started Feb 09 09:14:05 AM UTC 25
Finished Feb 09 09:14:38 AM UTC 25
Peak memory 235104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856120065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3856120065 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.1810445923
Short name T254
Test name
Test status
Simulation time 8065203434 ps
CPU time 22.27 seconds
Started Feb 09 09:14:05 AM UTC 25
Finished Feb 09 09:14:29 AM UTC 25
Peak memory 230720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810445923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1810445923 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.1408477039
Short name T260
Test name
Test status
Simulation time 8946985615 ps
CPU time 271.98 seconds
Started Feb 09 09:11:51 AM UTC 25
Finished Feb 09 09:16:27 AM UTC 25
Peak memory 315408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408477039 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1408477039 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.2817495962
Short name T263
Test name
Test status
Simulation time 48779340774 ps
CPU time 238.63 seconds
Started Feb 09 09:12:38 AM UTC 25
Finished Feb 09 09:16:40 AM UTC 25
Peak memory 487552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817495962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.kmac_error.2817495962 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.1430072237
Short name T67
Test name
Test status
Simulation time 6726279128 ps
CPU time 20.1 seconds
Started Feb 09 09:13:43 AM UTC 25
Finished Feb 09 09:14:05 AM UTC 25
Peak memory 230660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430072237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1430072237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.869128324
Short name T39
Test name
Test status
Simulation time 47861654 ps
CPU time 2.18 seconds
Started Feb 09 09:14:29 AM UTC 25
Finished Feb 09 09:14:33 AM UTC 25
Peak memory 230600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869128324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.869128324 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2369836814
Short name T316
Test name
Test status
Simulation time 18049185488 ps
CPU time 1100.65 seconds
Started Feb 09 09:08:59 AM UTC 25
Finished Feb 09 09:27:32 AM UTC 25
Peak memory 981000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369836814 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2369836814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.386598413
Short name T268
Test name
Test status
Simulation time 42574353207 ps
CPU time 352.37 seconds
Started Feb 09 09:11:59 AM UTC 25
Finished Feb 09 09:17:56 AM UTC 25
Peak memory 450952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386598413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.kmac_mubi.386598413 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.2427132167
Short name T249
Test name
Test status
Simulation time 87319348072 ps
CPU time 252.52 seconds
Started Feb 09 09:09:26 AM UTC 25
Finished Feb 09 09:13:42 AM UTC 25
Peak memory 499776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427132167 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2427132167 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.2065237272
Short name T175
Test name
Test status
Simulation time 3069814899 ps
CPU time 44.24 seconds
Started Feb 09 09:08:58 AM UTC 25
Finished Feb 09 09:09:45 AM UTC 25
Peak memory 230796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065237272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.kmac_smoke.2065237272 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.2519189649
Short name T324
Test name
Test status
Simulation time 465566438702 ps
CPU time 960.28 seconds
Started Feb 09 09:14:29 AM UTC 25
Finished Feb 09 09:30:41 AM UTC 25
Peak memory 516484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519189649 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2519189649 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_kmac.4030203656
Short name T243
Test name
Test status
Simulation time 606876050 ps
CPU time 6.4 seconds
Started Feb 09 09:10:40 AM UTC 25
Finished Feb 09 09:10:48 AM UTC 25
Peak memory 230812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4030203656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.kmac_test_vectors_kmac.4030203656 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_kmac_xof.3871846859
Short name T244
Test name
Test status
Simulation time 253260081 ps
CPU time 6.94 seconds
Started Feb 09 09:10:49 AM UTC 25
Finished Feb 09 09:10:57 AM UTC 25
Peak memory 230752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3871846859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 8.kmac_test_vectors_kmac_xof.3871846859 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_224.1664130323
Short name T340
Test name
Test status
Simulation time 19759894369 ps
CPU time 1620.22 seconds
Started Feb 09 09:09:39 AM UTC 25
Finished Feb 09 09:36:56 AM UTC 25
Peak memory 1216448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664130323 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1664130323 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_256.2904913556
Short name T346
Test name
Test status
Simulation time 18316354160 ps
CPU time 1723.96 seconds
Started Feb 09 09:09:45 AM UTC 25
Finished Feb 09 09:38:49 AM UTC 25
Peak memory 1138688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904913556 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2904913556 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_384.2193197543
Short name T339
Test name
Test status
Simulation time 48339300483 ps
CPU time 1599.23 seconds
Started Feb 09 09:09:46 AM UTC 25
Finished Feb 09 09:36:43 AM UTC 25
Peak memory 2379828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193197543 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2193197543 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_512.3354584000
Short name T296
Test name
Test status
Simulation time 43280683892 ps
CPU time 798.44 seconds
Started Feb 09 09:10:06 AM UTC 25
Finished Feb 09 09:23:33 AM UTC 25
Peak memory 712696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354584000 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3354584000 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_shake_128.1802398960
Short name T638
Test name
Test status
Simulation time 756327999980 ps
CPU time 7480.74 seconds
Started Feb 09 09:10:07 AM UTC 25
Finished Feb 09 11:16:07 AM UTC 25
Peak memory 7954464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802398960 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.1802398960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/8.kmac_test_vectors_shake_256.1264017792
Short name T440
Test name
Test status
Simulation time 75458692164 ps
CPU time 3647 seconds
Started Feb 09 09:10:16 AM UTC 25
Finished Feb 09 10:11:41 AM UTC 25
Peak memory 2213824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264017792 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1264017792 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.157760317
Short name T275
Test name
Test status
Simulation time 24928368 ps
CPU time 1.3 seconds
Started Feb 09 09:18:54 AM UTC 25
Finished Feb 09 09:18:56 AM UTC 25
Peak memory 214468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157760317 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.157760317 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.4214614304
Short name T276
Test name
Test status
Simulation time 17910375975 ps
CPU time 135.19 seconds
Started Feb 09 09:16:50 AM UTC 25
Finished Feb 09 09:19:07 AM UTC 25
Peak memory 282696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214614304 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.4214614304 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.4046288465
Short name T290
Test name
Test status
Simulation time 49973051383 ps
CPU time 354.23 seconds
Started Feb 09 09:16:52 AM UTC 25
Finished Feb 09 09:22:51 AM UTC 25
Peak memory 466964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046288465 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.4046288465 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.197130987
Short name T310
Test name
Test status
Simulation time 38501751132 ps
CPU time 721.1 seconds
Started Feb 09 09:14:40 AM UTC 25
Finished Feb 09 09:26:49 AM UTC 25
Peak memory 262160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197130987 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_un
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.197130987 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.3721812816
Short name T274
Test name
Test status
Simulation time 1172925034 ps
CPU time 28.67 seconds
Started Feb 09 09:18:22 AM UTC 25
Finished Feb 09 09:18:52 AM UTC 25
Peak memory 235276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721812816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3721812816 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.2935050816
Short name T273
Test name
Test status
Simulation time 127741922 ps
CPU time 13.39 seconds
Started Feb 09 09:18:27 AM UTC 25
Finished Feb 09 09:18:42 AM UTC 25
Peak memory 235244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935050816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2935050816 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.1307947306
Short name T280
Test name
Test status
Simulation time 6325489617 ps
CPU time 80.26 seconds
Started Feb 09 09:18:39 AM UTC 25
Finished Feb 09 09:20:02 AM UTC 25
Peak memory 230800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307947306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1307947306 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.3284550181
Short name T269
Test name
Test status
Simulation time 3121399588 ps
CPU time 77.32 seconds
Started Feb 09 09:16:53 AM UTC 25
Finished Feb 09 09:18:12 AM UTC 25
Peak memory 272388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284550181 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3284550181 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.3190757857
Short name T37
Test name
Test status
Simulation time 5307787418 ps
CPU time 86.1 seconds
Started Feb 09 09:18:13 AM UTC 25
Finished Feb 09 09:19:41 AM UTC 25
Peak memory 278532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190757857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.kmac_error.3190757857 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.1315817396
Short name T68
Test name
Test status
Simulation time 4930721712 ps
CPU time 7.87 seconds
Started Feb 09 09:18:17 AM UTC 25
Finished Feb 09 09:18:27 AM UTC 25
Peak memory 230788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315817396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1315817396 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.2364853113
Short name T7
Test name
Test status
Simulation time 45579122 ps
CPU time 1.92 seconds
Started Feb 09 09:18:42 AM UTC 25
Finished Feb 09 09:18:45 AM UTC 25
Peak memory 229768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364853113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2364853113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.3190620626
Short name T483
Test name
Test status
Simulation time 121755839193 ps
CPU time 4324.63 seconds
Started Feb 09 09:14:34 AM UTC 25
Finished Feb 09 10:27:23 AM UTC 25
Peak memory 4661268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190620626 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.3190620626 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.4015628674
Short name T272
Test name
Test status
Simulation time 1481269030 ps
CPU time 41.92 seconds
Started Feb 09 09:17:57 AM UTC 25
Finished Feb 09 09:18:41 AM UTC 25
Peak memory 264520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015628674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.kmac_mubi.4015628674 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.441774912
Short name T278
Test name
Test status
Simulation time 28853133844 ps
CPU time 280.33 seconds
Started Feb 09 09:14:34 AM UTC 25
Finished Feb 09 09:19:18 AM UTC 25
Peak memory 417808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441774912 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unm
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.441774912 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.3809134556
Short name T257
Test name
Test status
Simulation time 3316263819 ps
CPU time 40.48 seconds
Started Feb 09 09:14:30 AM UTC 25
Finished Feb 09 09:15:12 AM UTC 25
Peak memory 230788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809134556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.kmac_smoke.3809134556 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.2397619865
Short name T47
Test name
Test status
Simulation time 80730714866 ps
CPU time 1633.79 seconds
Started Feb 09 09:18:43 AM UTC 25
Finished Feb 09 09:46:15 AM UTC 25
Peak memory 682404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/o
s_regression/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397619865 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2397619865 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_kmac.1182326678
Short name T265
Test name
Test status
Simulation time 123280887 ps
CPU time 5.38 seconds
Started Feb 09 09:16:41 AM UTC 25
Finished Feb 09 09:16:49 AM UTC 25
Peak memory 230748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1182326678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.kmac_test_vectors_kmac.1182326678 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_kmac_xof.3396906192
Short name T267
Test name
Test status
Simulation time 728981448 ps
CPU time 6.9 seconds
Started Feb 09 09:16:42 AM UTC 25
Finished Feb 09 09:16:52 AM UTC 25
Peak memory 230756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3396906192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 9.kmac_test_vectors_kmac_xof.3396906192 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_224.1688286617
Short name T359
Test name
Test status
Simulation time 38427018658 ps
CPU time 1731.12 seconds
Started Feb 09 09:15:14 AM UTC 25
Finished Feb 09 09:44:24 AM UTC 25
Peak memory 1232836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688286617 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1688286617 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_256.1884666491
Short name T356
Test name
Test status
Simulation time 18444296136 ps
CPU time 1535.45 seconds
Started Feb 09 09:15:59 AM UTC 25
Finished Feb 09 09:41:51 AM UTC 25
Peak memory 1146936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884666491 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.1884666491 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_384.3140987118
Short name T397
Test name
Test status
Simulation time 459645125237 ps
CPU time 2520.86 seconds
Started Feb 09 09:16:02 AM UTC 25
Finished Feb 09 09:58:32 AM UTC 25
Peak memory 2359224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140987118 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3140987118 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_512.3754543897
Short name T341
Test name
Test status
Simulation time 138196798631 ps
CPU time 1252.28 seconds
Started Feb 09 09:16:28 AM UTC 25
Finished Feb 09 09:37:35 AM UTC 25
Peak memory 1763264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754543897 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3754543897 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_shake_128.1234631788
Short name T508
Test name
Test status
Simulation time 204472300475 ps
CPU time 4528.57 seconds
Started Feb 09 09:16:29 AM UTC 25
Finished Feb 09 10:32:45 AM UTC 25
Peak memory 2723772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234631788 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.1234631788 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/coverage/default/9.kmac_test_vectors_shake_256.2088302235
Short name T480
Test name
Test status
Simulation time 44729202807 ps
CPU time 4182.81 seconds
Started Feb 09 09:16:40 AM UTC 25
Finished Feb 09 10:27:08 AM UTC 25
Peak memory 2236352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-v
cs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088302235 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.2088302235 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_test_vectors_shake_256/latest
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