LC_CTRL Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.820s	1.045ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.070s	217.998us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.030s	45.763us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.080s	101.234us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.720s	133.452us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.150s	25.712us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.030s	45.763us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	133.452us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.150s	403.083us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.800s	392.166us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.920s	12.727us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.260s	122.638us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.990s	580.132us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_prog_failure	4.260s	122.638us	50	50	100.00
		lc_ctrl_errors	21.990s	580.132us	50	50	100.00
		lc_ctrl_security_escalation	14.210s	379.117us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.857m	4.714ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.530s	908.688us	20	20	100.00
		lc_ctrl_jtag_errors	2.255m	5.428ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.300s	618.877us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.880s	1.215ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.530s	908.688us	20	20	100.00
		lc_ctrl_jtag_errors	2.255m	5.428ms	20	20	100.00
		lc_ctrl_jtag_access	30.380s	1.450ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.820s	6.795ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.560s	274.972us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.400s	185.864us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.740s	2.681ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	27.490s	1.409ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.970s	48.948us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.980s	216.886us	9	10	90.00
		lc_ctrl_jtag_alert_test	2.040s	135.906us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	42.240s	1.970ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.120s	19.190us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.136m	41.201ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.360s	24.736us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.840s	376.984us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.840s	376.984us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.070s	217.998us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	45.763us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	133.452us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	49.634us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.070s	217.998us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	45.763us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	133.452us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	49.634us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
		lc_ctrl_tl_intg_err	4.450s	123.032us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.450s	123.032us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.800s	392.166us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	55.890s	560.083us	50	50	100.00
		lc_ctrl_sec_cm	1.151m	625.714us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.210s	379.117us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.150s	403.083us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.880s	1.215ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.990s	2.694ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.990s	2.694ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.000s	1.007ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.620s	444.019us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.620s	444.019us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.875h	153.745ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			988	1030	95.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.23	97.18	95.26	91.98	100.00	95.88	98.48	94.82

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.555240103
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:99631210-5a01-4575-be43-3716b381ceae
```
  - 1.lc_ctrl_stress_all_with_rand_reset.2632087202
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:334f8035-7f9a-4f52-9189-64d19b5f5624
```
  - ... and 21 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 10 failures.
  - 9.lc_ctrl_stress_all_with_rand_reset.3896067369
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7f56cf85-adf5-4011-a174-69e5281752c8
```
  - 20.lc_ctrl_stress_all_with_rand_reset.2296489887
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e680184f-9969-4180-80ac-e4b91b47b3b6
```
  - ... and 8 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 4 failures:

Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

6.lc_ctrl_stress_all_with_rand_reset.2746758531
Line 3154, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 9270974445 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x4d734a00
  UVM_INFO @ 9270974445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.lc_ctrl_stress_all_with_rand_reset.4124345334
Line 448, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 1319687584 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x1acd9e0c
  UVM_INFO @ 1319687584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

21.lc_ctrl_stress_all_with_rand_reset.3321598253
Line 16051, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18081929667 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 18081929667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.lc_ctrl_stress_all_with_rand_reset.3510646886
Line 8845, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14536203916 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 14536203916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_jtag_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2387365475
    Line 304, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  73829557 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @  73829557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 5.lc_ctrl_stress_all_with_rand_reset.3663993418
    Line 2363, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7907405969 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked2
  UVM_INFO @ 7907405969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.lc_ctrl_stress_all_with_rand_reset.12288151
    Line 3789, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4823051454 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
  UVM_INFO @ 4823051454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```