LC_CTRL Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: `f8b3c19a2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.730s	250.316us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.030s	45.406us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.030s	13.957us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.920s	48.581us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.230s	60.204us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.000s	28.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.030s	13.957us	20	20	100.00
		lc_ctrl_csr_aliasing	1.230s	60.204us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.290s	62.765us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.780s	356.418us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	14.077us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.730s	198.737us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.070s	589.004us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_prog_failure	4.730s	198.737us	50	50	100.00
		lc_ctrl_errors	23.070s	589.004us	50	50	100.00
		lc_ctrl_security_escalation	16.360s	2.927ms	50	50	100.00
		lc_ctrl_jtag_state_failure	3.034m	5.204ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.440s	954.094us	20	20	100.00
		lc_ctrl_jtag_errors	2.036m	4.718ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.260s	643.239us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.910s	1.070ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.440s	954.094us	20	20	100.00
		lc_ctrl_jtag_errors	2.036m	4.718ms	20	20	100.00
		lc_ctrl_jtag_access	33.390s	1.558ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	26.180s	3.497ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.560s	279.032us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.590s	180.819us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.090s	1.333ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.720s	1.415ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.950s	44.053us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.580s	128.730us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.910s	108.488us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	22.000s	2.186ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.370s	85.247us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.483m	23.023ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	251.414us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.800s	131.078us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.800s	131.078us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.030s	45.406us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	13.957us	20	20	100.00
		lc_ctrl_csr_aliasing	1.230s	60.204us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	96.751us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.030s	45.406us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	13.957us	20	20	100.00
		lc_ctrl_csr_aliasing	1.230s	60.204us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	96.751us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
		lc_ctrl_tl_intg_err	3.890s	105.053us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.890s	105.053us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.780s	356.418us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.046m	4.089ms	50	50	100.00
		lc_ctrl_sec_cm	42.810s	392.439us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.360s	2.927ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.290s	62.765us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.910s	1.070ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	33.560s	1.780ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	33.560s	1.780ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.310s	2.445ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.810s	729.055us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.810s	729.055us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.304h	220.665ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			987	1030	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.11	97.18	94.81	91.98	100.00	95.67	98.48	94.64

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.1370392475
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e7e7c536-597c-46a1-afd3-55199527f985
```
  - 2.lc_ctrl_stress_all_with_rand_reset.1908087661
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e64b1eef-fb8c-4e7f-9ddc-ce0d4a7d0a16
```
  - ... and 21 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 11 failures.
  - 5.lc_ctrl_stress_all_with_rand_reset.1573016719
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c6f60aff-9f6e-43ef-823f-84f5f0e4d410
```
  - 10.lc_ctrl_stress_all_with_rand_reset.3258977209
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:dca73e53-51cc-46d0-93b4-e7439462eb6e
```
  - ... and 9 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 5 failures:

Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

8.lc_ctrl_stress_all_with_rand_reset.4091152303
Line 9770, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 36709169604 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x4cad1584
  UVM_INFO @ 36709169604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.lc_ctrl_stress_all_with_rand_reset.552079934
Line 7240, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 5803104199 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x7c362600
  UVM_INFO @ 5803104199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.lc_ctrl_stress_all_with_rand_reset.66672388
    Line 4297, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6195677413 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 6195677413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.lc_ctrl_stress_all_with_rand_reset.689117480
    Line 84766, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.lc_ctrl_stress_all_with_rand_reset.962231739
    Line 15558, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22334538360 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked3
  UVM_INFO @ 22334538360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.lc_ctrl_stress_all_with_rand_reset.2310514519
    Line 16089, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32630036168 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
  UVM_INFO @ 32630036168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```