ASSERT | PROPERTIES | SEQUENCES | |
Total | 384 | 0 | 10 |
Category 0 | 384 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 384 | 0 | 10 |
Severity 0 | 384 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 384 | 100.00 |
Uncovered | 5 | 1.30 |
Success | 379 | 98.70 |
Failure | 0 | 0.00 |
Incomplete | 6 | 1.56 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.FpvSecCmCtrlKmacIfFsmCheck_A | 0 | 0 | 64979160 | 0 | 0 | 0 | |
tb.dut.FpvSecCmCtrlLcCntCheck_A | 0 | 0 | 61119180 | 0 | 0 | 0 | |
tb.dut.FpvSecCmCtrlLcFsmCheck_A | 0 | 0 | 64918526 | 0 | 0 | 0 | |
tb.dut.FpvSecCmTapRegWeOnehotCheck_A | 0 | 0 | 66768896 | 0 | 0 | 0 | |
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A | 0 | 0 | 66768896 | 0 | 0 | 1988 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_lc_ctrl_fsm.ClkBypStaysOnOnceAsserted_A | 0 | 0 | 66768896 | 3314055 | 0 | 79 | |
tb.dut.u_lc_ctrl_fsm.EscStaysOnOnceAsserted_A | 0 | 0 | 66768896 | 14044602 | 0 | 6 | |
tb.dut.u_lc_ctrl_fsm.FlashRmaStaysOnOnceAsserted_A | 0 | 0 | 66768896 | 466550 | 0 | 14 | |
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A | 0 | 0 | 66768896 | 0 | 0 | 1988 | |
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.OutputDelay_A | 0 | 0 | 66498771 | 63284797 | 0 | 2370 | |
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A | 0 | 0 | 66375334 | 63163713 | 0 | 2376 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 69388671 | 936 | 936 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 69388671 | 76 | 76 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 69388671 | 76 | 76 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 69388671 | 41 | 41 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 69388671 | 22 | 22 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 69388671 | 33 | 33 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 69388671 | 40 | 40 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 69388671 | 4216 | 4216 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 69388671 | 10571 | 10571 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 69388671 | 1091931 | 1091931 | 308 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 69388671 | 936 | 936 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 69388671 | 76 | 76 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 69388671 | 76 | 76 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 69388671 | 41 | 41 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 69388671 | 22 | 22 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 69388671 | 33 | 33 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 69388671 | 40 | 40 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 69388671 | 4216 | 4216 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 69388671 | 10571 | 10571 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 69388671 | 1091931 | 1091931 | 308 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |