Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.35	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	2	62	96.88
Crosses	60	5	55	91.67

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	2	43	95.56	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	3	27	90.00	100	1	1	0
scrap_state1_xp	30	2	28	93.33	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148351120

1

T46

3751

T69

2305

T70

3751

auto[1]

1185780

1

T1

693

T9

9012

T4

196

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148295150

1

T46

3751

T69

2305

T70

3751

auto[1]

1241750

1

T1

1089

T9

9159

T4

98

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5584735	1			T46	196		T69	129		T70	196
auto[IdleSt]	39304775	1			T46	3555		T69	2176		T70	3555
auto[ClkMuxSt]	28220	1			T1	18		T2	18		T3	18
auto[CntIncrSt]	28170	1			T1	18		T2	18		T3	18
auto[CntProgSt]	51350	1			T1	36		T2	36		T3	36
auto[TransCheckSt]	23210	1			T2	18		T3	18		T9	44
auto[TokenHashSt]	70087540	1			T2	11777		T3	11304		T9	10596
auto[FlashRmaSt]	22440	1			T2	50		T3	50		T9	27
auto[TokenCheck0St]	9920	1			T2	18		T3	18		T9	17
auto[TokenCheck1St]	7610	1			T2	18		T3	18		T9	17
auto[TransProgSt]	13330	1			T2	36		T3	36		T9	24
auto[PostTransSt]	15186350	1			T1	1452		T2	7600		T3	981
auto[ScrapSt]	91265	1			T78	701		T79	701		T80	701
auto[EscalateSt]	6569820	1			T1	2645		T9	12339		T4	7041
auto[InvalidSt]	12527065	1			T4	6529		T42	9478		T22	2461

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	2	43	95.56

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1
arcs[TokenCheck0St=>EscalateSt]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1100	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12527065	1			T4	6529		T42	9478		T22	2461
EscalateSt	6569820	1			T1	2645		T9	12339		T4	7041
ScrapSt	91265	1			T78	701		T79	701		T80	701
PostTransSt	15186350	1			T1	1452		T2	7600		T3	981
TransProgSt	13330	1			T2	36		T3	36		T9	24
TokenCheck1St	7610	1			T2	18		T3	18		T9	17
TokenCheck0St	9920	1			T2	18		T3	18		T9	17
FlashRmaSt	22440	1			T2	50		T3	50		T9	27
TokenHashSt	70087540	1			T2	11777		T3	11304		T9	10596
TransCheckSt	23210	1			T2	18		T3	18		T9	44
CntProgSt	51350	1			T1	36		T2	36		T3	36
CntIncrSt	28170	1			T1	18		T2	18		T3	18
ClkMuxSt	28220	1			T1	18		T2	18		T3	18
IdleSt	39304775	1			T46	3555		T69	2176		T70	3555
ResetSt	5584735	1			T46	196		T69	129		T70	196
arcs[ResetSt=>IdleSt]	42970	1			T46	2		T69	3		T70	2
arcs[IdleSt=>ScrapSt]	170	1			T78	1		T79	1		T80	1
arcs[IdleSt=>ClkMuxSt]	28220	1			T1	18		T2	18		T3	18
arcs[ClkMuxSt=>CntIncrSt]	28170	1			T1	18		T2	18		T3	18
arcs[CntIncrSt=>PostTransSt]	1440	1			T11	12		T5	12		T15	12
arcs[CntIncrSt=>CntProgSt]	26630	1			T1	18		T2	18		T3	18
arcs[CntProgSt=>PostTransSt]	3070	1			T1	18		T11	6		T19	18
arcs[CntProgSt=>TransCheckSt]	23210	1			T2	18		T3	18		T9	44
arcs[TransCheckSt=>PostTransSt]	2680	1			T11	9		T5	11		T15	11
arcs[TransCheckSt=>TokenHashSt]	20380	1			T2	18		T3	18		T9	41
arcs[TokenHashSt=>PostTransSt]	9110	1			T11	28		T21	72		T22	12
arcs[TokenHashSt=>FlashRmaSt]	9970	1			T2	18		T3	18		T9	18
arcs[FlashRmaSt=>TokenCheck0St]	9920	1			T2	18		T3	18		T9	17
arcs[TokenCheck0St=>PostTransSt]	2310	1			T11	9		T22	8		T5	9
arcs[TokenCheck0St=>TokenCheck1St]	7610	1			T2	18		T3	18		T9	17
arcs[TokenCheck1St=>PostTransSt]	620	1			T22	1		T40	1		T16	11
arcs[TransProgSt=>PostTransSt]	6540	1			T2	18		T3	18		T9	8
arcs[IdleSt=>EscalateSt]	250	1			T9	5		T23	5		T94	5
arcs[ClkMuxSt=>EscalateSt]	50	1			T9	1		T23	1		T94	1
arcs[CntIncrSt=>EscalateSt]	100	1			T9	2		T23	2		T94	2
arcs[CntProgSt=>EscalateSt]	350	1			T9	7		T23	7		T94	7
arcs[TransCheckSt=>EscalateSt]	150	1			T9	3		T23	3		T94	3
arcs[TokenHashSt=>EscalateSt]	1300	1			T9	23		T11	1		T23	23
arcs[FlashRmaSt=>EscalateSt]	50	1			T9	1		T23	1		T94	1
arcs[TokenCheck1St=>EscalateSt]	200	1			T9	4		T23	4		T94	4
arcs[TransProgSt=>EscalateSt]	250	1			T9	5		T23	5		T94	5
arcs[PostTransSt=>EscalateSt]	3520	1			T1	18		T9	8		T11	7
arcs[InvalidSt=>EscalateSt]	12120	1			T4	3		T42	63		T22	14

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	3	27	90.00	3

Automatically Generated Cross Bins for scrap_state0_xp

Uncovered bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[ResetSt]]	0	1	1
[auto[1]]	[auto[TokenCheck0St]]	0	1	1
[auto[1]]	[auto[ScrapSt]]	0	1	1

Covered bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5584735	1			T46	196		T69	129		T70	196
auto[0]	auto[IdleSt]	39304525	1			T46	3555		T69	2176		T70	3555
auto[0]	auto[ClkMuxSt]	28170	1			T1	18		T2	18		T3	18
auto[0]	auto[CntIncrSt]	28120	1			T1	18		T2	18		T3	18
auto[0]	auto[CntProgSt]	51150	1			T1	36		T2	36		T3	36
auto[0]	auto[TransCheckSt]	23110	1			T2	18		T3	18		T9	42
auto[0]	auto[TokenHashSt]	70086590	1			T2	11777		T3	11304		T9	10578
auto[0]	auto[FlashRmaSt]	22390	1			T2	50		T3	50		T9	26
auto[0]	auto[TokenCheck0St]	9920	1			T2	18		T3	18		T9	17
auto[0]	auto[TokenCheck1St]	7460	1			T2	18		T3	18		T9	14
auto[0]	auto[TransProgSt]	13130	1			T2	36		T3	36		T9	20
auto[0]	auto[PostTransSt]	15184630	1			T1	1445		T2	7600		T3	981
auto[0]	auto[ScrapSt]	91265	1			T78	701		T79	701		T80	701
auto[0]	auto[EscalateSt]	5393690	1			T1	1959		T9	3371		T4	6847
auto[0]	auto[InvalidSt]	12521135	1			T4	6527		T42	9441		T22	2454
auto[1]	auto[IdleSt]	250	1			T9	5		T23	5		T94	5
auto[1]	auto[ClkMuxSt]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[CntIncrSt]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[CntProgSt]	200	1			T9	4		T23	4		T94	4
auto[1]	auto[TransCheckSt]	100	1			T9	2		T23	2		T94	2
auto[1]	auto[TokenHashSt]	950	1			T9	18		T23	18		T5	1
auto[1]	auto[FlashRmaSt]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[TokenCheck1St]	150	1			T9	3		T23	3		T94	3
auto[1]	auto[TransProgSt]	200	1			T9	4		T23	4		T94	4
auto[1]	auto[PostTransSt]	1720	1			T1	7		T9	5		T11	4
auto[1]	auto[EscalateSt]	1176130	1			T1	686		T9	8968		T4	194
auto[1]	auto[InvalidSt]	5930	1			T4	2		T42	37		T22	7

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	2	28	93.33	2

Automatically Generated Cross Bins for scrap_state1_xp

Uncovered bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[TokenCheck0St]]	0	1	1
[auto[1]]	[auto[ScrapSt]]	0	1	1

Covered bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5584685	1			T46	196		T69	129		T70	196
auto[0]	auto[IdleSt]	39304575	1			T46	3555		T69	2176		T70	3555
auto[0]	auto[ClkMuxSt]	28170	1			T1	18		T2	18		T3	18
auto[0]	auto[CntIncrSt]	28070	1			T1	18		T2	18		T3	18
auto[0]	auto[CntProgSt]	51050	1			T1	36		T2	36		T3	36
auto[0]	auto[TransCheckSt]	23160	1			T2	18		T3	18		T9	43
auto[0]	auto[TokenHashSt]	70086690	1			T2	11777		T3	11304		T9	10581
auto[0]	auto[FlashRmaSt]	22390	1			T2	50		T3	50		T9	26
auto[0]	auto[TokenCheck0St]	9920	1			T2	18		T3	18		T9	17
auto[0]	auto[TokenCheck1St]	7560	1			T2	18		T3	18		T9	16
auto[0]	auto[TransProgSt]	13080	1			T2	36		T3	36		T9	19
auto[0]	auto[PostTransSt]	15184350	1			T1	1441		T2	7600		T3	981
auto[0]	auto[ScrapSt]	91265	1			T78	701		T79	701		T80	701
auto[0]	auto[EscalateSt]	5338210	1			T1	1567		T9	3224		T4	6944
auto[0]	auto[InvalidSt]	12520875	1			T4	6528		T42	9452		T22	2454
auto[1]	auto[ResetSt]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[IdleSt]	200	1			T9	4		T23	4		T94	4
auto[1]	auto[ClkMuxSt]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[CntIncrSt]	100	1			T9	2		T23	2		T94	2
auto[1]	auto[CntProgSt]	300	1			T9	6		T23	6		T94	6
auto[1]	auto[TransCheckSt]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[TokenHashSt]	850	1			T9	15		T11	1		T23	15
auto[1]	auto[FlashRmaSt]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[TokenCheck1St]	50	1			T9	1		T23	1		T94	1
auto[1]	auto[TransProgSt]	250	1			T9	5		T23	5		T94	5
auto[1]	auto[PostTransSt]	2000	1			T1	11		T9	7		T11	3
auto[1]	auto[EscalateSt]	1231610	1			T1	1078		T9	9115		T4	97
auto[1]	auto[InvalidSt]	6190	1			T4	1		T42	26		T22	7