Unified Coverage Report :: Cond split page

Go back

 LINE       1235
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1236
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T73,T95,T96
1	1	1	Covered	T46,T69,T70

 LINE       1239
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1240
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1243
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T20,T6,T7

 LINE       1244
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T78,T79,T80
1	1	1	Covered	T3,T10,T12

 LINE       1249
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1250
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T73,T95,T96
1	1	1	Covered	T46,T69,T70

 LINE       1253
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1254
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T73,T95,T96
1	1	1	Covered	T46,T69,T70

 LINE       1257
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1258
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T46,T69,T70

 LINE       1261
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1262
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T73,T95,T96
1	1	1	Covered	T46,T69,T70

 LINE       1265
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T46,T69,T70

 LINE       1266
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T73,T95,T96
1	1	1	Covered	T46,T69,T70

 LINE       1269
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1270
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T46,T69,T70

 LINE       1273
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T69,T71,T81

 LINE       1274
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1275
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1276
 EXPRESSION (addr_hit[16] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       1277
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1278
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1279
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1280
 EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1281
 EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1282
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1283
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1284
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1285
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1286
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T78,T79,T80
1	1	1	Covered	T1,T3,T9

 LINE       1287
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1288
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1289
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Covered	T78,T79,T80
1	1	1	Covered	T1,T3,T9

 LINE       1290
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1291
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1292
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       1294
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T69,T70
1	0	1	Covered	T46,T69,T70
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9