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LINE 1282
EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1283
EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1284
EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1285
EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1286
EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1287
EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1288
EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1289
EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1290
EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1291
EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1292
EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1293
EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1294
EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T75,T76,T97 |
| 1 | 0 | 1 | Covered | T75,T76,T97 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T2,T4,T5 |