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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.66 96.94 91.76 84.26 90.70 94.70 98.48 91.79


Total test records in report: 980
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T752 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.86774235033722462620454043232100097695018985883354365624043630991843009189361 Nov 22 01:36:49 PM PST 23 Nov 22 01:36:53 PM PST 23 16404398 ps
T83 /workspace/coverage/default/3.lc_ctrl_sec_cm.23945167712676880729110958535347872971005368645315696878246498078529410047625 Nov 22 01:37:13 PM PST 23 Nov 22 01:37:51 PM PST 23 386472866 ps
T753 /workspace/coverage/default/5.lc_ctrl_smoke.58099951035266086896215811413303786496757044123032852393994093977891047249717 Nov 22 01:37:26 PM PST 23 Nov 22 01:37:34 PM PST 23 291295056 ps
T754 /workspace/coverage/default/31.lc_ctrl_sec_mubi.102190431119908705551794921016543865867508404339340317310791486354770291586372 Nov 22 01:39:05 PM PST 23 Nov 22 01:39:21 PM PST 23 1010128591 ps
T755 /workspace/coverage/default/10.lc_ctrl_security_escalation.75467654115109375168288606720084805570513221052563948724005562465277047919341 Nov 22 01:37:54 PM PST 23 Nov 22 01:38:08 PM PST 23 625328098 ps
T756 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.52202437055552894937017937305584025163828303910301298557972746341678427221779 Nov 22 01:37:25 PM PST 23 Nov 22 01:37:29 PM PST 23 16404398 ps
T757 /workspace/coverage/default/18.lc_ctrl_alert_test.58794143119294111800459896716114454559945914368364387475134660824115581172135 Nov 22 01:38:05 PM PST 23 Nov 22 01:38:11 PM PST 23 42189906 ps
T758 /workspace/coverage/default/14.lc_ctrl_stress_all.89209238263449939696630237751626975545487707341742221524054031252966549095090 Nov 22 01:37:53 PM PST 23 Nov 22 01:42:42 PM PST 23 36820395678 ps
T759 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.108241148940140552972099377371848345637020988716518075592363356937837097015916 Nov 22 01:37:45 PM PST 23 Nov 22 01:37:53 PM PST 23 19636515 ps
T760 /workspace/coverage/default/48.lc_ctrl_jtag_access.25566388189691528949589170303402128560389243965757776083292137782274651955271 Nov 22 01:39:47 PM PST 23 Nov 22 01:39:57 PM PST 23 1895300081 ps
T761 /workspace/coverage/default/47.lc_ctrl_state_failure.109374025256334856917247616134156662777114204568991141794698300032021431874778 Nov 22 01:39:59 PM PST 23 Nov 22 01:40:21 PM PST 23 487150632 ps
T762 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.59310289823382821989398047008336084717428850794117890660368470002052682305420 Nov 22 01:38:10 PM PST 23 Nov 22 01:38:32 PM PST 23 1491321170 ps
T763 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.6394421229163898467714144469189131866190858577568516371896765224173631123322 Nov 22 01:38:05 PM PST 23 Nov 22 01:38:21 PM PST 23 964986095 ps
T764 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.74697101264450460365900466286634351800791016212871311844251261394107429092659 Nov 22 01:38:15 PM PST 23 Nov 22 01:38:32 PM PST 23 964986095 ps
T765 /workspace/coverage/default/23.lc_ctrl_sec_mubi.87075067686415418779320252187201099258622546466162563217166569297751066239712 Nov 22 01:38:10 PM PST 23 Nov 22 01:38:30 PM PST 23 1010128591 ps
T766 /workspace/coverage/default/2.lc_ctrl_errors.131940906480412110010788196163251801856031320717166562814625140037254045293 Nov 22 01:36:52 PM PST 23 Nov 22 01:37:11 PM PST 23 978628843 ps
T767 /workspace/coverage/default/47.lc_ctrl_state_post_trans.53417268645778953435875482746237080846218872960605356769867120874832360321069 Nov 22 01:40:06 PM PST 23 Nov 22 01:40:14 PM PST 23 217117078 ps
T768 /workspace/coverage/default/8.lc_ctrl_security_escalation.37163321358312626940304723086691748341611769379020883997630581720671587640140 Nov 22 01:37:55 PM PST 23 Nov 22 01:38:09 PM PST 23 625328098 ps
T769 /workspace/coverage/default/17.lc_ctrl_security_escalation.106319082682177742688495437233441963444883268961756644807245064243601987338269 Nov 22 01:37:59 PM PST 23 Nov 22 01:38:10 PM PST 23 625328098 ps
T770 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.31558836949843218774384554350813273134052665795304924533539738457907551631681 Nov 22 01:37:39 PM PST 23 Nov 22 01:37:50 PM PST 23 1406053995 ps
T771 /workspace/coverage/default/35.lc_ctrl_state_failure.51124364675464909163754273208374140208750643117387136548039932348989092067925 Nov 22 01:39:13 PM PST 23 Nov 22 01:39:35 PM PST 23 487150632 ps
T772 /workspace/coverage/default/5.lc_ctrl_jtag_priority.9547151992833389571678021015262853930583581003616028856286721678811246654812 Nov 22 01:37:44 PM PST 23 Nov 22 01:38:04 PM PST 23 2797596434 ps
T773 /workspace/coverage/default/6.lc_ctrl_state_failure.99542441694332533573964547178951305832440374592172607171325249565148526553422 Nov 22 01:38:00 PM PST 23 Nov 22 01:38:25 PM PST 23 487150632 ps
T774 /workspace/coverage/default/7.lc_ctrl_jtag_access.61421419213886593770220224654891039743985450961834181671604197190727181050736 Nov 22 01:37:42 PM PST 23 Nov 22 01:37:54 PM PST 23 1895300081 ps
T775 /workspace/coverage/default/19.lc_ctrl_errors.77990839519855345845760717247147211998337087349664086001270559440720391707406 Nov 22 01:38:09 PM PST 23 Nov 22 01:38:29 PM PST 23 978628843 ps
T776 /workspace/coverage/default/13.lc_ctrl_stress_all.20008237404311408455512431004058524816655142001838368323931297385862365161515 Nov 22 01:37:43 PM PST 23 Nov 22 01:42:35 PM PST 23 36820395678 ps
T777 /workspace/coverage/default/39.lc_ctrl_state_post_trans.89030718115968776048271769156629374276859322039154106279715918776856174569970 Nov 22 01:39:18 PM PST 23 Nov 22 01:39:26 PM PST 23 217117078 ps
T778 /workspace/coverage/default/36.lc_ctrl_prog_failure.55175891034801716255902209831852055607189901793859055156651641636323007779899 Nov 22 01:39:15 PM PST 23 Nov 22 01:39:20 PM PST 23 159313969 ps
T779 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.13707372503704269299204871664426862522293435684297045374645980966695038797190 Nov 22 01:39:59 PM PST 23 Nov 22 01:40:01 PM PST 23 16404398 ps
T780 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.48125510981971134990720142470975813942554592256744284177115699885062505427586 Nov 22 01:37:52 PM PST 23 Nov 22 01:38:14 PM PST 23 1491321170 ps
T781 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.92903566901353396801509756906011702345476940735158003929700008198088421868639 Nov 22 01:40:00 PM PST 23 Nov 22 01:40:12 PM PST 23 964986095 ps
T782 /workspace/coverage/default/45.lc_ctrl_prog_failure.76528129832590949004228121146553560897840518024181161573727039776782496679255 Nov 22 01:39:39 PM PST 23 Nov 22 01:39:44 PM PST 23 159313969 ps
T783 /workspace/coverage/default/23.lc_ctrl_state_post_trans.71497562606874655891258992600515398033656946328568069420585662101466251830621 Nov 22 01:38:03 PM PST 23 Nov 22 01:38:15 PM PST 23 217117078 ps
T784 /workspace/coverage/default/25.lc_ctrl_prog_failure.54068951083857779420692628101882142805074885992467624337545390803265853659056 Nov 22 01:38:12 PM PST 23 Nov 22 01:38:21 PM PST 23 159313969 ps
T785 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.111857959113542614347777610891513159048556914583778769749013191571662946536914 Nov 22 01:37:27 PM PST 23 Nov 22 01:37:30 PM PST 23 16404398 ps
T786 /workspace/coverage/default/44.lc_ctrl_security_escalation.77516485852439195338417209198153148902732497954308036160509660593619908118970 Nov 22 01:39:43 PM PST 23 Nov 22 01:39:53 PM PST 23 625328098 ps
T787 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.13058311741113221098267700457778408801986332767085965971250159489649353378177 Nov 22 01:39:53 PM PST 23 Nov 22 01:40:12 PM PST 23 1321911811 ps
T788 /workspace/coverage/default/30.lc_ctrl_prog_failure.19470227907881802079963125010469161565387446976022945336847073786532713231044 Nov 22 01:39:02 PM PST 23 Nov 22 01:39:06 PM PST 23 159313969 ps
T789 /workspace/coverage/default/0.lc_ctrl_smoke.667973187724416358420442283093899676089234579114622273198438981532392987335 Nov 22 01:36:52 PM PST 23 Nov 22 01:37:01 PM PST 23 291295056 ps
T790 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.8981238445189568150245116828658959492969727122483927830846242990004352511191 Nov 22 01:39:05 PM PST 23 Nov 22 01:39:06 PM PST 23 16404398 ps
T791 /workspace/coverage/default/36.lc_ctrl_smoke.80680628807945897614741616926288715531172411725261667254087927519735493499969 Nov 22 01:39:14 PM PST 23 Nov 22 01:39:21 PM PST 23 291295056 ps
T792 /workspace/coverage/default/34.lc_ctrl_errors.57403243172515078298292325384899475266715645752642369772165781300119094245170 Nov 22 01:39:11 PM PST 23 Nov 22 01:39:25 PM PST 23 978628843 ps
T793 /workspace/coverage/default/41.lc_ctrl_sec_mubi.73203540408662911320258030117839760693115145108203236202413119086885222934752 Nov 22 01:39:42 PM PST 23 Nov 22 01:40:00 PM PST 23 1010128591 ps
T794 /workspace/coverage/default/38.lc_ctrl_stress_all.7479085677522663721834282023252562891441702662517027068980882700650725072993 Nov 22 01:39:16 PM PST 23 Nov 22 01:44:06 PM PST 23 36820395678 ps
T795 /workspace/coverage/default/30.lc_ctrl_alert_test.75666173814106671841786964810613581512577933642692559157877609632866238856360 Nov 22 01:39:03 PM PST 23 Nov 22 01:39:05 PM PST 23 42189906 ps
T796 /workspace/coverage/default/6.lc_ctrl_smoke.88901640517488787805686202007065295276335847204294675142234088643571255921875 Nov 22 01:37:59 PM PST 23 Nov 22 01:38:06 PM PST 23 291295056 ps
T797 /workspace/coverage/default/4.lc_ctrl_smoke.81070915114209286204321176828915693860378931195857505221906930997505446234906 Nov 22 01:37:13 PM PST 23 Nov 22 01:37:18 PM PST 23 291295056 ps
T798 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.55701181748910973380504640765677750578093968010669649510195726229709042457771 Nov 22 01:39:08 PM PST 23 Nov 22 01:39:21 PM PST 23 964986095 ps
T799 /workspace/coverage/default/5.lc_ctrl_errors.2657094477560013712182823401339675753130546523184225988966332647204989684861 Nov 22 01:37:55 PM PST 23 Nov 22 01:38:14 PM PST 23 978628843 ps
T800 /workspace/coverage/default/9.lc_ctrl_jtag_access.37092741536730545213378335373449570033873985264389541585294592187477487639267 Nov 22 01:38:11 PM PST 23 Nov 22 01:38:28 PM PST 23 1895300081 ps
T801 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.103409573946025280240934285551785473062631037365836617477528400996442565546475 Nov 22 01:37:45 PM PST 23 Nov 22 01:38:08 PM PST 23 1321911811 ps
T802 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.45620216583457804543178982266878739481043447080488964089459901236805562267836 Nov 22 01:37:30 PM PST 23 Nov 22 01:37:36 PM PST 23 420615450 ps
T803 /workspace/coverage/default/2.lc_ctrl_jtag_priority.107979114344976681866716494793103664671981492903460155926718478366884820692694 Nov 22 01:36:58 PM PST 23 Nov 22 01:37:15 PM PST 23 2797596434 ps
T804 /workspace/coverage/default/27.lc_ctrl_jtag_access.50639066066483443302959069041648270327855115960556448037117894749272590604759 Nov 22 01:38:18 PM PST 23 Nov 22 01:38:32 PM PST 23 1895300081 ps
T805 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.37212084307859140156701676670288530118308138282296817258180534095992407148068 Nov 22 01:36:58 PM PST 23 Nov 22 01:37:18 PM PST 23 1491321170 ps
T806 /workspace/coverage/default/37.lc_ctrl_errors.90853363949234391659836849143515143374831922975771898642545196823360433745962 Nov 22 01:39:19 PM PST 23 Nov 22 01:39:35 PM PST 23 978628843 ps
T807 /workspace/coverage/default/0.lc_ctrl_prog_failure.93806352104989153530014487339213601673895829628540451275764412935246497590212 Nov 22 01:36:53 PM PST 23 Nov 22 01:37:01 PM PST 23 159313969 ps
T808 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.105214832414975574924512922487731625038165735935939209623067521010115347780258 Nov 22 01:36:56 PM PST 23 Nov 22 01:37:17 PM PST 23 1321911811 ps
T809 /workspace/coverage/default/22.lc_ctrl_smoke.101128164553727232864010509108541977071178120874092667160006147416067424538602 Nov 22 01:38:35 PM PST 23 Nov 22 01:38:42 PM PST 23 291295056 ps
T810 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.59879018220180989860991113307617238405444409012160561000314218337416312932316 Nov 22 01:37:59 PM PST 23 Nov 22 01:38:13 PM PST 23 964986095 ps
T811 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.31297726747834129632034565982785909275961894118750848337826813970721868412513 Nov 22 01:37:59 PM PST 23 Nov 22 01:38:56 PM PST 23 5030489285 ps
T812 /workspace/coverage/default/40.lc_ctrl_jtag_access.340243062595911746475050883044849307675456221394643705240033769975312991297 Nov 22 01:39:29 PM PST 23 Nov 22 01:39:39 PM PST 23 1895300081 ps
T813 /workspace/coverage/default/43.lc_ctrl_alert_test.98261910827386016618677560864980635791260053267841697104522536274002307842323 Nov 22 01:40:16 PM PST 23 Nov 22 01:40:17 PM PST 23 42189906 ps
T814 /workspace/coverage/default/34.lc_ctrl_sec_mubi.101590452067632928458728881877540891588679189294980881363550541974225889635896 Nov 22 01:39:14 PM PST 23 Nov 22 01:39:30 PM PST 23 1010128591 ps
T815 /workspace/coverage/default/8.lc_ctrl_jtag_priority.49706210125373160367907751889481627500357300793848059523648486840751938200846 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:20 PM PST 23 2797596434 ps
T816 /workspace/coverage/default/14.lc_ctrl_alert_test.106562324144721359378498918035013369011706057004681703346426876800128857361746 Nov 22 01:37:59 PM PST 23 Nov 22 01:38:03 PM PST 23 42189906 ps
T817 /workspace/coverage/default/21.lc_ctrl_errors.90324368380216369876239824807321157035479462145072989088999589742152404806304 Nov 22 01:38:25 PM PST 23 Nov 22 01:38:40 PM PST 23 978628843 ps
T818 /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.22836280940575663131512256221918359890248414152527736720409954086432976421542 Nov 22 01:38:01 PM PST 23 Nov 22 01:38:15 PM PST 23 1406053995 ps
T819 /workspace/coverage/default/37.lc_ctrl_stress_all.13319580981331221503053610057860382114842413229775498300085282774576995595475 Nov 22 01:39:16 PM PST 23 Nov 22 01:43:59 PM PST 23 36820395678 ps
T820 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.54440104432235315165137012922714962720473666618353254198295133215959307802897 Nov 22 01:37:44 PM PST 23 Nov 22 01:37:52 PM PST 23 16404398 ps
T821 /workspace/coverage/default/7.lc_ctrl_state_post_trans.74007659593653336493988648030762625445443590362712755940198734627384532709324 Nov 22 01:37:36 PM PST 23 Nov 22 01:37:44 PM PST 23 217117078 ps
T822 /workspace/coverage/default/10.lc_ctrl_jtag_errors.51947412573476677791141478177933203417388767171013154610530017039723188451620 Nov 22 01:38:01 PM PST 23 Nov 22 01:38:44 PM PST 23 5872518263 ps
T823 /workspace/coverage/default/13.lc_ctrl_alert_test.76651847441758299050512828939752246590741574556336938804885866284271179032581 Nov 22 01:37:57 PM PST 23 Nov 22 01:38:02 PM PST 23 42189906 ps
T824 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.587739230202305223472820849165589724187756828046975266879082694035518132035 Nov 22 01:38:35 PM PST 23 Nov 22 01:38:48 PM PST 23 964986095 ps
T825 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.67573599275510939643780991950051287833816078328515653319133665053668580986257 Nov 22 01:37:55 PM PST 23 Nov 22 01:38:15 PM PST 23 1321911811 ps
T826 /workspace/coverage/default/25.lc_ctrl_smoke.60515390614963972567073172370553149461388859767369383473289844576901838658461 Nov 22 01:38:10 PM PST 23 Nov 22 01:38:21 PM PST 23 291295056 ps
T827 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.29477098017157012582090338788528808116431069259986499931438389275848410152062 Nov 22 01:38:00 PM PST 23 Nov 22 01:38:13 PM PST 23 1406053995 ps
T828 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.105869062799456539292909433751944606524760095548611504799844459626624936121130 Nov 22 01:40:00 PM PST 23 Nov 22 01:40:03 PM PST 23 16404398 ps
T829 /workspace/coverage/default/28.lc_ctrl_errors.10354815674681159661024958956250389044487596555624644476912322524847497372378 Nov 22 01:39:07 PM PST 23 Nov 22 01:39:23 PM PST 23 978628843 ps
T830 /workspace/coverage/default/36.lc_ctrl_stress_all.16684892703746999434977761961745973668631620992030509039478965093062294475781 Nov 22 01:39:13 PM PST 23 Nov 22 01:44:00 PM PST 23 36820395678 ps
T831 /workspace/coverage/default/22.lc_ctrl_alert_test.102993858741596089323484538119843563013268264759949395723286234972347307793133 Nov 22 01:38:08 PM PST 23 Nov 22 01:38:15 PM PST 23 42189906 ps
T832 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.83698912907419818114053975225059200574892613838093121437325899344096946019265 Nov 22 01:38:08 PM PST 23 Nov 22 01:38:25 PM PST 23 964986095 ps
T833 /workspace/coverage/default/36.lc_ctrl_errors.9780053638290470023559006972031077839407811358986554303666016348790945249077 Nov 22 01:39:16 PM PST 23 Nov 22 01:39:31 PM PST 23 978628843 ps
T834 /workspace/coverage/default/6.lc_ctrl_alert_test.94808348076524211878773809525343305001815201452700223823780659921590038149934 Nov 22 01:37:34 PM PST 23 Nov 22 01:37:36 PM PST 23 42189906 ps
T835 /workspace/coverage/default/7.lc_ctrl_alert_test.111023428622729493882935919413199241758209765735028321784554255906650553890644 Nov 22 01:37:56 PM PST 23 Nov 22 01:38:01 PM PST 23 42189906 ps
T836 /workspace/coverage/default/27.lc_ctrl_stress_all.30146729380868588774936165940296871549309724529267671382406575523651215237979 Nov 22 01:39:07 PM PST 23 Nov 22 01:43:50 PM PST 23 36820395678 ps
T837 /workspace/coverage/default/10.lc_ctrl_errors.95448080308783760104696495085487890613868308972109742582398390905918409115875 Nov 22 01:37:54 PM PST 23 Nov 22 01:38:13 PM PST 23 978628843 ps
T838 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.59927702602276752020069054959121674514677464806032078693225705453124227840750 Nov 22 01:39:18 PM PST 23 Nov 22 01:39:30 PM PST 23 964986095 ps
T839 /workspace/coverage/default/38.lc_ctrl_state_post_trans.109628434579249536386080037782018209745413825928881993816457995028062618847081 Nov 22 01:39:14 PM PST 23 Nov 22 01:39:22 PM PST 23 217117078 ps
T840 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.17662170372752283926344423822845517067769672657541050317664228999901264924322 Nov 22 01:38:10 PM PST 23 Nov 22 01:38:27 PM PST 23 1480535542 ps
T841 /workspace/coverage/default/26.lc_ctrl_state_failure.95621670731584329806705550087777646639492930096338050340526163465101751587043 Nov 22 01:38:31 PM PST 23 Nov 22 01:38:53 PM PST 23 487150632 ps
T842 /workspace/coverage/default/6.lc_ctrl_stress_all.29061913527527398345825818640400384431161621090133039206199002913434662485574 Nov 22 01:37:28 PM PST 23 Nov 22 01:42:21 PM PST 23 36820395678 ps
T843 /workspace/coverage/default/13.lc_ctrl_prog_failure.43937035373440886618707856799308528682143685229244724892051711725665835900864 Nov 22 01:37:42 PM PST 23 Nov 22 01:37:47 PM PST 23 159313969 ps
T844 /workspace/coverage/default/20.lc_ctrl_smoke.104923415175470534422847175971206881900342107883343233818681748808173693725173 Nov 22 01:38:13 PM PST 23 Nov 22 01:38:24 PM PST 23 291295056 ps
T845 /workspace/coverage/default/11.lc_ctrl_sec_mubi.1845846567621223461556140293589604023920010497233705829002635027554730057341 Nov 22 01:37:58 PM PST 23 Nov 22 01:38:16 PM PST 23 1010128591 ps
T846 /workspace/coverage/default/12.lc_ctrl_security_escalation.85155030076935756069209965405018070879069569755270317099381331877118895292370 Nov 22 01:37:57 PM PST 23 Nov 22 01:38:09 PM PST 23 625328098 ps
T847 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.92246440721768612044806112500246349186357263790338251855437832963652756851204 Nov 22 01:37:53 PM PST 23 Nov 22 01:38:08 PM PST 23 1348822310 ps
T848 /workspace/coverage/default/21.lc_ctrl_alert_test.92108984804207393945033594453359855938789019548393827413665493295464066284976 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:07 PM PST 23 42189906 ps
T849 /workspace/coverage/default/12.lc_ctrl_state_failure.34862041177613480615748359286482541936877903563757534401979601393983793718095 Nov 22 01:37:58 PM PST 23 Nov 22 01:38:22 PM PST 23 487150632 ps
T850 /workspace/coverage/default/6.lc_ctrl_jtag_smoke.49746522910698480869605425385795823963748289039119071075457274026323453522153 Nov 22 01:38:05 PM PST 23 Nov 22 01:38:20 PM PST 23 1348822310 ps
T851 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.88496179713334533448762513411148812678271351708340134374673633655399754290089 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:17 PM PST 23 964986095 ps
T852 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.63834129257035875978838639730421842359965255333088533105559824992504654970527 Nov 22 01:36:50 PM PST 23 Nov 22 01:37:10 PM PST 23 1321911811 ps
T853 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.68684033272433085559172407098305419572858359929443857319797996728700442299346 Nov 22 01:38:10 PM PST 23 Nov 22 01:38:33 PM PST 23 1321911811 ps
T854 /workspace/coverage/default/45.lc_ctrl_state_failure.67888639560926873530516171672599778786112404925045894809645321155070631058050 Nov 22 01:39:48 PM PST 23 Nov 22 01:40:10 PM PST 23 487150632 ps
T855 /workspace/coverage/default/20.lc_ctrl_jtag_access.105966622555169504861600636543206495190270277197422231298827478800832019617301 Nov 22 01:38:09 PM PST 23 Nov 22 01:38:25 PM PST 23 1895300081 ps
T856 /workspace/coverage/default/36.lc_ctrl_security_escalation.24894573592758015500989146632787252254431122463139354628468864830937818157442 Nov 22 01:39:16 PM PST 23 Nov 22 01:39:26 PM PST 23 625328098 ps
T857 /workspace/coverage/default/15.lc_ctrl_security_escalation.44729475403999549600864260227237062929065591762048606645571824344203827870541 Nov 22 01:37:59 PM PST 23 Nov 22 01:38:10 PM PST 23 625328098 ps
T858 /workspace/coverage/default/33.lc_ctrl_alert_test.770045466908383574750404369210297192156372175785489715610310951950827780470 Nov 22 01:39:10 PM PST 23 Nov 22 01:39:12 PM PST 23 42189906 ps
T859 /workspace/coverage/default/30.lc_ctrl_state_post_trans.71871607696789827483969033215454278892357226677196424612151314680820161679751 Nov 22 01:39:06 PM PST 23 Nov 22 01:39:14 PM PST 23 217117078 ps
T860 /workspace/coverage/default/1.lc_ctrl_prog_failure.83501969416736392850511038152023212501575191388784063917354531877215652960474 Nov 22 01:36:47 PM PST 23 Nov 22 01:36:51 PM PST 23 159313969 ps
T861 /workspace/coverage/default/18.lc_ctrl_prog_failure.17414825156056422093885885954383154561545522057588664316215092669081578961465 Nov 22 01:38:07 PM PST 23 Nov 22 01:38:16 PM PST 23 159313969 ps
T862 /workspace/coverage/default/47.lc_ctrl_jtag_access.68390959441619371516193569438667884786381183309394198887489410562198706176539 Nov 22 01:39:52 PM PST 23 Nov 22 01:40:03 PM PST 23 1895300081 ps
T863 /workspace/coverage/default/24.lc_ctrl_prog_failure.79883377596909626025756287214167986254292969776143786561611296850867355912503 Nov 22 01:38:10 PM PST 23 Nov 22 01:38:20 PM PST 23 159313969 ps
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T865 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.99368501817066666965753481352981725738683933992214546013433412273746100694677 Nov 22 01:38:00 PM PST 23 Nov 22 01:38:15 PM PST 23 1480535542 ps
T866 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.40157858684601648211165193182962453227291281896008512525644359861922686679504 Nov 22 01:38:04 PM PST 23 Nov 22 01:38:26 PM PST 23 1321911811 ps
T867 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.83367512407889613982735966083532733366352664408557543837760065201429643065346 Nov 22 01:38:12 PM PST 23 Nov 22 01:38:30 PM PST 23 964986095 ps
T868 /workspace/coverage/default/36.lc_ctrl_alert_test.81029163704811668770982275768804110460027406040418204492562846145066328955812 Nov 22 01:39:14 PM PST 23 Nov 22 01:39:16 PM PST 23 42189906 ps
T869 /workspace/coverage/default/20.lc_ctrl_prog_failure.18605399221737855736259301680636370775492905899882156621998039624709472422139 Nov 22 01:38:06 PM PST 23 Nov 22 01:38:14 PM PST 23 159313969 ps
T870 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.112256185311359781302345121176684187469796853732604605245212448234836860633229 Nov 22 01:39:54 PM PST 23 Nov 22 01:40:06 PM PST 23 964986095 ps
T871 /workspace/coverage/default/48.lc_ctrl_errors.5489556627292135114872206402763959023294364608897408653516737247990189677580 Nov 22 01:39:51 PM PST 23 Nov 22 01:40:06 PM PST 23 978628843 ps
T872 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.35683876555885646161217052625984963814558963134068382906874752760449343083852 Nov 22 01:40:03 PM PST 23 Nov 22 01:40:17 PM PST 23 964986095 ps
T873 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.76063068359083016395138444004419716141074067785185212837636097487660806539714 Nov 22 01:39:09 PM PST 23 Nov 22 01:39:22 PM PST 23 964986095 ps
T874 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.42066521044392663785374073894141960871130011298684823926212094338832549558053 Nov 22 01:39:04 PM PST 23 Nov 22 01:39:21 PM PST 23 1321911811 ps
T875 /workspace/coverage/default/28.lc_ctrl_stress_all.36895534099834937369130201491077698692358901052504688786886332296823147985187 Nov 22 01:39:04 PM PST 23 Nov 22 01:43:50 PM PST 23 36820395678 ps
T876 /workspace/coverage/default/3.lc_ctrl_jtag_priority.42005460874563878245333312986262935399002297866072529273411674214639062811704 Nov 22 01:37:21 PM PST 23 Nov 22 01:37:37 PM PST 23 2797596434 ps
T877 /workspace/coverage/default/32.lc_ctrl_jtag_access.37379776451243358349441390891096961183966568165866773041544753369271745350051 Nov 22 01:39:08 PM PST 23 Nov 22 01:39:19 PM PST 23 1895300081 ps
T878 /workspace/coverage/default/17.lc_ctrl_sec_mubi.68693738848553296443861291393109933073497027437967039658349152304044516930206 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:21 PM PST 23 1010128591 ps
T879 /workspace/coverage/default/19.lc_ctrl_alert_test.27282449786800835227830188560550234227257575998773239227928009798762337864235 Nov 22 01:38:07 PM PST 23 Nov 22 01:38:14 PM PST 23 42189906 ps
T880 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.4032156252178699503954944571864206539318008494252996337642840202844248835082 Nov 22 01:39:04 PM PST 23 Nov 22 01:39:17 PM PST 23 964986095 ps
T881 /workspace/coverage/default/11.lc_ctrl_smoke.59004980607594280501948325812930004878156732818533931314780580984658143177872 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:11 PM PST 23 291295056 ps
T882 /workspace/coverage/default/46.lc_ctrl_alert_test.88607345257480066527695004742169909504759268596457266889101819066380965901861 Nov 22 01:39:46 PM PST 23 Nov 22 01:39:48 PM PST 23 42189906 ps
T883 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.82836223726293813877102249254732600698938694305259497344098543757021888235517 Nov 22 01:36:49 PM PST 23 Nov 22 01:37:42 PM PST 23 5030489285 ps
T884 /workspace/coverage/default/27.lc_ctrl_sec_mubi.81884833535402709924451994223035863107384654297623815577795236653598434066312 Nov 22 01:38:18 PM PST 23 Nov 22 01:38:37 PM PST 23 1010128591 ps
T885 /workspace/coverage/default/33.lc_ctrl_prog_failure.106987344366918453297911310650459079536673874472334264853242269116483207994992 Nov 22 01:39:09 PM PST 23 Nov 22 01:39:13 PM PST 23 159313969 ps
T886 /workspace/coverage/default/49.lc_ctrl_state_failure.52352209955524269864303609358444269596374661772108205239239365644296650828620 Nov 22 01:39:52 PM PST 23 Nov 22 01:40:14 PM PST 23 487150632 ps
T887 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.81863949300821041999467910818998683622581833816676999762900632077613318067550 Nov 22 01:37:54 PM PST 23 Nov 22 01:38:16 PM PST 23 1491321170 ps
T888 /workspace/coverage/default/3.lc_ctrl_sec_mubi.63099170167611744346994437106086993725082780733534994521644636104122499447729 Nov 22 01:37:09 PM PST 23 Nov 22 01:37:25 PM PST 23 1010128591 ps
T889 /workspace/coverage/default/18.lc_ctrl_sec_mubi.93802575170132750092851841637978647062870909893297794283538925846568822271072 Nov 22 01:38:00 PM PST 23 Nov 22 01:38:18 PM PST 23 1010128591 ps
T890 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.93520329334044389730285818801711318457563751752905326927914656071456426742389 Nov 22 01:38:11 PM PST 23 Nov 22 01:38:28 PM PST 23 1406053995 ps
T891 /workspace/coverage/default/46.lc_ctrl_state_post_trans.20039125052325216839636188482594553246930992876343405446907710369482288500515 Nov 22 01:39:38 PM PST 23 Nov 22 01:39:48 PM PST 23 217117078 ps
T892 /workspace/coverage/default/26.lc_ctrl_errors.101659526562923216015599706593861009034762959916727994638489189164298200885084 Nov 22 01:38:19 PM PST 23 Nov 22 01:38:36 PM PST 23 978628843 ps
T893 /workspace/coverage/default/46.lc_ctrl_errors.13005328784405311918426369556844143120857230349231174955060167476911262339750 Nov 22 01:39:49 PM PST 23 Nov 22 01:40:05 PM PST 23 978628843 ps
T894 /workspace/coverage/default/40.lc_ctrl_state_post_trans.41299670193366613829455100510690799440310760254529808909763791144191754803448 Nov 22 01:39:28 PM PST 23 Nov 22 01:39:36 PM PST 23 217117078 ps
T895 /workspace/coverage/default/5.lc_ctrl_sec_mubi.11739148268715419356441035763796585835156810304525250991934049065032415089602 Nov 22 01:38:01 PM PST 23 Nov 22 01:38:20 PM PST 23 1010128591 ps
T896 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.28161822586555284579826798424098313725554399139788880704907710717288424902361 Nov 22 01:36:55 PM PST 23 Nov 22 01:37:11 PM PST 23 964986095 ps
T897 /workspace/coverage/default/33.lc_ctrl_state_failure.108952356888575499753044874334983047648834524788209318515791247151489904289927 Nov 22 01:39:08 PM PST 23 Nov 22 01:39:31 PM PST 23 487150632 ps
T898 /workspace/coverage/default/0.lc_ctrl_errors.67377315587611641424702551935233029258839633348466351194103669208190634315427 Nov 22 01:36:52 PM PST 23 Nov 22 01:37:12 PM PST 23 978628843 ps
T899 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.81403964407072180274878912240598332462104464622562176326201922270004258846936 Nov 22 01:37:41 PM PST 23 Nov 22 01:37:55 PM PST 23 964986095 ps
T900 /workspace/coverage/default/2.lc_ctrl_jtag_errors.77466126678496560313967098367217160632021529171237774450337398915139736556682 Nov 22 01:36:55 PM PST 23 Nov 22 01:37:43 PM PST 23 5872518263 ps
T901 /workspace/coverage/default/14.lc_ctrl_prog_failure.45262812094464639588501964647401917923159149829450174561395429296119570904073 Nov 22 01:37:56 PM PST 23 Nov 22 01:38:03 PM PST 23 159313969 ps
T902 /workspace/coverage/default/24.lc_ctrl_alert_test.75517614143125618059139957385879633713647742599910207313558700525229433463395 Nov 22 01:38:04 PM PST 23 Nov 22 01:38:10 PM PST 23 42189906 ps
T903 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.30098173781447066672916433616038557662804255329134806122768388931592589080809 Nov 22 01:39:47 PM PST 23 Nov 22 01:39:59 PM PST 23 964986095 ps
T904 /workspace/coverage/default/35.lc_ctrl_stress_all.46342433560933481470733358272377618901750747015677294796648148098623081613392 Nov 22 01:39:15 PM PST 23 Nov 22 01:44:04 PM PST 23 36820395678 ps
T905 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.88923981275242870760523236634047514342967768034317644292493287067841753203190 Nov 22 01:36:58 PM PST 23 Nov 22 01:37:13 PM PST 23 964986095 ps
T906 /workspace/coverage/default/47.lc_ctrl_alert_test.109309349638100035704569509689059667499010774453003222181842993226465541981118 Nov 22 01:39:54 PM PST 23 Nov 22 01:39:55 PM PST 23 42189906 ps
T907 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.37960312610923408275227591193337862117549745776348700346154194192641932417465 Nov 22 01:39:53 PM PST 23 Nov 22 01:40:11 PM PST 23 1321911811 ps
T908 /workspace/coverage/default/4.lc_ctrl_jtag_priority.63491497926303808711949567038254950349843858853790325203898991988187586714051 Nov 22 01:37:29 PM PST 23 Nov 22 01:37:43 PM PST 23 2797596434 ps
T909 /workspace/coverage/default/44.lc_ctrl_prog_failure.13499403187829133956330885129092673650888146270088778009254045044023886562869 Nov 22 01:39:38 PM PST 23 Nov 22 01:39:43 PM PST 23 159313969 ps
T910 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.48107559432000584961355129661027946582533170773755828909236448923447918983932 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:16 PM PST 23 964986095 ps
T911 /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.95973701363132015695090164535861682580641500449713610945940420527600882389783 Nov 22 01:37:59 PM PST 23 Nov 22 01:38:14 PM PST 23 1480535542 ps
T912 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.55852425719668818307835855690181285725604028055186063162516844899066454617791 Nov 22 01:38:01 PM PST 23 Nov 22 01:38:04 PM PST 23 16404398 ps
T913 /workspace/coverage/default/43.lc_ctrl_security_escalation.12306723514386284000261432454391742560438389470352703427556036185605734026003 Nov 22 01:39:58 PM PST 23 Nov 22 01:40:07 PM PST 23 625328098 ps
T914 /workspace/coverage/default/6.lc_ctrl_jtag_access.64096445367128164556058618361049337719798288238524035568796633010253162385497 Nov 22 01:38:09 PM PST 23 Nov 22 01:38:24 PM PST 23 1895300081 ps
T915 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.17074005187847883487496032757516634543908905627477502074176298967343559607414 Nov 22 01:39:18 PM PST 23 Nov 22 01:39:36 PM PST 23 1321911811 ps
T916 /workspace/coverage/default/9.lc_ctrl_jtag_errors.36561390060880745527013734552423363425847692802749853265564569960864248280181 Nov 22 01:38:07 PM PST 23 Nov 22 01:38:53 PM PST 23 5872518263 ps
T917 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.26652345220105077736133429535050679138898430507030183077688699186518651405901 Nov 22 01:37:03 PM PST 23 Nov 22 01:37:55 PM PST 23 5030489285 ps
T918 /workspace/coverage/default/15.lc_ctrl_jtag_errors.68172704294329082484160385159243725285247434054808341304860205204414620392824 Nov 22 01:38:04 PM PST 23 Nov 22 01:38:49 PM PST 23 5872518263 ps
T919 /workspace/coverage/default/8.lc_ctrl_prog_failure.74163199038778425015938954638993145049690471917796355912616839007023695044455 Nov 22 01:37:46 PM PST 23 Nov 22 01:37:57 PM PST 23 159313969 ps
T920 /workspace/coverage/default/9.lc_ctrl_security_escalation.59867929422190894094173985985287347159554685319736323721767664917302493510461 Nov 22 01:38:10 PM PST 23 Nov 22 01:38:25 PM PST 23 625328098 ps
T921 /workspace/coverage/default/30.lc_ctrl_stress_all.63487691860283554978933056193470281521348062869187290119761789429915481482719 Nov 22 01:39:07 PM PST 23 Nov 22 01:43:51 PM PST 23 36820395678 ps
T922 /workspace/coverage/default/36.lc_ctrl_sec_mubi.40184283541020280847568898499883014260700676861407681345069433196869189665617 Nov 22 01:39:16 PM PST 23 Nov 22 01:39:32 PM PST 23 1010128591 ps
T923 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.57707624498736441385454574360520630086567889011705453178328033282027771586142 Nov 22 01:39:17 PM PST 23 Nov 22 01:39:36 PM PST 23 1321911811 ps
T924 /workspace/coverage/default/30.lc_ctrl_jtag_access.66756577971859473656027954663740917659480014759149212937521424023312919273168 Nov 22 01:39:06 PM PST 23 Nov 22 01:39:17 PM PST 23 1895300081 ps
T925 /workspace/coverage/default/45.lc_ctrl_state_post_trans.54690971300849992368199811544563132779952504967933176646083575509744696384903 Nov 22 01:39:44 PM PST 23 Nov 22 01:39:52 PM PST 23 217117078 ps
T926 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.62204998150500713112932647610522009939231849630872247106197903158162913281682 Nov 22 01:39:05 PM PST 23 Nov 22 01:39:24 PM PST 23 1321911811 ps
T927 /workspace/coverage/default/19.lc_ctrl_prog_failure.27339354312370942871829942930067629800264550238032977451496608412967111570725 Nov 22 01:38:05 PM PST 23 Nov 22 01:38:13 PM PST 23 159313969 ps
T928 /workspace/coverage/default/34.lc_ctrl_alert_test.59643692248787970832503016474853714050370463486678051156401618705266319435098 Nov 22 01:39:15 PM PST 23 Nov 22 01:39:18 PM PST 23 42189906 ps
T929 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.51569869908678644434560509873963991381597574843702337774503058495794516753027 Nov 22 01:39:05 PM PST 23 Nov 22 01:39:06 PM PST 23 16404398 ps
T930 /workspace/coverage/default/11.lc_ctrl_prog_failure.102887390717753724803162406502222350103527854598578305780074168947944192065125 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:09 PM PST 23 159313969 ps
T931 /workspace/coverage/default/2.lc_ctrl_jtag_access.95427714938449962915287892453005604416589763011833861749172305387919620214443 Nov 22 01:36:57 PM PST 23 Nov 22 01:37:11 PM PST 23 1895300081 ps
T932 /workspace/coverage/default/14.lc_ctrl_smoke.110171118107906809987688484717476231435202462124695399129960206411934691035231 Nov 22 01:37:46 PM PST 23 Nov 22 01:37:59 PM PST 23 291295056 ps
T933 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.54685732495802321322618064177325477954030353118271843657594808505024207338623 Nov 22 01:39:16 PM PST 23 Nov 22 01:39:34 PM PST 23 1321911811 ps
T934 /workspace/coverage/default/19.lc_ctrl_jtag_errors.59282973071354867371561061376888005908348543829908576052819557645915015781308 Nov 22 01:38:12 PM PST 23 Nov 22 01:39:01 PM PST 23 5872518263 ps
T935 /workspace/coverage/default/34.lc_ctrl_security_escalation.84170667205150660778540580327834439267007055872501630471332605502541755392012 Nov 22 01:39:11 PM PST 23 Nov 22 01:39:20 PM PST 23 625328098 ps
T936 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4374055275538143029977337013783543612102765062136223800534195128817848583287 Nov 22 01:39:45 PM PST 23 Nov 22 01:39:57 PM PST 23 964986095 ps
T937 /workspace/coverage/default/49.lc_ctrl_prog_failure.112179434144096705484712599039803671347135645904626870974528970050417577869360 Nov 22 01:39:52 PM PST 23 Nov 22 01:39:55 PM PST 23 159313969 ps
T938 /workspace/coverage/default/0.lc_ctrl_state_post_trans.31214373257847970721439743315881056622884226814154463572614364029448093855808 Nov 22 01:36:52 PM PST 23 Nov 22 01:37:04 PM PST 23 217117078 ps
T939 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.102951331407789282387907532770038805913267801190265273431842084848260099299332 Nov 22 01:36:48 PM PST 23 Nov 22 01:37:02 PM PST 23 1480535542 ps
T940 /workspace/coverage/default/42.lc_ctrl_stress_all.9963788919231530158582331429934637748651171874043237581199223573150055488780 Nov 22 01:39:55 PM PST 23 Nov 22 01:44:48 PM PST 23 36820395678 ps
T941 /workspace/coverage/default/33.lc_ctrl_state_post_trans.35447732623904726618681148489251799606066389806132455692360901339167905824789 Nov 22 01:39:10 PM PST 23 Nov 22 01:39:18 PM PST 23 217117078 ps
T942 /workspace/coverage/default/42.lc_ctrl_state_post_trans.72641190971120842704067295220255363918065824830691146653324627554635339002566 Nov 22 01:39:30 PM PST 23 Nov 22 01:39:38 PM PST 23 217117078 ps
T943 /workspace/coverage/default/1.lc_ctrl_jtag_access.56290240732886216508294638930528502248469046991411826008198627124567824762399 Nov 22 01:36:44 PM PST 23 Nov 22 01:36:55 PM PST 23 1895300081 ps
T944 /workspace/coverage/default/25.lc_ctrl_state_post_trans.66811608405564482274764910152423575888915314273295592419227607607022880882952 Nov 22 01:38:04 PM PST 23 Nov 22 01:38:17 PM PST 23 217117078 ps
T945 /workspace/coverage/default/8.lc_ctrl_errors.7584150133464431122150311201322905960798131944042029973983516149995684584638 Nov 22 01:37:44 PM PST 23 Nov 22 01:38:06 PM PST 23 978628843 ps
T946 /workspace/coverage/default/21.lc_ctrl_sec_mubi.93198919541321493015603147067981377910174503999056937527057868294332637979344 Nov 22 01:38:14 PM PST 23 Nov 22 01:38:35 PM PST 23 1010128591 ps
T947 /workspace/coverage/default/47.lc_ctrl_smoke.23152228775576027106583706763015876245642681164667281109047025247189421007973 Nov 22 01:39:53 PM PST 23 Nov 22 01:39:59 PM PST 23 291295056 ps
T948 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.88385035379301272366562719433580414749109463062023174929368059301948563367462 Nov 22 01:37:56 PM PST 23 Nov 22 01:38:12 PM PST 23 1480535542 ps
T949 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.84325843027670139742930552340326192455169100826932354648588365712890767273657 Nov 22 01:37:57 PM PST 23 Nov 22 01:38:07 PM PST 23 420615450 ps
T950 /workspace/coverage/default/2.lc_ctrl_alert_test.24353038473299599777475173699022056250059430627783161459396913548289138238003 Nov 22 01:37:00 PM PST 23 Nov 22 01:37:04 PM PST 23 42189906 ps
T951 /workspace/coverage/default/25.lc_ctrl_sec_mubi.50135766286190474441608178151839677121124820526359032241329493654203791972252 Nov 22 01:38:31 PM PST 23 Nov 22 01:38:49 PM PST 23 1010128591 ps
T952 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.84722287341607288817750449682550859019189437680466068406610424316233165617193 Nov 22 01:38:09 PM PST 23 Nov 22 01:38:20 PM PST 23 420615450 ps
T953 /workspace/coverage/default/12.lc_ctrl_state_post_trans.78555637195500448379430712021821418375554012153538474172516209301861565016459 Nov 22 01:37:53 PM PST 23 Nov 22 01:38:06 PM PST 23 217117078 ps
T954 /workspace/coverage/default/45.lc_ctrl_jtag_access.80690982388656925675298341849333762827703249632512497128992385730413978202187 Nov 22 01:39:47 PM PST 23 Nov 22 01:39:58 PM PST 23 1895300081 ps
T955 /workspace/coverage/default/1.lc_ctrl_alert_test.14536263498533116204380446883438132942603348920021547851886872139610671528471 Nov 22 01:36:51 PM PST 23 Nov 22 01:36:56 PM PST 23 42189906 ps
T956 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.93201469289511406246320871853897852402774941898960411076576294864765158086185 Nov 22 01:37:55 PM PST 23 Nov 22 01:38:09 PM PST 23 1348822310 ps
T957 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.99849816338767157889676749706280411519534087076264110019730913624918762665676 Nov 22 01:39:41 PM PST 23 Nov 22 01:40:00 PM PST 23 1321911811 ps
T958 /workspace/coverage/default/45.lc_ctrl_smoke.13377338561092170751859563853867507952243606467296710560040207056609436915835 Nov 22 01:39:51 PM PST 23 Nov 22 01:39:57 PM PST 23 291295056 ps
T959 /workspace/coverage/default/8.lc_ctrl_state_post_trans.15991278634276406742073357446234235165949830746895187175325239832822059495849 Nov 22 01:37:57 PM PST 23 Nov 22 01:38:07 PM PST 23 217117078 ps
T960 /workspace/coverage/default/7.lc_ctrl_security_escalation.22533781704320134321506409056798230457735734298810068885065221939072314603678 Nov 22 01:37:25 PM PST 23 Nov 22 01:37:37 PM PST 23 625328098 ps
T961 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.53999927820840631333931934230869229933111254976735455777004604351010232936218 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:21 PM PST 23 1321911811 ps
T962 /workspace/coverage/default/2.lc_ctrl_smoke.110899546648842006563129581463174069355911211095775886325184240324390515650809 Nov 22 01:36:47 PM PST 23 Nov 22 01:36:53 PM PST 23 291295056 ps
T963 /workspace/coverage/default/31.lc_ctrl_state_post_trans.30789754958278534108035151324464178415248753133463536808587572310752009562354 Nov 22 01:39:06 PM PST 23 Nov 22 01:39:14 PM PST 23 217117078 ps
T964 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.48792220996723970193959760130822074941428172794517629514146961488349673643906 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:18 PM PST 23 1480535542 ps
T965 /workspace/coverage/default/28.lc_ctrl_alert_test.96820766381751485980732200591748388292932589466436710396151133625813037987122 Nov 22 01:39:05 PM PST 23 Nov 22 01:39:07 PM PST 23 42189906 ps
T966 /workspace/coverage/default/44.lc_ctrl_jtag_access.1575048576755408931844204715319169108509597258885866864935555296539356060630 Nov 22 01:39:47 PM PST 23 Nov 22 01:39:58 PM PST 23 1895300081 ps
T967 /workspace/coverage/default/9.lc_ctrl_state_post_trans.101737609604347059516671374430680503756982032219217413590045275932415204980840 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:13 PM PST 23 217117078 ps
T968 /workspace/coverage/default/47.lc_ctrl_sec_mubi.44880038476996115750277847656027326556562046063202784307591031381380067013917 Nov 22 01:39:48 PM PST 23 Nov 22 01:40:03 PM PST 23 1010128591 ps
T969 /workspace/coverage/default/8.lc_ctrl_state_failure.14671329932343713830811587623793971900502511673996721635042243666703749667468 Nov 22 01:37:55 PM PST 23 Nov 22 01:38:20 PM PST 23 487150632 ps
T970 /workspace/coverage/default/30.lc_ctrl_state_failure.66717316559320135947412196320902813881764243392288030603974900031825460633275 Nov 22 01:39:06 PM PST 23 Nov 22 01:39:29 PM PST 23 487150632 ps
T971 /workspace/coverage/default/11.lc_ctrl_jtag_errors.31834407774024020692931063513087539859983957403404906274288814864705469835906 Nov 22 01:38:09 PM PST 23 Nov 22 01:38:58 PM PST 23 5872518263 ps
T972 /workspace/coverage/default/26.lc_ctrl_alert_test.71903777194930883131863178386887249690281278650543043768923602580611485850246 Nov 22 01:38:17 PM PST 23 Nov 22 01:38:22 PM PST 23 42189906 ps
T973 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.89328570497525705036125081761587729356597751299040113085896095571323065548247 Nov 22 01:38:17 PM PST 23 Nov 22 01:38:22 PM PST 23 16404398 ps
T974 /workspace/coverage/default/19.lc_ctrl_jtag_access.8556441371429022258811832191700364772373590644769435589918084059866468881586 Nov 22 01:38:01 PM PST 23 Nov 22 01:38:14 PM PST 23 1895300081 ps
T975 /workspace/coverage/default/3.lc_ctrl_state_failure.111038397561148187485686467927601901469211576778256288567848306152497638908540 Nov 22 01:37:20 PM PST 23 Nov 22 01:37:45 PM PST 23 487150632 ps
T976 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.104432047155443236294062383717002510147996412355693223165026847682798496747468 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:14 PM PST 23 197527949 ps
T977 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.76040512353763778832416147489604832111854660494951455175607164916327855402826 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:07 PM PST 23 41172057 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.54863470137411113458524047682187370283342298360421819471350138749844810438277 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 191438712 ps
T979 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.38865807584266826608549939437092076455341693800479999806169957605732158711652 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 66993279 ps
T980 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.48091241148828168241451185348492950158236728359201482977639250950727203601709 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:12 PM PST 23 219831342 ps

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.9453593290124549041607630655474314177103406763485200373494155464770072246117
Short name T46
Test name
Test status
Simulation time 66993279 ps
CPU time 1.34 seconds
Started Nov 22 12:33:53 PM PST 23
Finished Nov 22 12:33:55 PM PST 23
Peak memory 210964 kb
Host smart-6ec99c8b-0b8f-4d3a-8ae5-f847e92a6ed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9453593290124549041607630655474314177103406763485200373494155464770072246117 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_same_csr_outstanding.945359329012454904160763065547431417710340676348520037349
4155464770072246117
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.87485089985670633302127035850865764107264823078667570821947424770895928630935
Short name T11
Test name
Test status
Simulation time 978628843 ps
CPU time 12.92 seconds
Started Nov 22 01:39:50 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 217468 kb
Host smart-68f36c8d-2217-41c1-950a-ecc229bdfa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87485089985670633302127035850865764107264823078667570821947424770895928630935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.lc_ctrl_errors.87485089985670633302127035850865764107264823078667570821947424770895928630935
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.50710520127118002108462316373480177725025972176577035920124915786576593890203
Short name T5
Test name
Test status
Simulation time 36820395678 ps
CPU time 292.13 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:43:11 PM PST 23
Peak memory 283472 kb
Host smart-cefbaf0a-8c24-4cd2-a901-d8250da14ee6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507105201271180021084623163734801777250259721765770359201249157865
76593890203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.50710520127118002108462316373480177725025972176577035920
124915786576593890203
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.54843891378414085810332420423977970995859759627674008411164116991968477068988
Short name T75
Test name
Test status
Simulation time 360562359 ps
CPU time 2.22 seconds
Started Nov 22 12:33:07 PM PST 23
Finished Nov 22 12:33:14 PM PST 23
Peak memory 210296 kb
Host smart-50eee18d-dd35-4554-8d54-3614422b0486
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54843891378414085810332420423977970995859759627674008
411164116991968477068988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.54843891378414085810332420423977970
995859759627674008411164116991968477068988
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.45641165552327531517563554697136382650393639584834706326066230590910536495056
Short name T78
Test name
Test status
Simulation time 208277863 ps
CPU time 2.69 seconds
Started Nov 22 12:33:30 PM PST 23
Finished Nov 22 12:33:34 PM PST 23
Peak memory 217336 kb
Host smart-9497d275-bd2b-468a-ae8e-a044ccaeaaa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45641165552327531517563554697136382650393639584834706326066230590910536495056 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_err.45641165552327531517563554697136382650393639584834706326066230590910536495056
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.18488189016580783700592663304091007019013753828622664257286773962707658156094
Short name T22
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.39 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:05 PM PST 23
Peak memory 218472 kb
Host smart-678bd560-737f-46be-be67-6fb95c810f26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18488189016580783700592663304091007019013753828622664257286773962707658156094 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.18488189016580783700592663304091007019013753828622664257286773962707658156094
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.69134581051343895240464332151727045997836312726161685746712670625033569487839
Short name T95
Test name
Test status
Simulation time 219831342 ps
CPU time 3.33 seconds
Started Nov 22 12:33:28 PM PST 23
Finished Nov 22 12:33:32 PM PST 23
Peak memory 217272 kb
Host smart-2bbaea34-08e6-4503-9e01-bfd7a10a7375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69134581051343895240464332151727045997836312726161685746712670625033569487839 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.69134581051343895240464332151727045997836312726161685746712670625033569487839
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.107530620386759870675056898631281188660911795597967738744775698397872207582997
Short name T16
Test name
Test status
Simulation time 964986095 ps
CPU time 10.87 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 217316 kb
Host smart-2ea58e3e-cf5c-4ab8-8e90-9a7f5485a7f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107530620386759870675056898631281188660911795597967738744775698397872207582997 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.107530620386759870675056898631281188660911795597967738744775698397872207582997
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.11627870205343103813919622666944070363552696465323908856033050372154386241218
Short name T292
Test name
Test status
Simulation time 625328098 ps
CPU time 8.13 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 217416 kb
Host smart-75da37af-a78a-4f24-add7-a5807094b8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11627870205343103813919622666944070363552696465323908856033050372154386241218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.lc_ctrl_security_escalation.11627870205343103813919622666944070363552696465323908856033050372154386241218
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.107438267761084771464388096702069511069547872448343510383851528404395151878028
Short name T81
Test name
Test status
Simulation time 33332834 ps
CPU time 0.94 seconds
Started Nov 22 12:33:04 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 210852 kb
Host smart-211bf086-56b1-44ee-b761-b8c8ba9f6cc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107438267761084771464388096702069511069547872448343510383851528404395151878028 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset.107438267761084771464388096702069511069547872448343510383851528404395151878028
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.90432775881773570393071376967109435165107327366048903588049367471245654276992
Short name T13
Test name
Test status
Simulation time 16404398 ps
CPU time 0.7 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:05 PM PST 23
Peak memory 207616 kb
Host smart-c53b7b8b-929e-4dcb-b011-e517d25489f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90432775881773570393071376967109435165107327366048903588049367471245654276992 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_volatile_unlock_smoke.90432775881773570393071376967109435165107327366048903
588049367471245654276992
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.114123701764904619691234933323955097857392258186462666106001748300063051897930
Short name T27
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.78 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:37:12 PM PST 23
Peak memory 246808 kb
Host smart-2aae03a3-0857-4c9c-900f-3c16e61ec26d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114123701764904619691234933323955097857392258186462666106001748300063051897930 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_state_post_trans.11412370176490461969123493332395509785739225818646266610
6001748300063051897930
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.77441694423278901720412568349593055297780543047490573504441743950477134246805
Short name T63
Test name
Test status
Simulation time 386472866 ps
CPU time 36.94 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:37:25 PM PST 23
Peak memory 273492 kb
Host smart-329c066a-1a86-44c4-9cb4-de5058061f5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77441694423278901720412568349593055297780543047490573504441743950477134246805 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.77441694423278901720412568349593055297780543047490573504441743950477134246805
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.93215230357570700686483770903140507270894037377564394506281647162605884219384
Short name T29
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.58 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 208916 kb
Host smart-1d8210df-fce3-4334-a268-91301509044f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93215230357570700686483770903140507270894037377564394506281647162605884219384 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.93215230357570700686483770903140507270894037377564394506281647162605884219384
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.82275019534947239775406299445620743853149885456545288783388605281894502578910
Short name T280
Test name
Test status
Simulation time 5030489285 ps
CPU time 51.06 seconds
Started Nov 22 01:36:45 PM PST 23
Finished Nov 22 01:37:38 PM PST 23
Peak memory 269096 kb
Host smart-f9d4e8d1-9a24-4cc0-b899-1aada4c87b06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82275019534947239775406299445620743853149885456545288783388605281894502578910 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_state_failure.822750195349472397754062994456207438531498854565452887833886052
81894502578910
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.84409513814721306474044063206040364041000614221420943689441906789454350876816
Short name T136
Test name
Test status
Simulation time 140599833 ps
CPU time 1.81 seconds
Started Nov 22 12:32:52 PM PST 23
Finished Nov 22 12:32:59 PM PST 23
Peak memory 207988 kb
Host smart-3f900396-fbc9-4b1e-a4b8-af6dca538986
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84409513814721306474044063206040364041000614221420943689441906789454350876816 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash.84409513814721306474044063206040364041000614221420943689441906789454350876816
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.6553361949119367754280657762017496631432243227859189432060783341023664290481
Short name T68
Test name
Test status
Simulation time 42189906 ps
CPU time 0.97 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:37:52 PM PST 23
Peak memory 207760 kb
Host smart-f4dbd4b8-3619-49a6-9202-9700dac289dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6553361949119367754280657762017496631432243227859189432060783341023664290481 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.6553361949119367754280657762017496631432243227859189432060783341023664290481
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.21868758646737310453794532139418292470985703079148338902301262922786808624240
Short name T71
Test name
Test status
Simulation time 41172057 ps
CPU time 1.23 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:13 PM PST 23
Peak memory 217424 kb
Host smart-412e70d7-afe2-4c07-bde1-a5775e66fcc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186875864673731045379453213941829247098570
3079148338902301262922786808624240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2186875864673731
0453794532139418292470985703079148338902301262922786808624240
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.96790254062451047985010940108342387390753079160857550250463382123868774224089
Short name T320
Test name
Test status
Simulation time 217117078 ps
CPU time 7.26 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 246440 kb
Host smart-f35d364d-1591-4860-a8f8-c6344dc5682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96790254062451047985010940108342387390753079160857550250463382123868774224089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.lc_ctrl_state_post_trans.96790254062451047985010940108342387390753079160857550250463382123868774224089
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.33439163416846457099015991460117905184158397616232091458971036187878724188601
Short name T458
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.16 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 217412 kb
Host smart-cca14ec2-aa42-41fc-becf-e2203eb3e3b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33439163416846457099015991460117905184158397616232091458971036187878724188601 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_prog_failure.3343916341684645709901599146011790518415839761623209145897103618
7878724188601
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.16290686735668327925237918272220957125171047262654411201521052131660949014121
Short name T131
Test name
Test status
Simulation time 58636203 ps
CPU time 1.22 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 208232 kb
Host smart-a96af73c-d53c-4291-8f01-40b117421a54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290686735668327925237918272220957125171047262654411201521052131660949014121 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing.16290686735668327925237918272220957125171047262654411201521052131660949014121
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.108858101959938519293593757832948757071136228564929091961302514992572998128660
Short name T127
Test name
Test status
Simulation time 33332834 ps
CPU time 0.96 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 210880 kb
Host smart-79f9b7f0-d23f-4e56-9c76-84a8768eace4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108858101959938519293593757832948757071136228564929091961302514992572998128660 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset.108858101959938519293593757832948757071136228564929091961302514992572998128660
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.83460878728489635983785928623155409368735513816812524232101611515667527532167
Short name T188
Test name
Test status
Simulation time 24850759 ps
CPU time 0.85 seconds
Started Nov 22 12:32:46 PM PST 23
Finished Nov 22 12:32:48 PM PST 23
Peak memory 208452 kb
Host smart-ede6a675-91aa-40dc-b938-846cee09f652
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83460878728489635983785928623155409368735513816812524232101611515667527532167 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.83460878728489635983785928623155409368735513816812524232101611515667527532167
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.66950464173302947052574005227393920023193108878976679194082856498965563589818
Short name T252
Test name
Test status
Simulation time 197527949 ps
CPU time 1.64 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:09 PM PST 23
Peak memory 207400 kb
Host smart-5d6d9f5e-7c9f-4cb6-be1d-e990bde2bc87
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669504641733029470525740052273939200231931088789766
79194082856498965563589818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.66950464173302947052574005227393920
023193108878976679194082856498965563589818
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.90195106346387469159560000680095946401206188895174168456271306427369847536035
Short name T101
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.83 seconds
Started Nov 22 12:32:54 PM PST 23
Finished Nov 22 12:33:09 PM PST 23
Peak memory 207896 kb
Host smart-454cd3d9-8bb2-4634-aafa-c302d9ff749f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90195106346387469159560000680095946401206188895174168
456271306427369847536035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.90195106346387469159560000680095946
401206188895174168456271306427369847536035
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.73655510119059978002283080772681509861930170701889559000819565615949411785927
Short name T247
Test name
Test status
Simulation time 3460251847 ps
CPU time 15.27 seconds
Started Nov 22 12:32:55 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 207972 kb
Host smart-02826487-d92e-4db9-890d-803e13f8e6f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73655510119059978002283080772681509861930170701889559
000819565615949411785927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.73655510119059978002283080772681509
861930170701889559000819565615949411785927
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.63355651139104811014877470577112592874720384202099904987407512355438932282973
Short name T231
Test name
Test status
Simulation time 360562359 ps
CPU time 2.38 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:08 PM PST 23
Peak memory 209360 kb
Host smart-554456e8-8597-4c3b-97a6-37b8ebf7e315
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63355651139104811014877470577112592874720384202099904
987407512355438932282973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.63355651139104811014877470577112592
874720384202099904987407512355438932282973
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.79078019271718838075413857331426804979424963885005648451944155921472019051066
Short name T227
Test name
Test status
Simulation time 191438712 ps
CPU time 1.85 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 217436 kb
Host smart-d07ac851-88aa-4fdf-bc65-2435d2e6548b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790780
19271718838075413857331426804979424963885005648451944155921472019051066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.79078019271718838075413857331426804979424963885005648451944155921472019051066
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.18364242716013967096261607184909517425344944053350714647428278674678288371233
Short name T97
Test name
Test status
Simulation time 241456169 ps
CPU time 1.82 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 207684 kb
Host smart-5621883e-0109-440a-afe2-4b5612795888
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18364242716013967096261607184909517425344944053350714647428
278674678288371233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.18364242716013967096261607184909517425344944053
350714647428278674678288371233
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.11650004854904075503089858705013387841595977349822951827913891152820770569817
Short name T93
Test name
Test status
Simulation time 66993279 ps
CPU time 1.29 seconds
Started Nov 22 12:32:49 PM PST 23
Finished Nov 22 12:32:58 PM PST 23
Peak memory 210852 kb
Host smart-2a7ea68e-5477-4442-9be0-2fca2da87790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11650004854904075503089858705013387841595
977349822951827913891152820770569817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.116500048549040
75503089858705013387841595977349822951827913891152820770569817
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.32068564275319456874181199588983920647934182508544903949960425983907760173548
Short name T239
Test name
Test status
Simulation time 66993279 ps
CPU time 1.36 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 210984 kb
Host smart-dc7ec4db-9caa-46f0-92be-3da1bae9aeed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32068564275319456874181199588983920647934182508544903949960425983907760173548
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_same_csr_outstanding.320685642753194568741811995889839206479341825085449039499
60425983907760173548
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.25982133609712314118712342370922417342046361263490055647811964346661351786422
Short name T108
Test name
Test status
Simulation time 219831342 ps
CPU time 3.32 seconds
Started Nov 22 12:32:48 PM PST 23
Finished Nov 22 12:33:00 PM PST 23
Peak memory 217324 kb
Host smart-a4de9056-c04c-41bc-84cd-017dda616b04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25982133609712314118712342370922417342046361263490055647811964346661351786422 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.25982133609712314118712342370922417342046361263490055647811964346661351786422
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.35357144637480437770082611509147385213028299106921553695633130404396972741972
Short name T199
Test name
Test status
Simulation time 208277863 ps
CPU time 2.95 seconds
Started Nov 22 12:32:49 PM PST 23
Finished Nov 22 12:32:59 PM PST 23
Peak memory 217320 kb
Host smart-65fe4095-91ec-44f7-b84c-3afaa5bcddc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35357144637480437770082611509147385213028299106921553695633130404396972741972 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_err.35357144637480437770082611509147385213028299106921553695633130404396972741972
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.39822468288715526453474399548630379625552270735721232669920559956268009747211
Short name T121
Test name
Test status
Simulation time 58636203 ps
CPU time 1.22 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 208232 kb
Host smart-c81e8325-3cad-45b6-b315-50995b896aea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39822468288715526453474399548630379625552270735721232669920559956268009747211 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing.39822468288715526453474399548630379625552270735721232669920559956268009747211
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.18014829050367792049362956666437602348869369690997949950984983684945285931322
Short name T92
Test name
Test status
Simulation time 140599833 ps
CPU time 1.82 seconds
Started Nov 22 12:32:49 PM PST 23
Finished Nov 22 12:32:58 PM PST 23
Peak memory 208012 kb
Host smart-bdc5a094-8339-4f29-b97e-716a1739a36e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18014829050367792049362956666437602348869369690997949950984983684945285931322 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash.18014829050367792049362956666437602348869369690997949950984983684945285931322
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.53365302487128394646448876603380060619766472293927112140621652250638503585052
Short name T129
Test name
Test status
Simulation time 33332834 ps
CPU time 1.01 seconds
Started Nov 22 12:32:56 PM PST 23
Finished Nov 22 12:33:03 PM PST 23
Peak memory 210904 kb
Host smart-d016be38-4b3c-4f4b-b359-aeb28e86a3d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53365302487128394646448876603380060619766472293927112140621652250638503585052 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset.53365302487128394646448876603380060619766472293927112140621652250638503585052
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.36681187110295752648772539233849384357654754356109259175011529878905971227343
Short name T244
Test name
Test status
Simulation time 41172057 ps
CPU time 1.22 seconds
Started Nov 22 12:32:53 PM PST 23
Finished Nov 22 12:32:59 PM PST 23
Peak memory 217460 kb
Host smart-9b368145-6a68-4481-8098-3c6a4256bd2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668118711029575264877253923384938435765475
4356109259175011529878905971227343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3668118711029575
2648772539233849384357654754356109259175011529878905971227343
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.58033402995863189071599704800597294863699570008426833086411599100433785604279
Short name T162
Test name
Test status
Simulation time 24850759 ps
CPU time 0.91 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 208424 kb
Host smart-9caf83a3-73f5-4cc7-a804-44151fb70b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58033402995863189071599704800597294863699570008426833086411599100433785604279 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.58033402995863189071599704800597294863699570008426833086411599100433785604279
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.8725998357730691331627018072554149151346378943310831893333422958672116263928
Short name T216
Test name
Test status
Simulation time 197527949 ps
CPU time 1.69 seconds
Started Nov 22 12:32:52 PM PST 23
Finished Nov 22 12:32:58 PM PST 23
Peak memory 207360 kb
Host smart-1b29e30d-ac9d-4576-a2f9-dc9047fe4499
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872599835773069133162701807255414915134637894331083
1893333422958672116263928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.872599835773069133162701807255414915
1346378943310831893333422958672116263928
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.19846137826665708186722539291828396077052482616957399032229101090490784402421
Short name T237
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.28 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:21 PM PST 23
Peak memory 207916 kb
Host smart-42106539-43ad-4822-b684-069e9df63c20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846137826665708186722539291828396077052482616957399
032229101090490784402421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.19846137826665708186722539291828396
077052482616957399032229101090490784402421
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.38755182480076917081489896712385663967335437628739955223760674444670094586330
Short name T158
Test name
Test status
Simulation time 3460251847 ps
CPU time 15.46 seconds
Started Nov 22 12:32:49 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 207940 kb
Host smart-a5dad637-89c7-4f5e-98fb-2529886b34cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38755182480076917081489896712385663967335437628739955
223760674444670094586330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.38755182480076917081489896712385663
967335437628739955223760674444670094586330
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.95785416405007151747771961197753258553200277177957147324792469553047942033309
Short name T200
Test name
Test status
Simulation time 360562359 ps
CPU time 2.25 seconds
Started Nov 22 12:32:49 PM PST 23
Finished Nov 22 12:32:59 PM PST 23
Peak memory 210132 kb
Host smart-a995de76-2723-4798-bf8d-5346df6425b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95785416405007151747771961197753258553200277177957147
324792469553047942033309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.95785416405007151747771961197753258
553200277177957147324792469553047942033309
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.40569550486612450008624445780124439947846172625153963067918019819281838772187
Short name T161
Test name
Test status
Simulation time 191438712 ps
CPU time 1.86 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:16 PM PST 23
Peak memory 217440 kb
Host smart-1c8cbf95-0be6-4115-8ced-5ff1221ae5dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405695
50486612450008624445780124439947846172625153963067918019819281838772187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.40569550486612450008624445780124439947846172625153963067918019819281838772187
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.98979330097014323465687435269932166037016839613987085621217318889054288198509
Short name T104
Test name
Test status
Simulation time 241456169 ps
CPU time 1.82 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 208824 kb
Host smart-4dbed759-3cbb-4762-9580-67a6fc75cb5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98979330097014323465687435269932166037016839613987085621217
318889054288198509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.98979330097014323465687435269932166037016839613
987085621217318889054288198509
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.58711926536117017589183411334184219038081082422099398627222548708296777226819
Short name T70
Test name
Test status
Simulation time 66993279 ps
CPU time 1.32 seconds
Started Nov 22 12:32:51 PM PST 23
Finished Nov 22 12:32:58 PM PST 23
Peak memory 211004 kb
Host smart-9f901583-1859-41ef-803f-d483d45bf699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58711926536117017589183411334184219038081
082422099398627222548708296777226819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.587119265361170
17589183411334184219038081082422099398627222548708296777226819
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.70552396300259163517500784716817000859682895270947637445200245956066037966569
Short name T165
Test name
Test status
Simulation time 66993279 ps
CPU time 1.27 seconds
Started Nov 22 12:32:52 PM PST 23
Finished Nov 22 12:32:58 PM PST 23
Peak memory 210960 kb
Host smart-50ee101c-9ada-466c-bfce-bde25206a302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70552396300259163517500784716817000859682895270947637445200245956066037966569
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_same_csr_outstanding.705523963002591635175007847168170008596828952709476374452
00245956066037966569
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.108370605215513493911097443159055628359260427369654750171217543164144130634051
Short name T113
Test name
Test status
Simulation time 219831342 ps
CPU time 3.36 seconds
Started Nov 22 12:32:59 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217284 kb
Host smart-1d35fc09-fe64-4aa3-8524-e2a4cf0476ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108370605215513493911097443159055628359260427369654750171217543164144130634051 -assert nopostproc +
UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.108370605215513493911097443159055628359260427369654750171217543164144130634051
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.51561762586612151252012727882126860176356806625758748668252525013297113545435
Short name T148
Test name
Test status
Simulation time 208277863 ps
CPU time 2.97 seconds
Started Nov 22 12:32:51 PM PST 23
Finished Nov 22 12:32:59 PM PST 23
Peak memory 217400 kb
Host smart-ee831663-f515-42ad-9af8-53dac9d84986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51561762586612151252012727882126860176356806625758748668252525013297113545435 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_err.51561762586612151252012727882126860176356806625758748668252525013297113545435
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.104674096743643305395900525450252564538590766257547773228813753778293427092795
Short name T226
Test name
Test status
Simulation time 41172057 ps
CPU time 1.21 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217420 kb
Host smart-150c8a26-096b-4d6b-aa2d-d0d8b60da605
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046740967436433053959005254502525645385907
66257547773228813753778293427092795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.10467409674364
3305395900525450252564538590766257547773228813753778293427092795
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.72925461630715270573553672194135524385465805626607427033711058860113596978919
Short name T174
Test name
Test status
Simulation time 24850759 ps
CPU time 0.87 seconds
Started Nov 22 12:33:11 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 208568 kb
Host smart-daf1d3f8-78b1-4719-ad39-823dcef5c7a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72925461630715270573553672194135524385465805626607427033711058860113596978919 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.72925461630715270573553672194135524385465805626607427033711058860113596978919
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.53468034219021467366634786249143312064936158963781961021996460552419928058722
Short name T198
Test name
Test status
Simulation time 66993279 ps
CPU time 1.35 seconds
Started Nov 22 12:32:57 PM PST 23
Finished Nov 22 12:33:04 PM PST 23
Peak memory 210940 kb
Host smart-5a9499b6-ba36-4e5b-8474-7a2079315521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53468034219021467366634786249143312064936158963781961021996460552419928058722
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_same_csr_outstanding.53468034219021467366634786249143312064936158963781961021
996460552419928058722
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.6591105513026295883756785920479012665960269760226367943551797110348554113876
Short name T219
Test name
Test status
Simulation time 219831342 ps
CPU time 3.29 seconds
Started Nov 22 12:32:59 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217292 kb
Host smart-67b96736-5971-46c2-bb72-a0f1d532dd47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6591105513026295883756785920479012665960269760226367943551797110348554113876 -assert nopostproc +UV
M_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.6591105513026295883756785920479012665960269760226367943551797110348554113876
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.96478745938657651685360503330939501593407596803513876393285889363814341959986
Short name T228
Test name
Test status
Simulation time 208277863 ps
CPU time 2.78 seconds
Started Nov 22 12:33:22 PM PST 23
Finished Nov 22 12:33:26 PM PST 23
Peak memory 217388 kb
Host smart-c5cc6e8c-6696-4064-9fbb-f7f7226d9230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96478745938657651685360503330939501593407596803513876393285889363814341959986 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_err.96478745938657651685360503330939501593407596803513876393285889363814341959986
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.102644714253189353531721670692117909192469007011024555346740755280614351366978
Short name T215
Test name
Test status
Simulation time 41172057 ps
CPU time 1.18 seconds
Started Nov 22 12:33:08 PM PST 23
Finished Nov 22 12:33:13 PM PST 23
Peak memory 217416 kb
Host smart-e206cb6c-d8ad-4af7-855b-f036ee842399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026447142531893535317216706921179091924690
07011024555346740755280614351366978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.10264471425318
9353531721670692117909192469007011024555346740755280614351366978
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.51164555356477297914177202710936130986455383408933732118764511447703740489195
Short name T120
Test name
Test status
Simulation time 24850759 ps
CPU time 0.9 seconds
Started Nov 22 12:33:11 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 208564 kb
Host smart-01d5b823-065a-43ce-9302-34987d9f8e6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51164555356477297914177202710936130986455383408933732118764511447703740489195 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.51164555356477297914177202710936130986455383408933732118764511447703740489195
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.42151676455771676842913765192551220820450756405630982467133969548778566052459
Short name T117
Test name
Test status
Simulation time 66993279 ps
CPU time 1.35 seconds
Started Nov 22 12:32:57 PM PST 23
Finished Nov 22 12:33:04 PM PST 23
Peak memory 210932 kb
Host smart-dcf1e8f5-2518-46d8-a140-ee0ba1ca8868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42151676455771676842913765192551220820450756405630982467133969548778566052459
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_same_csr_outstanding.42151676455771676842913765192551220820450756405630982467
133969548778566052459
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.93621744690106765486676758806884924339384422738837050141776764624709483897155
Short name T112
Test name
Test status
Simulation time 219831342 ps
CPU time 3.38 seconds
Started Nov 22 12:32:57 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 217248 kb
Host smart-b732eb77-3b64-4292-8891-af9078531a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93621744690106765486676758806884924339384422738837050141776764624709483897155 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.93621744690106765486676758806884924339384422738837050141776764624709483897155
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.93222235221002225735879841317031550228677843104574983576043529001107418239345
Short name T206
Test name
Test status
Simulation time 208277863 ps
CPU time 2.92 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 217260 kb
Host smart-3dc85b3d-7fb8-417a-a8e4-621882b2dafa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93222235221002225735879841317031550228677843104574983576043529001107418239345 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_err.93222235221002225735879841317031550228677843104574983576043529001107418239345
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.69088335036718042171068683544248673941293266887253594944358773044026449771142
Short name T144
Test name
Test status
Simulation time 41172057 ps
CPU time 1.21 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 217408 kb
Host smart-4dcc2f85-2e41-47d4-9b2d-e76ed898028f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6908833503671804217106868354424867394129326
6887253594944358773044026449771142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.690883350367180
42171068683544248673941293266887253594944358773044026449771142
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.61087181204682136406038013604606186608314593637997048653311658142978498386138
Short name T186
Test name
Test status
Simulation time 24850759 ps
CPU time 0.85 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 207916 kb
Host smart-b2787aac-152c-4f2d-8115-1b2f1f52d4bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61087181204682136406038013604606186608314593637997048653311658142978498386138 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.61087181204682136406038013604606186608314593637997048653311658142978498386138
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.22298377406410336882587356258332290899304366953259790368222372735604177271776
Short name T182
Test name
Test status
Simulation time 66993279 ps
CPU time 1.27 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 210956 kb
Host smart-5c277e5d-0f9a-4848-ac42-f54d0d41dd28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22298377406410336882587356258332290899304366953259790368222372735604177271776
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_same_csr_outstanding.22298377406410336882587356258332290899304366953259790368
222372735604177271776
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.48091241148828168241451185348492950158236728359201482977639250950727203601709
Short name T980
Test name
Test status
Simulation time 219831342 ps
CPU time 3.39 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 217364 kb
Host smart-2096a718-34bc-4562-89c6-0194c4af525d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48091241148828168241451185348492950158236728359201482977639250950727203601709 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.48091241148828168241451185348492950158236728359201482977639250950727203601709
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.95770812897880409432928766032728358389738893893580543325305399040795399163325
Short name T224
Test name
Test status
Simulation time 208277863 ps
CPU time 2.8 seconds
Started Nov 22 12:32:57 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 217320 kb
Host smart-56adb29a-04d8-4d9e-bb5a-a689eabe0ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95770812897880409432928766032728358389738893893580543325305399040795399163325 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_err.95770812897880409432928766032728358389738893893580543325305399040795399163325
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.31101487015116773753138671215348715197681518271697802397560933292677749680286
Short name T143
Test name
Test status
Simulation time 41172057 ps
CPU time 1.23 seconds
Started Nov 22 12:33:27 PM PST 23
Finished Nov 22 12:33:30 PM PST 23
Peak memory 217416 kb
Host smart-1265a77e-1e0a-4b80-807b-445ead586788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110148701511677375313867121534871519768151
8271697802397560933292677749680286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.311014870151167
73753138671215348715197681518271697802397560933292677749680286
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.72776124205403955219874859833666540010812713636923341383382996525491426574158
Short name T175
Test name
Test status
Simulation time 24850759 ps
CPU time 0.88 seconds
Started Nov 22 12:33:28 PM PST 23
Finished Nov 22 12:33:30 PM PST 23
Peak memory 208416 kb
Host smart-c390d933-31c8-41dc-8d4f-0495bdd89d5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72776124205403955219874859833666540010812713636923341383382996525491426574158 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.72776124205403955219874859833666540010812713636923341383382996525491426574158
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.34729912522762681040725945177486928815289201318826973634076530583599429294455
Short name T160
Test name
Test status
Simulation time 66993279 ps
CPU time 1.35 seconds
Started Nov 22 12:33:16 PM PST 23
Finished Nov 22 12:33:18 PM PST 23
Peak memory 211032 kb
Host smart-c1f94081-2232-47ec-bd18-af37ca7f3020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34729912522762681040725945177486928815289201318826973634076530583599429294455
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_same_csr_outstanding.34729912522762681040725945177486928815289201318826973634
076530583599429294455
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.46492813175005850294111732486790469924424256018787321919070962282331255183306
Short name T263
Test name
Test status
Simulation time 219831342 ps
CPU time 3.22 seconds
Started Nov 22 12:33:42 PM PST 23
Finished Nov 22 12:33:46 PM PST 23
Peak memory 217312 kb
Host smart-2309b70a-1889-4b58-9a59-88a0fc648241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46492813175005850294111732486790469924424256018787321919070962282331255183306 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.46492813175005850294111732486790469924424256018787321919070962282331255183306
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.20051483477260892212553155450932606037907617905759847702738671998711108439409
Short name T191
Test name
Test status
Simulation time 208277863 ps
CPU time 2.79 seconds
Started Nov 22 12:33:28 PM PST 23
Finished Nov 22 12:33:31 PM PST 23
Peak memory 217340 kb
Host smart-b9a7ad87-4ff0-42e9-8105-84e8c7f88e02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20051483477260892212553155450932606037907617905759847702738671998711108439409 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_err.20051483477260892212553155450932606037907617905759847702738671998711108439409
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.96274333192335925656468590752743617030316648095071687568080482365605090325952
Short name T209
Test name
Test status
Simulation time 41172057 ps
CPU time 1.16 seconds
Started Nov 22 12:33:45 PM PST 23
Finished Nov 22 12:33:47 PM PST 23
Peak memory 217412 kb
Host smart-f3d6cbd6-4888-4b8b-a563-0b63a6341a15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9627433319233592565646859075274361703031664
8095071687568080482365605090325952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.962743331923359
25656468590752743617030316648095071687568080482365605090325952
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.75228150861905699342397435930343170648575099621390498286518174880665458981500
Short name T180
Test name
Test status
Simulation time 24850759 ps
CPU time 0.87 seconds
Started Nov 22 12:33:26 PM PST 23
Finished Nov 22 12:33:28 PM PST 23
Peak memory 208464 kb
Host smart-c585d66d-bc17-405b-9529-9f302464934d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75228150861905699342397435930343170648575099621390498286518174880665458981500 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.75228150861905699342397435930343170648575099621390498286518174880665458981500
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.17272410572909076834677081885576234753498146004927380794026680508656660244045
Short name T163
Test name
Test status
Simulation time 219831342 ps
CPU time 3.28 seconds
Started Nov 22 12:33:32 PM PST 23
Finished Nov 22 12:33:36 PM PST 23
Peak memory 217296 kb
Host smart-3c081749-fed8-45f0-a542-f8ab58689ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17272410572909076834677081885576234753498146004927380794026680508656660244045 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.17272410572909076834677081885576234753498146004927380794026680508656660244045
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.112375062096570231558391358075469780423406829461242013253657331578466109657090
Short name T236
Test name
Test status
Simulation time 208277863 ps
CPU time 2.72 seconds
Started Nov 22 12:33:27 PM PST 23
Finished Nov 22 12:33:31 PM PST 23
Peak memory 217360 kb
Host smart-0010d798-4480-4909-bd00-d41cf11dc26c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112375062096570231558391358075469780423406829461242013253657331578466109657090 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_err.112375062096570231558391358075469780423406829461242013253657331578466109657090
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.114205524607912824199342747732320575801996679878981996220977771760825895608313
Short name T69
Test name
Test status
Simulation time 41172057 ps
CPU time 1.21 seconds
Started Nov 22 12:33:43 PM PST 23
Finished Nov 22 12:33:45 PM PST 23
Peak memory 217416 kb
Host smart-d4082e3b-09b5-47d2-9e1e-520ba4dfc308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142055246079128241993427477323205758019966
79878981996220977771760825895608313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.11420552460791
2824199342747732320575801996679878981996220977771760825895608313
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.29094445130791408003079815528012313193387717761075783579497676338346485255934
Short name T116
Test name
Test status
Simulation time 24850759 ps
CPU time 0.83 seconds
Started Nov 22 12:33:26 PM PST 23
Finished Nov 22 12:33:28 PM PST 23
Peak memory 208456 kb
Host smart-036123b3-7716-4fe1-94eb-e6fbf28c9a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29094445130791408003079815528012313193387717761075783579497676338346485255934 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.29094445130791408003079815528012313193387717761075783579497676338346485255934
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.107848197603356311001542415223485959293816471297503907902177463554569331903920
Short name T257
Test name
Test status
Simulation time 66993279 ps
CPU time 1.35 seconds
Started Nov 22 12:33:34 PM PST 23
Finished Nov 22 12:33:37 PM PST 23
Peak memory 210972 kb
Host smart-b4a714ba-d32a-430a-8ee6-cbc95cf9f2f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107848197603356311001542415223485959293816471297503907902177463554569331903920
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_same_csr_outstanding.1078481976033563110015424152234859592938164712975039079
02177463554569331903920
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.62976134355004312504545421050884345675981885428785347046161376236814609126068
Short name T202
Test name
Test status
Simulation time 208277863 ps
CPU time 2.75 seconds
Started Nov 22 12:33:26 PM PST 23
Finished Nov 22 12:33:30 PM PST 23
Peak memory 217356 kb
Host smart-80b6f8ac-1b77-4ac7-9ed3-f41367b24216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62976134355004312504545421050884345675981885428785347046161376236814609126068 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_err.62976134355004312504545421050884345675981885428785347046161376236814609126068
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.74961123203085663856612373219867416352120181117314104816544307304965755195046
Short name T145
Test name
Test status
Simulation time 41172057 ps
CPU time 1.26 seconds
Started Nov 22 12:33:35 PM PST 23
Finished Nov 22 12:33:37 PM PST 23
Peak memory 217424 kb
Host smart-51b16354-a15a-4035-b1f6-85940e3b2643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7496112320308566385661237321986741635212018
1117314104816544307304965755195046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.749611232030856
63856612373219867416352120181117314104816544307304965755195046
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.97476081032665002187694705236024954457391541898032244781781619709846287829074
Short name T123
Test name
Test status
Simulation time 24850759 ps
CPU time 0.86 seconds
Started Nov 22 12:33:46 PM PST 23
Finished Nov 22 12:33:48 PM PST 23
Peak memory 208452 kb
Host smart-20df3659-cbeb-47a0-bd87-2011321a6c5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97476081032665002187694705236024954457391541898032244781781619709846287829074 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.97476081032665002187694705236024954457391541898032244781781619709846287829074
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.69710872368846589094349317242937087655108113989137237956576075166056085114776
Short name T115
Test name
Test status
Simulation time 66993279 ps
CPU time 1.27 seconds
Started Nov 22 12:33:28 PM PST 23
Finished Nov 22 12:33:30 PM PST 23
Peak memory 210040 kb
Host smart-3e4031ab-454c-48cf-a735-6ac638d1daa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69710872368846589094349317242937087655108113989137237956576075166056085114776
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_same_csr_outstanding.69710872368846589094349317242937087655108113989137237956
576075166056085114776
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.69524492449189090346437856425361892087959544048453362124685828548733188886220
Short name T221
Test name
Test status
Simulation time 219831342 ps
CPU time 3.07 seconds
Started Nov 22 12:33:28 PM PST 23
Finished Nov 22 12:33:32 PM PST 23
Peak memory 217288 kb
Host smart-87bca352-af12-4219-8f2a-376e0e3c54c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69524492449189090346437856425361892087959544048453362124685828548733188886220 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.69524492449189090346437856425361892087959544048453362124685828548733188886220
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.78858823306247876759727202690101602119198624884649278329206592123115956948904
Short name T72
Test name
Test status
Simulation time 41172057 ps
CPU time 1.17 seconds
Started Nov 22 12:33:32 PM PST 23
Finished Nov 22 12:33:34 PM PST 23
Peak memory 217428 kb
Host smart-b26d4b5b-cdcc-4396-a486-7b0b59edfdaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7885882330624787675972720269010160211919862
4884649278329206592123115956948904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.788588233062478
76759727202690101602119198624884649278329206592123115956948904
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.107094602402691719537895103495224076651219667004757170087572385557117556831041
Short name T157
Test name
Test status
Simulation time 24850759 ps
CPU time 0.82 seconds
Started Nov 22 12:33:29 PM PST 23
Finished Nov 22 12:33:30 PM PST 23
Peak memory 208424 kb
Host smart-4937ecb8-a4fd-4c77-8645-f179b77fadb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107094602402691719537895103495224076651219667004757170087572385557117556831041 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.107094602402691719537895103495224076651219667004757170087572385557117556831041
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.37707716911070513490459596236922160399984060401167227484356573976502941254391
Short name T114
Test name
Test status
Simulation time 66993279 ps
CPU time 1.26 seconds
Started Nov 22 12:33:28 PM PST 23
Finished Nov 22 12:33:30 PM PST 23
Peak memory 210124 kb
Host smart-67d90101-8b24-4fef-8cc0-5bc885e92fdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37707716911070513490459596236922160399984060401167227484356573976502941254391
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_same_csr_outstanding.37707716911070513490459596236922160399984060401167227484
356573976502941254391
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.26668235253910376632113342977433557134018912899345288589636174344375070468561
Short name T73
Test name
Test status
Simulation time 219831342 ps
CPU time 3.3 seconds
Started Nov 22 12:33:36 PM PST 23
Finished Nov 22 12:33:40 PM PST 23
Peak memory 217304 kb
Host smart-d6ee3cb1-d54d-44c7-aacc-72acbb8a0fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26668235253910376632113342977433557134018912899345288589636174344375070468561 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.26668235253910376632113342977433557134018912899345288589636174344375070468561
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.31997516233946982130589198327098689163525054010497797929058313894190818911117
Short name T243
Test name
Test status
Simulation time 208277863 ps
CPU time 2.92 seconds
Started Nov 22 12:33:35 PM PST 23
Finished Nov 22 12:33:39 PM PST 23
Peak memory 217376 kb
Host smart-842c303e-1996-4e2b-9089-ea0444b69cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31997516233946982130589198327098689163525054010497797929058313894190818911117 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_err.31997516233946982130589198327098689163525054010497797929058313894190818911117
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.80269124688055611185811798072316975106483675861282217080611122231981973910474
Short name T147
Test name
Test status
Simulation time 41172057 ps
CPU time 1.22 seconds
Started Nov 22 12:33:37 PM PST 23
Finished Nov 22 12:33:39 PM PST 23
Peak memory 217412 kb
Host smart-a2c64860-63b1-47c5-9706-6ed9c62dc1fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8026912468805561118581179807231697510648367
5861282217080611122231981973910474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.802691246880556
11185811798072316975106483675861282217080611122231981973910474
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.42777649472345041578733050386974722434180405223723969357547799504541757747220
Short name T203
Test name
Test status
Simulation time 24850759 ps
CPU time 0.84 seconds
Started Nov 22 12:33:29 PM PST 23
Finished Nov 22 12:33:30 PM PST 23
Peak memory 208416 kb
Host smart-69e685c6-a2bf-448e-97d1-79ae3b88141f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42777649472345041578733050386974722434180405223723969357547799504541757747220 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.42777649472345041578733050386974722434180405223723969357547799504541757747220
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.83624750081544231418195348505027749506369296455025824092851222718489269546744
Short name T255
Test name
Test status
Simulation time 66993279 ps
CPU time 1.32 seconds
Started Nov 22 12:34:40 PM PST 23
Finished Nov 22 12:34:46 PM PST 23
Peak memory 210984 kb
Host smart-63713ac8-dfe6-41b6-a7aa-12f585304d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83624750081544231418195348505027749506369296455025824092851222718489269546744
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_same_csr_outstanding.83624750081544231418195348505027749506369296455025824092
851222718489269546744
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.99050994239932042507719212386344576965398176512486135300892297273183128710291
Short name T96
Test name
Test status
Simulation time 219831342 ps
CPU time 3.24 seconds
Started Nov 22 12:33:47 PM PST 23
Finished Nov 22 12:33:51 PM PST 23
Peak memory 217268 kb
Host smart-2e86caea-a794-4fd2-9b58-3d7fdde3fbdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99050994239932042507719212386344576965398176512486135300892297273183128710291 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.99050994239932042507719212386344576965398176512486135300892297273183128710291
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.17385105501831325757958963347922519132290887704072430075714664534698289117988
Short name T248
Test name
Test status
Simulation time 208277863 ps
CPU time 2.7 seconds
Started Nov 22 12:33:29 PM PST 23
Finished Nov 22 12:33:33 PM PST 23
Peak memory 217348 kb
Host smart-6a25a0cb-f975-452e-93fc-3676e2b17165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17385105501831325757958963347922519132290887704072430075714664534698289117988 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_err.17385105501831325757958963347922519132290887704072430075714664534698289117988
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.55563301017322139754813485201482992499164533466865448572968615958411333302250
Short name T185
Test name
Test status
Simulation time 41172057 ps
CPU time 1.26 seconds
Started Nov 22 12:33:35 PM PST 23
Finished Nov 22 12:33:38 PM PST 23
Peak memory 217424 kb
Host smart-b52557d6-7053-497f-bad8-ccb9412169ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5556330101732213975481348520148299249916453
3466865448572968615958411333302250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.555633010173221
39754813485201482992499164533466865448572968615958411333302250
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.29761321890574697976302568576397912276588423538321711403981920488357402161575
Short name T122
Test name
Test status
Simulation time 24850759 ps
CPU time 0.85 seconds
Started Nov 22 12:33:35 PM PST 23
Finished Nov 22 12:33:37 PM PST 23
Peak memory 208456 kb
Host smart-d5fbcc57-9042-405b-b1e2-f06bd9fd9760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761321890574697976302568576397912276588423538321711403981920488357402161575 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.29761321890574697976302568576397912276588423538321711403981920488357402161575
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3336476537406936244206582538404620107876771472649794855196232577746465727659
Short name T193
Test name
Test status
Simulation time 66993279 ps
CPU time 1.33 seconds
Started Nov 22 12:33:35 PM PST 23
Finished Nov 22 12:33:38 PM PST 23
Peak memory 210960 kb
Host smart-d247f827-47e3-4ea2-a21a-ecbf51efa56c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336476537406936244206582538404620107876771472649794855196232577746465727659 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_same_csr_outstanding.333647653740693624420658253840462010787677147264979485519
6232577746465727659
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.73335595329188843530158035319876569591269655566316200163795093335787791025153
Short name T110
Test name
Test status
Simulation time 219831342 ps
CPU time 3.32 seconds
Started Nov 22 12:33:46 PM PST 23
Finished Nov 22 12:33:50 PM PST 23
Peak memory 217296 kb
Host smart-0ae13358-a87a-4f8c-a6ae-5bd9c62f43c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73335595329188843530158035319876569591269655566316200163795093335787791025153 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.73335595329188843530158035319876569591269655566316200163795093335787791025153
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.9703354673668057363658771485037192619035980746224350318388382643856640473050
Short name T79
Test name
Test status
Simulation time 208277863 ps
CPU time 2.73 seconds
Started Nov 22 12:33:35 PM PST 23
Finished Nov 22 12:33:39 PM PST 23
Peak memory 217356 kb
Host smart-c1c5f3a2-9fa4-4401-82c2-3150a339bea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9703354673668057363658771485037192619035980746224350318388382643856640473050 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_err.9703354673668057363658771485037192619035980746224350318388382643856640473050
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.69537186780716441012558117639797517222382419325934245730673831271041623302651
Short name T124
Test name
Test status
Simulation time 58636203 ps
CPU time 1.2 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 208232 kb
Host smart-c192d76c-06bd-44e9-bf6d-1f4c7e15dff6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69537186780716441012558117639797517222382419325934245730673831271041623302651 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing.69537186780716441012558117639797517222382419325934245730673831271041623302651
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.34980416125604583017177150845077131565676695741381855156675419357921824397659
Short name T242
Test name
Test status
Simulation time 140599833 ps
CPU time 1.84 seconds
Started Nov 22 12:32:53 PM PST 23
Finished Nov 22 12:32:59 PM PST 23
Peak memory 207996 kb
Host smart-d0273f97-b18d-49dd-a4f7-985a7f2e4ade
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980416125604583017177150845077131565676695741381855156675419357921824397659 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash.34980416125604583017177150845077131565676695741381855156675419357921824397659
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.36893234713992094072606029947188499500031184739359704039298664614031225853803
Short name T132
Test name
Test status
Simulation time 33332834 ps
CPU time 0.93 seconds
Started Nov 22 12:33:08 PM PST 23
Finished Nov 22 12:33:13 PM PST 23
Peak memory 210884 kb
Host smart-5d6c7167-bac9-473a-b708-92716d26e573
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36893234713992094072606029947188499500031184739359704039298664614031225853803 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset.36893234713992094072606029947188499500031184739359704039298664614031225853803
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.58543841315435884389006537967209106705385339528946449829158223076386265078138
Short name T260
Test name
Test status
Simulation time 41172057 ps
CPU time 1.23 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 217412 kb
Host smart-ff1939b8-0542-4ecc-aaf0-397b1ef471b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5854384131543588438900653796720910670538533
9528946449829158223076386265078138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.5854384131543588
4389006537967209106705385339528946449829158223076386265078138
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.31207019736292745558916049083494051619574349690479930471012123883127935483103
Short name T98
Test name
Test status
Simulation time 24850759 ps
CPU time 0.89 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 208432 kb
Host smart-ec883938-238f-4d9e-bfb7-0e02d3e13375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207019736292745558916049083494051619574349690479930471012123883127935483103 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.31207019736292745558916049083494051619574349690479930471012123883127935483103
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.78397021028438003059147262660352861378698168305890426462938498861608093446205
Short name T222
Test name
Test status
Simulation time 197527949 ps
CPU time 1.58 seconds
Started Nov 22 12:32:52 PM PST 23
Finished Nov 22 12:33:04 PM PST 23
Peak memory 207364 kb
Host smart-ea2d7f78-0c63-48c6-aeca-1a7599d1e9b3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783970210284380030591472626603528613786981683058904
26462938498861608093446205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.78397021028438003059147262660352861
378698168305890426462938498861608093446205
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.86879716720660940221350481148276274985858334165671786502475404591134033918380
Short name T76
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.3 seconds
Started Nov 22 12:32:57 PM PST 23
Finished Nov 22 12:33:14 PM PST 23
Peak memory 207924 kb
Host smart-c0f7bc44-5a0a-4b18-aaf6-3cea198a62b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86879716720660940221350481148276274985858334165671786
502475404591134033918380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.86879716720660940221350481148276274
985858334165671786502475404591134033918380
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.40075745306210171547071339209285382070540987944650228263985451792136293326626
Short name T249
Test name
Test status
Simulation time 3460251847 ps
CPU time 14.96 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:22 PM PST 23
Peak memory 208056 kb
Host smart-0b4621fa-00a7-4f70-b3c6-1f1c78fb6d2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40075745306210171547071339209285382070540987944650228
263985451792136293326626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.40075745306210171547071339209285382
070540987944650228263985451792136293326626
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.30474126944108506210646432507119678694826367192737873506437507397738491312049
Short name T156
Test name
Test status
Simulation time 360562359 ps
CPU time 2.32 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:08 PM PST 23
Peak memory 210276 kb
Host smart-447929e0-da40-4384-b951-8ac901ae5df3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30474126944108506210646432507119678694826367192737873
506437507397738491312049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.30474126944108506210646432507119678
694826367192737873506437507397738491312049
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.88479559783713340851757605707870984541146357552508986589702320561679921374355
Short name T99
Test name
Test status
Simulation time 191438712 ps
CPU time 1.8 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 217444 kb
Host smart-c4ed3975-42ad-4996-90d8-927e1874fe54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884795
59783713340851757605707870984541146357552508986589702320561679921374355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.88479559783713340851757605707870984541146357552508986589702320561679921374355
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.18615349425781662988181523238360565430871467560074299123434403675137961132826
Short name T241
Test name
Test status
Simulation time 241456169 ps
CPU time 1.77 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:14 PM PST 23
Peak memory 208732 kb
Host smart-dfc32c9d-b0f0-4418-a8d6-2a58f4b5cdde
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18615349425781662988181523238360565430871467560074299123434
403675137961132826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.18615349425781662988181523238360565430871467560
074299123434403675137961132826
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.69390043855948202620511234931795630057691130371818171615001234054815687487521
Short name T118
Test name
Test status
Simulation time 66993279 ps
CPU time 1.32 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 210964 kb
Host smart-cd931828-d07f-4e7f-97ed-34a415598559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69390043855948202620511234931795630057691
130371818171615001234054815687487521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.693900438559482
02620511234931795630057691130371818171615001234054815687487521
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.78001687890098474893775502112404657978146102590288758070873008203135477925942
Short name T150
Test name
Test status
Simulation time 66993279 ps
CPU time 1.29 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 210984 kb
Host smart-e2ccf61d-d41f-4082-bce5-6d430fc3d728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78001687890098474893775502112404657978146102590288758070873008203135477925942
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_same_csr_outstanding.780016878900984748937755021124046579781461025902887580708
73008203135477925942
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.46200694964750313334843963927206184310273097874902035689835028610465857051138
Short name T261
Test name
Test status
Simulation time 219831342 ps
CPU time 3.34 seconds
Started Nov 22 12:32:49 PM PST 23
Finished Nov 22 12:33:00 PM PST 23
Peak memory 217284 kb
Host smart-c646d89c-5bcb-40eb-9527-a63f0318a9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46200694964750313334843963927206184310273097874902035689835028610465857051138 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.46200694964750313334843963927206184310273097874902035689835028610465857051138
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.52676315914933763372309978031313308010745501079144510020816595688324293203509
Short name T218
Test name
Test status
Simulation time 208277863 ps
CPU time 2.96 seconds
Started Nov 22 12:32:52 PM PST 23
Finished Nov 22 12:33:00 PM PST 23
Peak memory 217368 kb
Host smart-ee0d4aa1-a1a3-495f-ac18-54b0ce3aff9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52676315914933763372309978031313308010745501079144510020816595688324293203509 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_err.52676315914933763372309978031313308010745501079144510020816595688324293203509
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.16696984512750830032334951765235567916036838661142830181759655095375646242276
Short name T126
Test name
Test status
Simulation time 58636203 ps
CPU time 1.21 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 208264 kb
Host smart-8ee59ba4-958f-47ac-955f-f0c86f725388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696984512750830032334951765235567916036838661142830181759655095375646242276 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing.16696984512750830032334951765235567916036838661142830181759655095375646242276
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.72048131555944688315819194826897145714509881574403081408358202320473170074955
Short name T142
Test name
Test status
Simulation time 140599833 ps
CPU time 1.82 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:14 PM PST 23
Peak memory 208008 kb
Host smart-f39f12d1-948d-4f65-92b5-f61d353b9001
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72048131555944688315819194826897145714509881574403081408358202320473170074955 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash.72048131555944688315819194826897145714509881574403081408358202320473170074955
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.54239216135557883736924312012847453563559320723569895485067455056721826651672
Short name T130
Test name
Test status
Simulation time 33332834 ps
CPU time 0.99 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 210844 kb
Host smart-a3bfbcf4-810a-4969-827c-179c1444c256
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54239216135557883736924312012847453563559320723569895485067455056721826651672 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset.54239216135557883736924312012847453563559320723569895485067455056721826651672
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.76040512353763778832416147489604832111854660494951455175607164916327855402826
Short name T977
Test name
Test status
Simulation time 41172057 ps
CPU time 1.2 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217432 kb
Host smart-c7ccbae2-d7fc-4a6c-a68e-225177e97c52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7604051235376377883241614748960483211185466
0494951455175607164916327855402826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.7604051235376377
8832416147489604832111854660494951455175607164916327855402826
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.12739223252209390190580707443147431116559412153475885632095475363863373931819
Short name T153
Test name
Test status
Simulation time 24850759 ps
CPU time 0.83 seconds
Started Nov 22 12:33:05 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 208504 kb
Host smart-7b5342da-743c-47b0-8259-2afb35afea67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12739223252209390190580707443147431116559412153475885632095475363863373931819 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.12739223252209390190580707443147431116559412153475885632095475363863373931819
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.46937776171288034568896770847008895243318107467437375616155561224970675016606
Short name T240
Test name
Test status
Simulation time 197527949 ps
CPU time 1.64 seconds
Started Nov 22 12:32:58 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 207320 kb
Host smart-dfa22e0a-09c0-42f1-8755-c74aca077493
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469377761712880345688967708470088952433181074674373
75616155561224970675016606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.46937776171288034568896770847008895
243318107467437375616155561224970675016606
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.16766411307405916089093250924850292267665486879083539599559477938495495279301
Short name T246
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.44 seconds
Started Nov 22 12:33:11 PM PST 23
Finished Nov 22 12:33:23 PM PST 23
Peak memory 208052 kb
Host smart-41a7eeb9-1870-4c44-85ba-8ec6cbad8dcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16766411307405916089093250924850292267665486879083539
599559477938495495279301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.16766411307405916089093250924850292
267665486879083539599559477938495495279301
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.51082117002471533513524396152893468008636718726761790189596901158688845700969
Short name T250
Test name
Test status
Simulation time 3460251847 ps
CPU time 15.73 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:20 PM PST 23
Peak memory 207960 kb
Host smart-32735023-2118-4e0f-804b-38874df40ea0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51082117002471533513524396152893468008636718726761790
189596901158688845700969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.51082117002471533513524396152893468
008636718726761790189596901158688845700969
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.9829804539235935900870815368764354962293624631056948753380901153276703308239
Short name T225
Test name
Test status
Simulation time 360562359 ps
CPU time 2.23 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 210328 kb
Host smart-96461cfd-578b-41ca-9fa4-9dc33b904bf5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98298045392359359008708153687643549622936246310569487
53380901153276703308239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.982980453923593590087081536876435496
2293624631056948753380901153276703308239
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.17252621783537062329387925468896885722962330326654238093397808915703671456837
Short name T234
Test name
Test status
Simulation time 191438712 ps
CPU time 1.87 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217436 kb
Host smart-4da0738e-cbb1-4697-a171-2dc0911fa9c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172526
21783537062329387925468896885722962330326654238093397808915703671456837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.17252621783537062329387925468896885722962330326654238093397808915703671456837
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.55372198941864724285649143007805004221605455766463263316352737008257462132149
Short name T181
Test name
Test status
Simulation time 241456169 ps
CPU time 1.74 seconds
Started Nov 22 12:32:53 PM PST 23
Finished Nov 22 12:32:59 PM PST 23
Peak memory 208760 kb
Host smart-fc8edd0f-994f-4f84-ae76-c601f31b0952
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55372198941864724285649143007805004221605455766463263316352
737008257462132149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.55372198941864724285649143007805004221605455766
463263316352737008257462132149
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.11614009350342435832263757940575258647652495283298575124205755636689345520019
Short name T134
Test name
Test status
Simulation time 66993279 ps
CPU time 1.27 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 210984 kb
Host smart-75fd43fb-e32c-4047-89dc-a16fcc2bb900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11614009350342435832263757940575258647652
495283298575124205755636689345520019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.116140093503424
35832263757940575258647652495283298575124205755636689345520019
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.86900656628649066337295990321864922689859384806255264147301882535852519381952
Short name T135
Test name
Test status
Simulation time 66993279 ps
CPU time 1.29 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 210948 kb
Host smart-b3558825-90a2-4680-90ba-936214f549c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86900656628649066337295990321864922689859384806255264147301882535852519381952
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_same_csr_outstanding.869006566286490663372959903218649226898593848062552641473
01882535852519381952
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.8222255085577506521139538213455678516342211596407327184740617630171149364982
Short name T197
Test name
Test status
Simulation time 219831342 ps
CPU time 3.31 seconds
Started Nov 22 12:32:59 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217272 kb
Host smart-6d207e66-2ac2-431e-9869-70a3d3e3f7c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8222255085577506521139538213455678516342211596407327184740617630171149364982 -assert nopostproc +UV
M_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.8222255085577506521139538213455678516342211596407327184740617630171149364982
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.14051216981437889498371381138356319357399905805757153769866439620020478753537
Short name T229
Test name
Test status
Simulation time 208277863 ps
CPU time 2.81 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 217368 kb
Host smart-2f6ebb03-9323-429f-965d-7c82fcf9e114
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14051216981437889498371381138356319357399905805757153769866439620020478753537 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_err.14051216981437889498371381138356319357399905805757153769866439620020478753537
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.97398336208847055417376822467397758309029131101659029081770090896062569333111
Short name T128
Test name
Test status
Simulation time 58636203 ps
CPU time 1.25 seconds
Started Nov 22 12:33:04 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 207896 kb
Host smart-0091a3c0-5f4e-47cf-b795-40a17f62bec5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97398336208847055417376822467397758309029131101659029081770090896062569333111 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing.97398336208847055417376822467397758309029131101659029081770090896062569333111
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.56107988966567609848111060348189697291595333101140751661625616841255155484348
Short name T251
Test name
Test status
Simulation time 140599833 ps
CPU time 1.74 seconds
Started Nov 22 12:33:05 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 207948 kb
Host smart-bdd4603a-1b71-4f8e-baca-631132a0fb01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56107988966567609848111060348189697291595333101140751661625616841255155484348 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash.56107988966567609848111060348189697291595333101140751661625616841255155484348
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.86814867605795657317296062446958955013568982991960260368352729073825802193885
Short name T238
Test name
Test status
Simulation time 41172057 ps
CPU time 1.21 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 217412 kb
Host smart-fd439c39-4c98-4434-8df6-4b3f18ea9aa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8681486760579565731729606244695895501356898
2991960260368352729073825802193885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.8681486760579565
7317296062446958955013568982991960260368352729073825802193885
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.35613307413308089768864364544286804325814467551315268544630622935542649342620
Short name T264
Test name
Test status
Simulation time 24850759 ps
CPU time 0.89 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 208528 kb
Host smart-8237cc31-692b-4b84-a7d4-87513a853ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35613307413308089768864364544286804325814467551315268544630622935542649342620 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.35613307413308089768864364544286804325814467551315268544630622935542649342620
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.32372577852463893824726693111168565000946677459180412386429508520954063195123
Short name T166
Test name
Test status
Simulation time 197527949 ps
CPU time 1.55 seconds
Started Nov 22 12:33:05 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 207344 kb
Host smart-52a485e2-eae0-4f42-9746-bf98d3a1bcaa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323725778524638938247266931111685650009466774591804
12386429508520954063195123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.32372577852463893824726693111168565
000946677459180412386429508520954063195123
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.75051703161510168356383949658424807087000349716605731482828335117316658396020
Short name T169
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.53 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:21 PM PST 23
Peak memory 207908 kb
Host smart-d257feaf-0064-46a7-be35-f5713370f79d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75051703161510168356383949658424807087000349716605731
482828335117316658396020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.75051703161510168356383949658424807
087000349716605731482828335117316658396020
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.18071578371383836603603944241682444569563671249008376214152086528173692063426
Short name T213
Test name
Test status
Simulation time 3460251847 ps
CPU time 15.03 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:25 PM PST 23
Peak memory 207960 kb
Host smart-098412a2-3a6c-4ec7-814a-64b3f447f3de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18071578371383836603603944241682444569563671249008376
214152086528173692063426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.18071578371383836603603944241682444
569563671249008376214152086528173692063426
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.54609444209015977147036967317845475540872529119142255510540456046752043809494
Short name T210
Test name
Test status
Simulation time 360562359 ps
CPU time 2.18 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 210312 kb
Host smart-fc933d19-f945-4601-b221-330881a4d16b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54609444209015977147036967317845475540872529119142255
510540456046752043809494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.54609444209015977147036967317845475
540872529119142255510540456046752043809494
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1359860279350725264112618168881355251841461604236486951647758582168175802487
Short name T196
Test name
Test status
Simulation time 191438712 ps
CPU time 1.9 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217400 kb
Host smart-18e3d82a-8dcc-4592-9881-e8e0708cbb2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135986
0279350725264112618168881355251841461604236486951647758582168175802487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_cs
r_mem_rw_with_rand_reset.1359860279350725264112618168881355251841461604236486951647758582168175802487
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.101258309673239098837884916172433047391958738674728841361542690012609010304287
Short name T258
Test name
Test status
Simulation time 241456169 ps
CPU time 1.66 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 208772 kb
Host smart-c95407b4-c058-4239-8f1a-8eaedab21ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10125830967323909883788491617243304739195873867472884136154
2690012609010304287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.1012583096732390988378849161724330473919587386
74728841361542690012609010304287
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.23289074423208710333224752416844074733457826162958083396427221980704703073684
Short name T245
Test name
Test status
Simulation time 66993279 ps
CPU time 1.29 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:13 PM PST 23
Peak memory 211000 kb
Host smart-b99f6f91-b94a-4ae1-b5b0-e28c9f4439ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23289074423208710333224752416844074733457
826162958083396427221980704703073684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.232890744232087
10333224752416844074733457826162958083396427221980704703073684
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.112469788786199892947300249689488663266578971717996755440378032668537077417197
Short name T171
Test name
Test status
Simulation time 66993279 ps
CPU time 1.28 seconds
Started Nov 22 12:33:04 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 210924 kb
Host smart-db3318cc-9a66-4ca2-afb8-8bdad584e63e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112469788786199892947300249689488663266578971717996755440378032668537077417197
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_same_csr_outstanding.11246978878619989294730024968948866326657897171799675544
0378032668537077417197
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.96243207227018934075003655781065605415011845914473478211293254845003986334898
Short name T107
Test name
Test status
Simulation time 219831342 ps
CPU time 3.3 seconds
Started Nov 22 12:33:07 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 217272 kb
Host smart-ecfed397-4bcc-4251-b17c-93dc378361ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96243207227018934075003655781065605415011845914473478211293254845003986334898 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.96243207227018934075003655781065605415011845914473478211293254845003986334898
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.40793535307473479914184206903005478606436469497373858062279158801736072639921
Short name T80
Test name
Test status
Simulation time 208277863 ps
CPU time 2.75 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 217348 kb
Host smart-160028df-5e76-4341-ad59-5ef4d6e24087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793535307473479914184206903005478606436469497373858062279158801736072639921 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_err.40793535307473479914184206903005478606436469497373858062279158801736072639921
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.8841146846238396976982235305142562500676310481501391658221068184766215223497
Short name T177
Test name
Test status
Simulation time 41172057 ps
CPU time 1.26 seconds
Started Nov 22 12:33:16 PM PST 23
Finished Nov 22 12:33:19 PM PST 23
Peak memory 215540 kb
Host smart-59f7cf75-32f6-4308-a77b-afd35514b4c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8841146846238396976982235305142562500676310
481501391658221068184766215223497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.88411468462383969
76982235305142562500676310481501391658221068184766215223497
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.67299125829071186015261126912721539239984096813980018713617944599362051690537
Short name T189
Test name
Test status
Simulation time 24850759 ps
CPU time 0.87 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:08 PM PST 23
Peak memory 208528 kb
Host smart-5db5f6ff-5f09-4986-a645-082b6319c3c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67299125829071186015261126912721539239984096813980018713617944599362051690537 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.67299125829071186015261126912721539239984096813980018713617944599362051690537
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.112733775206534276258480993882024040180619053132481021456423970746966721340423
Short name T100
Test name
Test status
Simulation time 197527949 ps
CPU time 1.58 seconds
Started Nov 22 12:33:16 PM PST 23
Finished Nov 22 12:33:20 PM PST 23
Peak memory 205448 kb
Host smart-bc14a4ed-d848-4a05-921e-c115d36addca
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112733775206534276258480993882024040180619053132481
021456423970746966721340423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1127337752065342762584809938820240
40180619053132481021456423970746966721340423
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.75521684947862874492426927123433375765301384303038709426176962585811063267541
Short name T159
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.35 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:14 PM PST 23
Peak memory 207916 kb
Host smart-1f0692f4-3232-46a7-bb7a-596a58312bf3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75521684947862874492426927123433375765301384303038709
426176962585811063267541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.75521684947862874492426927123433375
765301384303038709426176962585811063267541
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.78813920100907907305155735304407317256130978603914926075126180854155941927421
Short name T184
Test name
Test status
Simulation time 3460251847 ps
CPU time 14.87 seconds
Started Nov 22 12:33:16 PM PST 23
Finished Nov 22 12:33:33 PM PST 23
Peak memory 206116 kb
Host smart-66fa5ff5-5ca6-41c3-bd91-59c7e1e221ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78813920100907907305155735304407317256130978603914926
075126180854155941927421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.78813920100907907305155735304407317
256130978603914926075126180854155941927421
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.46208879560406366533460323376147018585311386289615747529336097623047044221819
Short name T106
Test name
Test status
Simulation time 191438712 ps
CPU time 1.83 seconds
Started Nov 22 12:33:13 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 217436 kb
Host smart-bbfdca8e-915f-42dc-beb8-cf10369c727e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462088
79560406366533460323376147018585311386289615747529336097623047044221819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.46208879560406366533460323376147018585311386289615747529336097623047044221819
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.5463135432598599474422533374007736495870541512745967959526151858640896441329
Short name T179
Test name
Test status
Simulation time 241456169 ps
CPU time 1.7 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 208756 kb
Host smart-efb308cc-4960-4125-8a41-f842e0095614
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54631354325985994744225333740077364958705415127459679595261
51858640896441329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.546313543259859947442253337400773649587054151274
5967959526151858640896441329
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.19232237590941478194864917808906184946244420085429212861433877476010917018351
Short name T190
Test name
Test status
Simulation time 66993279 ps
CPU time 1.32 seconds
Started Nov 22 12:33:13 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 210972 kb
Host smart-c90df392-2446-4815-9df8-13b16b08f8fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19232237590941478194864917808906184946244
420085429212861433877476010917018351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.192322375909414
78194864917808906184946244420085429212861433877476010917018351
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1867527112614205243184217455735231239815704629874018794941525077066461794255
Short name T201
Test name
Test status
Simulation time 66993279 ps
CPU time 1.38 seconds
Started Nov 22 12:32:57 PM PST 23
Finished Nov 22 12:33:04 PM PST 23
Peak memory 210948 kb
Host smart-1738ffb9-9c0d-4c04-bcad-87c8022cec61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867527112614205243184217455735231239815704629874018794941525077066461794255 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_same_csr_outstanding.1867527112614205243184217455735231239815704629874018794941
525077066461794255
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.54549870547319106955082171186571699762417643253175095711231637171794250437991
Short name T207
Test name
Test status
Simulation time 219831342 ps
CPU time 3.18 seconds
Started Nov 22 12:33:11 PM PST 23
Finished Nov 22 12:33:18 PM PST 23
Peak memory 217260 kb
Host smart-2c3f58b3-80f6-4db7-82ae-8692d2666cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54549870547319106955082171186571699762417643253175095711231637171794250437991 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.54549870547319106955082171186571699762417643253175095711231637171794250437991
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.46260847117038879672013576919029688069605571773021673839255934079810884278882
Short name T212
Test name
Test status
Simulation time 208277863 ps
CPU time 2.78 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 217376 kb
Host smart-600383c8-1692-4cb5-abce-49edd557caa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46260847117038879672013576919029688069605571773021673839255934079810884278882 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_err.46260847117038879672013576919029688069605571773021673839255934079810884278882
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.33674711785782099517532651867315121147505118870076489717906529040675827908549
Short name T146
Test name
Test status
Simulation time 41172057 ps
CPU time 1.25 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217408 kb
Host smart-262d0c6a-b918-414a-8622-680a9a5b4251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367471178578209951753265186731512114750511
8870076489717906529040675827908549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3367471178578209
9517532651867315121147505118870076489717906529040675827908549
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.47483334098513390368156420401471146903024343903587273036317384960968581862759
Short name T125
Test name
Test status
Simulation time 24850759 ps
CPU time 0.87 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 208440 kb
Host smart-b0e5ac0f-b366-4b3a-a354-1bb1f392467b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47483334098513390368156420401471146903024343903587273036317384960968581862759 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.47483334098513390368156420401471146903024343903587273036317384960968581862759
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.56540894995996026701791910611699816152185512640782345477969148864628364655346
Short name T164
Test name
Test status
Simulation time 197527949 ps
CPU time 1.6 seconds
Started Nov 22 12:32:57 PM PST 23
Finished Nov 22 12:33:04 PM PST 23
Peak memory 207284 kb
Host smart-55cf2bf3-1fd8-4ffe-ba47-1a1c5dd25933
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565408949959960267017919106116998161521855126407823
45477969148864628364655346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.56540894995996026701791910611699816
152185512640782345477969148864628364655346
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.466904210435340541314779166375476500397416124403957977101689898367172002594
Short name T194
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.31 seconds
Started Nov 22 12:33:11 PM PST 23
Finished Nov 22 12:33:23 PM PST 23
Peak memory 207960 kb
Host smart-1452291a-0caf-4024-97a9-9579e9506c4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46690421043534054131477916637547650039741612440395797
7101689898367172002594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4669042104353405413147791663754765003
97416124403957977101689898367172002594
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.99335770565367820973979065006066902778980632793120739252492487020324372461939
Short name T102
Test name
Test status
Simulation time 3460251847 ps
CPU time 15.31 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:19 PM PST 23
Peak memory 207968 kb
Host smart-a5402b21-28f2-40e7-9ea7-4b1e717fa785
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99335770565367820973979065006066902778980632793120739
252492487020324372461939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.99335770565367820973979065006066902
778980632793120739252492487020324372461939
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.47975488496616062320137178112066532161018110732409712843630120128612473408542
Short name T217
Test name
Test status
Simulation time 360562359 ps
CPU time 2.2 seconds
Started Nov 22 12:32:58 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 210300 kb
Host smart-8b8563d3-62ae-4131-a840-ed763755d9be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47975488496616062320137178112066532161018110732409712
843630120128612473408542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.47975488496616062320137178112066532
161018110732409712843630120128612473408542
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.50476617482002279349133016726681257891480938886596245201225438731749056887511
Short name T253
Test name
Test status
Simulation time 191438712 ps
CPU time 1.86 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:08 PM PST 23
Peak memory 217528 kb
Host smart-40583512-099a-4d0d-8e09-f6af01cdeaa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504766
17482002279349133016726681257891480938886596245201225438731749056887511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.50476617482002279349133016726681257891480938886596245201225438731749056887511
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.86049430855968165529642726423128956224596681883851042266067968138485224573690
Short name T223
Test name
Test status
Simulation time 241456169 ps
CPU time 1.68 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 208784 kb
Host smart-0aedade7-bdba-4698-b50b-92ebbcb10dd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86049430855968165529642726423128956224596681883851042266067
968138485224573690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.86049430855968165529642726423128956224596681883
851042266067968138485224573690
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.86626626038293808395326772955526671073124423727240701384370159367067644995019
Short name T170
Test name
Test status
Simulation time 66993279 ps
CPU time 1.31 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 210988 kb
Host smart-bf749c3b-d794-437a-bb25-5bebdfe6ee3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86626626038293808395326772955526671073124
423727240701384370159367067644995019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.866266260382938
08395326772955526671073124423727240701384370159367067644995019
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.93984833030986996080315569659095830128255080660931901126352133768017376866377
Short name T154
Test name
Test status
Simulation time 66993279 ps
CPU time 1.33 seconds
Started Nov 22 12:32:58 PM PST 23
Finished Nov 22 12:33:04 PM PST 23
Peak memory 210936 kb
Host smart-a52b93d4-a5ff-4284-842f-baf88bcf2287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93984833030986996080315569659095830128255080660931901126352133768017376866377
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_same_csr_outstanding.939848330309869960803155696590958301282550806609319011263
52133768017376866377
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.33461747688456170758129938345505347961605516632093597905952141268896032266252
Short name T232
Test name
Test status
Simulation time 219831342 ps
CPU time 3.36 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 216688 kb
Host smart-fe9bd832-5347-461e-86f8-ef7882030bac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461747688456170758129938345505347961605516632093597905952141268896032266252 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.33461747688456170758129938345505347961605516632093597905952141268896032266252
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.22860630374029013256334333652683348764485556323777798572807400884865612725114
Short name T205
Test name
Test status
Simulation time 208277863 ps
CPU time 2.72 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:09 PM PST 23
Peak memory 217384 kb
Host smart-19069722-99a9-4acf-b18f-972de9c07487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22860630374029013256334333652683348764485556323777798572807400884865612725114 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_err.22860630374029013256334333652683348764485556323777798572807400884865612725114
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.30467135679735767563991927995058695982934806647986501781360898502689992712797
Short name T149
Test name
Test status
Simulation time 41172057 ps
CPU time 1.21 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:13 PM PST 23
Peak memory 217408 kb
Host smart-9eeed152-be63-472f-ab9e-5b0e2b7ba1e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046713567973576756399192799505869598293480
6647986501781360898502689992712797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3046713567973576
7563991927995058695982934806647986501781360898502689992712797
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.88889892501687811271046781269904625507074232598007972214208029492851762065661
Short name T119
Test name
Test status
Simulation time 24850759 ps
CPU time 0.86 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 208228 kb
Host smart-37d5de21-da8a-42cb-809e-753a0ced4aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88889892501687811271046781269904625507074232598007972214208029492851762065661 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.88889892501687811271046781269904625507074232598007972214208029492851762065661
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.114635720028576398599523550543223181749221327918880610504615373773664718556113
Short name T220
Test name
Test status
Simulation time 197527949 ps
CPU time 1.55 seconds
Started Nov 22 12:33:04 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 207324 kb
Host smart-821319b9-3bda-44d0-91e1-9efa3426593d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114635720028576398599523550543223181749221327918880
610504615373773664718556113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1146357200285763985995235505432231
81749221327918880610504615373773664718556113
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.69198659068404105509471447321351743886778343811149956501923739773568827705422
Short name T235
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.29 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:18 PM PST 23
Peak memory 207864 kb
Host smart-cc923b1a-e930-4ded-86a9-1678d8b17732
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69198659068404105509471447321351743886778343811149956
501923739773568827705422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.69198659068404105509471447321351743
886778343811149956501923739773568827705422
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.66327557947478189852549398825468496238129805150101968111819541115447237426381
Short name T178
Test name
Test status
Simulation time 3460251847 ps
CPU time 15.73 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:20 PM PST 23
Peak memory 207948 kb
Host smart-7c045839-88f0-4982-a51e-94f918faab49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66327557947478189852549398825468496238129805150101968
111819541115447237426381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.66327557947478189852549398825468496
238129805150101968111819541115447237426381
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.111018813826561822073685519759938804691372903501515119064189885679251273624023
Short name T155
Test name
Test status
Simulation time 360562359 ps
CPU time 2.41 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:09 PM PST 23
Peak memory 210268 kb
Host smart-cd602f55-2967-4821-a879-20f719581449
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101881382656182207368551975993880469137290350151511
9064189885679251273624023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1110188138265618220736855197599388
04691372903501515119064189885679251273624023
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.79297221727088397686181025381840675960421137232933743159120320713185455932137
Short name T183
Test name
Test status
Simulation time 191438712 ps
CPU time 1.89 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217436 kb
Host smart-a9e30af2-8604-42c6-b1e8-5a74665cee9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792972
21727088397686181025381840675960421137232933743159120320713185455932137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.79297221727088397686181025381840675960421137232933743159120320713185455932137
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.65374654659189260646259480608885260721058880354658120751839436932048804447633
Short name T168
Test name
Test status
Simulation time 241456169 ps
CPU time 1.72 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 208720 kb
Host smart-b3a2fcb6-6784-4485-b24a-73b67d070c9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65374654659189260646259480608885260721058880354658120751839
436932048804447633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.65374654659189260646259480608885260721058880354
658120751839436932048804447633
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.38178985204746555368861910777191657920205719885617514408362478929077119472769
Short name T172
Test name
Test status
Simulation time 66993279 ps
CPU time 1.31 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:09 PM PST 23
Peak memory 210968 kb
Host smart-da2f5410-656d-499a-8ee8-90406c21999b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38178985204746555368861910777191657920205
719885617514408362478929077119472769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.381789852047465
55368861910777191657920205719885617514408362478929077119472769
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.84697601135515573934596366397835620875613201500773558640163810084496968567803
Short name T173
Test name
Test status
Simulation time 66993279 ps
CPU time 1.4 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 210944 kb
Host smart-54290652-aac8-483c-b83e-2b3ba8d00156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84697601135515573934596366397835620875613201500773558640163810084496968567803
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_same_csr_outstanding.846976011355155739345963663978356208756132015007735586401
63810084496968567803
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.114086009307253270678873208679928115418778632389099350083636832907436816399306
Short name T195
Test name
Test status
Simulation time 219831342 ps
CPU time 3.28 seconds
Started Nov 22 12:33:03 PM PST 23
Finished Nov 22 12:33:11 PM PST 23
Peak memory 217280 kb
Host smart-ea3c56f7-c291-4c89-80cf-1fc13c37a2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114086009307253270678873208679928115418778632389099350083636832907436816399306 -assert nopostproc +
UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.114086009307253270678873208679928115418778632389099350083636832907436816399306
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.45080524352381596332622298480073313217359445341031237509937212527549906797850
Short name T233
Test name
Test status
Simulation time 208277863 ps
CPU time 2.8 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:08 PM PST 23
Peak memory 217348 kb
Host smart-a0f0919d-791b-4fbc-87fc-779b2f7c1f67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45080524352381596332622298480073313217359445341031237509937212527549906797850 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_err.45080524352381596332622298480073313217359445341031237509937212527549906797850
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.12597556916241669134555035238264843377416477075678977500345737442247885421689
Short name T214
Test name
Test status
Simulation time 41172057 ps
CPU time 1.19 seconds
Started Nov 22 12:33:08 PM PST 23
Finished Nov 22 12:33:13 PM PST 23
Peak memory 217392 kb
Host smart-8b114428-d0a0-4f4e-8560-6ae6974c199d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259755691624166913455503523826484337741647
7075678977500345737442247885421689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1259755691624166
9134555035238264843377416477075678977500345737442247885421689
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.96009567981560044104952545179198199004265001279989035370275320184372796558249
Short name T152
Test name
Test status
Simulation time 24850759 ps
CPU time 0.85 seconds
Started Nov 22 12:33:07 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 208420 kb
Host smart-9f51ebbf-70a2-4bf5-88cc-b2c96d5a9aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96009567981560044104952545179198199004265001279989035370275320184372796558249 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.96009567981560044104952545179198199004265001279989035370275320184372796558249
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.43309688497226276760913666622165641245758106375302723450370145581498079989921
Short name T74
Test name
Test status
Simulation time 197527949 ps
CPU time 1.59 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:08 PM PST 23
Peak memory 207264 kb
Host smart-0e028d0d-f6db-4e8d-b8a1-666d51584768
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433096884972262767609136666221656412457581063753027
23450370145581498079989921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.43309688497226276760913666622165641
245758106375302723450370145581498079989921
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.96278279999274371477553373405353595287757379966294916779304374957935139984982
Short name T262
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.22 seconds
Started Nov 22 12:33:11 PM PST 23
Finished Nov 22 12:33:23 PM PST 23
Peak memory 207992 kb
Host smart-6a182767-0caf-4b2c-ab73-7d61bd6b7ea7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96278279999274371477553373405353595287757379966294916
779304374957935139984982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.96278279999274371477553373405353595
287757379966294916779304374957935139984982
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.10052038011943551477867675871116884235082812363481689000114176873318106743727
Short name T105
Test name
Test status
Simulation time 3460251847 ps
CPU time 14.98 seconds
Started Nov 22 12:33:08 PM PST 23
Finished Nov 22 12:33:27 PM PST 23
Peak memory 207988 kb
Host smart-90bd4b61-dcb1-4fec-b0ee-d2e98fc2be57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10052038011943551477867675871116884235082812363481689
000114176873318106743727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.10052038011943551477867675871116884
235082812363481689000114176873318106743727
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.70842541600217961871071052713512137303682388531596146580501512616004905719118
Short name T192
Test name
Test status
Simulation time 360562359 ps
CPU time 2.28 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 210272 kb
Host smart-68ad21a0-1798-4f04-94d9-ce32c5be4623
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70842541600217961871071052713512137303682388531596146
580501512616004905719118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.70842541600217961871071052713512137
303682388531596146580501512616004905719118
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1771048145097610067581207997767249651220798505778638814818817978385410094771
Short name T204
Test name
Test status
Simulation time 191438712 ps
CPU time 1.72 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217452 kb
Host smart-3cf1b0c6-fce8-49ad-aec1-335c49d8468b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177104
8145097610067581207997767249651220798505778638814818817978385410094771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_cs
r_mem_rw_with_rand_reset.1771048145097610067581207997767249651220798505778638814818817978385410094771
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.15326191825796678357764955445881846508925325664464043929097113785873937076564
Short name T230
Test name
Test status
Simulation time 241456169 ps
CPU time 1.76 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 208572 kb
Host smart-ce0c3001-ce2b-4200-9fbb-f26bb8f23a4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15326191825796678357764955445881846508925325664464043929097
113785873937076564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.15326191825796678357764955445881846508925325664
464043929097113785873937076564
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.88202634999689032325343783616887870682950260758639620557426309501987093491212
Short name T259
Test name
Test status
Simulation time 66993279 ps
CPU time 1.3 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 210916 kb
Host smart-017318a6-c3bf-4c73-93ec-0e798fa8dac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88202634999689032325343783616887870682950
260758639620557426309501987093491212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.882026349996890
32325343783616887870682950260758639620557426309501987093491212
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.14154898411790156787353427346279018391370113603864515279115707992719570674416
Short name T151
Test name
Test status
Simulation time 66993279 ps
CPU time 1.33 seconds
Started Nov 22 12:33:05 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 210940 kb
Host smart-48734391-c6dc-4616-93e3-3dc454e31a41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154898411790156787353427346279018391370113603864515279115707992719570674416
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_same_csr_outstanding.141548984117901567873534273462790183913701136038645152791
15707992719570674416
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.50309241460251429452856670612811302712328251867055763442278968275836204012566
Short name T109
Test name
Test status
Simulation time 219831342 ps
CPU time 3.32 seconds
Started Nov 22 12:33:07 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 217280 kb
Host smart-6882c3de-d807-4162-a21c-fe9409915862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50309241460251429452856670612811302712328251867055763442278968275836204012566 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.50309241460251429452856670612811302712328251867055763442278968275836204012566
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.20735603795453707013799290717315741626831641867237338859037607909442663801159
Short name T208
Test name
Test status
Simulation time 208277863 ps
CPU time 2.83 seconds
Started Nov 22 12:33:04 PM PST 23
Finished Nov 22 12:33:13 PM PST 23
Peak memory 217316 kb
Host smart-b23ccfc7-ab24-4a48-9a92-04a3a1c6cd40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735603795453707013799290717315741626831641867237338859037607909442663801159 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_err.20735603795453707013799290717315741626831641867237338859037607909442663801159
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.113445633127958460468947372893291862889637435987103685778836881632876775094166
Short name T256
Test name
Test status
Simulation time 41172057 ps
CPU time 1.2 seconds
Started Nov 22 12:33:13 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 217404 kb
Host smart-adee4e2f-776e-49fb-99be-18394e6ef91f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134456331279584604689473728932918628896374
35987103685778836881632876775094166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.113445633127958
460468947372893291862889637435987103685778836881632876775094166
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.71990786308506562295553864032210779082876367351695972421270534318934985628700
Short name T176
Test name
Test status
Simulation time 24850759 ps
CPU time 0.86 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 208432 kb
Host smart-638c5530-5ac3-4ccd-bf41-06ddd760b350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71990786308506562295553864032210779082876367351695972421270534318934985628700 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.71990786308506562295553864032210779082876367351695972421270534318934985628700
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.104432047155443236294062383717002510147996412355693223165026847682798496747468
Short name T976
Test name
Test status
Simulation time 197527949 ps
CPU time 1.5 seconds
Started Nov 22 12:33:09 PM PST 23
Finished Nov 22 12:33:14 PM PST 23
Peak memory 207324 kb
Host smart-af2a6d13-f5bc-4677-9c05-e9ec25294153
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104432047155443236294062383717002510147996412355693
223165026847682798496747468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1044320471554432362940623837170025
10147996412355693223165026847682798496747468
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.55656585506477729456407237559991970393247714446435557019149802306270799101919
Short name T103
Test name
Test status
Simulation time 1837157689 ps
CPU time 8.53 seconds
Started Nov 22 12:33:04 PM PST 23
Finished Nov 22 12:33:18 PM PST 23
Peak memory 207600 kb
Host smart-c50f7cf2-837c-42e8-befe-f1f23e02ce74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55656585506477729456407237559991970393247714446435557
019149802306270799101919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.55656585506477729456407237559991970
393247714446435557019149802306270799101919
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.79191628151167010142124863741751273241464789286087900287882525331763641290987
Short name T167
Test name
Test status
Simulation time 3460251847 ps
CPU time 15.55 seconds
Started Nov 22 12:33:04 PM PST 23
Finished Nov 22 12:33:26 PM PST 23
Peak memory 207964 kb
Host smart-bfd3848a-ff32-49b5-b967-c5b0a4a1ae26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79191628151167010142124863741751273241464789286087900
287882525331763641290987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.79191628151167010142124863741751273
241464789286087900287882525331763641290987
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.61501670762857964761300312583429952661391571476697724689604613467061339033289
Short name T254
Test name
Test status
Simulation time 360562359 ps
CPU time 2.19 seconds
Started Nov 22 12:32:56 PM PST 23
Finished Nov 22 12:33:04 PM PST 23
Peak memory 210308 kb
Host smart-77e467b0-4aea-4d09-b054-8c44aadd57cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61501670762857964761300312583429952661391571476697724
689604613467061339033289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.61501670762857964761300312583429952
661391571476697724689604613467061339033289
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.54863470137411113458524047682187370283342298360421819471350138749844810438277
Short name T978
Test name
Test status
Simulation time 191438712 ps
CPU time 1.87 seconds
Started Nov 22 12:33:02 PM PST 23
Finished Nov 22 12:33:07 PM PST 23
Peak memory 217440 kb
Host smart-551f5dbe-4240-4b26-8a84-d280e85e21c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548634
70137411113458524047682187370283342298360421819471350138749844810438277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_c
sr_mem_rw_with_rand_reset.54863470137411113458524047682187370283342298360421819471350138749844810438277
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.67273440906367141885184845172874026525067683620444412290376523603010587411680
Short name T211
Test name
Test status
Simulation time 241456169 ps
CPU time 1.73 seconds
Started Nov 22 12:33:05 PM PST 23
Finished Nov 22 12:33:12 PM PST 23
Peak memory 208708 kb
Host smart-02f14639-8789-4595-8e24-d6a7e8fad901
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67273440906367141885184845172874026525067683620444412290376
523603010587411680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.67273440906367141885184845172874026525067683620
444412290376523603010587411680
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.38865807584266826608549939437092076455341693800479999806169957605732158711652
Short name T979
Test name
Test status
Simulation time 66993279 ps
CPU time 1.35 seconds
Started Nov 22 12:33:00 PM PST 23
Finished Nov 22 12:33:05 PM PST 23
Peak memory 210972 kb
Host smart-1e77c186-de1b-4a32-ae11-2e42d998210a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38865807584266826608549939437092076455341
693800479999806169957605732158711652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.388658075842668
26608549939437092076455341693800479999806169957605732158711652
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.86362409493708916238817983250761722742999975129205193279915444266981227196699
Short name T133
Test name
Test status
Simulation time 66993279 ps
CPU time 1.36 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:15 PM PST 23
Peak memory 210848 kb
Host smart-0b94cb1b-1055-4bff-99de-80c186b91750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86362409493708916238817983250761722742999975129205193279915444266981227196699
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_same_csr_outstanding.863624094937089162388179832507617227429999751292051932799
15444266981227196699
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.80603760118465971876195354709661643076614634092164483448134005313562076409615
Short name T111
Test name
Test status
Simulation time 219831342 ps
CPU time 3.26 seconds
Started Nov 22 12:33:13 PM PST 23
Finished Nov 22 12:33:19 PM PST 23
Peak memory 217268 kb
Host smart-51e1929b-f41f-453a-9fef-3d9b928db75d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80603760118465971876195354709661643076614634092164483448134005313562076409615 -assert nopostproc +U
VM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.80603760118465971876195354709661643076614634092164483448134005313562076409615
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.77885555237399559052812849051439594892232393572732818684225029303042857744173
Short name T187
Test name
Test status
Simulation time 208277863 ps
CPU time 2.86 seconds
Started Nov 22 12:33:10 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 217336 kb
Host smart-4572d4f5-0048-4a10-a111-7e0545ba96dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77885555237399559052812849051439594892232393572732818684225029303042857744173 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_err.77885555237399559052812849051439594892232393572732818684225029303042857744173
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.14073587540883714696292549431156207992957744271148658116413140454109777630363
Short name T639
Test name
Test status
Simulation time 42189906 ps
CPU time 0.96 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:49 PM PST 23
Peak memory 207752 kb
Host smart-c86352c4-daf8-4d5b-bc95-99d5d01a3920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073587540883714696292549431156207992957744271148658116413140454109777630363 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.14073587540883714696292549431156207992957744271148658116413140454109777630363
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.88386340176212325240200098242403030529196170862101483280359708971541915621470
Short name T362
Test name
Test status
Simulation time 19636515 ps
CPU time 0.77 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 207552 kb
Host smart-95f68f4a-9c4c-4006-a719-220b0f38a0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88386340176212325240200098242403030529196170862101483280359708971541915621470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.88386340176212325240200098242403030529196170862101483280359708971541915621470
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.67377315587611641424702551935233029258839633348466351194103669208190634315427
Short name T898
Test name
Test status
Simulation time 978628843 ps
CPU time 14.67 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:37:12 PM PST 23
Peak memory 217460 kb
Host smart-d8a43da5-2abc-4847-a361-7c3115aa7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67377315587611641424702551935233029258839633348466351194103669208190634315427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.lc_ctrl_errors.67377315587611641424702551935233029258839633348466351194103669208190634315427
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.31392109426392804880317862076599311302683441412559590778810334842342342931563
Short name T271
Test name
Test status
Simulation time 5872518263 ps
CPU time 40.62 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:37:34 PM PST 23
Peak memory 217724 kb
Host smart-2c65ae7b-5667-4fad-b2c9-2d06bc4b5d3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31392109426392804880317862076599311302683441412559590778810334842342342931563 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_errors.31392109426392804880317862076599311302683441412559590778810334842342342931563
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.81665157170827077347794429264453033525948917615926399528478453603383399906286
Short name T569
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.73 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:37:08 PM PST 23
Peak memory 217364 kb
Host smart-d4e48f93-c4d3-4f97-b7e6-241150f55ce7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81665157170827077347794429264453033525948917615926399528478453603383399906286 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.81665157170827077347794429264453033525948917615926399528478453603383399906286
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.102951331407789282387907532770038805913267801190265273431842084848260099299332
Short name T939
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.25 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 217440 kb
Host smart-482d0832-cda5-4d71-ab22-a1aa399e46dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102951331407789282387907532770038805913267801190265273431842084848260099299332 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_prog_failure.1029513314077892823879075327700388059132678011902652734318420848
48260099299332
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.63158276599145103841461422463097402282469727193127055595966642647468450578446
Short name T538
Test name
Test status
Simulation time 1406053995 ps
CPU time 9.97 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 212052 kb
Host smart-159c4b3f-e666-4fd3-a539-1abbf5bc244f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63158276599145103841461422463097402282469727193127055595966642647468450578446 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_regwen_during_op.631582765991451038414614224630974022824697271931270555959
66642647468450578446
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.83450721424751827329888795218905403225257081402815951980765590430795923712874
Short name T2
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.89 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 212912 kb
Host smart-9ca0d5e0-02fa-433d-af66-607bf6063088
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83450721424751827329888795218905403225257081402815951980765590430795923712874 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.83450721424751827329888795218905403225257081402815951980765590430795923712874
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.82836223726293813877102249254732600698938694305259497344098543757021888235517
Short name T883
Test name
Test status
Simulation time 5030489285 ps
CPU time 50.13 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:42 PM PST 23
Peak memory 269040 kb
Host smart-65599a8e-a67c-4fd9-abe9-ed75084ce80c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82836223726293813877102249254732600698938694305259497344098543757021888235517 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_state_failure.828362237262938138771022492547326006989386943052594973440985437
57021888235517
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1131786057724223559769330547895714093427258600989134457310856058520681954259
Short name T424
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.19 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:37:08 PM PST 23
Peak memory 246732 kb
Host smart-39c797d6-007b-4280-ae0f-c92a3c6123e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131786057724223559769330547895714093427258600989134457310856058520681954259 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_state_post_trans.1131786057724223559769330547895714093427258600989134457310
856058520681954259
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.93806352104989153530014487339213601673895829628540451275764412935246497590212
Short name T807
Test name
Test status
Simulation time 159313969 ps
CPU time 2.95 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 217476 kb
Host smart-380e4306-35c5-4374-a7e4-f6b18dd32a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93806352104989153530014487339213601673895829628540451275764412935246497590212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_prog_failure.93806352104989153530014487339213601673895829628540451275764412935246497590212
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.112061191027123047015695909061656462770260303836533664904035742613122589686877
Short name T338
Test name
Test status
Simulation time 420615450 ps
CPU time 5.68 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:06 PM PST 23
Peak memory 213348 kb
Host smart-14b6206e-55ec-4491-8193-f22dd15babab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112061191027123047015695909061656462770260303836533664904035742613122589686877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.lc_ctrl_regwen_during_op.112061191027123047015695909061656462770260303836533664904035742613122589686877
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.11599738863221905616865151886014952272359558023583981616707186052382477726730
Short name T350
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.09 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:08 PM PST 23
Peak memory 217304 kb
Host smart-9367042f-f717-4816-a318-d3dd6661b688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599738863221905616865151886014952272359558023583981616707186052382477726730 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_digest.11599738863221905616865151886014952272359558023583981616707186052382477726730
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.39015027135922925657464805982989779963758016662033848685950577657263651128341
Short name T493
Test name
Test status
Simulation time 964986095 ps
CPU time 10.89 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:37:06 PM PST 23
Peak memory 217416 kb
Host smart-bb7a682f-4a2b-4aba-9a9a-2bacd48411e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39015027135922925657464805982989779963758016662033848685950577657263651128341 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.39015027135922925657464805982989779963758016662033848685950577657263651128341
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.66652707013836652311255632330942045416202163364285700585412189032797296206857
Short name T456
Test name
Test status
Simulation time 625328098 ps
CPU time 8.41 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:37:07 PM PST 23
Peak memory 217456 kb
Host smart-97206506-73cc-435d-b949-acd0a785d84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66652707013836652311255632330942045416202163364285700585412189032797296206857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.lc_ctrl_security_escalation.66652707013836652311255632330942045416202163364285700585412189032797296206857
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.667973187724416358420442283093899676089234579114622273198438981532392987335
Short name T789
Test name
Test status
Simulation time 291295056 ps
CPU time 4.74 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 213764 kb
Host smart-8260acd6-e866-45c6-9bd9-ff36315c662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667973187724416358420442283093899676089234579114622273198438981532392987335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.lc_ctrl_smoke.667973187724416358420442283093899676089234579114622273198438981532392987335
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.43602051396820553413908551423701004118509561889373648588202027149636465826913
Short name T541
Test name
Test status
Simulation time 487150632 ps
CPU time 20.17 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:37:17 PM PST 23
Peak memory 250448 kb
Host smart-2b4bf7ce-65c9-4b7d-84c2-96f8adbe3aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43602051396820553413908551423701004118509561889373648588202027149636465826913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_state_failure.43602051396820553413908551423701004118509561889373648588202027149636465826913
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.31214373257847970721439743315881056622884226814154463572614364029448093855808
Short name T938
Test name
Test status
Simulation time 217117078 ps
CPU time 7.06 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:37:04 PM PST 23
Peak memory 246324 kb
Host smart-399ee695-0db3-465f-ad85-2450a4a8e119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31214373257847970721439743315881056622884226814154463572614364029448093855808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.lc_ctrl_state_post_trans.31214373257847970721439743315881056622884226814154463572614364029448093855808
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.25691737222802253392821334979153582781108987405939013008694126358031550650247
Short name T421
Test name
Test status
Simulation time 36820395678 ps
CPU time 286.59 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:41:34 PM PST 23
Peak memory 279652 kb
Host smart-75d9827c-cb4f-418e-85cb-b58ac5318175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256917372228022533928213349791535827811089874059390130086941263580
31550650247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.256917372228022533928213349791535827811089874059390130086
94126358031550650247
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.27457010178641420568383039023312872015861543628406230601936950911320170269975
Short name T717
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:56 PM PST 23
Peak memory 207624 kb
Host smart-3d7b70d6-0203-4033-a9bb-91a63d04fa71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457010178641420568383039023312872015861543628406230601936950911320170269975 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_volatile_unlock_smoke.274570101786414205683830390233128720158615436284062306
01936950911320170269975
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.14536263498533116204380446883438132942603348920021547851886872139610671528471
Short name T955
Test name
Test status
Simulation time 42189906 ps
CPU time 0.92 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:56 PM PST 23
Peak memory 207776 kb
Host smart-3097394a-b24b-4ebd-83d1-160f3e2b5ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536263498533116204380446883438132942603348920021547851886872139610671528471 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.14536263498533116204380446883438132942603348920021547851886872139610671528471
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.42230682947117001586091794100792981047994292649203804977565190835628949652130
Short name T483
Test name
Test status
Simulation time 19636515 ps
CPU time 0.79 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 207532 kb
Host smart-9b13a1f9-0e26-4bb6-846e-f1ac16b9e7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42230682947117001586091794100792981047994292649203804977565190835628949652130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.42230682947117001586091794100792981047994292649203804977565190835628949652130
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.92777411699889677992787965938160829191581453995782289354649010712953836007150
Short name T358
Test name
Test status
Simulation time 978628843 ps
CPU time 14.1 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:37:07 PM PST 23
Peak memory 217336 kb
Host smart-19114624-d3a5-4f44-8121-879984c8d63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92777411699889677992787965938160829191581453995782289354649010712953836007150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.lc_ctrl_errors.92777411699889677992787965938160829191581453995782289354649010712953836007150
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.56290240732886216508294638930528502248469046991411826008198627124567824762399
Short name T943
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.84 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 208920 kb
Host smart-9f65be34-d193-4b7c-b490-63bf20c0092f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56290240732886216508294638930528502248469046991411826008198627124567824762399 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.56290240732886216508294638930528502248469046991411826008198627124567824762399
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1221339050898832055223600288108256563699803818122985325216212072530788439672
Short name T531
Test name
Test status
Simulation time 5872518263 ps
CPU time 37.82 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:37:27 PM PST 23
Peak memory 217616 kb
Host smart-71365a21-4de7-4deb-9264-540c1c7ede03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221339050898832055223600288108256563699803818122985325216212072530788439672 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_errors.1221339050898832055223600288108256563699803818122985325216212072530788439672
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.87224340688536102152655313682406952322273236597830125340392350034308129048568
Short name T48
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.72 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:37:07 PM PST 23
Peak memory 217364 kb
Host smart-3046f850-2295-479c-8993-a8c2af504305
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87224340688536102152655313682406952322273236597830125340392350034308129048568 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.87224340688536102152655313682406952322273236597830125340392350034308129048568
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.26609802903758057705038451491620977430918305691071645478804753465915062167471
Short name T600
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.23 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 217392 kb
Host smart-19e357e0-356d-444c-a7df-64387d5dc140
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26609802903758057705038451491620977430918305691071645478804753465915062167471 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_prog_failure.26609802903758057705038451491620977430918305691071645478804753465915062167471
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.70909064428651531711057119551070057532874097588935172771581227600844134447358
Short name T41
Test name
Test status
Simulation time 1406053995 ps
CPU time 9.96 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:00 PM PST 23
Peak memory 212240 kb
Host smart-1a8ac56a-a9f3-43d2-9e1b-69f3d6f8df5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70909064428651531711057119551070057532874097588935172771581227600844134447358 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_regwen_during_op.709090644286515317110571195510700575328740975889351727715
81227600844134447358
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.88762532975648067239928374746832698854613968268698977743055816010184677678837
Short name T379
Test name
Test status
Simulation time 1348822310 ps
CPU time 9.05 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 212984 kb
Host smart-c1677e9d-1eb2-491c-924d-58b6fb335caa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88762532975648067239928374746832698854613968268698977743055816010184677678837 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.88762532975648067239928374746832698854613968268698977743055816010184677678837
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.83501969416736392850511038152023212501575191388784063917354531877215652960474
Short name T860
Test name
Test status
Simulation time 159313969 ps
CPU time 2.94 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:51 PM PST 23
Peak memory 217452 kb
Host smart-c10941a0-a70b-4183-8a53-d16a897e9f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83501969416736392850511038152023212501575191388784063917354531877215652960474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_prog_failure.83501969416736392850511038152023212501575191388784063917354531877215652960474
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.5192612925140452500589475975535735324050266428399861716730016971805130833886
Short name T670
Test name
Test status
Simulation time 420615450 ps
CPU time 5.67 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 213228 kb
Host smart-c222a56c-cbbc-48cb-b54a-d792dc155094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5192612925140452500589475975535735324050266428399861716730016971805130833886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.lc_ctrl_regwen_during_op.5192612925140452500589475975535735324050266428399861716730016971805130833886
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.36720846463577970337990239977738761128045194872827955992853498672490986342402
Short name T65
Test name
Test status
Simulation time 386472866 ps
CPU time 36.48 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:37:24 PM PST 23
Peak memory 273616 kb
Host smart-25430a07-288c-4104-8214-c1e1d49c4d0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36720846463577970337990239977738761128045194872827955992853498672490986342402 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.36720846463577970337990239977738761128045194872827955992853498672490986342402
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.114174916520044291806538006791212603990768804085235342713506861002099734346902
Short name T526
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.16 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:37:04 PM PST 23
Peak memory 218480 kb
Host smart-d614efb1-dc94-4dfc-bec4-fc00bc32a352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114174916520044291806538006791212603990768804085235342713506861002099734346902 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.114174916520044291806538006791212603990768804085235342713506861002099734346902
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.63834129257035875978838639730421842359965255333088533105559824992504654970527
Short name T852
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.5 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:37:10 PM PST 23
Peak memory 217372 kb
Host smart-d66c4d21-34f9-45a0-8039-94d36c22f2f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63834129257035875978838639730421842359965255333088533105559824992504654970527 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_digest.63834129257035875978838639730421842359965255333088533105559824992504654970527
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.33820102945426904383270136410444281139885970036371188730246907872031076681498
Short name T589
Test name
Test status
Simulation time 964986095 ps
CPU time 10.88 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 217440 kb
Host smart-e571da55-8de3-4b9b-bbac-367d3991ec43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33820102945426904383270136410444281139885970036371188730246907872031076681498 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.33820102945426904383270136410444281139885970036371188730246907872031076681498
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.99666044387611661648553832364025613730714639079655426967406716841815317728958
Short name T495
Test name
Test status
Simulation time 625328098 ps
CPU time 8.27 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 217388 kb
Host smart-b429d582-f54f-43ef-a023-6c4ccfa2347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99666044387611661648553832364025613730714639079655426967406716841815317728958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_security_escalation.99666044387611661648553832364025613730714639079655426967406716841815317728958
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.110266577483417897750525361121375818558361990833203967877431935468309595257135
Short name T654
Test name
Test status
Simulation time 291295056 ps
CPU time 4.57 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 213828 kb
Host smart-8bc4eec6-d715-4a58-ac98-8089b476b9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110266577483417897750525361121375818558361990833203967877431935468309595257135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_smoke.110266577483417897750525361121375818558361990833203967877431935468309595257135
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.17939716649000495743229235891689753184721404385647299698610007667107897385081
Short name T494
Test name
Test status
Simulation time 487150632 ps
CPU time 20.39 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:37:08 PM PST 23
Peak memory 250368 kb
Host smart-3d306faa-c142-4405-adee-6d1d902f6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17939716649000495743229235891689753184721404385647299698610007667107897385081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_state_failure.17939716649000495743229235891689753184721404385647299698610007667107897385081
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.81245508356079907663686072572579564518385540464046434501461711617371482792944
Short name T629
Test name
Test status
Simulation time 217117078 ps
CPU time 7.04 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 246220 kb
Host smart-8400a93b-906b-42a1-be07-a1ffe4d8e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81245508356079907663686072572579564518385540464046434501461711617371482792944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.lc_ctrl_state_post_trans.81245508356079907663686072572579564518385540464046434501461711617371482792944
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.72024355664579755551053575371260537614424918953174582406998532451205581127921
Short name T644
Test name
Test status
Simulation time 36820395678 ps
CPU time 286.78 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:41:38 PM PST 23
Peak memory 279468 kb
Host smart-2eca78e9-5746-47ea-b0ac-341f6ad7e087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720243556645797555510535753712605376144249189531745824069985324512
05581127921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.720243556645797555510535753712605376144249189531745824069
98532451205581127921
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.86774235033722462620454043232100097695018985883354365624043630991843009189361
Short name T752
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 207640 kb
Host smart-5c7bbdd9-0020-4969-8113-8c8acb4a0dab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86774235033722462620454043232100097695018985883354365624043630991843009189361 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_volatile_unlock_smoke.867742350337224626204540432321000976950189858833543656
24043630991843009189361
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.44705294340777475528826813226299252016189089166644012289177063573545272223943
Short name T444
Test name
Test status
Simulation time 42189906 ps
CPU time 1 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 207620 kb
Host smart-3bf4ab3f-85c6-4fc2-b098-d3095d0a9636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44705294340777475528826813226299252016189089166644012289177063573545272223943 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.44705294340777475528826813226299252016189089166644012289177063573545272223943
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.95448080308783760104696495085487890613868308972109742582398390905918409115875
Short name T837
Test name
Test status
Simulation time 978628843 ps
CPU time 13.31 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 217356 kb
Host smart-3ed8fa1a-a15b-4b00-a843-b8f832b72ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95448080308783760104696495085487890613868308972109742582398390905918409115875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.lc_ctrl_errors.95448080308783760104696495085487890613868308972109742582398390905918409115875
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.97496005410664759402925790216190415568653147879226610443197616766774902160813
Short name T613
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.3 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 209028 kb
Host smart-104461ca-1add-4c9b-a99f-ff65c81b0402
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97496005410664759402925790216190415568653147879226610443197616766774902160813 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.97496005410664759402925790216190415568653147879226610443197616766774902160813
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.51947412573476677791141478177933203417388767171013154610530017039723188451620
Short name T822
Test name
Test status
Simulation time 5872518263 ps
CPU time 39.47 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:44 PM PST 23
Peak memory 217784 kb
Host smart-9c77eb74-9a47-4bc2-b484-dbe2f5ab44c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51947412573476677791141478177933203417388767171013154610530017039723188451620 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_errors.51947412573476677791141478177933203417388767171013154610530017039723188451620
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.88385035379301272366562719433580414749109463062023174929368059301948563367462
Short name T948
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.42 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 217368 kb
Host smart-c7414fa7-1d34-444e-8e3f-4a7bb9abeef9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88385035379301272366562719433580414749109463062023174929368059301948563367462 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_prog_failure.8838503537930127236656271943358041474910946306202317492936805930
1948563367462
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.94225314328790413446629737846889749299171203706467693184920104635610039202957
Short name T447
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.88 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 212816 kb
Host smart-1fe5565b-b87c-49b0-ba79-9cdc437d252c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94225314328790413446629737846889749299171203706467693184920104635610039202957 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.94225314328790413446629737846889749299171203706467693184920104635610039202957
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.10884599965007532210953773609318938386331617932135526162172385663153650413042
Short name T293
Test name
Test status
Simulation time 5030489285 ps
CPU time 51.02 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:51 PM PST 23
Peak memory 269020 kb
Host smart-9d24aa4a-f2e9-4da3-9e16-c3bf1c673240
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884599965007532210953773609318938386331617932135526162172385663153650413042 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_state_failure.10884599965007532210953773609318938386331617932135526162172385
663153650413042
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.40136945232279439132491702185273369826658003119445547902265458174156861293188
Short name T485
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.19 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 246672 kb
Host smart-03b9181c-0efa-40c8-b73a-a745fc5e8d4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40136945232279439132491702185273369826658003119445547902265458174156861293188 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_state_post_trans.40136945232279439132491702185273369826658003119445547902
265458174156861293188
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.65544821763408396851183216474236257242221108795588505881845949531137325093641
Short name T332
Test name
Test status
Simulation time 159313969 ps
CPU time 2.98 seconds
Started Nov 22 01:37:43 PM PST 23
Finished Nov 22 01:37:48 PM PST 23
Peak memory 217448 kb
Host smart-56d4e1da-b645-48f8-b25f-c3bdffc164e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65544821763408396851183216474236257242221108795588505881845949531137325093641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.lc_ctrl_prog_failure.65544821763408396851183216474236257242221108795588505881845949531137325093641
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.50851972800811468877551054439032504944629631443804642818355986020294258612557
Short name T315
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.19 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 218500 kb
Host smart-2e54d10b-3e82-4a09-b6b0-00f13d825e55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50851972800811468877551054439032504944629631443804642818355986020294258612557 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.50851972800811468877551054439032504944629631443804642818355986020294258612557
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.80014724342022747891594311333384483190701266425654897374589604813077010272803
Short name T306
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.18 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 217380 kb
Host smart-98a6ecef-588c-4494-a1cb-c737b3196972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80014724342022747891594311333384483190701266425654897374589604813077010272803 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_digest.80014724342022747891594311333384483190701266425654897374589604813077010272803
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.101547432506112500764223997779945259117263625930374925668233412928559190557397
Short name T626
Test name
Test status
Simulation time 964986095 ps
CPU time 10.87 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 217312 kb
Host smart-c363e3b2-8dec-402e-9524-528a3053f773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101547432506112500764223997779945259117263625930374925668233412928559190557397 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.101547432506112500764223997779945259117263625930374925668233412928559190557397
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.75467654115109375168288606720084805570513221052563948724005562465277047919341
Short name T755
Test name
Test status
Simulation time 625328098 ps
CPU time 8.71 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 217492 kb
Host smart-e51f9e4e-45ab-49a2-8bfb-48c8fe6feb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75467654115109375168288606720084805570513221052563948724005562465277047919341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.lc_ctrl_security_escalation.75467654115109375168288606720084805570513221052563948724005562465277047919341
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.42262656722227387437988746689699515743553793695477770714407027918718063189504
Short name T3
Test name
Test status
Simulation time 291295056 ps
CPU time 4.47 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 213860 kb
Host smart-5673b17a-c13d-4639-8589-c550e1df28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42262656722227387437988746689699515743553793695477770714407027918718063189504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.lc_ctrl_smoke.42262656722227387437988746689699515743553793695477770714407027918718063189504
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.80368536750716583073053844434701386975808231153816872685351316763858559319175
Short name T300
Test name
Test status
Simulation time 487150632 ps
CPU time 20.39 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 250476 kb
Host smart-618633fd-8d19-4361-a23a-f56492061db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80368536750716583073053844434701386975808231153816872685351316763858559319175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.lc_ctrl_state_failure.80368536750716583073053844434701386975808231153816872685351316763858559319175
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.99916693336322330940726224447328665201228735513173428435936829380642947706680
Short name T747
Test name
Test status
Simulation time 217117078 ps
CPU time 7.05 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 246248 kb
Host smart-9fe98272-31dd-4408-b8b9-2ea169803fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99916693336322330940726224447328665201228735513173428435936829380642947706680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.lc_ctrl_state_post_trans.99916693336322330940726224447328665201228735513173428435936829380642947706680
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.19610774520667229370798041750808607624045547062746958193225612935764506512079
Short name T659
Test name
Test status
Simulation time 36820395678 ps
CPU time 287.7 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:42:48 PM PST 23
Peak memory 283460 kb
Host smart-681e257f-b277-4af5-b13d-0a9b4d759bb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196107745206672293707980417508086076240455470627469581932256129357
64506512079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.19610774520667229370798041750808607624045547062746958193
225612935764506512079
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.100378946491897510392425546875295150996592465959897916193698973051418544990042
Short name T742
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:00 PM PST 23
Peak memory 207620 kb
Host smart-3942841d-39ae-46f9-adbf-b76b56faf79f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100378946491897510392425546875295150996592465959897916193698973051418544990042 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_volatile_unlock_smoke.1003789464918975103924255468752951509965924659598979
16193698973051418544990042
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4921005374373871740836159768369299618349393297184245943092446895966628538345
Short name T471
Test name
Test status
Simulation time 42189906 ps
CPU time 0.94 seconds
Started Nov 22 01:37:51 PM PST 23
Finished Nov 22 01:37:57 PM PST 23
Peak memory 207656 kb
Host smart-4c8c0cf4-db81-421a-a242-b70a82947504
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4921005374373871740836159768369299618349393297184245943092446895966628538345 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4921005374373871740836159768369299618349393297184245943092446895966628538345
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.89404163678319528099527010389863360929540291772423634877634676579206245252096
Short name T375
Test name
Test status
Simulation time 978628843 ps
CPU time 13.19 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 217448 kb
Host smart-f8ec5555-e012-4426-8349-b636b5a1b407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89404163678319528099527010389863360929540291772423634877634676579206245252096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.lc_ctrl_errors.89404163678319528099527010389863360929540291772423634877634676579206245252096
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.106502213025826234900375820310998784627155836176758203165435558739395077657711
Short name T6
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.75 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 208988 kb
Host smart-213566d6-85e6-435a-a450-fc9ebe4f773a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106502213025826234900375820310998784627155836176758203165435558739395077657711 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.106502213025826234900375820310998784627155836176758203165435558739395077657711
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.31834407774024020692931063513087539859983957403404906274288814864705469835906
Short name T971
Test name
Test status
Simulation time 5872518263 ps
CPU time 42.27 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:58 PM PST 23
Peak memory 217708 kb
Host smart-e147f4e2-939e-4241-8464-ee128991404c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31834407774024020692931063513087539859983957403404906274288814864705469835906 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_errors.31834407774024020692931063513087539859983957403404906274288814864705469835906
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.99368501817066666965753481352981725738683933992214546013433412273746100694677
Short name T865
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.6 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 217436 kb
Host smart-bcd03cb8-83b3-4599-b954-a10e519e61cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99368501817066666965753481352981725738683933992214546013433412273746100694677 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_prog_failure.9936850181706666696575348135298172573868393399221454601343341227
3746100694677
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.78875478097634217519104336379830699669305241282683783641621430722424222463258
Short name T487
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.54 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 212696 kb
Host smart-af384f27-328e-45a4-8eee-f86b0a94c106
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78875478097634217519104336379830699669305241282683783641621430722424222463258 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.78875478097634217519104336379830699669305241282683783641621430722424222463258
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.23439617491301279582870116943096120498153436958857499834662102982478642672961
Short name T580
Test name
Test status
Simulation time 5030489285 ps
CPU time 49.92 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:39:05 PM PST 23
Peak memory 268996 kb
Host smart-ee082c4f-61b7-4073-a45f-13012ce8ddac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23439617491301279582870116943096120498153436958857499834662102982478642672961 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_state_failure.23439617491301279582870116943096120498153436958857499834662102
982478642672961
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.86863428125729406252572162997934346607472239771541749217811828421767919352613
Short name T598
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.6 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:27 PM PST 23
Peak memory 246704 kb
Host smart-42856cab-2b4f-4e95-9df2-9b3b3d7300e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86863428125729406252572162997934346607472239771541749217811828421767919352613 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_state_post_trans.86863428125729406252572162997934346607472239771541749217
811828421767919352613
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.102887390717753724803162406502222350103527854598578305780074168947944192065125
Short name T930
Test name
Test status
Simulation time 159313969 ps
CPU time 3.06 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 217356 kb
Host smart-229ca687-6282-477a-89ce-c53a118ed499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102887390717753724803162406502222350103527854598578305780074168947944192065125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.lc_ctrl_prog_failure.102887390717753724803162406502222350103527854598578305780074168947944192065125
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1845846567621223461556140293589604023920010497233705829002635027554730057341
Short name T845
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.48 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 218460 kb
Host smart-88384108-43dc-437e-af45-2b47f9f8fab1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845846567621223461556140293589604023920010497233705829002635027554730057341 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1845846567621223461556140293589604023920010497233705829002635027554730057341
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.77544202466795902326231889835728579549148457320522601184394776177410957799297
Short name T744
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.14 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 217416 kb
Host smart-681dc565-5036-437a-a686-b789bbd32eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77544202466795902326231889835728579549148457320522601184394776177410957799297 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_digest.77544202466795902326231889835728579549148457320522601184394776177410957799297
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.59879018220180989860991113307617238405444409012160561000314218337416312932316
Short name T810
Test name
Test status
Simulation time 964986095 ps
CPU time 10.8 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 217400 kb
Host smart-12c25707-d8ed-48f1-9359-f23a2e6ce3c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59879018220180989860991113307617238405444409012160561000314218337416312932316 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.59879018220180989860991113307617238405444409012160561000314218337416312932316
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.8739929159854620233391512231760795657270731845234277524252585692243513687252
Short name T653
Test name
Test status
Simulation time 625328098 ps
CPU time 8.98 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:22 PM PST 23
Peak memory 217480 kb
Host smart-3c44cb39-a10b-4fe0-b0ae-f373d3d5ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8739929159854620233391512231760795657270731845234277524252585692243513687252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.lc_ctrl_security_escalation.8739929159854620233391512231760795657270731845234277524252585692243513687252
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.59004980607594280501948325812930004878156732818533931314780580984658143177872
Short name T881
Test name
Test status
Simulation time 291295056 ps
CPU time 4.81 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 213708 kb
Host smart-b384f7f9-7cdc-4a14-bc28-f49498a4b94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59004980607594280501948325812930004878156732818533931314780580984658143177872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.lc_ctrl_smoke.59004980607594280501948325812930004878156732818533931314780580984658143177872
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.101804518272787255347880408126214641276025110400980411370313307649721788444629
Short name T298
Test name
Test status
Simulation time 487150632 ps
CPU time 21.46 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 250452 kb
Host smart-4bb4dbd0-d670-45d0-8dd4-97dcb2b96c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101804518272787255347880408126214641276025110400980411370313307649721788444629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.lc_ctrl_state_failure.101804518272787255347880408126214641276025110400980411370313307649721788444629
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.96034753342182146703765031456708586610123788239947692930771432118427834873297
Short name T621
Test name
Test status
Simulation time 36820395678 ps
CPU time 277.6 seconds
Started Nov 22 01:37:50 PM PST 23
Finished Nov 22 01:42:32 PM PST 23
Peak memory 283348 kb
Host smart-fdbbc697-963c-4582-baad-2ad633548ba2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960347533421821467037650314567085866101237882399476929307714321184
27834873297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.96034753342182146703765031456708586610123788239947692930
771432118427834873297
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.89596732895156886253652294496068749545598094574044985198271358759159158268713
Short name T477
Test name
Test status
Simulation time 978628843 ps
CPU time 13.29 seconds
Started Nov 22 01:37:42 PM PST 23
Finished Nov 22 01:37:58 PM PST 23
Peak memory 217368 kb
Host smart-32f9988a-e654-4aa4-b7a9-b0e8bcf340b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89596732895156886253652294496068749545598094574044985198271358759159158268713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.lc_ctrl_errors.89596732895156886253652294496068749545598094574044985198271358759159158268713
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.42635951916252874579540958968258874519704860568057187487794246533736912493178
Short name T381
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.69 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 209004 kb
Host smart-87264e76-f123-4a40-b3d8-140b66a01fc7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42635951916252874579540958968258874519704860568057187487794246533736912493178 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.42635951916252874579540958968258874519704860568057187487794246533736912493178
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3248480575684252190283915490491080737809730387233408399080501414471835961712
Short name T698
Test name
Test status
Simulation time 5872518263 ps
CPU time 39.12 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:39 PM PST 23
Peak memory 217776 kb
Host smart-0d6632fd-fc09-4749-8f7f-5789dbac37b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248480575684252190283915490491080737809730387233408399080501414471835961712 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_errors.3248480575684252190283915490491080737809730387233408399080501414471835961712
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.20348488039645340343637856517727895909399059734126795438127590895253053676905
Short name T634
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.29 seconds
Started Nov 22 01:37:43 PM PST 23
Finished Nov 22 01:37:54 PM PST 23
Peak memory 212776 kb
Host smart-811cef4b-2296-4bce-9bce-73c5dc5921a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20348488039645340343637856517727895909399059734126795438127590895253053676905 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.20348488039645340343637856517727895909399059734126795438127590895253053676905
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.68334737257739051309770438673568098851371231479486226271257495702543096455200
Short name T539
Test name
Test status
Simulation time 5030489285 ps
CPU time 49.34 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:49 PM PST 23
Peak memory 268864 kb
Host smart-3e87d85b-8a82-49fd-a302-2c69865ebc01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68334737257739051309770438673568098851371231479486226271257495702543096455200 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_state_failure.68334737257739051309770438673568098851371231479486226271257495
702543096455200
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.48344754105050190229968552922813758909126635363499288729495252195846440446821
Short name T518
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.24 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 246744 kb
Host smart-5ad6fe8c-afc2-4ee0-88fe-e657a73b47ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48344754105050190229968552922813758909126635363499288729495252195846440446821 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_state_post_trans.48344754105050190229968552922813758909126635363499288729
495252195846440446821
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.60826784602528979143119792759763120924276227431406935772648943828083115507573
Short name T19
Test name
Test status
Simulation time 159313969 ps
CPU time 2.86 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:03 PM PST 23
Peak memory 217436 kb
Host smart-c32ce325-c6d3-4c9e-a9c7-346229c23f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60826784602528979143119792759763120924276227431406935772648943828083115507573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.lc_ctrl_prog_failure.60826784602528979143119792759763120924276227431406935772648943828083115507573
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.92199007175858762894960467625024071523297749095965328000880406849472956114449
Short name T448
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.53 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 218476 kb
Host smart-7ea41d4e-7fed-46fe-8510-4923b8827047
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92199007175858762894960467625024071523297749095965328000880406849472956114449 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.92199007175858762894960467625024071523297749095965328000880406849472956114449
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.6849788832967249921586242233049383967340146489522516789727436358499675706752
Short name T390
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.95 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 217404 kb
Host smart-da58f999-4391-4344-8d4c-9c9e8ec93762
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6849788832967249921586242233049383967340146489522516789727436358499675706752 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_digest.6849788832967249921586242233049383967340146489522516789727436358499675706752
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.13356950783709604244979808957818162882093393102656892699378797782103252988586
Short name T524
Test name
Test status
Simulation time 964986095 ps
CPU time 10.74 seconds
Started Nov 22 01:37:41 PM PST 23
Finished Nov 22 01:37:54 PM PST 23
Peak memory 217336 kb
Host smart-6de4aa3c-905f-49f6-a9f0-0f0e5e7321fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13356950783709604244979808957818162882093393102656892699378797782103252988586 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.13356950783709604244979808957818162882093393102656892699378797782103252988586
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.85155030076935756069209965405018070879069569755270317099381331877118895292370
Short name T846
Test name
Test status
Simulation time 625328098 ps
CPU time 8.16 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 217456 kb
Host smart-82595045-570c-49d2-b523-8d4e2ba94f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85155030076935756069209965405018070879069569755270317099381331877118895292370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.lc_ctrl_security_escalation.85155030076935756069209965405018070879069569755270317099381331877118895292370
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.45529089442093475329664150773818402092502849002256733874962231950054813113909
Short name T542
Test name
Test status
Simulation time 291295056 ps
CPU time 4.61 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 213852 kb
Host smart-7765d7ce-05d8-43b7-9b1e-448606594bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45529089442093475329664150773818402092502849002256733874962231950054813113909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.lc_ctrl_smoke.45529089442093475329664150773818402092502849002256733874962231950054813113909
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.34862041177613480615748359286482541936877903563757534401979601393983793718095
Short name T849
Test name
Test status
Simulation time 487150632 ps
CPU time 20.49 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:22 PM PST 23
Peak memory 250468 kb
Host smart-49e4dce3-1913-4d4b-81cf-aa521d94a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34862041177613480615748359286482541936877903563757534401979601393983793718095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.lc_ctrl_state_failure.34862041177613480615748359286482541936877903563757534401979601393983793718095
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.78555637195500448379430712021821418375554012153538474172516209301861565016459
Short name T953
Test name
Test status
Simulation time 217117078 ps
CPU time 7.09 seconds
Started Nov 22 01:37:53 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 246344 kb
Host smart-01b2446c-c97f-46b4-8042-633ff1502713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78555637195500448379430712021821418375554012153538474172516209301861565016459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.lc_ctrl_state_post_trans.78555637195500448379430712021821418375554012153538474172516209301861565016459
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.59035700742502985679839919110799057184369186403289468771108605468252795949044
Short name T57
Test name
Test status
Simulation time 36820395678 ps
CPU time 277.3 seconds
Started Nov 22 01:37:43 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 283360 kb
Host smart-18ea1f67-6189-4622-9aa8-a31397aa275b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590357007425029856798399191107990571843691864032894687711086054682
52795949044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.59035700742502985679839919110799057184369186403289468771
108605468252795949044
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.48302196419825722785004958432105004899806058158242828803613760228073033281662
Short name T519
Test name
Test status
Simulation time 16404398 ps
CPU time 0.73 seconds
Started Nov 22 01:37:51 PM PST 23
Finished Nov 22 01:37:57 PM PST 23
Peak memory 207504 kb
Host smart-f05ba6da-46c0-4f0a-b29d-9ef24235bb6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48302196419825722785004958432105004899806058158242828803613760228073033281662 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_volatile_unlock_smoke.48302196419825722785004958432105004899806058158242828
803613760228073033281662
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.76651847441758299050512828939752246590741574556336938804885866284271179032581
Short name T823
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:02 PM PST 23
Peak memory 207836 kb
Host smart-c8e6c006-5bd3-4ccb-b88a-83629dbe4d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76651847441758299050512828939752246590741574556336938804885866284271179032581 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.76651847441758299050512828939752246590741574556336938804885866284271179032581
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.58897928428739834208306084574783119029253053813804847492638235132808794940085
Short name T476
Test name
Test status
Simulation time 978628843 ps
CPU time 12.97 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 217380 kb
Host smart-b03e13b5-9064-4ae3-9ac6-c887f6d8c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58897928428739834208306084574783119029253053813804847492638235132808794940085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.lc_ctrl_errors.58897928428739834208306084574783119029253053813804847492638235132808794940085
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1655861967107692024276187000254224440923572028681079734673060321468919893320
Short name T33
Test name
Test status
Simulation time 1895300081 ps
CPU time 10.06 seconds
Started Nov 22 01:37:53 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 208960 kb
Host smart-c26d41dd-abc5-4682-ad68-4eb77f71ab15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655861967107692024276187000254224440923572028681079734673060321468919893320 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1655861967107692024276187000254224440923572028681079734673060321468919893320
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.114068325967053509371108632590901197936065788560924578740760844750836280323340
Short name T661
Test name
Test status
Simulation time 5872518263 ps
CPU time 40.37 seconds
Started Nov 22 01:37:46 PM PST 23
Finished Nov 22 01:38:34 PM PST 23
Peak memory 217800 kb
Host smart-6d7c01e1-c225-4878-96ab-cf322da4522b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114068325967053509371108632590901197936065788560924578740760844750836280323340 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_errors.114068325967053509371108632590901197936065788560924578740760844750836280323340
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.11494773901041227334512915691418524703011788675846029045729000919363644469484
Short name T139
Test name
Test status
Simulation time 1480535542 ps
CPU time 10.77 seconds
Started Nov 22 01:37:45 PM PST 23
Finished Nov 22 01:38:03 PM PST 23
Peak memory 217448 kb
Host smart-175780d2-4085-4a45-b2ff-b99ad79831f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494773901041227334512915691418524703011788675846029045729000919363644469484 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_prog_failure.1149477390104122733451291569141852470301178867584602904572900091
9363644469484
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.32770980566672918958278474585834230856575372069549558112037277647873648742416
Short name T606
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.19 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:37:59 PM PST 23
Peak memory 212848 kb
Host smart-f6cb48ff-1eea-4b0e-8576-3e6b576e94d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770980566672918958278474585834230856575372069549558112037277647873648742416 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.32770980566672918958278474585834230856575372069549558112037277647873648742416
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.42390389513418758918027991082769665225975359451974662796091429787658744536408
Short name T700
Test name
Test status
Simulation time 5030489285 ps
CPU time 48.79 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:50 PM PST 23
Peak memory 268924 kb
Host smart-06ff4afc-120f-47e7-b7e3-ed38c2014f10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42390389513418758918027991082769665225975359451974662796091429787658744536408 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_state_failure.42390389513418758918027991082769665225975359451974662796091429
787658744536408
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.21705687661236725460497878942358944414764133500710851334427729764875923101035
Short name T594
Test name
Test status
Simulation time 1491321170 ps
CPU time 14.94 seconds
Started Nov 22 01:37:43 PM PST 23
Finished Nov 22 01:38:00 PM PST 23
Peak memory 246744 kb
Host smart-3600a613-4327-406c-be53-ee09bbe4cd92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21705687661236725460497878942358944414764133500710851334427729764875923101035 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_state_post_trans.21705687661236725460497878942358944414764133500710851334
427729764875923101035
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.43937035373440886618707856799308528682143685229244724892051711725665835900864
Short name T843
Test name
Test status
Simulation time 159313969 ps
CPU time 2.75 seconds
Started Nov 22 01:37:42 PM PST 23
Finished Nov 22 01:37:47 PM PST 23
Peak memory 217408 kb
Host smart-543f92a3-a042-4fab-bc3d-7bb45dd69fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43937035373440886618707856799308528682143685229244724892051711725665835900864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.lc_ctrl_prog_failure.43937035373440886618707856799308528682143685229244724892051711725665835900864
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.4810576334977859799486532941177210605245161095922502725716920451282183797429
Short name T686
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.43 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 218580 kb
Host smart-7a828ca9-adce-4f1f-aedd-5e1972d1deed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4810576334977859799486532941177210605245161095922502725716920451282183797429 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.4810576334977859799486532941177210605245161095922502725716920451282183797429
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4789318928636042313636200664094669063278393359385399836995963038157665657974
Short name T537
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.46 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 217324 kb
Host smart-cf580131-9883-47f7-8968-2aef0a21af8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4789318928636042313636200664094669063278393359385399836995963038157665657974 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_digest.4789318928636042313636200664094669063278393359385399836995963038157665657974
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.59831869750120467963064581986405332076618128208446522086837887831825351253556
Short name T667
Test name
Test status
Simulation time 964986095 ps
CPU time 10.88 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 217452 kb
Host smart-4df2dfc3-f0ad-409e-8a4a-3dd91cd6a87e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59831869750120467963064581986405332076618128208446522086837887831825351253556 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.59831869750120467963064581986405332076618128208446522086837887831825351253556
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.97174458292092124533854323851850185365856510463274335695823021983781808260324
Short name T366
Test name
Test status
Simulation time 625328098 ps
CPU time 8.16 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 217456 kb
Host smart-f74c5775-ae05-4e1b-b600-0e96ac3e450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97174458292092124533854323851850185365856510463274335695823021983781808260324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.lc_ctrl_security_escalation.97174458292092124533854323851850185365856510463274335695823021983781808260324
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.84021938110906056002506492606685045148524961828531984767916565335027313656798
Short name T535
Test name
Test status
Simulation time 291295056 ps
CPU time 4.84 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:37:56 PM PST 23
Peak memory 213852 kb
Host smart-ca870df8-c669-43d5-83f7-eb2c8352747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84021938110906056002506492606685045148524961828531984767916565335027313656798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.lc_ctrl_smoke.84021938110906056002506492606685045148524961828531984767916565335027313656798
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.67320965363326100118860970326243583691415810961689356172790473579341947461202
Short name T398
Test name
Test status
Simulation time 487150632 ps
CPU time 20.63 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 250436 kb
Host smart-38427537-1eb8-453b-afc9-853808923820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67320965363326100118860970326243583691415810961689356172790473579341947461202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.lc_ctrl_state_failure.67320965363326100118860970326243583691415810961689356172790473579341947461202
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.37878990347425220277561930717770009048858030715192794692910573786333325129698
Short name T726
Test name
Test status
Simulation time 217117078 ps
CPU time 6.77 seconds
Started Nov 22 01:37:45 PM PST 23
Finished Nov 22 01:37:58 PM PST 23
Peak memory 246256 kb
Host smart-167c98e2-9f99-4c83-8406-f9e9cf276c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37878990347425220277561930717770009048858030715192794692910573786333325129698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.lc_ctrl_state_post_trans.37878990347425220277561930717770009048858030715192794692910573786333325129698
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.20008237404311408455512431004058524816655142001838368323931297385862365161515
Short name T776
Test name
Test status
Simulation time 36820395678 ps
CPU time 289.54 seconds
Started Nov 22 01:37:43 PM PST 23
Finished Nov 22 01:42:35 PM PST 23
Peak memory 283400 kb
Host smart-16b5cc18-de5d-43c5-bd40-f395c1f34a7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200082374043114084555124310040585248166551420018383683239312973858
62365161515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.20008237404311408455512431004058524816655142001838368323
931297385862365161515
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.21370258975846961923465382087733792038290750832390470607904473700784371533562
Short name T504
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:37:42 PM PST 23
Finished Nov 22 01:37:45 PM PST 23
Peak memory 207508 kb
Host smart-61d43ab4-6c3d-4a76-93d6-666c204246f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21370258975846961923465382087733792038290750832390470607904473700784371533562 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_volatile_unlock_smoke.21370258975846961923465382087733792038290750832390470
607904473700784371533562
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.106562324144721359378498918035013369011706057004681703346426876800128857361746
Short name T816
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:03 PM PST 23
Peak memory 207732 kb
Host smart-7b781c84-55c7-4fbf-9441-de1f781e215c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106562324144721359378498918035013369011706057004681703346426876800128857361746 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.106562324144721359378498918035013369011706057004681703346426876800128857361746
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.35634262343138253192880220733917239601416109572169537374766902036152314787541
Short name T532
Test name
Test status
Simulation time 978628843 ps
CPU time 13.63 seconds
Started Nov 22 01:37:47 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 217416 kb
Host smart-b727ed07-fa75-422c-8b87-34a12915b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35634262343138253192880220733917239601416109572169537374766902036152314787541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.lc_ctrl_errors.35634262343138253192880220733917239601416109572169537374766902036152314787541
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1579943639195521768978276967244775247055985334960757628933059931797301805255
Short name T583
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.4 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 208976 kb
Host smart-9664c433-e345-4c43-ba2c-5847210949d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579943639195521768978276967244775247055985334960757628933059931797301805255 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1579943639195521768978276967244775247055985334960757628933059931797301805255
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.71492589611254411448276626322078646918556561978244756071845359229422803445564
Short name T464
Test name
Test status
Simulation time 5872518263 ps
CPU time 40.2 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:40 PM PST 23
Peak memory 217672 kb
Host smart-57367d73-dd6b-4375-894e-4e2245dba32a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71492589611254411448276626322078646918556561978244756071845359229422803445564 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_errors.71492589611254411448276626322078646918556561978244756071845359229422803445564
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.43218571489731841737515654132278565853538662705370390118057404123025062046873
Short name T664
Test name
Test status
Simulation time 1480535542 ps
CPU time 10.67 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 217376 kb
Host smart-63ec8fac-c5f4-45da-9f86-35f31f75d129
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43218571489731841737515654132278565853538662705370390118057404123025062046873 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_prog_failure.4321857148973184173751565413227856585353866270537039011805740412
3025062046873
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.69385836410511267101095558263517519670454343182217159972623644390120090920374
Short name T689
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.96 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 212872 kb
Host smart-8950e690-8842-454e-bc46-ca30e469f0bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69385836410511267101095558263517519670454343182217159972623644390120090920374 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.69385836410511267101095558263517519670454343182217159972623644390120090920374
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3272638809706535543707518145938510690275817390261042301994622492461052180575
Short name T642
Test name
Test status
Simulation time 5030489285 ps
CPU time 51.03 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:51 PM PST 23
Peak memory 269024 kb
Host smart-6b2c5c35-7253-40f6-95d7-0df887175d74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272638809706535543707518145938510690275817390261042301994622492461052180575 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_state_failure.327263880970653554370751814593851069027581739026104230199462249
2461052180575
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.101017438390137513395229475290728524330608375790768481591052647447589664586707
Short name T677
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.5 seconds
Started Nov 22 01:37:45 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 246676 kb
Host smart-902085c6-e0f5-4187-a873-8ef9e6f34105
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101017438390137513395229475290728524330608375790768481591052647447589664586707 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_state_post_trans.1010174383901375133952294752907285243306083757907684815
91052647447589664586707
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.45262812094464639588501964647401917923159149829450174561395429296119570904073
Short name T901
Test name
Test status
Simulation time 159313969 ps
CPU time 2.86 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:03 PM PST 23
Peak memory 217468 kb
Host smart-6055a595-ce93-4390-89dc-21159e98be93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45262812094464639588501964647401917923159149829450174561395429296119570904073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.lc_ctrl_prog_failure.45262812094464639588501964647401917923159149829450174561395429296119570904073
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.33040995645969858611051296348314000428893206165534943029739450819283631019670
Short name T543
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.11 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 218496 kb
Host smart-4d124245-2592-482b-bb44-567b4bdca59e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040995645969858611051296348314000428893206165534943029739450819283631019670 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.33040995645969858611051296348314000428893206165534943029739450819283631019670
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.103409573946025280240934285551785473062631037365836617477528400996442565546475
Short name T801
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.18 seconds
Started Nov 22 01:37:45 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 217312 kb
Host smart-b3448f2e-e871-4575-a710-23bd833157d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103409573946025280240934285551785473062631037365836617477528400996442565546475 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_digest.103409573946025280240934285551785473062631037365836617477528400996442565546475
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.114933371260781678196901059246344543754289691498964795970142034260487816019830
Short name T558
Test name
Test status
Simulation time 964986095 ps
CPU time 10.77 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 217352 kb
Host smart-9e481369-c3b7-47eb-ba69-37a1482bbde1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114933371260781678196901059246344543754289691498964795970142034260487816019830 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.114933371260781678196901059246344543754289691498964795970142034260487816019830
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.88213921094609626941883347240986321770483201942017366671071443766128529184302
Short name T633
Test name
Test status
Simulation time 625328098 ps
CPU time 8.39 seconds
Started Nov 22 01:37:46 PM PST 23
Finished Nov 22 01:38:02 PM PST 23
Peak memory 217504 kb
Host smart-7aebd48a-2cda-46d2-b1bc-c765ac65562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88213921094609626941883347240986321770483201942017366671071443766128529184302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.lc_ctrl_security_escalation.88213921094609626941883347240986321770483201942017366671071443766128529184302
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.110171118107906809987688484717476231435202462124695399129960206411934691035231
Short name T932
Test name
Test status
Simulation time 291295056 ps
CPU time 4.56 seconds
Started Nov 22 01:37:46 PM PST 23
Finished Nov 22 01:37:59 PM PST 23
Peak memory 213780 kb
Host smart-f8c721dd-c77e-4717-b194-b944ef4906bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110171118107906809987688484717476231435202462124695399129960206411934691035231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.lc_ctrl_smoke.110171118107906809987688484717476231435202462124695399129960206411934691035231
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.8498019156140885601037493512613829300588124587990516443146813644249965833976
Short name T617
Test name
Test status
Simulation time 487150632 ps
CPU time 20.52 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 250416 kb
Host smart-eb194544-7fd4-4a52-a115-9bb44e5d07a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8498019156140885601037493512613829300588124587990516443146813644249965833976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.lc_ctrl_state_failure.8498019156140885601037493512613829300588124587990516443146813644249965833976
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.111709338953218999718324913040961888416720770229663481607885259747371263680411
Short name T337
Test name
Test status
Simulation time 217117078 ps
CPU time 7.13 seconds
Started Nov 22 01:37:46 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 246312 kb
Host smart-f7d1ed4b-41d3-458b-9659-69b3b18775a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111709338953218999718324913040961888416720770229663481607885259747371263680411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.lc_ctrl_state_post_trans.111709338953218999718324913040961888416720770229663481607885259747371263680411
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.89209238263449939696630237751626975545487707341742221524054031252966549095090
Short name T758
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.28 seconds
Started Nov 22 01:37:53 PM PST 23
Finished Nov 22 01:42:42 PM PST 23
Peak memory 283400 kb
Host smart-e895b777-b929-494b-9a53-79020ed6fdba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892092382634499396966302377516269755454877073417422215240540312529
66549095090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.89209238263449939696630237751626975545487707341742221524
054031252966549095090
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.55053607247808065086901351267361075440237878924909746880760809336856875249136
Short name T330
Test name
Test status
Simulation time 16404398 ps
CPU time 0.73 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 207636 kb
Host smart-8df2eb45-6f19-4eeb-8438-3bcf0c396f42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55053607247808065086901351267361075440237878924909746880760809336856875249136 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_volatile_unlock_smoke.55053607247808065086901351267361075440237878924909746
880760809336856875249136
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.73344089410477145046650814578470511595477871221430575030904960072434310284727
Short name T736
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 207756 kb
Host smart-5d7f2351-5969-4439-a6fb-318efd23f4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73344089410477145046650814578470511595477871221430575030904960072434310284727 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.73344089410477145046650814578470511595477871221430575030904960072434310284727
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.76817116878753290900787073896573510401284860638893431770470780010195587535924
Short name T564
Test name
Test status
Simulation time 978628843 ps
CPU time 13.66 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 217412 kb
Host smart-d0fbac0b-c45b-43ec-9079-f98b9ff88659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76817116878753290900787073896573510401284860638893431770470780010195587535924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.lc_ctrl_errors.76817116878753290900787073896573510401284860638893431770470780010195587535924
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.40720964111759519026804899143686754098878514765850614138972920878983986388337
Short name T440
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.53 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 209008 kb
Host smart-5492dfe9-8998-4285-a275-b42ef31e040d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40720964111759519026804899143686754098878514765850614138972920878983986388337 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.40720964111759519026804899143686754098878514765850614138972920878983986388337
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.68172704294329082484160385159243725285247434054808341304860205204414620392824
Short name T918
Test name
Test status
Simulation time 5872518263 ps
CPU time 40.22 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:49 PM PST 23
Peak memory 217764 kb
Host smart-f91f69e0-9f3d-4a1f-a43f-5b786528d9ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68172704294329082484160385159243725285247434054808341304860205204414620392824 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_errors.68172704294329082484160385159243725285247434054808341304860205204414620392824
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.99943983957782717406741577176786460151506689570022749914045221891651679522527
Short name T554
Test name
Test status
Simulation time 1480535542 ps
CPU time 10.93 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 217320 kb
Host smart-7a7405bb-e0fe-44e1-b09d-83c8e3d8e0c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99943983957782717406741577176786460151506689570022749914045221891651679522527 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_prog_failure.9994398395778271740674157717678646015150668957002274991404522189
1651679522527
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.59689944619222290108318858052321982221001924280136433008248766309728913367982
Short name T710
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.65 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 212820 kb
Host smart-3d5ebd45-dad5-4b6c-a1b6-036089ffb3c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59689944619222290108318858052321982221001924280136433008248766309728913367982 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.59689944619222290108318858052321982221001924280136433008248766309728913367982
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.115718739936431724122766163511715050022808633777112931978608675642894872881534
Short name T864
Test name
Test status
Simulation time 5030489285 ps
CPU time 50.8 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:39:00 PM PST 23
Peak memory 269128 kb
Host smart-cdae0881-7c4c-4ec8-a27f-87141ec65888
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115718739936431724122766163511715050022808633777112931978608675642894872881534 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_state_failure.1157187399364317241227661635117150500228086337771129319786086
75642894872881534
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.53472943055915923918859209897636166045375335008575423581775063657712723713346
Short name T610
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.39 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 246768 kb
Host smart-8f3a12b6-c9a2-4e6b-80c8-d1dadbd1a21d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53472943055915923918859209897636166045375335008575423581775063657712723713346 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_state_post_trans.53472943055915923918859209897636166045375335008575423581
775063657712723713346
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.53334906393953563808939957308432157352437137778964294937810702133783604523161
Short name T556
Test name
Test status
Simulation time 159313969 ps
CPU time 2.89 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 217496 kb
Host smart-1424c5e1-94b9-40f5-a480-63139004f73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53334906393953563808939957308432157352437137778964294937810702133783604523161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.lc_ctrl_prog_failure.53334906393953563808939957308432157352437137778964294937810702133783604523161
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.14464357688511986570427326521290885320949091409634469796161590142762203357119
Short name T387
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.45 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 218452 kb
Host smart-9fb53893-41b4-4ca4-ab53-9c2e81adcfe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464357688511986570427326521290885320949091409634469796161590142762203357119 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.14464357688511986570427326521290885320949091409634469796161590142762203357119
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.72004939203499068571078495490428516681019916808019963971333861783758239581860
Short name T282
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.45 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 217264 kb
Host smart-d72b3ecb-c83a-4102-a3ff-d00da6a5ff9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72004939203499068571078495490428516681019916808019963971333861783758239581860 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_digest.72004939203499068571078495490428516681019916808019963971333861783758239581860
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.34560480099587146937476153461582395328273545980763223729947430711995030059929
Short name T672
Test name
Test status
Simulation time 964986095 ps
CPU time 11.02 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 217528 kb
Host smart-a5d22f9b-556f-4855-b636-0ec7b369b089
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560480099587146937476153461582395328273545980763223729947430711995030059929 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.34560480099587146937476153461582395328273545980763223729947430711995030059929
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.44729475403999549600864260227237062929065591762048606645571824344203827870541
Short name T857
Test name
Test status
Simulation time 625328098 ps
CPU time 8.22 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 217400 kb
Host smart-1e643dc4-c271-4228-8cb6-04abc2f08ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44729475403999549600864260227237062929065591762048606645571824344203827870541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.lc_ctrl_security_escalation.44729475403999549600864260227237062929065591762048606645571824344203827870541
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.12724859551757788333026389918768424972711777790553152174026568816996052960568
Short name T631
Test name
Test status
Simulation time 291295056 ps
CPU time 4.76 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:05 PM PST 23
Peak memory 213872 kb
Host smart-7cbe119c-a7f5-4dc1-82da-68d8c6e7562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12724859551757788333026389918768424972711777790553152174026568816996052960568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.lc_ctrl_smoke.12724859551757788333026389918768424972711777790553152174026568816996052960568
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.12281440640414599756182236043027938948153380417217471279942218576048663819545
Short name T474
Test name
Test status
Simulation time 487150632 ps
CPU time 20.93 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 250400 kb
Host smart-97270fed-541f-49d1-9855-33aeb3b168ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12281440640414599756182236043027938948153380417217471279942218576048663819545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.lc_ctrl_state_failure.12281440640414599756182236043027938948153380417217471279942218576048663819545
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.94220800014738019290870751937517302594240268503101350317535620687293825833621
Short name T409
Test name
Test status
Simulation time 217117078 ps
CPU time 7.08 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 246352 kb
Host smart-ef6cba1e-9ff0-457c-89e2-932c1754682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94220800014738019290870751937517302594240268503101350317535620687293825833621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.lc_ctrl_state_post_trans.94220800014738019290870751937517302594240268503101350317535620687293825833621
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.80120185883898093160244656654296302334413733847851757654115012893493063937156
Short name T472
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.87 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:42:48 PM PST 23
Peak memory 283320 kb
Host smart-b7791ede-a240-4b64-910d-bdc6094d982f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801201858838980931602446566542963023344137338478517576541150128934
93063937156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.80120185883898093160244656654296302334413733847851757654
115012893493063937156
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.10339691455061670028391955395569605066974522761147121682646695745380299106016
Short name T277
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:37:52 PM PST 23
Finished Nov 22 01:37:59 PM PST 23
Peak memory 207592 kb
Host smart-b1ac840e-0fca-42e5-b1dd-b5467f5ab338
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10339691455061670028391955395569605066974522761147121682646695745380299106016 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_volatile_unlock_smoke.10339691455061670028391955395569605066974522761147121
682646695745380299106016
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.111504048923426559556217751487483718044918921353047753318249043866252139253350
Short name T630
Test name
Test status
Simulation time 42189906 ps
CPU time 1.01 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 207172 kb
Host smart-fef7791a-b5c4-4e6a-bea5-728d8e1fad74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111504048923426559556217751487483718044918921353047753318249043866252139253350 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.111504048923426559556217751487483718044918921353047753318249043866252139253350
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.105876804989292547688445955560566898845079663316350213687501414211828811359161
Short name T546
Test name
Test status
Simulation time 978628843 ps
CPU time 13.96 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:26 PM PST 23
Peak memory 217488 kb
Host smart-52b992b9-23f9-45c6-b2dc-a9587539dde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105876804989292547688445955560566898845079663316350213687501414211828811359161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.lc_ctrl_errors.105876804989292547688445955560566898845079663316350213687501414211828811359161
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.51616206566265842841261176928547886156278216424915383966070297007428559550517
Short name T684
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.69 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 208988 kb
Host smart-171490f4-8e01-4ab7-b3ad-0e91fd43810a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51616206566265842841261176928547886156278216424915383966070297007428559550517 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.51616206566265842841261176928547886156278216424915383966070297007428559550517
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.89389238151127496744971705559611518278149929696872092957377287582602955018774
Short name T571
Test name
Test status
Simulation time 5872518263 ps
CPU time 40.2 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:45 PM PST 23
Peak memory 217768 kb
Host smart-489ff6ab-7b01-45af-890b-8a1b37148ffb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89389238151127496744971705559611518278149929696872092957377287582602955018774 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_errors.89389238151127496744971705559611518278149929696872092957377287582602955018774
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.48792220996723970193959760130822074941428172794517629514146961488349673643906
Short name T964
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.54 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 217452 kb
Host smart-e1099a53-160b-4289-8792-5a16ed049711
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48792220996723970193959760130822074941428172794517629514146961488349673643906 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_prog_failure.4879222099672397019395976013082207494142817279451762951414696148
8349673643906
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.99203078690626462693683741202732338951135880444516682433774881868106864826385
Short name T51
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.89 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 212884 kb
Host smart-899f1376-c87c-48cf-91e6-f8c88595e010
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99203078690626462693683741202732338951135880444516682433774881868106864826385 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.99203078690626462693683741202732338951135880444516682433774881868106864826385
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.13816856047506450111897042936206098611937727968893614082002102265015931939730
Short name T622
Test name
Test status
Simulation time 5030489285 ps
CPU time 50.68 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:55 PM PST 23
Peak memory 268996 kb
Host smart-7d1f8775-e40b-460b-93f2-834c55e676a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13816856047506450111897042936206098611937727968893614082002102265015931939730 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_state_failure.13816856047506450111897042936206098611937727968893614082002102
265015931939730
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.81863949300821041999467910818998683622581833816676999762900632077613318067550
Short name T887
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.98 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 246636 kb
Host smart-5a76c3e1-877f-4957-8a86-3f1509ab7186
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81863949300821041999467910818998683622581833816676999762900632077613318067550 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_state_post_trans.81863949300821041999467910818998683622581833816676999762
900632077613318067550
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.99668278075029196326400829369712066966652961126464878475605029192640569705231
Short name T601
Test name
Test status
Simulation time 159313969 ps
CPU time 2.85 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 217364 kb
Host smart-fdf01e47-7eb3-444b-8cc4-c461e83003d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99668278075029196326400829369712066966652961126464878475605029192640569705231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.lc_ctrl_prog_failure.99668278075029196326400829369712066966652961126464878475605029192640569705231
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.56915987297986495437242261458056799062203057348686698437648744410082253341837
Short name T615
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.44 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:26 PM PST 23
Peak memory 218300 kb
Host smart-1391e941-6d42-44af-bd46-aa7ef12632e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56915987297986495437242261458056799062203057348686698437648744410082253341837 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.56915987297986495437242261458056799062203057348686698437648744410082253341837
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.44760891751220882267149739420846642878191551037242385282946915478435088534389
Short name T386
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.76 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:26 PM PST 23
Peak memory 217412 kb
Host smart-2e34674c-f381-4866-8500-3caa2a1929ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44760891751220882267149739420846642878191551037242385282946915478435088534389 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_digest.44760891751220882267149739420846642878191551037242385282946915478435088534389
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.83698912907419818114053975225059200574892613838093121437325899344096946019265
Short name T832
Test name
Test status
Simulation time 964986095 ps
CPU time 10.88 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 217392 kb
Host smart-c2ccf1a9-d534-4db3-bb00-ca7adec002af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83698912907419818114053975225059200574892613838093121437325899344096946019265 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.83698912907419818114053975225059200574892613838093121437325899344096946019265
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.84410767771431536068935598959851382336135108088297899545244561741648049944430
Short name T461
Test name
Test status
Simulation time 625328098 ps
CPU time 8.43 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 217356 kb
Host smart-c179fa71-8f7d-4720-ace2-066e6d6720a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84410767771431536068935598959851382336135108088297899545244561741648049944430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.lc_ctrl_security_escalation.84410767771431536068935598959851382336135108088297899545244561741648049944430
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.84762330614691376453230056151878749439833349433777988892401387423099833048065
Short name T419
Test name
Test status
Simulation time 291295056 ps
CPU time 4.88 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 213856 kb
Host smart-b4dccbd1-38f9-41ee-af53-4c534e82e103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84762330614691376453230056151878749439833349433777988892401387423099833048065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.lc_ctrl_smoke.84762330614691376453230056151878749439833349433777988892401387423099833048065
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.40645400195394894763111027434511815993029438411174137434146949379401757238148
Short name T730
Test name
Test status
Simulation time 487150632 ps
CPU time 20.44 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:36 PM PST 23
Peak memory 250352 kb
Host smart-4b0a7eeb-59cf-47a4-9d73-484c1c17401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40645400195394894763111027434511815993029438411174137434146949379401757238148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.lc_ctrl_state_failure.40645400195394894763111027434511815993029438411174137434146949379401757238148
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.30222507924516210025338307517725989038907494924762049674853137991601395272765
Short name T39
Test name
Test status
Simulation time 217117078 ps
CPU time 6.96 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 246184 kb
Host smart-57a22799-8dbc-4933-bce0-4ee22f9dae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30222507924516210025338307517725989038907494924762049674853137991601395272765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.lc_ctrl_state_post_trans.30222507924516210025338307517725989038907494924762049674853137991601395272765
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.61412700329361671158810330851050070962707044326168370075472986628471284005506
Short name T623
Test name
Test status
Simulation time 36820395678 ps
CPU time 284.32 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:42:49 PM PST 23
Peak memory 283476 kb
Host smart-bd9b8861-1f2b-4d48-94ce-c206a0e8d4d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614127003293616711588103308510500709627070443261683700754729866284
71284005506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.61412700329361671158810330851050070962707044326168370075
472986628471284005506
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.92650470047433343293069651735788589076622433813631892601146866169106430324591
Short name T265
Test name
Test status
Simulation time 16404398 ps
CPU time 0.71 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 207432 kb
Host smart-a196b16c-09fb-4c9f-aa90-2a4bc1e6b9e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92650470047433343293069651735788589076622433813631892601146866169106430324591 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_volatile_unlock_smoke.92650470047433343293069651735788589076622433813631892
601146866169106430324591
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.29571781936540323560427339411029538527779453137450725089244503710248553665540
Short name T640
Test name
Test status
Simulation time 42189906 ps
CPU time 0.99 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 207716 kb
Host smart-db88c136-4535-4572-a6c9-d69f19d19860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29571781936540323560427339411029538527779453137450725089244503710248553665540 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.29571781936540323560427339411029538527779453137450725089244503710248553665540
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4883177016110838528347150693634615840852303128709749506757145515381857279898
Short name T565
Test name
Test status
Simulation time 978628843 ps
CPU time 14.58 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 217368 kb
Host smart-8779e81e-fc95-4dde-9462-6aa645f3b15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4883177016110838528347150693634615840852303128709749506757145515381857279898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.lc_ctrl_errors.4883177016110838528347150693634615840852303128709749506757145515381857279898
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.51311377617215892457462299004243293818367213521407916373128046952301946306176
Short name T31
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.68 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 209028 kb
Host smart-6d6826cd-7a55-4e6e-820f-90fcef534efc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51311377617215892457462299004243293818367213521407916373128046952301946306176 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.51311377617215892457462299004243293818367213521407916373128046952301946306176
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.82123502093016311679047361831366358081366304180517007508279616051805187348855
Short name T490
Test name
Test status
Simulation time 5872518263 ps
CPU time 41.55 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:44 PM PST 23
Peak memory 217728 kb
Host smart-b0150bd0-91e4-4f7e-85de-2a10e0cb39af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82123502093016311679047361831366358081366304180517007508279616051805187348855 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_errors.82123502093016311679047361831366358081366304180517007508279616051805187348855
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.53397706178302030904171530380142447310601651091286432234636799757926897713839
Short name T463
Test name
Test status
Simulation time 1480535542 ps
CPU time 10.76 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 217420 kb
Host smart-6b4521d9-850c-4f0e-9a7b-50ddca5b7ad0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53397706178302030904171530380142447310601651091286432234636799757926897713839 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_prog_failure.5339770617830203090417153038014244731060165109128643223463679975
7926897713839
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.41617703138862505368211253775530882032039374056536084135243468534027250086107
Short name T54
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.76 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 212792 kb
Host smart-6cae9a58-e0a5-4077-88b3-8696ab393ccc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617703138862505368211253775530882032039374056536084135243468534027250086107 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.41617703138862505368211253775530882032039374056536084135243468534027250086107
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.37083458097862237852121507780748750125352094239784170463219443680085546606402
Short name T612
Test name
Test status
Simulation time 5030489285 ps
CPU time 50.81 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:56 PM PST 23
Peak memory 268936 kb
Host smart-8f214baf-2dce-4175-a486-4e464cbed549
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37083458097862237852121507780748750125352094239784170463219443680085546606402 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_state_failure.37083458097862237852121507780748750125352094239784170463219443
680085546606402
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.38536076528216783503580782512648665468795668515597812815174815474756534126099
Short name T551
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.32 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:27 PM PST 23
Peak memory 246748 kb
Host smart-96008de7-4437-4ff1-a428-fdab0365bc57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536076528216783503580782512648665468795668515597812815174815474756534126099 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_state_post_trans.38536076528216783503580782512648665468795668515597812815
174815474756534126099
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.8431125315128383781733100611957116201094646500265490789275011309644881912352
Short name T89
Test name
Test status
Simulation time 159313969 ps
CPU time 2.95 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 217440 kb
Host smart-c3ca093a-e6cf-487e-8cba-8812cf8e2fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8431125315128383781733100611957116201094646500265490789275011309644881912352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.lc_ctrl_prog_failure.8431125315128383781733100611957116201094646500265490789275011309644881912352
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.68693738848553296443861291393109933073497027437967039658349152304044516930206
Short name T878
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.38 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 218496 kb
Host smart-f2f16055-8822-474d-b4f5-3ab63bba6997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68693738848553296443861291393109933073497027437967039658349152304044516930206 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.68693738848553296443861291393109933073497027437967039658349152304044516930206
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.40157858684601648211165193182962453227291281896008512525644359861922686679504
Short name T866
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.51 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:26 PM PST 23
Peak memory 217400 kb
Host smart-81093724-191d-4caa-82db-666cb920b5cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40157858684601648211165193182962453227291281896008512525644359861922686679504 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_digest.40157858684601648211165193182962453227291281896008512525644359861922686679504
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.108799855259208823239728557904352888518475482874905038108362957625848600412121
Short name T733
Test name
Test status
Simulation time 964986095 ps
CPU time 11.45 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 217244 kb
Host smart-4c937aaa-a776-4846-b173-9aedcbd0d2eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108799855259208823239728557904352888518475482874905038108362957625848600412121 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.108799855259208823239728557904352888518475482874905038108362957625848600412121
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.106319082682177742688495437233441963444883268961756644807245064243601987338269
Short name T769
Test name
Test status
Simulation time 625328098 ps
CPU time 8.12 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 217400 kb
Host smart-9668f948-1138-4af1-8e5c-8ffc319eb749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106319082682177742688495437233441963444883268961756644807245064243601987338269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.lc_ctrl_security_escalation.106319082682177742688495437233441963444883268961756644807245064243601987338269
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.57813686652379960574301151345398979814470377742008701330679106437425663596918
Short name T573
Test name
Test status
Simulation time 291295056 ps
CPU time 4.83 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 213780 kb
Host smart-5964e83e-42b8-471e-9cd4-992b1d8f173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57813686652379960574301151345398979814470377742008701330679106437425663596918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.lc_ctrl_smoke.57813686652379960574301151345398979814470377742008701330679106437425663596918
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.7324083319885235387115569900952356697198752668370977030959353271640190214556
Short name T279
Test name
Test status
Simulation time 487150632 ps
CPU time 21.37 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 250488 kb
Host smart-13878a0f-d629-446d-b878-eeea591d4088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7324083319885235387115569900952356697198752668370977030959353271640190214556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.lc_ctrl_state_failure.7324083319885235387115569900952356697198752668370977030959353271640190214556
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.98373726518264088666357088603240307069872994526476828814553300705805872657386
Short name T290
Test name
Test status
Simulation time 217117078 ps
CPU time 6.98 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 246252 kb
Host smart-80a004ca-2d7f-4e58-a7d7-82ff3ab50ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98373726518264088666357088603240307069872994526476828814553300705805872657386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.lc_ctrl_state_post_trans.98373726518264088666357088603240307069872994526476828814553300705805872657386
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.47255621384159415074632416713267397951053519964058661216320679868161916558723
Short name T591
Test name
Test status
Simulation time 36820395678 ps
CPU time 287.82 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:42:50 PM PST 23
Peak memory 283368 kb
Host smart-439277f7-ea53-4989-9eb6-2c1f8e26f2eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472556213841594150746324167132673979510535199640586612163206798681
61916558723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.47255621384159415074632416713267397951053519964058661216
320679868161916558723
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.77917783447950111596312936631257775312471937494110349112621292772133745320713
Short name T567
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 207612 kb
Host smart-0de63535-5a0c-4961-b0b1-103a46cff31d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77917783447950111596312936631257775312471937494110349112621292772133745320713 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_volatile_unlock_smoke.77917783447950111596312936631257775312471937494110349
112621292772133745320713
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.58794143119294111800459896716114454559945914368364387475134660824115581172135
Short name T757
Test name
Test status
Simulation time 42189906 ps
CPU time 0.89 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 207596 kb
Host smart-9b46d776-8895-4c8e-9301-7e34e1521892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58794143119294111800459896716114454559945914368364387475134660824115581172135 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.58794143119294111800459896716114454559945914368364387475134660824115581172135
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.28792425784927017979352916362466929700587003860870792191463336106266798742531
Short name T652
Test name
Test status
Simulation time 978628843 ps
CPU time 13.39 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 217464 kb
Host smart-4e03675a-77cb-47f5-a309-fd994f0b1f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28792425784927017979352916362466929700587003860870792191463336106266798742531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.lc_ctrl_errors.28792425784927017979352916362466929700587003860870792191463336106266798742531
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.65630683600965242692129122936271684214898182068892920420298139043435710256332
Short name T365
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.51 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 208968 kb
Host smart-981e2bff-113d-4387-83da-3e8246917a85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65630683600965242692129122936271684214898182068892920420298139043435710256332 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.65630683600965242692129122936271684214898182068892920420298139043435710256332
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.51964021479952856198962830002342412575099822253258146632264888083015217392765
Short name T470
Test name
Test status
Simulation time 5872518263 ps
CPU time 42.25 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:55 PM PST 23
Peak memory 217788 kb
Host smart-0241ffe6-d6fc-44dc-9b00-07f7051ff305
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51964021479952856198962830002342412575099822253258146632264888083015217392765 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_errors.51964021479952856198962830002342412575099822253258146632264888083015217392765
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.31144943699915908822831545683068982734663212864445960766704112762864976529077
Short name T694
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.15 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 217440 kb
Host smart-f23c1543-c365-42c4-82f2-8a7b69edd494
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31144943699915908822831545683068982734663212864445960766704112762864976529077 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_prog_failure.3114494369991590882283154568306898273466321286444596076670411276
2864976529077
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.108314132834418328626944079127295047573442966144468206179549473919827058084982
Short name T351
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.56 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 212876 kb
Host smart-09bfc146-b53f-4aa3-ac68-431eca854b81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108314132834418328626944079127295047573442966144468206179549473919827058084982 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.108314132834418328626944079127295047573442966144468206179549473919827058084982
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.31297726747834129632034565982785909275961894118750848337826813970721868412513
Short name T811
Test name
Test status
Simulation time 5030489285 ps
CPU time 53.17 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:56 PM PST 23
Peak memory 268984 kb
Host smart-a9e73776-b666-4744-8620-a150e211ba0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31297726747834129632034565982785909275961894118750848337826813970721868412513 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_state_failure.31297726747834129632034565982785909275961894118750848337826813
970721868412513
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.78411046443937346266218086198098617305142858777525188721439104455441910732989
Short name T665
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.28 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:27 PM PST 23
Peak memory 246796 kb
Host smart-5efa474d-5904-470d-935e-0bb79a829ba9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78411046443937346266218086198098617305142858777525188721439104455441910732989 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_state_post_trans.78411046443937346266218086198098617305142858777525188721
439104455441910732989
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.17414825156056422093885885954383154561545522057588664316215092669081578961465
Short name T861
Test name
Test status
Simulation time 159313969 ps
CPU time 2.88 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 217508 kb
Host smart-8d66bced-1f3d-4788-912f-4a65662f9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17414825156056422093885885954383154561545522057588664316215092669081578961465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.lc_ctrl_prog_failure.17414825156056422093885885954383154561545522057588664316215092669081578961465
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.93802575170132750092851841637978647062870909893297794283538925846568822271072
Short name T889
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.72 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 218504 kb
Host smart-28647817-f86d-4b69-bdd1-196a812f98f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93802575170132750092851841637978647062870909893297794283538925846568822271072 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.93802575170132750092851841637978647062870909893297794283538925846568822271072
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.28210560998588670422298679392332186615318062075476692782927944722871312495099
Short name T370
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.4 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 217312 kb
Host smart-309adb16-6918-4da2-a5b4-5962a4a88fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210560998588670422298679392332186615318062075476692782927944722871312495099 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_digest.28210560998588670422298679392332186615318062075476692782927944722871312495099
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.63284769947581835324926146776032992483434121951715113915294908714479575784075
Short name T517
Test name
Test status
Simulation time 964986095 ps
CPU time 11.3 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 217396 kb
Host smart-8ee9231c-574a-413d-adf7-d76e080a3cf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63284769947581835324926146776032992483434121951715113915294908714479575784075 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.63284769947581835324926146776032992483434121951715113915294908714479575784075
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.113420840929688311835172396277159062975702748694569992438448162036444829766575
Short name T516
Test name
Test status
Simulation time 291295056 ps
CPU time 4.77 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 213828 kb
Host smart-67922532-6947-49ee-a2df-1e34a7476c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113420840929688311835172396277159062975702748694569992438448162036444829766575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.lc_ctrl_smoke.113420840929688311835172396277159062975702748694569992438448162036444829766575
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.16617998378935355461765746862903335183190767003034736428269136054060773726066
Short name T42
Test name
Test status
Simulation time 487150632 ps
CPU time 21.09 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:26 PM PST 23
Peak memory 250372 kb
Host smart-6403f765-adc6-4a9a-8717-58642ba51e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16617998378935355461765746862903335183190767003034736428269136054060773726066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.lc_ctrl_state_failure.16617998378935355461765746862903335183190767003034736428269136054060773726066
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.72456493125612955834815493399429817945155586341662375714555600279469987934796
Short name T611
Test name
Test status
Simulation time 217117078 ps
CPU time 7.04 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 246324 kb
Host smart-0b988705-bc35-4ac7-93fc-68604036950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72456493125612955834815493399429817945155586341662375714555600279469987934796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.lc_ctrl_state_post_trans.72456493125612955834815493399429817945155586341662375714555600279469987934796
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.66003383811145079462133536621287332501987812746440711896341978865378547503797
Short name T507
Test name
Test status
Simulation time 36820395678 ps
CPU time 286.93 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:42:56 PM PST 23
Peak memory 283472 kb
Host smart-873c0cac-9c65-48e4-a6ae-633772619864
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660033838111450794621335366212873325019878127464407118963419788653
78547503797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.66003383811145079462133536621287332501987812746440711896
341978865378547503797
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.73326588299067293009991091953002284629362267393610823296637680495842500638350
Short name T12
Test name
Test status
Simulation time 16404398 ps
CPU time 0.71 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 207592 kb
Host smart-da8e1422-c6af-428d-8eee-22468c966a70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73326588299067293009991091953002284629362267393610823296637680495842500638350 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_volatile_unlock_smoke.73326588299067293009991091953002284629362267393610823
296637680495842500638350
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.27282449786800835227830188560550234227257575998773239227928009798762337864235
Short name T879
Test name
Test status
Simulation time 42189906 ps
CPU time 0.95 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 207776 kb
Host smart-72039aa0-377d-482a-a25c-4e2f9641185e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27282449786800835227830188560550234227257575998773239227928009798762337864235 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.27282449786800835227830188560550234227257575998773239227928009798762337864235
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.77990839519855345845760717247147211998337087349664086001270559440720391707406
Short name T775
Test name
Test status
Simulation time 978628843 ps
CPU time 14.12 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217348 kb
Host smart-92c3f17d-cb09-43a2-b7ca-7e14b15898cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77990839519855345845760717247147211998337087349664086001270559440720391707406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.lc_ctrl_errors.77990839519855345845760717247147211998337087349664086001270559440720391707406
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.8556441371429022258811832191700364772373590644769435589918084059866468881586
Short name T974
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.31 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 208908 kb
Host smart-b30a2253-bfcd-461b-871e-863c9cebb439
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8556441371429022258811832191700364772373590644769435589918084059866468881586 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.8556441371429022258811832191700364772373590644769435589918084059866468881586
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.59282973071354867371561061376888005908348543829908576052819557645915015781308
Short name T934
Test name
Test status
Simulation time 5872518263 ps
CPU time 41.77 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:39:01 PM PST 23
Peak memory 217784 kb
Host smart-45872329-6350-45bb-9c9b-6ca12d43a873
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59282973071354867371561061376888005908348543829908576052819557645915015781308 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_errors.59282973071354867371561061376888005908348543829908576052819557645915015781308
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.65915412587674865237633974838658854663733018059661798414060289381448688905566
Short name T445
Test name
Test status
Simulation time 1480535542 ps
CPU time 10.59 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 217372 kb
Host smart-7574939b-b7ae-46a6-a4fa-b8c1fc66fb3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65915412587674865237633974838658854663733018059661798414060289381448688905566 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_prog_failure.6591541258767486523763397483865885466373301805966179841406028938
1448688905566
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.27910385767464697058250823230729546261660900353767319597613707896403915158860
Short name T359
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.56 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 212852 kb
Host smart-719243a4-f065-456d-9ee0-081f7aa3d512
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27910385767464697058250823230729546261660900353767319597613707896403915158860 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.27910385767464697058250823230729546261660900353767319597613707896403915158860
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.58034506892963924758296699142261518692212989946976368080733078306296995777643
Short name T657
Test name
Test status
Simulation time 5030489285 ps
CPU time 49.4 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:39:04 PM PST 23
Peak memory 268996 kb
Host smart-ee5223bb-b1f5-4b81-9fc4-6b4d0e0acdca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58034506892963924758296699142261518692212989946976368080733078306296995777643 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_state_failure.58034506892963924758296699142261518692212989946976368080733078
306296995777643
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.59310289823382821989398047008336084717428850794117890660368470002052682305420
Short name T762
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.96 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 246716 kb
Host smart-789e08fc-2ae3-40f9-81ec-21824da543cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59310289823382821989398047008336084717428850794117890660368470002052682305420 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_state_post_trans.59310289823382821989398047008336084717428850794117890660
368470002052682305420
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.27339354312370942871829942930067629800264550238032977451496608412967111570725
Short name T927
Test name
Test status
Simulation time 159313969 ps
CPU time 2.93 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 217492 kb
Host smart-a227e105-cbb1-4ca5-bc47-bbadc776fb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27339354312370942871829942930067629800264550238032977451496608412967111570725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.lc_ctrl_prog_failure.27339354312370942871829942930067629800264550238032977451496608412967111570725
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.42704464415908809213303049487310283275924386048983781542846242066516367211490
Short name T40
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.28 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 218496 kb
Host smart-ec2c6628-9850-4d25-a56b-8086d8d12c12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42704464415908809213303049487310283275924386048983781542846242066516367211490 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.42704464415908809213303049487310283275924386048983781542846242066516367211490
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.108970366336405956273478664155122902872015738020447792210246593970755058663327
Short name T721
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.64 seconds
Started Nov 22 01:38:13 PM PST 23
Finished Nov 22 01:38:36 PM PST 23
Peak memory 217440 kb
Host smart-2e878d24-00fb-4583-a5e4-dabad3f72c87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108970366336405956273478664155122902872015738020447792210246593970755058663327 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_digest.108970366336405956273478664155122902872015738020447792210246593970755058663327
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.97575412699664497878317921791859079791812874382704320049900043830292232645974
Short name T329
Test name
Test status
Simulation time 964986095 ps
CPU time 10.6 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 217456 kb
Host smart-7956cf32-15cf-4718-b185-f6b833d55115
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97575412699664497878317921791859079791812874382704320049900043830292232645974 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.97575412699664497878317921791859079791812874382704320049900043830292232645974
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3020833805318687392861892141744241744597082385458783799846338114852205236828
Short name T266
Test name
Test status
Simulation time 625328098 ps
CPU time 8.29 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 217572 kb
Host smart-0081a3cc-c4af-4e8e-85e5-a1b0e603f6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020833805318687392861892141744241744597082385458783799846338114852205236828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.lc_ctrl_security_escalation.3020833805318687392861892141744241744597082385458783799846338114852205236828
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.91576715225556278169635411717208642261540425260173425642031702934140718929145
Short name T49
Test name
Test status
Simulation time 291295056 ps
CPU time 4.67 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 213732 kb
Host smart-44e3729f-aaf3-4713-aaa5-5e5a830e0708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91576715225556278169635411717208642261540425260173425642031702934140718929145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.lc_ctrl_smoke.91576715225556278169635411717208642261540425260173425642031702934140718929145
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.42540100669642211934143808694772401224996313890032104068846477447098225889946
Short name T416
Test name
Test status
Simulation time 487150632 ps
CPU time 20.81 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 250472 kb
Host smart-61994c95-a7a6-4163-8122-20060c821054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42540100669642211934143808694772401224996313890032104068846477447098225889946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.lc_ctrl_state_failure.42540100669642211934143808694772401224996313890032104068846477447098225889946
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4803552989541816893250311782249269354302954088451975065013411954041140635845
Short name T648
Test name
Test status
Simulation time 217117078 ps
CPU time 6.89 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 246272 kb
Host smart-e8dd1fa7-706c-4484-abfd-1ce14f919215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4803552989541816893250311782249269354302954088451975065013411954041140635845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.lc_ctrl_state_post_trans.4803552989541816893250311782249269354302954088451975065013411954041140635845
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.37750035891165463776537586913699293604819556673225210319484304068824209518743
Short name T322
Test name
Test status
Simulation time 16404398 ps
CPU time 0.76 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 207444 kb
Host smart-a08cabfd-4c18-4c43-b511-ccc0ba1eb35d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37750035891165463776537586913699293604819556673225210319484304068824209518743 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_volatile_unlock_smoke.37750035891165463776537586913699293604819556673225210
319484304068824209518743
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.24353038473299599777475173699022056250059430627783161459396913548289138238003
Short name T950
Test name
Test status
Simulation time 42189906 ps
CPU time 0.96 seconds
Started Nov 22 01:37:00 PM PST 23
Finished Nov 22 01:37:04 PM PST 23
Peak memory 207756 kb
Host smart-4a318a2e-ab63-43e0-b7fe-47dc883cd951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353038473299599777475173699022056250059430627783161459396913548289138238003 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.24353038473299599777475173699022056250059430627783161459396913548289138238003
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.61778465304613677332433210038154014595660335073618391177806747666205915276285
Short name T624
Test name
Test status
Simulation time 19636515 ps
CPU time 0.81 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:00 PM PST 23
Peak memory 207580 kb
Host smart-31ea90d1-4e54-4c0c-ac97-0c4e22b9d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61778465304613677332433210038154014595660335073618391177806747666205915276285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.61778465304613677332433210038154014595660335073618391177806747666205915276285
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.131940906480412110010788196163251801856031320717166562814625140037254045293
Short name T766
Test name
Test status
Simulation time 978628843 ps
CPU time 13.81 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:37:11 PM PST 23
Peak memory 217364 kb
Host smart-b9c9ccfd-0a0d-4e16-8117-0273f4e7e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131940906480412110010788196163251801856031320717166562814625140037254045293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.lc_ctrl_errors.131940906480412110010788196163251801856031320717166562814625140037254045293
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.95427714938449962915287892453005604416589763011833861749172305387919620214443
Short name T931
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.47 seconds
Started Nov 22 01:36:57 PM PST 23
Finished Nov 22 01:37:11 PM PST 23
Peak memory 209004 kb
Host smart-80358ace-44c6-46bf-a63c-d7d4ab66f1fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95427714938449962915287892453005604416589763011833861749172305387919620214443 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.95427714938449962915287892453005604416589763011833861749172305387919620214443
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.77466126678496560313967098367217160632021529171237774450337398915139736556682
Short name T900
Test name
Test status
Simulation time 5872518263 ps
CPU time 42.6 seconds
Started Nov 22 01:36:55 PM PST 23
Finished Nov 22 01:37:43 PM PST 23
Peak memory 217764 kb
Host smart-d4afae59-0c19-4622-82e9-74c86df2fd0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77466126678496560313967098367217160632021529171237774450337398915139736556682 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_errors.77466126678496560313967098367217160632021529171237774450337398915139736556682
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.107979114344976681866716494793103664671981492903460155926718478366884820692694
Short name T803
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.35 seconds
Started Nov 22 01:36:58 PM PST 23
Finished Nov 22 01:37:15 PM PST 23
Peak memory 217364 kb
Host smart-5ae935cb-10d2-4356-b589-64d64cb91e74
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107979114344976681866716494793103664671981492903460155926718478366884820692694 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.107979114344976681866716494793103664671981492903460155926718478366884820692694
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.21821036591064739369354609068711591542625309018558393043185379969953718449739
Short name T671
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.05 seconds
Started Nov 22 01:36:58 PM PST 23
Finished Nov 22 01:37:13 PM PST 23
Peak memory 217436 kb
Host smart-b9b263f8-a184-4631-b3d5-6520914d6ebb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21821036591064739369354609068711591542625309018558393043185379969953718449739 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_prog_failure.21821036591064739369354609068711591542625309018558393043185379969953718449739
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.55850912780319140859645588114490592398769808196230303834706579574214243827043
Short name T420
Test name
Test status
Simulation time 1406053995 ps
CPU time 10.24 seconds
Started Nov 22 01:36:55 PM PST 23
Finished Nov 22 01:37:11 PM PST 23
Peak memory 212320 kb
Host smart-627cb317-37aa-4dd7-a847-e3245a667140
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55850912780319140859645588114490592398769808196230303834706579574214243827043 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_regwen_during_op.558509127803191408596455881144905923987698081962303038347
06579574214243827043
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.90605675981971865862188084483561088139753450625382677837469882142091166480429
Short name T91
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.69 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:10 PM PST 23
Peak memory 212892 kb
Host smart-c89e03ff-e38b-49ea-8363-7c10dc470da0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90605675981971865862188084483561088139753450625382677837469882142091166480429 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.90605675981971865862188084483561088139753450625382677837469882142091166480429
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.83531883478560551524964383595217529209381844472531932093148289301564694338556
Short name T452
Test name
Test status
Simulation time 5030489285 ps
CPU time 51.84 seconds
Started Nov 22 01:36:57 PM PST 23
Finished Nov 22 01:37:54 PM PST 23
Peak memory 268964 kb
Host smart-be0e5a65-69eb-492e-bec2-885e2192617c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83531883478560551524964383595217529209381844472531932093148289301564694338556 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_state_failure.835318834785605515249643835952175292093818444725319320931482893
01564694338556
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.37212084307859140156701676670288530118308138282296817258180534095992407148068
Short name T805
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.68 seconds
Started Nov 22 01:36:58 PM PST 23
Finished Nov 22 01:37:18 PM PST 23
Peak memory 246792 kb
Host smart-c6a865ab-d0d0-4dca-8dd4-a8668d4c0200
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37212084307859140156701676670288530118308138282296817258180534095992407148068 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_state_post_trans.372120843078591401567016766702885301183081382822968172581
80534095992407148068
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.66251667882021318314443910125065371432043709567072231955790365870896454576657
Short name T529
Test name
Test status
Simulation time 159313969 ps
CPU time 2.96 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 217376 kb
Host smart-2dae192f-0096-4c18-ae4a-a5b8ff85476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66251667882021318314443910125065371432043709567072231955790365870896454576657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_prog_failure.66251667882021318314443910125065371432043709567072231955790365870896454576657
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.7757249583091263261232260792781803016393224879764051855448202714317104613473
Short name T696
Test name
Test status
Simulation time 420615450 ps
CPU time 5.78 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 213356 kb
Host smart-77d64224-ee29-4314-80dd-662ac7d1e24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7757249583091263261232260792781803016393224879764051855448202714317104613473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.lc_ctrl_regwen_during_op.7757249583091263261232260792781803016393224879764051855448202714317104613473
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.25476895769451549406170960785295697272408222634420836893357735974954368327467
Short name T82
Test name
Test status
Simulation time 386472866 ps
CPU time 35.37 seconds
Started Nov 22 01:37:00 PM PST 23
Finished Nov 22 01:37:38 PM PST 23
Peak memory 273604 kb
Host smart-52d77d71-3716-4b31-a4e9-3c9c8ee318f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25476895769451549406170960785295697272408222634420836893357735974954368327467 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.25476895769451549406170960785295697272408222634420836893357735974954368327467
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.37991671921995921039737542979247924580607658224970481624660025790037161624611
Short name T289
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.23 seconds
Started Nov 22 01:36:57 PM PST 23
Finished Nov 22 01:37:16 PM PST 23
Peak memory 218392 kb
Host smart-c781b0da-a763-4fc9-8017-288b282c202a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37991671921995921039737542979247924580607658224970481624660025790037161624611 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.37991671921995921039737542979247924580607658224970481624660025790037161624611
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.39140828598707989377081932158862642457020392753316553505221807190568255750814
Short name T489
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.41 seconds
Started Nov 22 01:36:57 PM PST 23
Finished Nov 22 01:37:18 PM PST 23
Peak memory 217248 kb
Host smart-5c69c9b2-a056-4b8f-ae6c-c6c09d3d4838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39140828598707989377081932158862642457020392753316553505221807190568255750814 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_digest.39140828598707989377081932158862642457020392753316553505221807190568255750814
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.88923981275242870760523236634047514342967768034317644292493287067841753203190
Short name T905
Test name
Test status
Simulation time 964986095 ps
CPU time 11.58 seconds
Started Nov 22 01:36:58 PM PST 23
Finished Nov 22 01:37:13 PM PST 23
Peak memory 217296 kb
Host smart-12ab2e27-453c-4ce9-938b-ece8b99fc26e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88923981275242870760523236634047514342967768034317644292493287067841753203190 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.88923981275242870760523236634047514342967768034317644292493287067841753203190
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.25319623956261394115931910393856333567344710569744626204442200955598816051260
Short name T509
Test name
Test status
Simulation time 625328098 ps
CPU time 8.36 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:37:00 PM PST 23
Peak memory 217412 kb
Host smart-0477c255-76d8-413a-a105-7eda41401ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25319623956261394115931910393856333567344710569744626204442200955598816051260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.lc_ctrl_security_escalation.25319623956261394115931910393856333567344710569744626204442200955598816051260
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.110899546648842006563129581463174069355911211095775886325184240324390515650809
Short name T962
Test name
Test status
Simulation time 291295056 ps
CPU time 4.55 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 213836 kb
Host smart-1923bfbb-1a60-4817-acef-f832966709ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110899546648842006563129581463174069355911211095775886325184240324390515650809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_smoke.110899546648842006563129581463174069355911211095775886325184240324390515650809
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.49860520662864753779435168799406503889032446018043678617043459712396392249873
Short name T576
Test name
Test status
Simulation time 487150632 ps
CPU time 20.6 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:37:14 PM PST 23
Peak memory 250572 kb
Host smart-3dd8a073-4751-4d42-8128-3d033bb6e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49860520662864753779435168799406503889032446018043678617043459712396392249873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_state_failure.49860520662864753779435168799406503889032446018043678617043459712396392249873
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.74835510728195148979628947811107275166344684205404802171587874477599107275920
Short name T61
Test name
Test status
Simulation time 217117078 ps
CPU time 6.97 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:37:04 PM PST 23
Peak memory 246244 kb
Host smart-58767fae-5306-4d20-b981-b1d8babccaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74835510728195148979628947811107275166344684205404802171587874477599107275920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.lc_ctrl_state_post_trans.74835510728195148979628947811107275166344684205404802171587874477599107275920
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.53967900708521523395009724643971668721061298908876949786221441058004668324654
Short name T59
Test name
Test status
Simulation time 36820395678 ps
CPU time 285.81 seconds
Started Nov 22 01:37:02 PM PST 23
Finished Nov 22 01:41:49 PM PST 23
Peak memory 279436 kb
Host smart-b2bea3b8-f1c2-4de5-b2d9-017a5223b650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539679007085215233950097246439716687210612989088769497862214410580
04668324654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.539679007085215233950097246439716687210612989088769497862
21441058004668324654
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4335532778706226722945297606719529513961064609420247235048029810367590458139
Short name T275
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 207448 kb
Host smart-4677cbc7-aeea-4103-9c49-0993163be946
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4335532778706226722945297606719529513961064609420247235048029810367590458139 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_volatile_unlock_smoke.4335532778706226722945297606719529513961064609420247235
048029810367590458139
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.23596782788268617669318772302803975147232135872028466783636157095573759190413
Short name T605
Test name
Test status
Simulation time 42189906 ps
CPU time 0.98 seconds
Started Nov 22 01:38:15 PM PST 23
Finished Nov 22 01:38:22 PM PST 23
Peak memory 207460 kb
Host smart-fd2e9d6a-50dd-489b-b075-7756e4cb8c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23596782788268617669318772302803975147232135872028466783636157095573759190413 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.23596782788268617669318772302803975147232135872028466783636157095573759190413
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.66511704360714667520059598180371639252422194858842031049098343212367491435709
Short name T607
Test name
Test status
Simulation time 978628843 ps
CPU time 13.71 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 217292 kb
Host smart-759e71c8-0515-4503-844f-00b7760648e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66511704360714667520059598180371639252422194858842031049098343212367491435709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.lc_ctrl_errors.66511704360714667520059598180371639252422194858842031049098343212367491435709
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.105966622555169504861600636543206495190270277197422231298827478800832019617301
Short name T855
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.53 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 208988 kb
Host smart-61c0612a-e592-4c8e-9928-14290c19c0e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105966622555169504861600636543206495190270277197422231298827478800832019617301 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.105966622555169504861600636543206495190270277197422231298827478800832019617301
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.18605399221737855736259301680636370775492905899882156621998039624709472422139
Short name T869
Test name
Test status
Simulation time 159313969 ps
CPU time 3.01 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 217492 kb
Host smart-a6bc450a-217f-4c8d-9f68-2a89d293bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18605399221737855736259301680636370775492905899882156621998039624709472422139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.lc_ctrl_prog_failure.18605399221737855736259301680636370775492905899882156621998039624709472422139
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.106954860139047788193589697472941173290611758641715975306323439053052156596170
Short name T295
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.28 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 218504 kb
Host smart-87dc6168-9dd8-4294-8f0c-b21e9cc2d078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106954860139047788193589697472941173290611758641715975306323439053052156596170 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.106954860139047788193589697472941173290611758641715975306323439053052156596170
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.30118120120968159860301621292398059057500679123744793973500615634042715126976
Short name T473
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.15 seconds
Started Nov 22 01:38:11 PM PST 23
Finished Nov 22 01:38:33 PM PST 23
Peak memory 217344 kb
Host smart-845a05f0-e6bb-47d4-bf30-71f10eafab34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30118120120968159860301621292398059057500679123744793973500615634042715126976 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_digest.30118120120968159860301621292398059057500679123744793973500615634042715126976
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.275192060865021752295715778270508669367501468324989857061431333570690247974
Short name T656
Test name
Test status
Simulation time 964986095 ps
CPU time 10.76 seconds
Started Nov 22 01:38:15 PM PST 23
Finished Nov 22 01:38:31 PM PST 23
Peak memory 217136 kb
Host smart-13964ed3-6612-4fb9-9e82-bc0953a5401c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275192060865021752295715778270508669367501468324989857061431333570690247974 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.275192060865021752295715778270508669367501468324989857061431333570690247974
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.91897445047685345074931919785055235435326970282596254633655890149510334945542
Short name T273
Test name
Test status
Simulation time 625328098 ps
CPU time 8.06 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 217260 kb
Host smart-9bd1e891-50c3-4534-b5de-eb7645a5ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91897445047685345074931919785055235435326970282596254633655890149510334945542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.lc_ctrl_security_escalation.91897445047685345074931919785055235435326970282596254633655890149510334945542
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.104923415175470534422847175971206881900342107883343233818681748808173693725173
Short name T844
Test name
Test status
Simulation time 291295056 ps
CPU time 4.63 seconds
Started Nov 22 01:38:13 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 213692 kb
Host smart-01ad378e-d224-4580-893e-f7c7737f6dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104923415175470534422847175971206881900342107883343233818681748808173693725173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.lc_ctrl_smoke.104923415175470534422847175971206881900342107883343233818681748808173693725173
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.92377703952042527074706131658874521713470305266969544862805004408191253222234
Short name T534
Test name
Test status
Simulation time 487150632 ps
CPU time 20.31 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:39 PM PST 23
Peak memory 250240 kb
Host smart-12b35daa-e4e7-4ee0-bc76-60a2b9285046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92377703952042527074706131658874521713470305266969544862805004408191253222234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.lc_ctrl_state_failure.92377703952042527074706131658874521713470305266969544862805004408191253222234
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.21528172762881238031463982654938209996577303053267710060315245895961370438092
Short name T303
Test name
Test status
Simulation time 217117078 ps
CPU time 7.19 seconds
Started Nov 22 01:38:11 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 246276 kb
Host smart-08706e0f-8d26-4162-b8bc-b02ae2651bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21528172762881238031463982654938209996577303053267710060315245895961370438092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.lc_ctrl_state_post_trans.21528172762881238031463982654938209996577303053267710060315245895961370438092
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1591724211343968813510080876593688078938696758275356435296508286685730703612
Short name T349
Test name
Test status
Simulation time 36820395678 ps
CPU time 292.71 seconds
Started Nov 22 01:38:14 PM PST 23
Finished Nov 22 01:43:13 PM PST 23
Peak memory 279604 kb
Host smart-2fd8582e-b9d2-464f-8162-a72dcd662189
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159172421134396881351008087659368807893869675827535643529650828668
5730703612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.159172421134396881351008087659368807893869675827535643529
6508286685730703612
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.39318454237977958771495162363353876200172867642727462889667139739818921299513
Short name T427
Test name
Test status
Simulation time 16404398 ps
CPU time 0.71 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 207432 kb
Host smart-f4ec6ece-4517-457a-8d51-f5b6b6e7ebf1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39318454237977958771495162363353876200172867642727462889667139739818921299513 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_volatile_unlock_smoke.39318454237977958771495162363353876200172867642727462
889667139739818921299513
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.92108984804207393945033594453359855938789019548393827413665493295464066284976
Short name T848
Test name
Test status
Simulation time 42189906 ps
CPU time 0.94 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:07 PM PST 23
Peak memory 207632 kb
Host smart-f856d121-43a6-4e5a-83a8-93a3c20808eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92108984804207393945033594453359855938789019548393827413665493295464066284976 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.92108984804207393945033594453359855938789019548393827413665493295464066284976
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.90324368380216369876239824807321157035479462145072989088999589742152404806304
Short name T817
Test name
Test status
Simulation time 978628843 ps
CPU time 13.31 seconds
Started Nov 22 01:38:25 PM PST 23
Finished Nov 22 01:38:40 PM PST 23
Peak memory 217336 kb
Host smart-adef730f-a451-46cb-98de-f0a485ab2750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90324368380216369876239824807321157035479462145072989088999589742152404806304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.lc_ctrl_errors.90324368380216369876239824807321157035479462145072989088999589742152404806304
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.54478967125713385550269232274995188993230354051809446220593504422531675675680
Short name T32
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.14 seconds
Started Nov 22 01:38:17 PM PST 23
Finished Nov 22 01:38:31 PM PST 23
Peak memory 208972 kb
Host smart-332996f6-975f-4201-b941-11cfd76162b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54478967125713385550269232274995188993230354051809446220593504422531675675680 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.54478967125713385550269232274995188993230354051809446220593504422531675675680
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.106454306169782770636762692355568224264544166091803512344753811292719309943221
Short name T291
Test name
Test status
Simulation time 159313969 ps
CPU time 2.85 seconds
Started Nov 22 01:38:25 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217476 kb
Host smart-7c55c73a-6c6c-40e7-8572-4d25882db449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106454306169782770636762692355568224264544166091803512344753811292719309943221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.lc_ctrl_prog_failure.106454306169782770636762692355568224264544166091803512344753811292719309943221
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.93198919541321493015603147067981377910174503999056937527057868294332637979344
Short name T946
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.6 seconds
Started Nov 22 01:38:14 PM PST 23
Finished Nov 22 01:38:35 PM PST 23
Peak memory 218512 kb
Host smart-484434e6-4d1a-4a4c-b55e-b55c3268c2c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93198919541321493015603147067981377910174503999056937527057868294332637979344 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.93198919541321493015603147067981377910174503999056937527057868294332637979344
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.80861046057574418251216405848622260430170445378083534613499123161676610656565
Short name T704
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.76 seconds
Started Nov 22 01:38:32 PM PST 23
Finished Nov 22 01:38:50 PM PST 23
Peak memory 217400 kb
Host smart-13f6aaa4-fa71-46a1-b6cc-5e36436bb53c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80861046057574418251216405848622260430170445378083534613499123161676610656565 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_digest.80861046057574418251216405848622260430170445378083534613499123161676610656565
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.587739230202305223472820849165589724187756828046975266879082694035518132035
Short name T824
Test name
Test status
Simulation time 964986095 ps
CPU time 10.38 seconds
Started Nov 22 01:38:35 PM PST 23
Finished Nov 22 01:38:48 PM PST 23
Peak memory 216044 kb
Host smart-9f6cb28c-259b-4ae3-a95b-e3c2d3aa986b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587739230202305223472820849165589724187756828046975266879082694035518132035 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.587739230202305223472820849165589724187756828046975266879082694035518132035
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.90979662078419805899665973198160559230401290399287458074228527591925700757890
Short name T674
Test name
Test status
Simulation time 625328098 ps
CPU time 8.05 seconds
Started Nov 22 01:38:16 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217456 kb
Host smart-e138f2f0-b3f5-43e8-82e8-d65364fcfd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90979662078419805899665973198160559230401290399287458074228527591925700757890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.lc_ctrl_security_escalation.90979662078419805899665973198160559230401290399287458074228527591925700757890
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.27459913199328756452797412914314355949359283290435939869982547300770874968781
Short name T367
Test name
Test status
Simulation time 291295056 ps
CPU time 4.51 seconds
Started Nov 22 01:38:19 PM PST 23
Finished Nov 22 01:38:27 PM PST 23
Peak memory 213816 kb
Host smart-866ce727-b387-49ff-8e15-413b10cd577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27459913199328756452797412914314355949359283290435939869982547300770874968781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.lc_ctrl_smoke.27459913199328756452797412914314355949359283290435939869982547300770874968781
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.97388424115444580974644721449331495504909109153310325846108745502567762595777
Short name T741
Test name
Test status
Simulation time 487150632 ps
CPU time 21.03 seconds
Started Nov 22 01:38:25 PM PST 23
Finished Nov 22 01:38:47 PM PST 23
Peak memory 250376 kb
Host smart-ca083ce5-c105-4d2b-ab0f-69495c809606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97388424115444580974644721449331495504909109153310325846108745502567762595777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.lc_ctrl_state_failure.97388424115444580974644721449331495504909109153310325846108745502567762595777
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.19901632921260200422519173783945232968996279141324897331873086805972018222461
Short name T585
Test name
Test status
Simulation time 217117078 ps
CPU time 7.02 seconds
Started Nov 22 01:38:15 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 246008 kb
Host smart-2eeaf6ac-8e90-442d-81fe-f75594049dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19901632921260200422519173783945232968996279141324897331873086805972018222461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.lc_ctrl_state_post_trans.19901632921260200422519173783945232968996279141324897331873086805972018222461
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.38107048364736892818193307232881059809815618625867763268466212726908938532432
Short name T713
Test name
Test status
Simulation time 36820395678 ps
CPU time 285.45 seconds
Started Nov 22 01:38:47 PM PST 23
Finished Nov 22 01:43:33 PM PST 23
Peak memory 283472 kb
Host smart-52c53436-19eb-42fd-a6af-39518e40fdc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381070483647368928181933072328810598098156186258677632684662127269
08938532432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.38107048364736892818193307232881059809815618625867763268
466212726908938532432
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.30850409326435846821935983434818735863338542573808387167477603267889453675238
Short name T636
Test name
Test status
Simulation time 16404398 ps
CPU time 0.7 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 207232 kb
Host smart-5685ffb7-a663-4013-ab24-6ca7a12f1601
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30850409326435846821935983434818735863338542573808387167477603267889453675238 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_volatile_unlock_smoke.30850409326435846821935983434818735863338542573808387
167477603267889453675238
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.102993858741596089323484538119843563013268264759949395723286234972347307793133
Short name T831
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 207728 kb
Host smart-9facde87-5975-4941-a6b5-d64656808b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102993858741596089323484538119843563013268264759949395723286234972347307793133 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.102993858741596089323484538119843563013268264759949395723286234972347307793133
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.11462620830314131880700703454946756364835845809069925043211944956350536340219
Short name T297
Test name
Test status
Simulation time 978628843 ps
CPU time 13.65 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 217400 kb
Host smart-6ac9d5e2-ae78-4ec7-91a8-7ba5ee2b6fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11462620830314131880700703454946756364835845809069925043211944956350536340219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.lc_ctrl_errors.11462620830314131880700703454946756364835845809069925043211944956350536340219
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.18551591041172170016129055612364578610404595898248204576579224275202996616423
Short name T497
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.14 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 208944 kb
Host smart-2add43cb-7d76-49d1-adea-909fd990ac03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18551591041172170016129055612364578610404595898248204576579224275202996616423 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.18551591041172170016129055612364578610404595898248204576579224275202996616423
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.15143590717479329355407632248815598767815570747692865798115991095659067112901
Short name T369
Test name
Test status
Simulation time 159313969 ps
CPU time 3.06 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 217356 kb
Host smart-3f636dc5-dbc9-42df-97ea-802ea2c0e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15143590717479329355407632248815598767815570747692865798115991095659067112901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.lc_ctrl_prog_failure.15143590717479329355407632248815598767815570747692865798115991095659067112901
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.98290377029014869536266858691753010607693358246357103675404879585425131850621
Short name T572
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.12 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 218480 kb
Host smart-819e3fd7-ac0b-4fe3-bd1a-12608e4cda19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98290377029014869536266858691753010607693358246357103675404879585425131850621 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.98290377029014869536266858691753010607693358246357103675404879585425131850621
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.62862826073205128963468350465985230312101431534434765815457901372065993792328
Short name T274
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.92 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 217396 kb
Host smart-db05ade7-ca91-49d1-9b0c-0fd2aabf518d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62862826073205128963468350465985230312101431534434765815457901372065993792328 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_digest.62862826073205128963468350465985230312101431534434765815457901372065993792328
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.48107559432000584961355129661027946582533170773755828909236448923447918983932
Short name T910
Test name
Test status
Simulation time 964986095 ps
CPU time 10.74 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 217344 kb
Host smart-ba145a69-35e9-4741-960e-c6a970533be8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48107559432000584961355129661027946582533170773755828909236448923447918983932 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.48107559432000584961355129661027946582533170773755828909236448923447918983932
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.33317560844619176798740497950265297629791158363848427422413098724189508846745
Short name T582
Test name
Test status
Simulation time 625328098 ps
CPU time 8.08 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 217456 kb
Host smart-e4a6707b-a128-4d5a-922a-e4332ea6e52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33317560844619176798740497950265297629791158363848427422413098724189508846745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.lc_ctrl_security_escalation.33317560844619176798740497950265297629791158363848427422413098724189508846745
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.101128164553727232864010509108541977071178120874092667160006147416067424538602
Short name T809
Test name
Test status
Simulation time 291295056 ps
CPU time 4.32 seconds
Started Nov 22 01:38:35 PM PST 23
Finished Nov 22 01:38:42 PM PST 23
Peak memory 212612 kb
Host smart-4c021076-2a87-48dc-ad66-59ed339fba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101128164553727232864010509108541977071178120874092667160006147416067424538602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.lc_ctrl_smoke.101128164553727232864010509108541977071178120874092667160006147416067424538602
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.77079796652866576229766326392377504351600256632836887935369766173533528321626
Short name T368
Test name
Test status
Simulation time 487150632 ps
CPU time 20.8 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 250472 kb
Host smart-5b3fc56e-f983-4070-802f-bb8071d400f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77079796652866576229766326392377504351600256632836887935369766173533528321626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.lc_ctrl_state_failure.77079796652866576229766326392377504351600256632836887935369766173533528321626
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.29739006679865741871704538453728916546882130600761059490302117437666417300896
Short name T707
Test name
Test status
Simulation time 217117078 ps
CPU time 6.91 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 246276 kb
Host smart-56e5791f-537f-404d-af24-121ee41de8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29739006679865741871704538453728916546882130600761059490302117437666417300896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.lc_ctrl_state_post_trans.29739006679865741871704538453728916546882130600761059490302117437666417300896
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.21936377352393393842186187379849282433947027698868457485132820182421979942440
Short name T590
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.38 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:42:50 PM PST 23
Peak memory 283456 kb
Host smart-b79e3d8e-e53f-4de3-83da-c5be80295ad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219363773523933938421861873798492824339470276988684574851328201824
21979942440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.21936377352393393842186187379849282433947027698868457485
132820182421979942440
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.101362784849201173647494771569637285991665028635639151627129182067982139075261
Short name T680
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:38:33 PM PST 23
Finished Nov 22 01:38:34 PM PST 23
Peak memory 207588 kb
Host smart-251ee6c5-ee98-4c96-8f6d-28de2a858ddf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101362784849201173647494771569637285991665028635639151627129182067982139075261 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_volatile_unlock_smoke.1013627848492011736474947715696372859916650286356391
51627129182067982139075261
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.84279667181421986354468402113845338613854640895558242387274043409627608698468
Short name T67
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 207776 kb
Host smart-b921f870-266e-4f75-b52e-9f85ebd262f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84279667181421986354468402113845338613854640895558242387274043409627608698468 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.84279667181421986354468402113845338613854640895558242387274043409627608698468
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.107545693213650512912836481491247517456811522865016630385602464746026382098013
Short name T649
Test name
Test status
Simulation time 978628843 ps
CPU time 13.84 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 217320 kb
Host smart-dfa9b4a3-c6b5-46c1-898e-9d9624f7a81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107545693213650512912836481491247517456811522865016630385602464746026382098013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.lc_ctrl_errors.107545693213650512912836481491247517456811522865016630385602464746026382098013
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.62746338540523284009904337472730352099230314904060143442999402985642786050745
Short name T725
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.11 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 208844 kb
Host smart-02f5b1d4-1185-4d2c-bb61-2e92822b1ee6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62746338540523284009904337472730352099230314904060143442999402985642786050745 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.62746338540523284009904337472730352099230314904060143442999402985642786050745
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.14618477353141124871087178211909672867692981119900546600300892535725787279961
Short name T443
Test name
Test status
Simulation time 159313969 ps
CPU time 2.89 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 217328 kb
Host smart-3c76046a-335c-41f3-bdb5-991692246733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14618477353141124871087178211909672867692981119900546600300892535725787279961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.lc_ctrl_prog_failure.14618477353141124871087178211909672867692981119900546600300892535725787279961
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.87075067686415418779320252187201099258622546466162563217166569297751066239712
Short name T765
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.04 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 218540 kb
Host smart-7cdb28d2-dae2-476b-a08c-2a80dcff4e3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87075067686415418779320252187201099258622546466162563217166569297751066239712 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.87075067686415418779320252187201099258622546466162563217166569297751066239712
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.25330911626584990020684366617516935736253764406581894587142167341636367240002
Short name T505
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.5 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217264 kb
Host smart-3313155f-051d-41e2-a40a-a511d5127cc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25330911626584990020684366617516935736253764406581894587142167341636367240002 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_digest.25330911626584990020684366617516935736253764406581894587142167341636367240002
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.13430116357295307588625242616454758013407241364543979445423120436328040274946
Short name T603
Test name
Test status
Simulation time 964986095 ps
CPU time 10.47 seconds
Started Nov 22 01:38:11 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 217456 kb
Host smart-aff848bf-158b-473c-a5e4-c21a1000e260
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13430116357295307588625242616454758013407241364543979445423120436328040274946 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.13430116357295307588625242616454758013407241364543979445423120436328040274946
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.181910549976511657203571230624806922638795227640174628175696557025899287920
Short name T728
Test name
Test status
Simulation time 625328098 ps
CPU time 8.15 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 217300 kb
Host smart-94a60644-1da5-4f7b-b541-f7549a89fce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181910549976511657203571230624806922638795227640174628175696557025899287920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.lc_ctrl_security_escalation.181910549976511657203571230624806922638795227640174628175696557025899287920
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.75215520292421663780008580399187592813378710041437119035236260113598027921015
Short name T553
Test name
Test status
Simulation time 291295056 ps
CPU time 4.8 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 213708 kb
Host smart-076fe249-f927-45c5-b5ff-cff6179ebcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75215520292421663780008580399187592813378710041437119035236260113598027921015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.lc_ctrl_smoke.75215520292421663780008580399187592813378710041437119035236260113598027921015
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.108638128172923645203528091817615064509511157304246089109965609061055724800873
Short name T380
Test name
Test status
Simulation time 487150632 ps
CPU time 20.69 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 250288 kb
Host smart-62213049-f693-4285-8e69-ac82838f73f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108638128172923645203528091817615064509511157304246089109965609061055724800873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.lc_ctrl_state_failure.108638128172923645203528091817615064509511157304246089109965609061055724800873
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.71497562606874655891258992600515398033656946328568069420585662101466251830621
Short name T783
Test name
Test status
Simulation time 217117078 ps
CPU time 7.07 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 246344 kb
Host smart-56e106e3-5304-4b49-9218-f45e0562839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71497562606874655891258992600515398033656946328568069420585662101466251830621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.lc_ctrl_state_post_trans.71497562606874655891258992600515398033656946328568069420585662101466251830621
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.96158706594377499629253611194601553656721256835686471549574631900015416220263
Short name T441
Test name
Test status
Simulation time 36820395678 ps
CPU time 280.7 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:42:57 PM PST 23
Peak memory 283496 kb
Host smart-8d69f819-2495-4d53-8c6b-78dc4a49d35d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961587065943774996292536111946015536567212568356864715495746319000
15416220263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.96158706594377499629253611194601553656721256835686471549
574631900015416220263
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.6662223621944847464493554665905923955574947429028586398209992940163968527879
Short name T499
Test name
Test status
Simulation time 16404398 ps
CPU time 0.7 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:00 PM PST 23
Peak memory 207508 kb
Host smart-207c84c7-44f2-4f22-a99e-88b38f568548
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6662223621944847464493554665905923955574947429028586398209992940163968527879 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_volatile_unlock_smoke.666222362194484746449355466590592395557494742902858639
8209992940163968527879
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.75517614143125618059139957385879633713647742599910207313558700525229433463395
Short name T902
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 207732 kb
Host smart-6f2dee2e-a284-43f2-aa0f-f21948fd4abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75517614143125618059139957385879633713647742599910207313558700525229433463395 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.75517614143125618059139957385879633713647742599910207313558700525229433463395
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.110803835903379062574167893730255011705245517548808939713424304689834957671968
Short name T316
Test name
Test status
Simulation time 978628843 ps
CPU time 13.96 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217448 kb
Host smart-b4777a93-0217-45e4-8302-f73474e4545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110803835903379062574167893730255011705245517548808939713424304689834957671968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.lc_ctrl_errors.110803835903379062574167893730255011705245517548808939713424304689834957671968
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.103761413965539931102737786049285893842998713068775538368943618686352994917180
Short name T34
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.43 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 208792 kb
Host smart-f78c67c9-f145-4248-9b2f-1c36e5f46f42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103761413965539931102737786049285893842998713068775538368943618686352994917180 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.103761413965539931102737786049285893842998713068775538368943618686352994917180
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.79883377596909626025756287214167986254292969776143786561611296850867355912503
Short name T863
Test name
Test status
Simulation time 159313969 ps
CPU time 2.85 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 217456 kb
Host smart-9cb6868a-fc42-49b7-a140-df4a7dcfc2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79883377596909626025756287214167986254292969776143786561611296850867355912503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.lc_ctrl_prog_failure.79883377596909626025756287214167986254292969776143786561611296850867355912503
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.78804541881105403380860081471671880218754708668008499417941347190945086801938
Short name T432
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.01 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 218444 kb
Host smart-8c034850-bb25-45fc-a1a1-b72ecb2ac504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78804541881105403380860081471671880218754708668008499417941347190945086801938 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.78804541881105403380860081471671880218754708668008499417941347190945086801938
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.68684033272433085559172407098305419572858359929443857319797996728700442299346
Short name T853
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.51 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:33 PM PST 23
Peak memory 217344 kb
Host smart-6874ed61-8437-4b78-b299-fbd160c83566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68684033272433085559172407098305419572858359929443857319797996728700442299346 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_digest.68684033272433085559172407098305419572858359929443857319797996728700442299346
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.74697101264450460365900466286634351800791016212871311844251261394107429092659
Short name T764
Test name
Test status
Simulation time 964986095 ps
CPU time 11.65 seconds
Started Nov 22 01:38:15 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 217140 kb
Host smart-e1b8c035-3678-4259-8db7-9202b2b68aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74697101264450460365900466286634351800791016212871311844251261394107429092659 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.74697101264450460365900466286634351800791016212871311844251261394107429092659
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.23989363272588144604119903947963034170246135457594546803146262093038206204594
Short name T595
Test name
Test status
Simulation time 625328098 ps
CPU time 8.33 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 217436 kb
Host smart-691bc7f3-0e6e-429e-aefd-53c26a820533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23989363272588144604119903947963034170246135457594546803146262093038206204594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.lc_ctrl_security_escalation.23989363272588144604119903947963034170246135457594546803146262093038206204594
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.15661556482422881484969695832222627565998484187610531661742826620978779096890
Short name T628
Test name
Test status
Simulation time 291295056 ps
CPU time 4.7 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 213856 kb
Host smart-b8da7784-51c2-4ad4-af32-9fbfd4b67601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15661556482422881484969695832222627565998484187610531661742826620978779096890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.lc_ctrl_smoke.15661556482422881484969695832222627565998484187610531661742826620978779096890
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.68406428287906888695063632663361205986850457417899392121811560176414944340546
Short name T428
Test name
Test status
Simulation time 487150632 ps
CPU time 20.82 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:36 PM PST 23
Peak memory 250448 kb
Host smart-2a464cbe-0628-41cd-ac74-2e8b79b7ff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68406428287906888695063632663361205986850457417899392121811560176414944340546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.lc_ctrl_state_failure.68406428287906888695063632663361205986850457417899392121811560176414944340546
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.108380530886068378809253221977173987923815361958943748302230749205894206314093
Short name T401
Test name
Test status
Simulation time 217117078 ps
CPU time 7.35 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 246372 kb
Host smart-6a995717-07b4-44f4-8c67-64e200638713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108380530886068378809253221977173987923815361958943748302230749205894206314093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.lc_ctrl_state_post_trans.108380530886068378809253221977173987923815361958943748302230749205894206314093
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.35026352584887424325819382874363817345395652162483844881807428551037536990687
Short name T604
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.2 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:42:53 PM PST 23
Peak memory 283216 kb
Host smart-39f7fe9b-ce53-4e2d-8486-b62fa1ca9955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350263525848874243258193828743638173453956521624838448818074285510
37536990687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all.35026352584887424325819382874363817345395652162483844881
807428551037536990687
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.86470483080094338796606037109822721242708752651057372702995355180835099459866
Short name T740
Test name
Test status
Simulation time 16404398 ps
CPU time 0.71 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 207432 kb
Host smart-34767d86-6829-48f8-aa6e-2d363cf858d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86470483080094338796606037109822721242708752651057372702995355180835099459866 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_volatile_unlock_smoke.86470483080094338796606037109822721242708752651057372
702995355180835099459866
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.53226843392061003416382857805705441152480682854993792323988067670604285033253
Short name T323
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:16 PM PST 23
Peak memory 207736 kb
Host smart-83c851bb-9ef8-47ab-9b0f-5a937b79ec47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53226843392061003416382857805705441152480682854993792323988067670604285033253 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.53226843392061003416382857805705441152480682854993792323988067670604285033253
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.98527575980218647267982761300100752442065912676555108609614519862238835520149
Short name T688
Test name
Test status
Simulation time 978628843 ps
CPU time 13.69 seconds
Started Nov 22 01:38:25 PM PST 23
Finished Nov 22 01:38:40 PM PST 23
Peak memory 217468 kb
Host smart-581814a8-0edf-406d-98c3-72b7aebf1c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98527575980218647267982761300100752442065912676555108609614519862238835520149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.lc_ctrl_errors.98527575980218647267982761300100752442065912676555108609614519862238835520149
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.76600492175109393203563115580503729756420618164139686372289267088003235302886
Short name T406
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.4 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 209012 kb
Host smart-e0e4cb34-7fd8-4c22-bcdc-16c62e0bca27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76600492175109393203563115580503729756420618164139686372289267088003235302886 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.76600492175109393203563115580503729756420618164139686372289267088003235302886
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.54068951083857779420692628101882142805074885992467624337545390803265853659056
Short name T784
Test name
Test status
Simulation time 159313969 ps
CPU time 2.83 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 217492 kb
Host smart-14dc7706-16c5-425c-b7b5-d8ed5254dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54068951083857779420692628101882142805074885992467624337545390803265853659056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.lc_ctrl_prog_failure.54068951083857779420692628101882142805074885992467624337545390803265853659056
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.50135766286190474441608178151839677121124820526359032241329493654203791972252
Short name T951
Test name
Test status
Simulation time 1010128591 ps
CPU time 16.52 seconds
Started Nov 22 01:38:31 PM PST 23
Finished Nov 22 01:38:49 PM PST 23
Peak memory 218484 kb
Host smart-e0facb0b-b03e-4e38-a187-85183a584020
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50135766286190474441608178151839677121124820526359032241329493654203791972252 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.50135766286190474441608178151839677121124820526359032241329493654203791972252
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.98383689729418322052329019359868882021692256105103484869421346076431599923035
Short name T140
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.61 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:26 PM PST 23
Peak memory 217392 kb
Host smart-2f5c89f9-f4a1-4570-a5fb-9b9ff1e716d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98383689729418322052329019359868882021692256105103484869421346076431599923035 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_digest.98383689729418322052329019359868882021692256105103484869421346076431599923035
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.6394421229163898467714144469189131866190858577568516371896765224173631123322
Short name T763
Test name
Test status
Simulation time 964986095 ps
CPU time 10.95 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 217272 kb
Host smart-1490cabe-aefc-460d-b3d7-80efe3fbc17e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6394421229163898467714144469189131866190858577568516371896765224173631123322 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.6394421229163898467714144469189131866190858577568516371896765224173631123322
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.95388758901182309340745915850478934138798704040121178762335590388512549258086
Short name T638
Test name
Test status
Simulation time 625328098 ps
CPU time 8.52 seconds
Started Nov 22 01:38:15 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217456 kb
Host smart-5425e845-f9ee-4134-88e7-83f07fda385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95388758901182309340745915850478934138798704040121178762335590388512549258086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.lc_ctrl_security_escalation.95388758901182309340745915850478934138798704040121178762335590388512549258086
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.60515390614963972567073172370553149461388859767369383473289844576901838658461
Short name T826
Test name
Test status
Simulation time 291295056 ps
CPU time 4.64 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 213784 kb
Host smart-eee8081a-21f8-45dd-92fc-c2e64fe10b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60515390614963972567073172370553149461388859767369383473289844576901838658461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.lc_ctrl_smoke.60515390614963972567073172370553149461388859767369383473289844576901838658461
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.49298689297396079716174778237263069283800341904553288941672572649792756509656
Short name T550
Test name
Test status
Simulation time 487150632 ps
CPU time 21.27 seconds
Started Nov 22 01:38:32 PM PST 23
Finished Nov 22 01:38:54 PM PST 23
Peak memory 250456 kb
Host smart-c3a3bafe-201f-4143-b080-dd7e9a226522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49298689297396079716174778237263069283800341904553288941672572649792756509656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.lc_ctrl_state_failure.49298689297396079716174778237263069283800341904553288941672572649792756509656
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.66811608405564482274764910152423575888915314273295592419227607607022880882952
Short name T944
Test name
Test status
Simulation time 217117078 ps
CPU time 7.43 seconds
Started Nov 22 01:38:04 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 246304 kb
Host smart-62c12cf1-3e99-4758-a250-3b878e748a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66811608405564482274764910152423575888915314273295592419227607607022880882952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.lc_ctrl_state_post_trans.66811608405564482274764910152423575888915314273295592419227607607022880882952
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.45406834096517024951339254230078840829687878238580845142297696540209212852733
Short name T393
Test name
Test status
Simulation time 36820395678 ps
CPU time 280.87 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:42:47 PM PST 23
Peak memory 283280 kb
Host smart-88992d9f-58a7-47b7-ae5d-e29028928ce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454068340965170249513392542300788408296878782385808451422976965402
09212852733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.45406834096517024951339254230078840829687878238580845142
297696540209212852733
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.87119891721717032562142995035356994192944950835237576161004994623390079579638
Short name T735
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 207524 kb
Host smart-217833e5-5642-4faf-9df9-339f8965cfa1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87119891721717032562142995035356994192944950835237576161004994623390079579638 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_volatile_unlock_smoke.87119891721717032562142995035356994192944950835237576
161004994623390079579638
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.71903777194930883131863178386887249690281278650543043768923602580611485850246
Short name T972
Test name
Test status
Simulation time 42189906 ps
CPU time 0.96 seconds
Started Nov 22 01:38:17 PM PST 23
Finished Nov 22 01:38:22 PM PST 23
Peak memory 207696 kb
Host smart-c7db217b-74fe-431f-b1ca-5f00980db131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71903777194930883131863178386887249690281278650543043768923602580611485850246 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.71903777194930883131863178386887249690281278650543043768923602580611485850246
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.101659526562923216015599706593861009034762959916727994638489189164298200885084
Short name T892
Test name
Test status
Simulation time 978628843 ps
CPU time 13.85 seconds
Started Nov 22 01:38:19 PM PST 23
Finished Nov 22 01:38:36 PM PST 23
Peak memory 217368 kb
Host smart-c2d6e2ad-208f-4990-9cbf-625e030bd3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101659526562923216015599706593861009034762959916727994638489189164298200885084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.lc_ctrl_errors.101659526562923216015599706593861009034762959916727994638489189164298200885084
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.73919973117771927867761083998354832783802697619758958088025564252557215017501
Short name T8
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.22 seconds
Started Nov 22 01:38:27 PM PST 23
Finished Nov 22 01:38:37 PM PST 23
Peak memory 208960 kb
Host smart-4925cabe-fe3a-4845-ab9e-c51a7c3a0334
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73919973117771927867761083998354832783802697619758958088025564252557215017501 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.73919973117771927867761083998354832783802697619758958088025564252557215017501
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.22202562498714496611648356863807354917533433323622140570231282490508351628451
Short name T683
Test name
Test status
Simulation time 159313969 ps
CPU time 2.94 seconds
Started Nov 22 01:38:24 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217380 kb
Host smart-3d8376ca-6349-414e-85c8-e29338e41b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22202562498714496611648356863807354917533433323622140570231282490508351628451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.lc_ctrl_prog_failure.22202562498714496611648356863807354917533433323622140570231282490508351628451
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.45186038447924484710530903324114749818421983669603260870255233118215518849134
Short name T371
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.18 seconds
Started Nov 22 01:38:25 PM PST 23
Finished Nov 22 01:38:40 PM PST 23
Peak memory 218396 kb
Host smart-3337a59c-3052-4d66-a9a5-1eddfa6dc764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45186038447924484710530903324114749818421983669603260870255233118215518849134 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.45186038447924484710530903324114749818421983669603260870255233118215518849134
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.90612059221332389266805345298327442437150069348831522760350495673901938442104
Short name T492
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.08 seconds
Started Nov 22 01:38:11 PM PST 23
Finished Nov 22 01:38:33 PM PST 23
Peak memory 217276 kb
Host smart-d3dfefb5-21a0-4c0d-9605-03c3a366bb10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90612059221332389266805345298327442437150069348831522760350495673901938442104 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_digest.90612059221332389266805345298327442437150069348831522760350495673901938442104
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.86918676753713593452892693759243397158057651735301256802877276772035954342302
Short name T706
Test name
Test status
Simulation time 964986095 ps
CPU time 11.26 seconds
Started Nov 22 01:38:16 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 217408 kb
Host smart-e37cfddc-1861-4700-85e3-c3853fbc1f86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86918676753713593452892693759243397158057651735301256802877276772035954342302 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.86918676753713593452892693759243397158057651735301256802877276772035954342302
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.73965070807167410098003931651147947847553931528174619394697936830113239947905
Short name T346
Test name
Test status
Simulation time 625328098 ps
CPU time 8.69 seconds
Started Nov 22 01:38:14 PM PST 23
Finished Nov 22 01:38:29 PM PST 23
Peak memory 217496 kb
Host smart-04d69d83-71e4-49b6-b2d3-4986ff7bef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73965070807167410098003931651147947847553931528174619394697936830113239947905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.lc_ctrl_security_escalation.73965070807167410098003931651147947847553931528174619394697936830113239947905
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.88472332721606795123750644563900217707804553341128243103922842554820419872628
Short name T355
Test name
Test status
Simulation time 291295056 ps
CPU time 4.58 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 213860 kb
Host smart-db7e1131-15fb-4ece-91c0-645fcbb93da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88472332721606795123750644563900217707804553341128243103922842554820419872628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.lc_ctrl_smoke.88472332721606795123750644563900217707804553341128243103922842554820419872628
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.95621670731584329806705550087777646639492930096338050340526163465101751587043
Short name T841
Test name
Test status
Simulation time 487150632 ps
CPU time 21.31 seconds
Started Nov 22 01:38:31 PM PST 23
Finished Nov 22 01:38:53 PM PST 23
Peak memory 250452 kb
Host smart-96e1953c-400c-4d40-b590-e9c76ace7b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95621670731584329806705550087777646639492930096338050340526163465101751587043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.lc_ctrl_state_failure.95621670731584329806705550087777646639492930096338050340526163465101751587043
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.92314124141923008867188374037490931430585565364573821540233573095923267374083
Short name T643
Test name
Test status
Simulation time 217117078 ps
CPU time 6.98 seconds
Started Nov 22 01:38:28 PM PST 23
Finished Nov 22 01:38:37 PM PST 23
Peak memory 246364 kb
Host smart-9156168d-48d0-4b46-99b4-78f4b3f01dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92314124141923008867188374037490931430585565364573821540233573095923267374083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.lc_ctrl_state_post_trans.92314124141923008867188374037490931430585565364573821540233573095923267374083
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.100185882327426370847527505637189204408398060631505411752735946599279414825220
Short name T521
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.22 seconds
Started Nov 22 01:38:18 PM PST 23
Finished Nov 22 01:43:05 PM PST 23
Peak memory 283056 kb
Host smart-0a3c479a-9ff5-48a4-9fa1-b5d26e3b37a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100185882327426370847527505637189204408398060631505411752735946599
279414825220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.1001858823274263708475275056371892044083980606315054117
52735946599279414825220
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.89328570497525705036125081761587729356597751299040113085896095571323065548247
Short name T973
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:38:17 PM PST 23
Finished Nov 22 01:38:22 PM PST 23
Peak memory 207580 kb
Host smart-9743cb7c-3174-411c-8711-d885b10e7792
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89328570497525705036125081761587729356597751299040113085896095571323065548247 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_volatile_unlock_smoke.89328570497525705036125081761587729356597751299040113
085896095571323065548247
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.60216546762997143451531964246022858683316200123178279351993542704447678514921
Short name T307
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:10 PM PST 23
Peak memory 207736 kb
Host smart-33aae58f-a52f-486f-a104-03580ecbc255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60216546762997143451531964246022858683316200123178279351993542704447678514921 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.60216546762997143451531964246022858683316200123178279351993542704447678514921
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.58642043145584273501310501305159589867592989841693735485789726472361841220996
Short name T647
Test name
Test status
Simulation time 978628843 ps
CPU time 15.58 seconds
Started Nov 22 01:38:24 PM PST 23
Finished Nov 22 01:38:41 PM PST 23
Peak memory 217456 kb
Host smart-e252a183-7df8-46ba-85e8-45c28ae46bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58642043145584273501310501305159589867592989841693735485789726472361841220996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.lc_ctrl_errors.58642043145584273501310501305159589867592989841693735485789726472361841220996
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.50639066066483443302959069041648270327855115960556448037117894749272590604759
Short name T804
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.57 seconds
Started Nov 22 01:38:18 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 208724 kb
Host smart-8775ea75-43c2-4533-929a-2ef214d042e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50639066066483443302959069041648270327855115960556448037117894749272590604759 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.50639066066483443302959069041648270327855115960556448037117894749272590604759
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.11106456094283534148473223753874598218643964826577343233616083803133046722912
Short name T1
Test name
Test status
Simulation time 159313969 ps
CPU time 2.91 seconds
Started Nov 22 01:38:17 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 217200 kb
Host smart-ed59a2e4-3ed5-4b90-83a2-b1d754417c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11106456094283534148473223753874598218643964826577343233616083803133046722912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.lc_ctrl_prog_failure.11106456094283534148473223753874598218643964826577343233616083803133046722912
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.81884833535402709924451994223035863107384654297623815577795236653598434066312
Short name T884
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.49 seconds
Started Nov 22 01:38:18 PM PST 23
Finished Nov 22 01:38:37 PM PST 23
Peak memory 218200 kb
Host smart-5a56d84a-8ded-4d13-8b40-0e73d30db5f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81884833535402709924451994223035863107384654297623815577795236653598434066312 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.81884833535402709924451994223035863107384654297623815577795236653598434066312
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.81018199415757173781186965880760945197639260242054866201647562569642336362403
Short name T374
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.42 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 217336 kb
Host smart-702d7c06-ac44-4ed9-8249-c3b38522e163
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81018199415757173781186965880760945197639260242054866201647562569642336362403 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_digest.81018199415757173781186965880760945197639260242054866201647562569642336362403
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.76063068359083016395138444004419716141074067785185212837636097487660806539714
Short name T873
Test name
Test status
Simulation time 964986095 ps
CPU time 11.4 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 217392 kb
Host smart-05c1c7b9-02f4-4b27-9dce-f3bda0ee5d86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76063068359083016395138444004419716141074067785185212837636097487660806539714 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.76063068359083016395138444004419716141074067785185212837636097487660806539714
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.66668748676003863033912909582675043724289797625926286089775661877789846744026
Short name T574
Test name
Test status
Simulation time 625328098 ps
CPU time 8.56 seconds
Started Nov 22 01:38:13 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 217468 kb
Host smart-b39c0871-18d3-40a3-ae9f-127ced643ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66668748676003863033912909582675043724289797625926286089775661877789846744026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.lc_ctrl_security_escalation.66668748676003863033912909582675043724289797625926286089775661877789846744026
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.101016671178429168382684093022762370187417880474827771226148279434220216273704
Short name T433
Test name
Test status
Simulation time 291295056 ps
CPU time 4.79 seconds
Started Nov 22 01:38:24 PM PST 23
Finished Nov 22 01:38:31 PM PST 23
Peak memory 213852 kb
Host smart-d463d480-938d-4d43-895b-8eda3b832824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101016671178429168382684093022762370187417880474827771226148279434220216273704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.lc_ctrl_smoke.101016671178429168382684093022762370187417880474827771226148279434220216273704
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.75902629283502904829205095767428110780688322742094929026879253805285684834904
Short name T281
Test name
Test status
Simulation time 487150632 ps
CPU time 21.04 seconds
Started Nov 22 01:38:26 PM PST 23
Finished Nov 22 01:38:48 PM PST 23
Peak memory 250416 kb
Host smart-99176903-4083-44fb-a4ae-a100ddf81841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75902629283502904829205095767428110780688322742094929026879253805285684834904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.lc_ctrl_state_failure.75902629283502904829205095767428110780688322742094929026879253805285684834904
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.34500704137456858085905607437072290929644334946163270233888471525148264101896
Short name T356
Test name
Test status
Simulation time 217117078 ps
CPU time 7.09 seconds
Started Nov 22 01:38:13 PM PST 23
Finished Nov 22 01:38:27 PM PST 23
Peak memory 246324 kb
Host smart-f8a881f0-5040-40ba-aa17-636ecb08e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34500704137456858085905607437072290929644334946163270233888471525148264101896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.lc_ctrl_state_post_trans.34500704137456858085905607437072290929644334946163270233888471525148264101896
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.30146729380868588774936165940296871549309724529267671382406575523651215237979
Short name T836
Test name
Test status
Simulation time 36820395678 ps
CPU time 281.49 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:43:50 PM PST 23
Peak memory 283360 kb
Host smart-31c2d94d-358c-40bd-b35b-623925ff55da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301467293808685887749361659402968715493097245292676713824065755236
51215237979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.30146729380868588774936165940296871549309724529267671382
406575523651215237979
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1831017098744655582524527683221052008884958355846852866115961885393962665186
Short name T522
Test name
Test status
Simulation time 16404398 ps
CPU time 0.81 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 207560 kb
Host smart-789c10ce-1628-4d59-9c63-adc9917d3444
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831017098744655582524527683221052008884958355846852866115961885393962665186 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_volatile_unlock_smoke.183101709874465558252452768322105200888495835584685286
6115961885393962665186
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.96820766381751485980732200591748388292932589466436710396151133625813037987122
Short name T965
Test name
Test status
Simulation time 42189906 ps
CPU time 0.97 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:07 PM PST 23
Peak memory 207712 kb
Host smart-a5f337aa-7769-4ff0-a2dd-352fb6e02c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96820766381751485980732200591748388292932589466436710396151133625813037987122 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.96820766381751485980732200591748388292932589466436710396151133625813037987122
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.10354815674681159661024958956250389044487596555624644476912322524847497372378
Short name T829
Test name
Test status
Simulation time 978628843 ps
CPU time 14.39 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:23 PM PST 23
Peak memory 217392 kb
Host smart-b990ff6f-017e-4019-945a-0fd8814b782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10354815674681159661024958956250389044487596555624644476912322524847497372378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.lc_ctrl_errors.10354815674681159661024958956250389044487596555624644476912322524847497372378
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.89389511349398648731192375578663150231231540200458419936984952156746478105358
Short name T660
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.81 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:15 PM PST 23
Peak memory 209008 kb
Host smart-3c8b7502-6dd7-45c3-960e-a526371db6a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89389511349398648731192375578663150231231540200458419936984952156746478105358 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.89389511349398648731192375578663150231231540200458419936984952156746478105358
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.29252639414767926781325470525325143201957407591266067722900917430349992705101
Short name T488
Test name
Test status
Simulation time 159313969 ps
CPU time 2.98 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:13 PM PST 23
Peak memory 217492 kb
Host smart-e5e985f9-f9fc-427c-91d4-e96dd19dc2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29252639414767926781325470525325143201957407591266067722900917430349992705101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.lc_ctrl_prog_failure.29252639414767926781325470525325143201957407591266067722900917430349992705101
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.79484336089713943933574492799971221568164967655864931691929191277126126978244
Short name T620
Test name
Test status
Simulation time 1010128591 ps
CPU time 15.1 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:24 PM PST 23
Peak memory 218508 kb
Host smart-21c9b678-d3a8-4db4-bd10-cd390c07aae0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79484336089713943933574492799971221568164967655864931691929191277126126978244 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.79484336089713943933574492799971221568164967655864931691929191277126126978244
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.21088799350015773038536860770537388132713039659402649187938198891612470175129
Short name T336
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.71 seconds
Started Nov 22 01:39:03 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 217436 kb
Host smart-456f4996-12e5-44f0-a08e-4529cd00df38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21088799350015773038536860770537388132713039659402649187938198891612470175129 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_digest.21088799350015773038536860770537388132713039659402649187938198891612470175129
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.18270874428042740872521016349356660848682768714572601384071440402239680836214
Short name T719
Test name
Test status
Simulation time 964986095 ps
CPU time 11.57 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 217412 kb
Host smart-001207cf-1e0c-4e5f-9ec8-7ea16a6cbef4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18270874428042740872521016349356660848682768714572601384071440402239680836214 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.18270874428042740872521016349356660848682768714572601384071440402239680836214
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.78308963632569087838579679337960567750641848007743153219508641285783502056394
Short name T308
Test name
Test status
Simulation time 625328098 ps
CPU time 8.53 seconds
Started Nov 22 01:39:11 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 217444 kb
Host smart-c3d7a3c8-ca71-46e7-bb93-014f077b5f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78308963632569087838579679337960567750641848007743153219508641285783502056394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.lc_ctrl_security_escalation.78308963632569087838579679337960567750641848007743153219508641285783502056394
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.100426247533938021290129853135233678106329932745624733628815466577541723044112
Short name T52
Test name
Test status
Simulation time 291295056 ps
CPU time 4.67 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 213832 kb
Host smart-2e6aca31-d96c-4061-b5f5-290c83a329fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100426247533938021290129853135233678106329932745624733628815466577541723044112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.lc_ctrl_smoke.100426247533938021290129853135233678106329932745624733628815466577541723044112
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.94233344144217550631040918152846229861227955593362915154100984540526513975006
Short name T718
Test name
Test status
Simulation time 487150632 ps
CPU time 21.03 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:29 PM PST 23
Peak memory 250480 kb
Host smart-85a43f83-31c3-441e-ac6f-10b43f7475e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94233344144217550631040918152846229861227955593362915154100984540526513975006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.lc_ctrl_state_failure.94233344144217550631040918152846229861227955593362915154100984540526513975006
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.50780448460551383911827577616887980039865641790060366063244081610586155278123
Short name T581
Test name
Test status
Simulation time 217117078 ps
CPU time 7.01 seconds
Started Nov 22 01:39:10 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 246324 kb
Host smart-b4d8614a-4dc6-45bc-a2c3-7ab1de92724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50780448460551383911827577616887980039865641790060366063244081610586155278123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.lc_ctrl_state_post_trans.50780448460551383911827577616887980039865641790060366063244081610586155278123
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.36895534099834937369130201491077698692358901052504688786886332296823147985187
Short name T875
Test name
Test status
Simulation time 36820395678 ps
CPU time 285.07 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:43:50 PM PST 23
Peak memory 283440 kb
Host smart-af690fb6-8c43-4660-89bc-8cce25e0090b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368955340998349373691302014910776986923589010525046887868863322968
23147985187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.36895534099834937369130201491077698692358901052504688786
886332296823147985187
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.51569869908678644434560509873963991381597574843702337774503058495794516753027
Short name T929
Test name
Test status
Simulation time 16404398 ps
CPU time 0.78 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:06 PM PST 23
Peak memory 207560 kb
Host smart-759cd2b8-0b92-4661-8b82-4fa62f798156
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51569869908678644434560509873963991381597574843702337774503058495794516753027 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_volatile_unlock_smoke.51569869908678644434560509873963991381597574843702337
774503058495794516753027
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.114569241787550456432762437241884264816757570678543895317937339795229561465883
Short name T608
Test name
Test status
Simulation time 42189906 ps
CPU time 0.96 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:08 PM PST 23
Peak memory 207748 kb
Host smart-545e0764-5b34-4729-aeb8-a52c7a100664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114569241787550456432762437241884264816757570678543895317937339795229561465883 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.114569241787550456432762437241884264816757570678543895317937339795229561465883
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.66123586402742945933942619191635385152269637133544655647686127198556554673692
Short name T515
Test name
Test status
Simulation time 978628843 ps
CPU time 13.61 seconds
Started Nov 22 01:39:03 PM PST 23
Finished Nov 22 01:39:17 PM PST 23
Peak memory 217344 kb
Host smart-e93a1c49-5944-49ca-a9a7-8d10e1629961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66123586402742945933942619191635385152269637133544655647686127198556554673692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.lc_ctrl_errors.66123586402742945933942619191635385152269637133544655647686127198556554673692
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.96336194610418983787432772620525984523351857542002677273555419136627609286718
Short name T404
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.68 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:16 PM PST 23
Peak memory 209032 kb
Host smart-41078514-5846-47c0-be37-6d418f449e76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96336194610418983787432772620525984523351857542002677273555419136627609286718 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.96336194610418983787432772620525984523351857542002677273555419136627609286718
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.56194908999780729919838900949302299962472580211776937107720007896014492276377
Short name T575
Test name
Test status
Simulation time 159313969 ps
CPU time 2.88 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 217508 kb
Host smart-8e2b70c7-e960-4f8a-a614-bbf862a7068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56194908999780729919838900949302299962472580211776937107720007896014492276377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.lc_ctrl_prog_failure.56194908999780729919838900949302299962472580211776937107720007896014492276377
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.43919333127393513287533530257979240989460723425981709828457277021999844344481
Short name T45
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.45 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 218500 kb
Host smart-e60e2ee0-63bb-4001-a544-6f21632c0ff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43919333127393513287533530257979240989460723425981709828457277021999844344481 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.43919333127393513287533530257979240989460723425981709828457277021999844344481
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.62204998150500713112932647610522009939231849630872247106197903158162913281682
Short name T926
Test name
Test status
Simulation time 1321911811 ps
CPU time 17.99 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:24 PM PST 23
Peak memory 217436 kb
Host smart-a148813d-241a-4fb8-a2f0-4c458d35f705
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62204998150500713112932647610522009939231849630872247106197903158162913281682 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_digest.62204998150500713112932647610522009939231849630872247106197903158162913281682
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.4032156252178699503954944571864206539318008494252996337642840202844248835082
Short name T880
Test name
Test status
Simulation time 964986095 ps
CPU time 11.47 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:17 PM PST 23
Peak memory 217284 kb
Host smart-915b1414-6da1-4357-8948-d779aee10b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032156252178699503954944571864206539318008494252996337642840202844248835082 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.4032156252178699503954944571864206539318008494252996337642840202844248835082
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1016319776752599730672544046370417881221600231911299990523034347290164328794
Short name T270
Test name
Test status
Simulation time 625328098 ps
CPU time 7.98 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:13 PM PST 23
Peak memory 217392 kb
Host smart-7085a0bc-8980-4d91-9242-630be0bf4e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016319776752599730672544046370417881221600231911299990523034347290164328794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.lc_ctrl_security_escalation.1016319776752599730672544046370417881221600231911299990523034347290164328794
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4700099940393108831357433803449374945748806113005351112058560883201273156522
Short name T55
Test name
Test status
Simulation time 291295056 ps
CPU time 4.62 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 213860 kb
Host smart-b06f6f8f-8c30-47f3-9d3b-0ddbb7514de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4700099940393108831357433803449374945748806113005351112058560883201273156522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.lc_ctrl_smoke.4700099940393108831357433803449374945748806113005351112058560883201273156522
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.111706721861720322595727023674139865019979578865934718340414980048018986361661
Short name T334
Test name
Test status
Simulation time 487150632 ps
CPU time 20.42 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:28 PM PST 23
Peak memory 250440 kb
Host smart-3f03cddf-ff07-486e-99be-d72b55e81c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111706721861720322595727023674139865019979578865934718340414980048018986361661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.lc_ctrl_state_failure.111706721861720322595727023674139865019979578865934718340414980048018986361661
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.86383682564206477850157122585054391910842001584102650057033935437419089994928
Short name T559
Test name
Test status
Simulation time 217117078 ps
CPU time 7.04 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:13 PM PST 23
Peak memory 246248 kb
Host smart-b9057d13-d51c-4b18-a55d-b889724d1884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86383682564206477850157122585054391910842001584102650057033935437419089994928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.lc_ctrl_state_post_trans.86383682564206477850157122585054391910842001584102650057033935437419089994928
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.111600680567419486749553190316629792102642724103025975339947295576907275193328
Short name T60
Test name
Test status
Simulation time 36820395678 ps
CPU time 287.17 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:43:55 PM PST 23
Peak memory 283368 kb
Host smart-e34987d7-f5cf-4cb3-9ddb-3ad2aeb8f26b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111600680567419486749553190316629792102642724103025975339947295576
907275193328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.1116006805674194867495531903166297921026427241030259753
39947295576907275193328
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4840323806141532527052445748075042142303800359517970354968182467238954437796
Short name T675
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:07 PM PST 23
Peak memory 207612 kb
Host smart-34f6ea73-6282-40cf-9505-d41a4229968d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4840323806141532527052445748075042142303800359517970354968182467238954437796 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_volatile_unlock_smoke.484032380614153252705244574807504214230380035951797035
4968182467238954437796
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.31288866686736039233634359700847738225506812425756824117601013479609760944371
Short name T399
Test name
Test status
Simulation time 42189906 ps
CPU time 0.98 seconds
Started Nov 22 01:37:17 PM PST 23
Finished Nov 22 01:37:25 PM PST 23
Peak memory 207768 kb
Host smart-a757ca81-49c7-4c08-9283-a8d0b33b20a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31288866686736039233634359700847738225506812425756824117601013479609760944371 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.31288866686736039233634359700847738225506812425756824117601013479609760944371
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.28924483318610227484227838585793971027732540234324557855416723773148982664178
Short name T552
Test name
Test status
Simulation time 19636515 ps
CPU time 0.77 seconds
Started Nov 22 01:37:06 PM PST 23
Finished Nov 22 01:37:07 PM PST 23
Peak memory 207552 kb
Host smart-7724621e-a836-46ad-95bc-c7e8ef0c63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28924483318610227484227838585793971027732540234324557855416723773148982664178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.28924483318610227484227838585793971027732540234324557855416723773148982664178
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.6704046842581794747067155746817451332711408549846639935303113939686765396957
Short name T43
Test name
Test status
Simulation time 978628843 ps
CPU time 14.68 seconds
Started Nov 22 01:37:03 PM PST 23
Finished Nov 22 01:37:19 PM PST 23
Peak memory 217460 kb
Host smart-b0bb5d7d-9dc1-46a5-9082-c964dddb357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6704046842581794747067155746817451332711408549846639935303113939686765396957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.lc_ctrl_errors.6704046842581794747067155746817451332711408549846639935303113939686765396957
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.75121785643260953339369594370326854715411705865863149579260060087988975068706
Short name T734
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.62 seconds
Started Nov 22 01:37:11 PM PST 23
Finished Nov 22 01:37:21 PM PST 23
Peak memory 208980 kb
Host smart-17cb09d0-7fc1-4fc2-9dd1-2214220727a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75121785643260953339369594370326854715411705865863149579260060087988975068706 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.75121785643260953339369594370326854715411705865863149579260060087988975068706
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.93155075652393251126492344766662980784165066207608544705405265973086923283083
Short name T720
Test name
Test status
Simulation time 5872518263 ps
CPU time 41.81 seconds
Started Nov 22 01:37:03 PM PST 23
Finished Nov 22 01:37:46 PM PST 23
Peak memory 217764 kb
Host smart-4644c062-6818-48a6-9475-77fe11a6b442
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93155075652393251126492344766662980784165066207608544705405265973086923283083 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_errors.93155075652393251126492344766662980784165066207608544705405265973086923283083
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.42005460874563878245333312986262935399002297866072529273411674214639062811704
Short name T876
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.3 seconds
Started Nov 22 01:37:21 PM PST 23
Finished Nov 22 01:37:37 PM PST 23
Peak memory 217348 kb
Host smart-1869ed64-50f5-4635-b469-b92f390f1a20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005460874563878245333312986262935399002297866072529273411674214639062811704 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.42005460874563878245333312986262935399002297866072529273411674214639062811704
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.80298311806160556802049207027385485423948133081643527204342118161272955403623
Short name T446
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.52 seconds
Started Nov 22 01:37:24 PM PST 23
Finished Nov 22 01:37:40 PM PST 23
Peak memory 217444 kb
Host smart-49001c29-0555-4d4d-9542-61a22081ee2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80298311806160556802049207027385485423948133081643527204342118161272955403623 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prog_failure.80298311806160556802049207027385485423948133081643527204342118161272955403623
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.32782848520009833642709043511534879967996634056559205224579454112729683115655
Short name T738
Test name
Test status
Simulation time 1406053995 ps
CPU time 10.42 seconds
Started Nov 22 01:37:22 PM PST 23
Finished Nov 22 01:37:34 PM PST 23
Peak memory 212284 kb
Host smart-3b912656-e2cc-483f-ae85-a3d713322623
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32782848520009833642709043511534879967996634056559205224579454112729683115655 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_regwen_during_op.327828485200098336427090435115348799679966340565592052245
79454112729683115655
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.11419975926469562575758357229422109194228041764461439819051871523872115894056
Short name T501
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.62 seconds
Started Nov 22 01:37:08 PM PST 23
Finished Nov 22 01:37:17 PM PST 23
Peak memory 212892 kb
Host smart-d51ac898-dd71-4733-af95-cfcb75dc1910
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11419975926469562575758357229422109194228041764461439819051871523872115894056 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.11419975926469562575758357229422109194228041764461439819051871523872115894056
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.26652345220105077736133429535050679138898430507030183077688699186518651405901
Short name T917
Test name
Test status
Simulation time 5030489285 ps
CPU time 51.59 seconds
Started Nov 22 01:37:03 PM PST 23
Finished Nov 22 01:37:55 PM PST 23
Peak memory 269136 kb
Host smart-2744c57b-d36e-454f-a4cd-e2db5badc535
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26652345220105077736133429535050679138898430507030183077688699186518651405901 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_state_failure.266523452201050777361334295350506791388984305070301830776886991
86518651405901
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.94357946834951680231367842503549342499676160169617757695325074244077662054275
Short name T4
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.69 seconds
Started Nov 22 01:37:08 PM PST 23
Finished Nov 22 01:37:24 PM PST 23
Peak memory 246796 kb
Host smart-9afca353-f7f2-47d4-bbae-8441501f6682
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94357946834951680231367842503549342499676160169617757695325074244077662054275 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_state_post_trans.943579468349516802313678425035493424996761601696177576953
25074244077662054275
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.39965749587283888737154309525074371853867567647609887429829630392577233835544
Short name T545
Test name
Test status
Simulation time 159313969 ps
CPU time 3.03 seconds
Started Nov 22 01:37:02 PM PST 23
Finished Nov 22 01:37:06 PM PST 23
Peak memory 217284 kb
Host smart-609ce61e-2d4f-437b-bba9-1eab3a94fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39965749587283888737154309525074371853867567647609887429829630392577233835544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_prog_failure.39965749587283888737154309525074371853867567647609887429829630392577233835544
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.31832714435277145278586254621159461561669117349861072749732788015092856591795
Short name T528
Test name
Test status
Simulation time 420615450 ps
CPU time 5.94 seconds
Started Nov 22 01:37:03 PM PST 23
Finished Nov 22 01:37:09 PM PST 23
Peak memory 213344 kb
Host smart-89fb870e-6591-4254-a8ba-6f4981287846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31832714435277145278586254621159461561669117349861072749732788015092856591795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.lc_ctrl_regwen_during_op.31832714435277145278586254621159461561669117349861072749732788015092856591795
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.23945167712676880729110958535347872971005368645315696878246498078529410047625
Short name T83
Test name
Test status
Simulation time 386472866 ps
CPU time 37.17 seconds
Started Nov 22 01:37:13 PM PST 23
Finished Nov 22 01:37:51 PM PST 23
Peak memory 273612 kb
Host smart-c143b47f-d3f2-414d-acb4-866ff7525cae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23945167712676880729110958535347872971005368645315696878246498078529410047625 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.23945167712676880729110958535347872971005368645315696878246498078529410047625
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.63099170167611744346994437106086993725082780733534994521644636104122499447729
Short name T888
Test name
Test status
Simulation time 1010128591 ps
CPU time 15.04 seconds
Started Nov 22 01:37:09 PM PST 23
Finished Nov 22 01:37:25 PM PST 23
Peak memory 218476 kb
Host smart-54aab573-d90d-434e-924d-f82c84c3d377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63099170167611744346994437106086993725082780733534994521644636104122499447729 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.63099170167611744346994437106086993725082780733534994521644636104122499447729
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.105214832414975574924512922487731625038165735935939209623067521010115347780258
Short name T808
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.21 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:17 PM PST 23
Peak memory 217288 kb
Host smart-59e0fbb4-a9b7-4fc7-b0b2-bed085e70b6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105214832414975574924512922487731625038165735935939209623067521010115347780258 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_digest.105214832414975574924512922487731625038165735935939209623067521010115347780258
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.28161822586555284579826798424098313725554399139788880704907710717288424902361
Short name T896
Test name
Test status
Simulation time 964986095 ps
CPU time 10.65 seconds
Started Nov 22 01:36:55 PM PST 23
Finished Nov 22 01:37:11 PM PST 23
Peak memory 217300 kb
Host smart-8c600bcf-a3f8-4a5c-bcc5-09d08c3a42ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28161822586555284579826798424098313725554399139788880704907710717288424902361 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.28161822586555284579826798424098313725554399139788880704907710717288424902361
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.76176256446840432875940085313602127514470984142499175975807862119006566785223
Short name T687
Test name
Test status
Simulation time 625328098 ps
CPU time 8.28 seconds
Started Nov 22 01:36:59 PM PST 23
Finished Nov 22 01:37:10 PM PST 23
Peak memory 217476 kb
Host smart-fe1c1a82-a06f-480f-881e-ba540ee9a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76176256446840432875940085313602127514470984142499175975807862119006566785223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_security_escalation.76176256446840432875940085313602127514470984142499175975807862119006566785223
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.15570819941278317146941681275727778246504542532640556769163934110145652304378
Short name T436
Test name
Test status
Simulation time 291295056 ps
CPU time 4.57 seconds
Started Nov 22 01:37:00 PM PST 23
Finished Nov 22 01:37:07 PM PST 23
Peak memory 213864 kb
Host smart-a371928b-a820-443b-b690-808c488e32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15570819941278317146941681275727778246504542532640556769163934110145652304378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_smoke.15570819941278317146941681275727778246504542532640556769163934110145652304378
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.111038397561148187485686467927601901469211576778256288567848306152497638908540
Short name T975
Test name
Test status
Simulation time 487150632 ps
CPU time 20.84 seconds
Started Nov 22 01:37:20 PM PST 23
Finished Nov 22 01:37:45 PM PST 23
Peak memory 250476 kb
Host smart-cac20839-36b4-474c-9527-b3b5dd590d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111038397561148187485686467927601901469211576778256288567848306152497638908540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_state_failure.111038397561148187485686467927601901469211576778256288567848306152497638908540
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3804152621177621145817711619356664117428080135056143068493409456530196556811
Short name T24
Test name
Test status
Simulation time 217117078 ps
CPU time 7.12 seconds
Started Nov 22 01:36:59 PM PST 23
Finished Nov 22 01:37:09 PM PST 23
Peak memory 246344 kb
Host smart-a2f4668d-7118-444a-941d-9c9e21809669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804152621177621145817711619356664117428080135056143068493409456530196556811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.lc_ctrl_state_post_trans.3804152621177621145817711619356664117428080135056143068493409456530196556811
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.88658563682986060587254624671118227733141940863891846062426432210472058298899
Short name T335
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.65 seconds
Started Nov 22 01:37:18 PM PST 23
Finished Nov 22 01:42:07 PM PST 23
Peak memory 279616 kb
Host smart-3ce075cf-c482-4e6a-8f77-6c2c59849d92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886585636829860605872546246711182277331419408638918460624264322104
72058298899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.886585636829860605872546246711182277331419408638918460624
26432210472058298899
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.45204512012200319088440292369525992401846514163403531529937273947487953326599
Short name T438
Test name
Test status
Simulation time 16404398 ps
CPU time 0.76 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 207584 kb
Host smart-62d17594-0b29-41d0-a706-ff1aca76bec4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45204512012200319088440292369525992401846514163403531529937273947487953326599 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_volatile_unlock_smoke.452045120122003190884402923695259924018465141634035315
29937273947487953326599
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.75666173814106671841786964810613581512577933642692559157877609632866238856360
Short name T795
Test name
Test status
Simulation time 42189906 ps
CPU time 0.97 seconds
Started Nov 22 01:39:03 PM PST 23
Finished Nov 22 01:39:05 PM PST 23
Peak memory 207708 kb
Host smart-e3ad7099-bc0d-455b-b5b9-13fa21e455f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75666173814106671841786964810613581512577933642692559157877609632866238856360 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.75666173814106671841786964810613581512577933642692559157877609632866238856360
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.44847265905073140640186659277985177217534563681914863093148920049377119666799
Short name T423
Test name
Test status
Simulation time 978628843 ps
CPU time 13.9 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 217372 kb
Host smart-1cea0dfc-48fe-4d08-b1e9-3cf5dd28ed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44847265905073140640186659277985177217534563681914863093148920049377119666799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.lc_ctrl_errors.44847265905073140640186659277985177217534563681914863093148920049377119666799
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.66756577971859473656027954663740917659480014759149212937521424023312919273168
Short name T924
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.71 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:17 PM PST 23
Peak memory 208976 kb
Host smart-39a9d6f2-6974-4e5c-bb88-a756c6d709e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66756577971859473656027954663740917659480014759149212937521424023312919273168 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.66756577971859473656027954663740917659480014759149212937521424023312919273168
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.19470227907881802079963125010469161565387446976022945336847073786532713231044
Short name T788
Test name
Test status
Simulation time 159313969 ps
CPU time 2.96 seconds
Started Nov 22 01:39:02 PM PST 23
Finished Nov 22 01:39:06 PM PST 23
Peak memory 217332 kb
Host smart-d35dc840-c634-40b3-9a58-474ae96a873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19470227907881802079963125010469161565387446976022945336847073786532713231044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.lc_ctrl_prog_failure.19470227907881802079963125010469161565387446976022945336847073786532713231044
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.59459357858020979013040721695307225677148948484885084091802841081898858044130
Short name T90
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.59 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 218488 kb
Host smart-cffa006f-b5d4-43dc-88d8-c591b84b6acc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59459357858020979013040721695307225677148948484885084091802841081898858044130 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.59459357858020979013040721695307225677148948484885084091802841081898858044130
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.42066521044392663785374073894141960871130011298684823926212094338832549558053
Short name T874
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.59 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 217400 kb
Host smart-9af276eb-d1ed-4559-9733-7816e54c20e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42066521044392663785374073894141960871130011298684823926212094338832549558053 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_digest.42066521044392663785374073894141960871130011298684823926212094338832549558053
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.55701181748910973380504640765677750578093968010669649510195726229709042457771
Short name T798
Test name
Test status
Simulation time 964986095 ps
CPU time 11.9 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 217424 kb
Host smart-95647652-d699-4b07-ad32-34106f8f32fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55701181748910973380504640765677750578093968010669649510195726229709042457771 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.55701181748910973380504640765677750578093968010669649510195726229709042457771
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.74807164838045185338321965416054887687106114661406607816527615970882748204004
Short name T23
Test name
Test status
Simulation time 625328098 ps
CPU time 8.51 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:16 PM PST 23
Peak memory 217420 kb
Host smart-c7891981-5780-4447-a5ee-e046d350506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74807164838045185338321965416054887687106114661406607816527615970882748204004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.lc_ctrl_security_escalation.74807164838045185338321965416054887687106114661406607816527615970882748204004
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.82649588554776892179820008550654784888884049232838977395514711182706368874753
Short name T616
Test name
Test status
Simulation time 291295056 ps
CPU time 4.66 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 213800 kb
Host smart-d7510f1d-b613-4150-bdd7-8a117ffeefa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82649588554776892179820008550654784888884049232838977395514711182706368874753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.lc_ctrl_smoke.82649588554776892179820008550654784888884049232838977395514711182706368874753
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.66717316559320135947412196320902813881764243392288030603974900031825460633275
Short name T970
Test name
Test status
Simulation time 487150632 ps
CPU time 21.92 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:29 PM PST 23
Peak memory 250436 kb
Host smart-bd612a0a-04b4-4de3-85ac-21ad4d7ad092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66717316559320135947412196320902813881764243392288030603974900031825460633275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.lc_ctrl_state_failure.66717316559320135947412196320902813881764243392288030603974900031825460633275
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.71871607696789827483969033215454278892357226677196424612151314680820161679751
Short name T859
Test name
Test status
Simulation time 217117078 ps
CPU time 7.41 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:14 PM PST 23
Peak memory 246336 kb
Host smart-5e20416e-8246-4937-a847-ae2ae5798411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71871607696789827483969033215454278892357226677196424612151314680820161679751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.lc_ctrl_state_post_trans.71871607696789827483969033215454278892357226677196424612151314680820161679751
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.63487691860283554978933056193470281521348062869187290119761789429915481482719
Short name T921
Test name
Test status
Simulation time 36820395678 ps
CPU time 283.09 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:43:51 PM PST 23
Peak memory 283420 kb
Host smart-f0c8273b-fd7f-4d6d-82d6-bdee1d0d61e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634876918602835549789330561934702815213480628691872901197617894299
15481482719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.63487691860283554978933056193470281521348062869187290119
761789429915481482719
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.37877428935513042038202398211916237323480130486804342499084615737987153242688
Short name T301
Test name
Test status
Simulation time 16404398 ps
CPU time 0.74 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:06 PM PST 23
Peak memory 207592 kb
Host smart-f1c0a227-398c-45f1-b4e7-36b49f93beec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37877428935513042038202398211916237323480130486804342499084615737987153242688 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_volatile_unlock_smoke.37877428935513042038202398211916237323480130486804342
499084615737987153242688
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.107306603949135004297627328799421842435395656247152029020718839388609952178912
Short name T658
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:10 PM PST 23
Peak memory 207696 kb
Host smart-969153ba-7935-4a56-994b-449e6ab77044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107306603949135004297627328799421842435395656247152029020718839388609952178912 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.107306603949135004297627328799421842435395656247152029020718839388609952178912
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.63915375106509572620589316282175036201681227985029011497234374208487555562502
Short name T314
Test name
Test status
Simulation time 978628843 ps
CPU time 13.54 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 217416 kb
Host smart-8e7d09f6-745c-4d9e-818b-dc1735c950e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63915375106509572620589316282175036201681227985029011497234374208487555562502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.lc_ctrl_errors.63915375106509572620589316282175036201681227985029011497234374208487555562502
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.84458830379630744645161914496830190578077786805164489362509765158158734924108
Short name T7
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.76 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 209024 kb
Host smart-0791bd41-1dca-40c6-b233-3e19bcea2e6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84458830379630744645161914496830190578077786805164489362509765158158734924108 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.84458830379630744645161914496830190578077786805164489362509765158158734924108
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.47215300852198919105397027404590289617514192838988670579796879067788354292871
Short name T645
Test name
Test status
Simulation time 159313969 ps
CPU time 3.02 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 217476 kb
Host smart-ce6a7804-3cc0-4117-94a9-303506a84c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47215300852198919105397027404590289617514192838988670579796879067788354292871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.lc_ctrl_prog_failure.47215300852198919105397027404590289617514192838988670579796879067788354292871
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.102190431119908705551794921016543865867508404339340317310791486354770291586372
Short name T754
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.7 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 218400 kb
Host smart-845f7530-e08e-495d-b09c-fa75c5ae6765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102190431119908705551794921016543865867508404339340317310791486354770291586372 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.102190431119908705551794921016543865867508404339340317310791486354770291586372
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.58983889030999602629177712620658782594886910083256842339297507932723151436873
Short name T748
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.53 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:26 PM PST 23
Peak memory 217360 kb
Host smart-38608a84-7fcb-47b6-b093-d20082c517f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58983889030999602629177712620658782594886910083256842339297507932723151436873 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_digest.58983889030999602629177712620658782594886910083256842339297507932723151436873
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.104921804056487278569023593446434368145996394419583642422734631266756731941542
Short name T681
Test name
Test status
Simulation time 964986095 ps
CPU time 11.03 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:16 PM PST 23
Peak memory 217396 kb
Host smart-b77af040-d844-4e15-a3e6-e8781eb7911b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104921804056487278569023593446434368145996394419583642422734631266756731941542 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.104921804056487278569023593446434368145996394419583642422734631266756731941542
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.40560556164264620965988194369050904751681017607689248756465414741418709400836
Short name T272
Test name
Test status
Simulation time 625328098 ps
CPU time 8.41 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:14 PM PST 23
Peak memory 217476 kb
Host smart-eb9e7371-eec1-402e-8fe3-51a359b4c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40560556164264620965988194369050904751681017607689248756465414741418709400836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.lc_ctrl_security_escalation.40560556164264620965988194369050904751681017607689248756465414741418709400836
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.60778173731899684998244094000547351598741896945796007001710013787732940414706
Short name T749
Test name
Test status
Simulation time 291295056 ps
CPU time 4.75 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:13 PM PST 23
Peak memory 213852 kb
Host smart-db58f21e-2b2e-40b5-80fc-567cc2fd8650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60778173731899684998244094000547351598741896945796007001710013787732940414706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.lc_ctrl_smoke.60778173731899684998244094000547351598741896945796007001710013787732940414706
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.53209626091281767798504640436920363896482482138333898739384505377685389318222
Short name T468
Test name
Test status
Simulation time 487150632 ps
CPU time 21.41 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:29 PM PST 23
Peak memory 250448 kb
Host smart-533bdf43-6cf0-408b-a53b-2f2d1949c2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53209626091281767798504640436920363896482482138333898739384505377685389318222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.lc_ctrl_state_failure.53209626091281767798504640436920363896482482138333898739384505377685389318222
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.30789754958278534108035151324464178415248753133463536808587572310752009562354
Short name T963
Test name
Test status
Simulation time 217117078 ps
CPU time 7.19 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:14 PM PST 23
Peak memory 246292 kb
Host smart-8d337f01-44f1-4dc4-a445-3fa896aee131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30789754958278534108035151324464178415248753133463536808587572310752009562354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.lc_ctrl_state_post_trans.30789754958278534108035151324464178415248753133463536808587572310752009562354
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.82287296184722960613211639727432955194287316520010443705468664411252359441692
Short name T422
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.59 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:43:53 PM PST 23
Peak memory 283476 kb
Host smart-10184817-7492-4e17-a72b-4dbf963e134f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822872961847229606132116397274329551942873165200104437054686644112
52359441692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.82287296184722960613211639727432955194287316520010443705
468664411252359441692
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.8981238445189568150245116828658959492969727122483927830846242990004352511191
Short name T790
Test name
Test status
Simulation time 16404398 ps
CPU time 0.74 seconds
Started Nov 22 01:39:05 PM PST 23
Finished Nov 22 01:39:06 PM PST 23
Peak memory 207620 kb
Host smart-7ce69668-0c07-4b71-9ea9-dea63218b919
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8981238445189568150245116828658959492969727122483927830846242990004352511191 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_volatile_unlock_smoke.898123844518956815024511682865895949296972712248392783
0846242990004352511191
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.10258774768734020785966615758088611140757137929503987736260576300425941198415
Short name T66
Test name
Test status
Simulation time 42189906 ps
CPU time 0.92 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:08 PM PST 23
Peak memory 207768 kb
Host smart-8e3dc5ef-beb0-48c0-a44f-572e8c12d4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10258774768734020785966615758088611140757137929503987736260576300425941198415 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.10258774768734020785966615758088611140757137929503987736260576300425941198415
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.75446719171269661358527059099671733624383328243762577615298874853979522341434
Short name T711
Test name
Test status
Simulation time 978628843 ps
CPU time 14.06 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:25 PM PST 23
Peak memory 217412 kb
Host smart-28a19425-37c9-49f6-b41c-653ed0913826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75446719171269661358527059099671733624383328243762577615298874853979522341434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.lc_ctrl_errors.75446719171269661358527059099671733624383328243762577615298874853979522341434
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.37379776451243358349441390891096961183966568165866773041544753369271745350051
Short name T877
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.26 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 209032 kb
Host smart-37f8ead8-f294-4d0f-85a6-8396c64eb79b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37379776451243358349441390891096961183966568165866773041544753369271745350051 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.37379776451243358349441390891096961183966568165866773041544753369271745350051
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4446401026908057126815557790578357944316299308941432969745061662460439531233
Short name T449
Test name
Test status
Simulation time 159313969 ps
CPU time 2.88 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:10 PM PST 23
Peak memory 217436 kb
Host smart-bb7cffa3-f902-44a5-ad16-68035a2bb811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4446401026908057126815557790578357944316299308941432969745061662460439531233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.lc_ctrl_prog_failure.4446401026908057126815557790578357944316299308941432969745061662460439531233
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.24377642805218373133959180757159431856614569530466036925737320680235107080921
Short name T555
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.3 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:24 PM PST 23
Peak memory 218380 kb
Host smart-f03220d2-3137-4a22-8d16-1d486219fbd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24377642805218373133959180757159431856614569530466036925737320680235107080921 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.24377642805218373133959180757159431856614569530466036925737320680235107080921
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.37656794031625945380945229968070889644131216404422808109345896684098273642222
Short name T708
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.23 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:24 PM PST 23
Peak memory 217444 kb
Host smart-be0c0074-e601-4cbb-84a0-f225c2a9b875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37656794031625945380945229968070889644131216404422808109345896684098273642222 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_digest.37656794031625945380945229968070889644131216404422808109345896684098273642222
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.42130938962312415967984308985183560215569643789544651401988642033728190322295
Short name T296
Test name
Test status
Simulation time 964986095 ps
CPU time 11.2 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 217428 kb
Host smart-4fd84472-954b-4f2c-aca7-34ec4565f30e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130938962312415967984308985183560215569643789544651401988642033728190322295 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.42130938962312415967984308985183560215569643789544651401988642033728190322295
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.50087406532328392468068030733222110295222964731341790552626629114377888165611
Short name T570
Test name
Test status
Simulation time 625328098 ps
CPU time 8.19 seconds
Started Nov 22 01:39:04 PM PST 23
Finished Nov 22 01:39:14 PM PST 23
Peak memory 217464 kb
Host smart-bac7ac94-c325-4da3-9f28-5f4abf653420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50087406532328392468068030733222110295222964731341790552626629114377888165611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.lc_ctrl_security_escalation.50087406532328392468068030733222110295222964731341790552626629114377888165611
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.115318794767753857247152475404626973131754855339807267505707654782715042163979
Short name T496
Test name
Test status
Simulation time 291295056 ps
CPU time 4.35 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:14 PM PST 23
Peak memory 213732 kb
Host smart-68ab9290-8a01-4718-a732-39accd998f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115318794767753857247152475404626973131754855339807267505707654782715042163979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.lc_ctrl_smoke.115318794767753857247152475404626973131754855339807267505707654782715042163979
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.96939645638873255190675713934871290813883398866238707949927810827861217437392
Short name T592
Test name
Test status
Simulation time 487150632 ps
CPU time 20.95 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:28 PM PST 23
Peak memory 250468 kb
Host smart-fb46938f-10d9-45ee-82e9-8108e17e6f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96939645638873255190675713934871290813883398866238707949927810827861217437392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.lc_ctrl_state_failure.96939645638873255190675713934871290813883398866238707949927810827861217437392
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.53818339913247518419572476686287213894978183343567980756550776093627501308878
Short name T343
Test name
Test status
Simulation time 217117078 ps
CPU time 7.23 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:16 PM PST 23
Peak memory 246292 kb
Host smart-31600819-5d47-4999-862b-4fcbc416df10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53818339913247518419572476686287213894978183343567980756550776093627501308878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.lc_ctrl_state_post_trans.53818339913247518419572476686287213894978183343567980756550776093627501308878
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.77712947216108480082804277868119807871065614156466797912837001625060432196286
Short name T457
Test name
Test status
Simulation time 36820395678 ps
CPU time 279.05 seconds
Started Nov 22 01:39:10 PM PST 23
Finished Nov 22 01:43:50 PM PST 23
Peak memory 283324 kb
Host smart-7e708d01-44e2-482d-b705-d3c2d1b975e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777129472161084800828042778681198078710656141564667979128370016250
60432196286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.77712947216108480082804277868119807871065614156466797912
837001625060432196286
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.82042876606573030815479578261072597945462109310648359498148762527304769160662
Short name T678
Test name
Test status
Simulation time 16404398 ps
CPU time 0.74 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:09 PM PST 23
Peak memory 207632 kb
Host smart-8e6760bd-e461-4c93-b7b5-5b6c9dfda1c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82042876606573030815479578261072597945462109310648359498148762527304769160662 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_volatile_unlock_smoke.82042876606573030815479578261072597945462109310648359
498148762527304769160662
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.770045466908383574750404369210297192156372175785489715610310951950827780470
Short name T858
Test name
Test status
Simulation time 42189906 ps
CPU time 0.96 seconds
Started Nov 22 01:39:10 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 207760 kb
Host smart-dcdfe934-ae15-4503-b293-22e9ee4bba78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770045466908383574750404369210297192156372175785489715610310951950827780470 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.770045466908383574750404369210297192156372175785489715610310951950827780470
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.97777348021119264083645654525210981293307016142968098214388975136034761151039
Short name T460
Test name
Test status
Simulation time 978628843 ps
CPU time 13.72 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:29 PM PST 23
Peak memory 217448 kb
Host smart-924c21cf-6b6d-4a61-ac44-feace51c2d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97777348021119264083645654525210981293307016142968098214388975136034761151039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.lc_ctrl_errors.97777348021119264083645654525210981293307016142968098214388975136034761151039
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.18830550821906621887012532822764655918063022020570986739120717909486827846670
Short name T435
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.11 seconds
Started Nov 22 01:39:13 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 208896 kb
Host smart-95036a2c-dfef-4e3f-9ec1-979c8ea826c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830550821906621887012532822764655918063022020570986739120717909486827846670 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.18830550821906621887012532822764655918063022020570986739120717909486827846670
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.106987344366918453297911310650459079536673874472334264853242269116483207994992
Short name T885
Test name
Test status
Simulation time 159313969 ps
CPU time 2.9 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:13 PM PST 23
Peak memory 217420 kb
Host smart-a6870249-9793-4883-93a7-beec8e6e7feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106987344366918453297911310650459079536673874472334264853242269116483207994992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.lc_ctrl_prog_failure.106987344366918453297911310650459079536673874472334264853242269116483207994992
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.40040423642490040136766598441003428659952843716686824560469447623715219454643
Short name T413
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.26 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:25 PM PST 23
Peak memory 218380 kb
Host smart-aee43b14-33c8-4e1f-8869-62cbca7ba7f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40040423642490040136766598441003428659952843716686824560469447623715219454643 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.40040423642490040136766598441003428659952843716686824560469447623715219454643
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.5337964783643817068548174094448755351818950064369881095649332238982824125946
Short name T294
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.73 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:27 PM PST 23
Peak memory 217444 kb
Host smart-b8acdf83-2894-47d0-87db-8c91607a3640
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5337964783643817068548174094448755351818950064369881095649332238982824125946 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_digest.5337964783643817068548174094448755351818950064369881095649332238982824125946
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.70687069068324257111908716383748558387381667770815372552853318338740907088663
Short name T577
Test name
Test status
Simulation time 625328098 ps
CPU time 7.97 seconds
Started Nov 22 01:39:11 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 217460 kb
Host smart-9fee19a7-210b-46b3-9968-32e9789de76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70687069068324257111908716383748558387381667770815372552853318338740907088663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.lc_ctrl_security_escalation.70687069068324257111908716383748558387381667770815372552853318338740907088663
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.76184071996455451375493332536030260582674604941930899203852686516410842248227
Short name T596
Test name
Test status
Simulation time 291295056 ps
CPU time 4.82 seconds
Started Nov 22 01:39:06 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 213868 kb
Host smart-22a67add-00a8-4303-bd3e-c5e66307f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76184071996455451375493332536030260582674604941930899203852686516410842248227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.lc_ctrl_smoke.76184071996455451375493332536030260582674604941930899203852686516410842248227
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.108952356888575499753044874334983047648834524788209318515791247151489904289927
Short name T897
Test name
Test status
Simulation time 487150632 ps
CPU time 21.29 seconds
Started Nov 22 01:39:08 PM PST 23
Finished Nov 22 01:39:31 PM PST 23
Peak memory 250464 kb
Host smart-da415aa3-fac4-4abd-93dc-1224a401b767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108952356888575499753044874334983047648834524788209318515791247151489904289927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.lc_ctrl_state_failure.108952356888575499753044874334983047648834524788209318515791247151489904289927
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.35447732623904726618681148489251799606066389806132455692360901339167905824789
Short name T941
Test name
Test status
Simulation time 217117078 ps
CPU time 7.32 seconds
Started Nov 22 01:39:10 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 246348 kb
Host smart-78360cbe-0a49-4fae-b37b-999395d47126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35447732623904726618681148489251799606066389806132455692360901339167905824789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.lc_ctrl_state_post_trans.35447732623904726618681148489251799606066389806132455692360901339167905824789
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.106143440250320238012042813490176092958811161290602936521159334902746060742730
Short name T459
Test name
Test status
Simulation time 36820395678 ps
CPU time 288.95 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:43:57 PM PST 23
Peak memory 283348 kb
Host smart-cf3bbbb7-c939-4dab-a11a-a456b0ab7af3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106143440250320238012042813490176092958811161290602936521159334902
746060742730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.1061434402503202380120428134901760929588111612906029365
21159334902746060742730
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.12038572926889763319643492622969551442279700949026768402720191301947493052187
Short name T286
Test name
Test status
Simulation time 16404398 ps
CPU time 0.74 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:11 PM PST 23
Peak memory 207536 kb
Host smart-781d5eb3-df3c-441d-919a-70c47a9dc939
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12038572926889763319643492622969551442279700949026768402720191301947493052187 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_volatile_unlock_smoke.12038572926889763319643492622969551442279700949026768
402720191301947493052187
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.59643692248787970832503016474853714050370463486678051156401618705266319435098
Short name T928
Test name
Test status
Simulation time 42189906 ps
CPU time 0.91 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 207592 kb
Host smart-f6973888-83c9-4983-b08c-10229498f76e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59643692248787970832503016474853714050370463486678051156401618705266319435098 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.59643692248787970832503016474853714050370463486678051156401618705266319435098
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.57403243172515078298292325384899475266715645752642369772165781300119094245170
Short name T792
Test name
Test status
Simulation time 978628843 ps
CPU time 13.75 seconds
Started Nov 22 01:39:11 PM PST 23
Finished Nov 22 01:39:25 PM PST 23
Peak memory 217408 kb
Host smart-64606101-fc35-4d19-b6c4-579b8f403ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57403243172515078298292325384899475266715645752642369772165781300119094245170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.lc_ctrl_errors.57403243172515078298292325384899475266715645752642369772165781300119094245170
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.100889118484187962508443428432833139099197905177908026087444204450136556172855
Short name T486
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.25 seconds
Started Nov 22 01:39:10 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 209008 kb
Host smart-4f603dbb-d846-40c1-b1df-931ca4f7914f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100889118484187962508443428432833139099197905177908026087444204450136556172855 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.100889118484187962508443428432833139099197905177908026087444204450136556172855
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.58067435734526096949410344598821992345957936038562101328093971964300997771527
Short name T326
Test name
Test status
Simulation time 159313969 ps
CPU time 2.87 seconds
Started Nov 22 01:39:09 PM PST 23
Finished Nov 22 01:39:13 PM PST 23
Peak memory 217364 kb
Host smart-73e00e63-69fb-4ead-83a3-78eb2aff5c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58067435734526096949410344598821992345957936038562101328093971964300997771527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.lc_ctrl_prog_failure.58067435734526096949410344598821992345957936038562101328093971964300997771527
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.101590452067632928458728881877540891588679189294980881363550541974225889635896
Short name T814
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.68 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:30 PM PST 23
Peak memory 218584 kb
Host smart-0790cf35-cba9-4763-8fe7-beb579cdfda3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101590452067632928458728881877540891588679189294980881363550541974225889635896 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.101590452067632928458728881877540891588679189294980881363550541974225889635896
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.113867431030465549429023847435099220176790318568429323796194577340638630242729
Short name T442
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.7 seconds
Started Nov 22 01:39:18 PM PST 23
Finished Nov 22 01:39:37 PM PST 23
Peak memory 217360 kb
Host smart-7b4adedc-8b4a-4d3c-87ec-e6e9d0755ec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113867431030465549429023847435099220176790318568429323796194577340638630242729 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_digest.113867431030465549429023847435099220176790318568429323796194577340638630242729
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.64939914791658083807665059942078648485503538426931681381514015471362683078984
Short name T376
Test name
Test status
Simulation time 964986095 ps
CPU time 10.74 seconds
Started Nov 22 01:39:12 PM PST 23
Finished Nov 22 01:39:23 PM PST 23
Peak memory 217372 kb
Host smart-56569c69-efea-4c8d-a785-09a5dcbcd471
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64939914791658083807665059942078648485503538426931681381514015471362683078984 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.64939914791658083807665059942078648485503538426931681381514015471362683078984
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.84170667205150660778540580327834439267007055872501630471332605502541755392012
Short name T935
Test name
Test status
Simulation time 625328098 ps
CPU time 8.51 seconds
Started Nov 22 01:39:11 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 217488 kb
Host smart-4c08c616-0f72-458f-9a5a-0198566b3585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84170667205150660778540580327834439267007055872501630471332605502541755392012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.lc_ctrl_security_escalation.84170667205150660778540580327834439267007055872501630471332605502541755392012
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.102358439788858604514541752479885226042253426947873693085610122493553709413137
Short name T50
Test name
Test status
Simulation time 291295056 ps
CPU time 4.88 seconds
Started Nov 22 01:39:11 PM PST 23
Finished Nov 22 01:39:17 PM PST 23
Peak memory 213856 kb
Host smart-2894f512-1886-46c3-b813-9fe01bdc6d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102358439788858604514541752479885226042253426947873693085610122493553709413137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.lc_ctrl_smoke.102358439788858604514541752479885226042253426947873693085610122493553709413137
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.41723040941816887444216930907733943833015625885695216622915611026359947236715
Short name T372
Test name
Test status
Simulation time 487150632 ps
CPU time 20.88 seconds
Started Nov 22 01:39:11 PM PST 23
Finished Nov 22 01:39:32 PM PST 23
Peak memory 250412 kb
Host smart-895b6eb0-f8a3-4926-9397-683d18ac69f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41723040941816887444216930907733943833015625885695216622915611026359947236715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.lc_ctrl_state_failure.41723040941816887444216930907733943833015625885695216622915611026359947236715
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.54229269927798057879754083789682804197046429635809464075954518267467963898729
Short name T339
Test name
Test status
Simulation time 217117078 ps
CPU time 7.18 seconds
Started Nov 22 01:39:11 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 246272 kb
Host smart-f6cc05ee-47f7-4701-ab4a-29f69001727a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54229269927798057879754083789682804197046429635809464075954518267467963898729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.lc_ctrl_state_post_trans.54229269927798057879754083789682804197046429635809464075954518267467963898729
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.75401740974003373043681582395171283532552036125553468696764023568639307786352
Short name T352
Test name
Test status
Simulation time 36820395678 ps
CPU time 292.55 seconds
Started Nov 22 01:39:12 PM PST 23
Finished Nov 22 01:44:06 PM PST 23
Peak memory 283472 kb
Host smart-b73cd49b-0147-483f-8742-c73e4e0fdd38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754017409740033730436815823951712835325520361255534686967640235686
39307786352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.75401740974003373043681582395171283532552036125553468696
764023568639307786352
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.102554092261183166111654895876000943878588152777102841505605007526075833954265
Short name T462
Test name
Test status
Simulation time 16404398 ps
CPU time 0.7 seconds
Started Nov 22 01:39:07 PM PST 23
Finished Nov 22 01:39:09 PM PST 23
Peak memory 207600 kb
Host smart-5082765d-2c2a-4484-8f5a-6f2591be1acc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102554092261183166111654895876000943878588152777102841505605007526075833954265 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_volatile_unlock_smoke.1025540922611831661116548958760009438785881527771028
41505605007526075833954265
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.76196277484023597236935686699692804461461429928611467511496575352986069817421
Short name T425
Test name
Test status
Simulation time 42189906 ps
CPU time 0.89 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 207720 kb
Host smart-ec9d8632-e06d-43c7-90e9-16260a108204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76196277484023597236935686699692804461461429928611467511496575352986069817421 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.76196277484023597236935686699692804461461429928611467511496575352986069817421
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.29798116517833713182336626805772694172610191058538892753918195684542209759541
Short name T414
Test name
Test status
Simulation time 978628843 ps
CPU time 14.01 seconds
Started Nov 22 01:39:12 PM PST 23
Finished Nov 22 01:39:27 PM PST 23
Peak memory 217308 kb
Host smart-e7a4196f-8053-4b8d-9bfa-1ee415e830b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29798116517833713182336626805772694172610191058538892753918195684542209759541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.lc_ctrl_errors.29798116517833713182336626805772694172610191058538892753918195684542209759541
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.75824539560150047532189029717249410670390272697493910008728663293233822813923
Short name T685
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.49 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:27 PM PST 23
Peak memory 208964 kb
Host smart-5ab86b80-d7c2-48c9-be50-253da9c2732c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75824539560150047532189029717249410670390272697493910008728663293233822813923 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.75824539560150047532189029717249410670390272697493910008728663293233822813923
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.11139496859449308544296306917834708947362621054014069388885495628279805999615
Short name T586
Test name
Test status
Simulation time 159313969 ps
CPU time 3.05 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 217416 kb
Host smart-444c917f-f2f9-4fe3-b61f-115b081a6958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11139496859449308544296306917834708947362621054014069388885495628279805999615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.lc_ctrl_prog_failure.11139496859449308544296306917834708947362621054014069388885495628279805999615
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.108202946135770218664443529764700219876245126973181034027021775892638991933172
Short name T310
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.33 seconds
Started Nov 22 01:39:12 PM PST 23
Finished Nov 22 01:39:27 PM PST 23
Peak memory 218492 kb
Host smart-69ca2833-d1b1-4b64-a92a-76ba02b18f32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108202946135770218664443529764700219876245126973181034027021775892638991933172 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.108202946135770218664443529764700219876245126973181034027021775892638991933172
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.54685732495802321322618064177325477954030353118271843657594808505024207338623
Short name T933
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.77 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:34 PM PST 23
Peak memory 217436 kb
Host smart-8c5bdb72-9ac0-43eb-992e-598163c71b68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54685732495802321322618064177325477954030353118271843657594808505024207338623 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_digest.54685732495802321322618064177325477954030353118271843657594808505024207338623
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.54139017252013793542831300055898564550935885494600465813769259273619555729680
Short name T619
Test name
Test status
Simulation time 964986095 ps
CPU time 10.82 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:28 PM PST 23
Peak memory 217328 kb
Host smart-56690b06-0b0c-415c-99e6-13ffcc03d57b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54139017252013793542831300055898564550935885494600465813769259273619555729680 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.54139017252013793542831300055898564550935885494600465813769259273619555729680
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.70705437611256198976655930324969734209749891611019263027350309485152738837528
Short name T304
Test name
Test status
Simulation time 625328098 ps
CPU time 8.44 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:26 PM PST 23
Peak memory 217380 kb
Host smart-c1523470-d7bf-45e4-ae47-7f54daa730d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70705437611256198976655930324969734209749891611019263027350309485152738837528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.lc_ctrl_security_escalation.70705437611256198976655930324969734209749891611019263027350309485152738837528
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.27800096105844185344693019089918978978536826463573857401480894352791599928844
Short name T431
Test name
Test status
Simulation time 291295056 ps
CPU time 4.57 seconds
Started Nov 22 01:39:13 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 213856 kb
Host smart-198112a3-1560-47c8-9d1f-11a26e198f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27800096105844185344693019089918978978536826463573857401480894352791599928844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.lc_ctrl_smoke.27800096105844185344693019089918978978536826463573857401480894352791599928844
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.51124364675464909163754273208374140208750643117387136548039932348989092067925
Short name T771
Test name
Test status
Simulation time 487150632 ps
CPU time 20.27 seconds
Started Nov 22 01:39:13 PM PST 23
Finished Nov 22 01:39:35 PM PST 23
Peak memory 250448 kb
Host smart-1a46c5a5-c22d-4f1e-9a96-1aade78fe2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51124364675464909163754273208374140208750643117387136548039932348989092067925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.lc_ctrl_state_failure.51124364675464909163754273208374140208750643117387136548039932348989092067925
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.66336119352027235734688736965225559175461243334462619368190683982122816738500
Short name T691
Test name
Test status
Simulation time 217117078 ps
CPU time 7.04 seconds
Started Nov 22 01:39:13 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 246320 kb
Host smart-4f0c7a40-69f9-4388-afeb-bd90679518fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66336119352027235734688736965225559175461243334462619368190683982122816738500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.lc_ctrl_state_post_trans.66336119352027235734688736965225559175461243334462619368190683982122816738500
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.46342433560933481470733358272377618901750747015677294796648148098623081613392
Short name T904
Test name
Test status
Simulation time 36820395678 ps
CPU time 286.7 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:44:04 PM PST 23
Peak memory 283400 kb
Host smart-c4b50f45-6374-4072-a32b-1c65c601e2da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463424335609334814707333582723776189017507470156772947966481480986
23081613392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.46342433560933481470733358272377618901750747015677294796
648148098623081613392
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.35808772857122599313943653575953095468518605632872535165693222575577416900492
Short name T14
Test name
Test status
Simulation time 16404398 ps
CPU time 0.73 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 207616 kb
Host smart-e21d6857-e71f-4c27-a4ee-aaee2ce2b2f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35808772857122599313943653575953095468518605632872535165693222575577416900492 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_volatile_unlock_smoke.35808772857122599313943653575953095468518605632872535
165693222575577416900492
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.81029163704811668770982275768804110460027406040418204492562846145066328955812
Short name T868
Test name
Test status
Simulation time 42189906 ps
CPU time 0.91 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:16 PM PST 23
Peak memory 207732 kb
Host smart-8699613b-3b57-487e-bb5b-874e0ebca9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81029163704811668770982275768804110460027406040418204492562846145066328955812 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.81029163704811668770982275768804110460027406040418204492562846145066328955812
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.9780053638290470023559006972031077839407811358986554303666016348790945249077
Short name T833
Test name
Test status
Simulation time 978628843 ps
CPU time 13.44 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:31 PM PST 23
Peak memory 217448 kb
Host smart-193e9f55-e2ba-48f1-b9c7-b5e9118173d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9780053638290470023559006972031077839407811358986554303666016348790945249077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.lc_ctrl_errors.9780053638290470023559006972031077839407811358986554303666016348790945249077
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.57965049483752582997767606241931211935547864884031692398042255454986212062027
Short name T395
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.62 seconds
Started Nov 22 01:39:12 PM PST 23
Finished Nov 22 01:39:23 PM PST 23
Peak memory 209004 kb
Host smart-42c7640e-fc72-4a2a-83bb-22f4a4cedf2b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57965049483752582997767606241931211935547864884031692398042255454986212062027 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.57965049483752582997767606241931211935547864884031692398042255454986212062027
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.55175891034801716255902209831852055607189901793859055156651641636323007779899
Short name T778
Test name
Test status
Simulation time 159313969 ps
CPU time 3.11 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 217460 kb
Host smart-b723c1db-77a9-44b4-b02c-9ff4ea4f0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55175891034801716255902209831852055607189901793859055156651641636323007779899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.lc_ctrl_prog_failure.55175891034801716255902209831852055607189901793859055156651641636323007779899
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.40184283541020280847568898499883014260700676861407681345069433196869189665617
Short name T922
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.11 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:32 PM PST 23
Peak memory 218500 kb
Host smart-85138413-086c-4d49-836a-721508bbf6cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40184283541020280847568898499883014260700676861407681345069433196869189665617 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.40184283541020280847568898499883014260700676861407681345069433196869189665617
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.57707624498736441385454574360520630086567889011705453178328033282027771586142
Short name T923
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.34 seconds
Started Nov 22 01:39:17 PM PST 23
Finished Nov 22 01:39:36 PM PST 23
Peak memory 217412 kb
Host smart-fc3a9d47-8076-46cc-ad17-f70404c6e356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57707624498736441385454574360520630086567889011705453178328033282027771586142 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_digest.57707624498736441385454574360520630086567889011705453178328033282027771586142
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.50445216199595142844604009122238976977422580183453474893221965371771931332846
Short name T540
Test name
Test status
Simulation time 964986095 ps
CPU time 10.83 seconds
Started Nov 22 01:39:19 PM PST 23
Finished Nov 22 01:39:31 PM PST 23
Peak memory 217312 kb
Host smart-3cb6dc14-d4a1-42ad-bb70-39b8205e30f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50445216199595142844604009122238976977422580183453474893221965371771931332846 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.50445216199595142844604009122238976977422580183453474893221965371771931332846
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.24894573592758015500989146632787252254431122463139354628468864830937818157442
Short name T856
Test name
Test status
Simulation time 625328098 ps
CPU time 8.53 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:26 PM PST 23
Peak memory 217380 kb
Host smart-fa3024e9-da47-4ff5-aa03-d0010b08b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24894573592758015500989146632787252254431122463139354628468864830937818157442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.lc_ctrl_security_escalation.24894573592758015500989146632787252254431122463139354628468864830937818157442
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.80680628807945897614741616926288715531172411725261667254087927519735493499969
Short name T791
Test name
Test status
Simulation time 291295056 ps
CPU time 4.5 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 213808 kb
Host smart-c17a518f-caab-420f-bce4-0765ac82f310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80680628807945897614741616926288715531172411725261667254087927519735493499969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.lc_ctrl_smoke.80680628807945897614741616926288715531172411725261667254087927519735493499969
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.68849699528105143188820307537932577416636569831528405626819647964036152516873
Short name T377
Test name
Test status
Simulation time 487150632 ps
CPU time 20.63 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:36 PM PST 23
Peak memory 250308 kb
Host smart-0f812b36-f47d-4bfb-8daf-5a4b46f762d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68849699528105143188820307537932577416636569831528405626819647964036152516873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.lc_ctrl_state_failure.68849699528105143188820307537932577416636569831528405626819647964036152516873
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.43009009992801725554762925588905145680928211869797913773543013563730488249975
Short name T503
Test name
Test status
Simulation time 217117078 ps
CPU time 7.32 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:23 PM PST 23
Peak memory 246272 kb
Host smart-2e2713c0-c5f7-498e-988a-25eb86211c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43009009992801725554762925588905145680928211869797913773543013563730488249975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.lc_ctrl_state_post_trans.43009009992801725554762925588905145680928211869797913773543013563730488249975
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.16684892703746999434977761961745973668631620992030509039478965093062294475781
Short name T830
Test name
Test status
Simulation time 36820395678 ps
CPU time 286.1 seconds
Started Nov 22 01:39:13 PM PST 23
Finished Nov 22 01:44:00 PM PST 23
Peak memory 283472 kb
Host smart-1cd69eae-7f2a-4e8e-9150-f1a88f14d241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166848927037469994349777619617459736686316209920305090394789650930
62294475781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.16684892703746999434977761961745973668631620992030509039
478965093062294475781
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.81612638924736895745686137173196513838554402363032743835324855100187836396255
Short name T36
Test name
Test status
Simulation time 16404398 ps
CPU time 0.77 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 207576 kb
Host smart-612fcfed-7b68-4003-bbcf-f38e0f2fc0e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81612638924736895745686137173196513838554402363032743835324855100187836396255 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_volatile_unlock_smoke.81612638924736895745686137173196513838554402363032743
835324855100187836396255
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.92073010321687558679570425512529802969573513473377831904348641142664948819720
Short name T333
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:17 PM PST 23
Peak memory 207836 kb
Host smart-3c72d07c-66ed-46b4-8f68-1962890df8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92073010321687558679570425512529802969573513473377831904348641142664948819720 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.92073010321687558679570425512529802969573513473377831904348641142664948819720
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.90853363949234391659836849143515143374831922975771898642545196823360433745962
Short name T806
Test name
Test status
Simulation time 978628843 ps
CPU time 13.45 seconds
Started Nov 22 01:39:19 PM PST 23
Finished Nov 22 01:39:35 PM PST 23
Peak memory 217368 kb
Host smart-22d9e964-3982-4a78-9768-43c80b94d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90853363949234391659836849143515143374831922975771898642545196823360433745962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.lc_ctrl_errors.90853363949234391659836849143515143374831922975771898642545196823360433745962
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.93308235450620487253757225959195695579845825724657881258413124752896309727915
Short name T743
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.38 seconds
Started Nov 22 01:39:19 PM PST 23
Finished Nov 22 01:39:30 PM PST 23
Peak memory 208908 kb
Host smart-f705d27b-da9e-4a06-be8c-a7a00bdbf8d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93308235450620487253757225959195695579845825724657881258413124752896309727915 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.93308235450620487253757225959195695579845825724657881258413124752896309727915
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.52305750122779031797454783006669558813601627830037286954968488890137261699104
Short name T597
Test name
Test status
Simulation time 159313969 ps
CPU time 3.19 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 217460 kb
Host smart-f3cdcd74-842e-4836-9f72-21c050d4a7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52305750122779031797454783006669558813601627830037286954968488890137261699104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.lc_ctrl_prog_failure.52305750122779031797454783006669558813601627830037286954968488890137261699104
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1572703271540760371543513679099874082217972072100989745269521230762398735146
Short name T407
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.48 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:31 PM PST 23
Peak memory 218496 kb
Host smart-229c705e-10bf-4738-853f-5dc588140ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572703271540760371543513679099874082217972072100989745269521230762398735146 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1572703271540760371543513679099874082217972072100989745269521230762398735146
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.58712966801443418518505982554959341257450298874379149109600850880848092171368
Short name T618
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.34 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:33 PM PST 23
Peak memory 217416 kb
Host smart-22acde8b-8887-43a8-ba7c-2ccbdf5e3c38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58712966801443418518505982554959341257450298874379149109600850880848092171368 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_digest.58712966801443418518505982554959341257450298874379149109600850880848092171368
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.72805488895022529507441783099654636433720858173309435284419085957368583480788
Short name T513
Test name
Test status
Simulation time 964986095 ps
CPU time 11.22 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:29 PM PST 23
Peak memory 217412 kb
Host smart-edaab773-ab35-4fe7-a713-a31c3ab647da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72805488895022529507441783099654636433720858173309435284419085957368583480788 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.72805488895022529507441783099654636433720858173309435284419085957368583480788
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.55875014837790237650343639240789368030251850324620170508207106600893263014049
Short name T655
Test name
Test status
Simulation time 625328098 ps
CPU time 8.4 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:25 PM PST 23
Peak memory 217572 kb
Host smart-0e67a274-482b-402a-8cca-3dfd0aea31fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55875014837790237650343639240789368030251850324620170508207106600893263014049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.lc_ctrl_security_escalation.55875014837790237650343639240789368030251850324620170508207106600893263014049
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.88610418080718425905195423138281965108304479750389503062722488947693463820434
Short name T321
Test name
Test status
Simulation time 291295056 ps
CPU time 4.83 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:21 PM PST 23
Peak memory 213816 kb
Host smart-694aab65-a050-49ba-bcf4-23d65af66d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88610418080718425905195423138281965108304479750389503062722488947693463820434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.lc_ctrl_smoke.88610418080718425905195423138281965108304479750389503062722488947693463820434
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.64965696139979415652942255324581479248786632814759539616167641726915205028688
Short name T701
Test name
Test status
Simulation time 487150632 ps
CPU time 20.61 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:37 PM PST 23
Peak memory 250308 kb
Host smart-f9d15656-e3c0-478d-aee4-2099531c855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64965696139979415652942255324581479248786632814759539616167641726915205028688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.lc_ctrl_state_failure.64965696139979415652942255324581479248786632814759539616167641726915205028688
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.57229895557493586238232144041332500949328497185661602875659713329041870394688
Short name T62
Test name
Test status
Simulation time 217117078 ps
CPU time 6.84 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:25 PM PST 23
Peak memory 246328 kb
Host smart-91dbf79f-f727-4969-aeb8-749ccb5c2315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57229895557493586238232144041332500949328497185661602875659713329041870394688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.lc_ctrl_state_post_trans.57229895557493586238232144041332500949328497185661602875659713329041870394688
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.13319580981331221503053610057860382114842413229775498300085282774576995595475
Short name T819
Test name
Test status
Simulation time 36820395678 ps
CPU time 281.24 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:43:59 PM PST 23
Peak memory 283472 kb
Host smart-1cb86d7b-3679-4149-9452-ab7c3a2d13a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133195809813312215030536100578603821148424132297754983000852827745
76995595475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.13319580981331221503053610057860382114842413229775498300
085282774576995595475
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.102422419992993634489931742904350145254724282809509811042616061534791780465475
Short name T388
Test name
Test status
Simulation time 16404398 ps
CPU time 0.74 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 207580 kb
Host smart-de6c2bb6-0b65-4cd4-aaca-14d095720953
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102422419992993634489931742904350145254724282809509811042616061534791780465475 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_volatile_unlock_smoke.1024224199929936344899317429043501452547242828095098
11042616061534791780465475
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.103080108910343029570040331817596381618671259808238149199949978747928860655827
Short name T566
Test name
Test status
Simulation time 42189906 ps
CPU time 0.99 seconds
Started Nov 22 01:39:18 PM PST 23
Finished Nov 22 01:39:20 PM PST 23
Peak memory 207772 kb
Host smart-fafb75fb-6a22-4e17-b29a-fc7fa643e45c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103080108910343029570040331817596381618671259808238149199949978747928860655827 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.103080108910343029570040331817596381618671259808238149199949978747928860655827
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.41677927198496000406748206080818438432840128662675673533700240127899456440644
Short name T478
Test name
Test status
Simulation time 978628843 ps
CPU time 13.54 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:32 PM PST 23
Peak memory 217380 kb
Host smart-499171d5-ae0a-4362-872a-d92f713f0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41677927198496000406748206080818438432840128662675673533700240127899456440644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.lc_ctrl_errors.41677927198496000406748206080818438432840128662675673533700240127899456440644
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.24235395212842948306969885171927415994056008297759885929787606697453856772213
Short name T637
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.39 seconds
Started Nov 22 01:39:17 PM PST 23
Finished Nov 22 01:39:29 PM PST 23
Peak memory 209012 kb
Host smart-e5600e3e-24e8-4e45-83a5-9020a65a58ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24235395212842948306969885171927415994056008297759885929787606697453856772213 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.24235395212842948306969885171927415994056008297759885929787606697453856772213
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.46522663508318933255149141994305935993755570918399701569423599888192543273497
Short name T578
Test name
Test status
Simulation time 159313969 ps
CPU time 2.82 seconds
Started Nov 22 01:39:17 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 217408 kb
Host smart-d7b4dde4-4db0-413a-ad69-9a5797fdc687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46522663508318933255149141994305935993755570918399701569423599888192543273497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.lc_ctrl_prog_failure.46522663508318933255149141994305935993755570918399701569423599888192543273497
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.62275055598853537496985278276866187445627718696649726596178594491096492539925
Short name T361
Test name
Test status
Simulation time 1010128591 ps
CPU time 13.97 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:30 PM PST 23
Peak memory 218416 kb
Host smart-75bd9628-8ad4-4bcf-961b-be3000d0910c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62275055598853537496985278276866187445627718696649726596178594491096492539925 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.62275055598853537496985278276866187445627718696649726596178594491096492539925
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.17074005187847883487496032757516634543908905627477502074176298967343559607414
Short name T915
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.65 seconds
Started Nov 22 01:39:18 PM PST 23
Finished Nov 22 01:39:36 PM PST 23
Peak memory 217440 kb
Host smart-fad77f12-dcf0-47db-a742-396962467d71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074005187847883487496032757516634543908905627477502074176298967343559607414 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_digest.17074005187847883487496032757516634543908905627477502074176298967343559607414
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.59927702602276752020069054959121674514677464806032078693225705453124227840750
Short name T838
Test name
Test status
Simulation time 964986095 ps
CPU time 10.8 seconds
Started Nov 22 01:39:18 PM PST 23
Finished Nov 22 01:39:30 PM PST 23
Peak memory 217344 kb
Host smart-63947af8-e5e2-4a63-8e1d-6f345cd2f85f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59927702602276752020069054959121674514677464806032078693225705453124227840750 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.59927702602276752020069054959121674514677464806032078693225705453124227840750
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.39963325936560116896929915062439508365343352433858191598988837143149458238840
Short name T646
Test name
Test status
Simulation time 625328098 ps
CPU time 8.29 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:24 PM PST 23
Peak memory 217384 kb
Host smart-edd72d4e-80ee-4000-bdf7-61fd9be9974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39963325936560116896929915062439508365343352433858191598988837143149458238840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.lc_ctrl_security_escalation.39963325936560116896929915062439508365343352433858191598988837143149458238840
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.65075332203192274772982996605833398047180883635481428123553871439848680893482
Short name T53
Test name
Test status
Simulation time 291295056 ps
CPU time 4.36 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 213764 kb
Host smart-d4dc3213-4963-427c-9d9b-27e2a97e2801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65075332203192274772982996605833398047180883635481428123553871439848680893482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.lc_ctrl_smoke.65075332203192274772982996605833398047180883635481428123553871439848680893482
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.87171944794736026663989137795889958583777863911483806688763198307466143714967
Short name T512
Test name
Test status
Simulation time 487150632 ps
CPU time 21.35 seconds
Started Nov 22 01:39:18 PM PST 23
Finished Nov 22 01:39:41 PM PST 23
Peak memory 250468 kb
Host smart-f13b82fd-3145-47e7-9b8a-cd3ae0b3450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87171944794736026663989137795889958583777863911483806688763198307466143714967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.lc_ctrl_state_failure.87171944794736026663989137795889958583777863911483806688763198307466143714967
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.109628434579249536386080037782018209745413825928881993816457995028062618847081
Short name T839
Test name
Test status
Simulation time 217117078 ps
CPU time 7.21 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 246328 kb
Host smart-db920783-c9b0-48b6-bdd9-6701f26da5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109628434579249536386080037782018209745413825928881993816457995028062618847081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 38.lc_ctrl_state_post_trans.109628434579249536386080037782018209745413825928881993816457995028062618847081
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.7479085677522663721834282023252562891441702662517027068980882700650725072993
Short name T794
Test name
Test status
Simulation time 36820395678 ps
CPU time 288.12 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:44:06 PM PST 23
Peak memory 279552 kb
Host smart-0a60d94c-6663-4064-9cc2-aff05c4456f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747908567752266372183428202325256289144170266251702706898088270065
0725072993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.747908567752266372183428202325256289144170266251702706898
0882700650725072993
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.42851903756712291722463507243785094135005476721459767795507706135443721296998
Short name T467
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:39:14 PM PST 23
Finished Nov 22 01:39:16 PM PST 23
Peak memory 207608 kb
Host smart-facbb759-9621-4a0a-a6d3-ea57d1dc4f1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851903756712291722463507243785094135005476721459767795507706135443721296998 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_volatile_unlock_smoke.42851903756712291722463507243785094135005476721459767
795507706135443721296998
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.74922830835675262932154280561100700312737415957168635002211769903372434103336
Short name T508
Test name
Test status
Simulation time 42189906 ps
CPU time 0.92 seconds
Started Nov 22 01:39:26 PM PST 23
Finished Nov 22 01:39:27 PM PST 23
Peak memory 207716 kb
Host smart-50eef942-eb12-4f4a-ba55-1c86b4199819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74922830835675262932154280561100700312737415957168635002211769903372434103336 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.74922830835675262932154280561100700312737415957168635002211769903372434103336
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.69616848001565440817930021340299502115242635844204175701126513267410996162450
Short name T544
Test name
Test status
Simulation time 978628843 ps
CPU time 13.42 seconds
Started Nov 22 01:39:15 PM PST 23
Finished Nov 22 01:39:31 PM PST 23
Peak memory 217472 kb
Host smart-fd0668ab-71ab-4063-9962-b8a1a286a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69616848001565440817930021340299502115242635844204175701126513267410996162450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.lc_ctrl_errors.69616848001565440817930021340299502115242635844204175701126513267410996162450
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.45700565827427814003874398510657941539071473001173113944063201111958213595433
Short name T557
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.28 seconds
Started Nov 22 01:39:30 PM PST 23
Finished Nov 22 01:39:40 PM PST 23
Peak memory 208972 kb
Host smart-d34c1424-74b0-4da6-bf6c-71b49dc71c80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45700565827427814003874398510657941539071473001173113944063201111958213595433 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.45700565827427814003874398510657941539071473001173113944063201111958213595433
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.81549797458896827557005364116970703465210262842302745143964040878949335685749
Short name T360
Test name
Test status
Simulation time 159313969 ps
CPU time 2.87 seconds
Started Nov 22 01:39:19 PM PST 23
Finished Nov 22 01:39:24 PM PST 23
Peak memory 217376 kb
Host smart-a08e2bfb-8aeb-4e43-b970-351a9492ff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81549797458896827557005364116970703465210262842302745143964040878949335685749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.lc_ctrl_prog_failure.81549797458896827557005364116970703465210262842302745143964040878949335685749
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.53527024754297041005322096164207190521673711435556607302263713979671727170302
Short name T383
Test name
Test status
Simulation time 1010128591 ps
CPU time 13.99 seconds
Started Nov 22 01:39:27 PM PST 23
Finished Nov 22 01:39:42 PM PST 23
Peak memory 218504 kb
Host smart-aa9f4ff1-1625-4fff-b54d-504fb4e0b596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53527024754297041005322096164207190521673711435556607302263713979671727170302 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.53527024754297041005322096164207190521673711435556607302263713979671727170302
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.115584289226805231380064678852687256429631008611020203011745694185610889907839
Short name T278
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.73 seconds
Started Nov 22 01:39:28 PM PST 23
Finished Nov 22 01:39:44 PM PST 23
Peak memory 217388 kb
Host smart-cd96e89e-6a4a-4015-a2de-d0b7adda07cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115584289226805231380064678852687256429631008611020203011745694185610889907839 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_digest.115584289226805231380064678852687256429631008611020203011745694185610889907839
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.94301712448787023395796796359469662370137796818861592891173210922615469246415
Short name T466
Test name
Test status
Simulation time 964986095 ps
CPU time 10.66 seconds
Started Nov 22 01:39:20 PM PST 23
Finished Nov 22 01:39:32 PM PST 23
Peak memory 217292 kb
Host smart-4bc7aa74-31da-4d5b-a272-6cb9b9afc308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94301712448787023395796796359469662370137796818861592891173210922615469246415 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.94301712448787023395796796359469662370137796818861592891173210922615469246415
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.103891540228694102470307218018175501675013222758542752980540740587104618660751
Short name T533
Test name
Test status
Simulation time 625328098 ps
CPU time 8.29 seconds
Started Nov 22 01:39:21 PM PST 23
Finished Nov 22 01:39:30 PM PST 23
Peak memory 217336 kb
Host smart-ca6ad21d-f2d3-4a6c-a856-6a02274b582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103891540228694102470307218018175501675013222758542752980540740587104618660751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.lc_ctrl_security_escalation.103891540228694102470307218018175501675013222758542752980540740587104618660751
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.114866020934440520086617537543928471882316406626311688914428926378342437866108
Short name T732
Test name
Test status
Simulation time 291295056 ps
CPU time 4.46 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:22 PM PST 23
Peak memory 213860 kb
Host smart-f9d05d55-c31d-4147-9238-a57dfe6f6007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114866020934440520086617537543928471882316406626311688914428926378342437866108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.lc_ctrl_smoke.114866020934440520086617537543928471882316406626311688914428926378342437866108
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.76389167982514973359483542237354165393198271467421257902934600332511600166833
Short name T751
Test name
Test status
Simulation time 487150632 ps
CPU time 21.55 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:39 PM PST 23
Peak memory 250452 kb
Host smart-1a2198e3-8c63-416d-aa31-64bbd23e7190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76389167982514973359483542237354165393198271467421257902934600332511600166833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.lc_ctrl_state_failure.76389167982514973359483542237354165393198271467421257902934600332511600166833
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.89030718115968776048271769156629374276859322039154106279715918776856174569970
Short name T777
Test name
Test status
Simulation time 217117078 ps
CPU time 6.87 seconds
Started Nov 22 01:39:18 PM PST 23
Finished Nov 22 01:39:26 PM PST 23
Peak memory 246276 kb
Host smart-14358330-a26f-4992-9a69-0ae4a82b40b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89030718115968776048271769156629374276859322039154106279715918776856174569970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.lc_ctrl_state_post_trans.89030718115968776048271769156629374276859322039154106279715918776856174569970
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.19253155079963285595249082555595525047884501415828659884359615581331906036315
Short name T47
Test name
Test status
Simulation time 36820395678 ps
CPU time 279.76 seconds
Started Nov 22 01:39:19 PM PST 23
Finished Nov 22 01:44:01 PM PST 23
Peak memory 283320 kb
Host smart-cc2e6199-9f65-4b43-a550-6523fd473826
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192531550799632855952490825555955250478845014158286598843596155813
31906036315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.19253155079963285595249082555595525047884501415828659884
359615581331906036315
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.109566832182165247350625942460825929338759632980021525743649864038429055995657
Short name T484
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:39:17 PM PST 23
Finished Nov 22 01:39:19 PM PST 23
Peak memory 207624 kb
Host smart-6408b02c-0875-4da9-9ede-d5c05e62f905
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109566832182165247350625942460825929338759632980021525743649864038429055995657 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_volatile_unlock_smoke.1095668321821652473506259424608259293387596329800215
25743649864038429055995657
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.26279104621715356326240940140321752162780857272589175843061891582683028575873
Short name T382
Test name
Test status
Simulation time 42189906 ps
CPU time 0.99 seconds
Started Nov 22 01:37:40 PM PST 23
Finished Nov 22 01:37:41 PM PST 23
Peak memory 207776 kb
Host smart-b977e766-36ec-4a6e-af58-b327e9bcb5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26279104621715356326240940140321752162780857272589175843061891582683028575873 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.26279104621715356326240940140321752162780857272589175843061891582683028575873
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.99500404704654833453245028537849050403056284108018082028416275322089411927572
Short name T357
Test name
Test status
Simulation time 19636515 ps
CPU time 0.79 seconds
Started Nov 22 01:37:24 PM PST 23
Finished Nov 22 01:37:29 PM PST 23
Peak memory 207576 kb
Host smart-aadba6cb-272b-41f9-b6f5-03e1e7cf2ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99500404704654833453245028537849050403056284108018082028416275322089411927572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.99500404704654833453245028537849050403056284108018082028416275322089411927572
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.38446377413277725021853393642624862981314301288267119628656147640274627846376
Short name T344
Test name
Test status
Simulation time 978628843 ps
CPU time 13.56 seconds
Started Nov 22 01:37:26 PM PST 23
Finished Nov 22 01:37:43 PM PST 23
Peak memory 217448 kb
Host smart-1c985b35-f402-4176-b818-57adc841e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38446377413277725021853393642624862981314301288267119628656147640274627846376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.lc_ctrl_errors.38446377413277725021853393642624862981314301288267119628656147640274627846376
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.79112770650554825263318635388748546269172479662948715278315627412213685643551
Short name T30
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.49 seconds
Started Nov 22 01:37:30 PM PST 23
Finished Nov 22 01:37:40 PM PST 23
Peak memory 208952 kb
Host smart-3172eef3-5e24-400a-a0ac-029635f3f4b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79112770650554825263318635388748546269172479662948715278315627412213685643551 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.79112770650554825263318635388748546269172479662948715278315627412213685643551
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.92051013672353714203758332967622572093124049556720566189982429602144029610526
Short name T588
Test name
Test status
Simulation time 5872518263 ps
CPU time 41.58 seconds
Started Nov 22 01:37:25 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 217812 kb
Host smart-9e913c70-5658-424a-83a7-8e6ce9be7599
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92051013672353714203758332967622572093124049556720566189982429602144029610526 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_errors.92051013672353714203758332967622572093124049556720566189982429602144029610526
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.63491497926303808711949567038254950349843858853790325203898991988187586714051
Short name T908
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.18 seconds
Started Nov 22 01:37:29 PM PST 23
Finished Nov 22 01:37:43 PM PST 23
Peak memory 217356 kb
Host smart-239397ba-8aa5-4cd0-b6fa-e98d4a2f880b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63491497926303808711949567038254950349843858853790325203898991988187586714051 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.63491497926303808711949567038254950349843858853790325203898991988187586714051
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.72845748785531982002696451191706304217090911127548919615356257532004139636477
Short name T408
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.54 seconds
Started Nov 22 01:37:13 PM PST 23
Finished Nov 22 01:37:26 PM PST 23
Peak memory 217348 kb
Host smart-909e41f7-a338-4f2d-b3c0-581b86db6d37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72845748785531982002696451191706304217090911127548919615356257532004139636477 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prog_failure.72845748785531982002696451191706304217090911127548919615356257532004139636477
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.75183752495657566753496099433978577842032920102949558720008137373711013538599
Short name T405
Test name
Test status
Simulation time 1406053995 ps
CPU time 9.67 seconds
Started Nov 22 01:37:27 PM PST 23
Finished Nov 22 01:37:39 PM PST 23
Peak memory 212320 kb
Host smart-c6215cf6-ceab-41e0-a0e2-3d20f87bd15b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75183752495657566753496099433978577842032920102949558720008137373711013538599 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_regwen_during_op.751837524956575667534960994339785778420329201029495587200
08137373711013538599
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.78952206415033863123921837857750535027346995027389791301856027662826792021295
Short name T327
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.71 seconds
Started Nov 22 01:37:13 PM PST 23
Finished Nov 22 01:37:23 PM PST 23
Peak memory 212876 kb
Host smart-fe70aa97-bb86-47ef-a3ad-35dd2789db81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78952206415033863123921837857750535027346995027389791301856027662826792021295 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.78952206415033863123921837857750535027346995027389791301856027662826792021295
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.64417260811546703697476980603247656985662249615031973515988213824111330134763
Short name T28
Test name
Test status
Simulation time 5030489285 ps
CPU time 49.78 seconds
Started Nov 22 01:37:26 PM PST 23
Finished Nov 22 01:38:19 PM PST 23
Peak memory 269156 kb
Host smart-ce65eebc-29da-4e72-a605-637c5ead3e11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64417260811546703697476980603247656985662249615031973515988213824111330134763 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_state_failure.644172608115467036974769806032476569856622496150319735159882138
24111330134763
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.54341848366092396463262052219592522671846650113649736515302629625717890114633
Short name T690
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.85 seconds
Started Nov 22 01:37:24 PM PST 23
Finished Nov 22 01:37:44 PM PST 23
Peak memory 246824 kb
Host smart-5de863db-12df-434e-966f-87499a997b05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54341848366092396463262052219592522671846650113649736515302629625717890114633 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_state_post_trans.543418483660923964632620522195925226718466501136497365153
02629625717890114633
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.18339783449394469768504919105691738378378579816330958667108656180191345345442
Short name T397
Test name
Test status
Simulation time 159313969 ps
CPU time 2.98 seconds
Started Nov 22 01:37:23 PM PST 23
Finished Nov 22 01:37:28 PM PST 23
Peak memory 217428 kb
Host smart-03b00e6f-1800-4000-ab1e-5620c400b25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18339783449394469768504919105691738378378579816330958667108656180191345345442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_prog_failure.18339783449394469768504919105691738378378579816330958667108656180191345345442
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.45620216583457804543178982266878739481043447080488964089459901236805562267836
Short name T802
Test name
Test status
Simulation time 420615450 ps
CPU time 5.61 seconds
Started Nov 22 01:37:30 PM PST 23
Finished Nov 22 01:37:36 PM PST 23
Peak memory 213296 kb
Host smart-63ef353e-2ef5-4afc-8f99-a1bd5dd5b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45620216583457804543178982266878739481043447080488964089459901236805562267836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.lc_ctrl_regwen_during_op.45620216583457804543178982266878739481043447080488964089459901236805562267836
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.101939344554869461336767729703048959961005278442459349340263526049705560074964
Short name T64
Test name
Test status
Simulation time 386472866 ps
CPU time 36.6 seconds
Started Nov 22 01:37:37 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 273556 kb
Host smart-43f7e8cc-3b38-4fab-a0e9-506e8f41851e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101939344554869461336767729703048959961005278442459349340263526049705560074964 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.101939344554869461336767729703048959961005278442459349340263526049705560074964
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.40721004664261999036213170957868592178690292524211896940848723887488405922891
Short name T662
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.55 seconds
Started Nov 22 01:37:29 PM PST 23
Finished Nov 22 01:37:45 PM PST 23
Peak memory 218436 kb
Host smart-025e67c9-0390-4b2f-bba7-ede8291fec7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721004664261999036213170957868592178690292524211896940848723887488405922891 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.40721004664261999036213170957868592178690292524211896940848723887488405922891
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.47697268188099811228824266073234184523466782747953781161303491196186428784448
Short name T712
Test name
Test status
Simulation time 1321911811 ps
CPU time 17.08 seconds
Started Nov 22 01:37:26 PM PST 23
Finished Nov 22 01:37:46 PM PST 23
Peak memory 217428 kb
Host smart-aa497727-a518-4f6c-8795-7f1cf5b620ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47697268188099811228824266073234184523466782747953781161303491196186428784448 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_digest.47697268188099811228824266073234184523466782747953781161303491196186428784448
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.25760859776117373242314476329829665572800260296406555309238816810386782525159
Short name T651
Test name
Test status
Simulation time 964986095 ps
CPU time 11.05 seconds
Started Nov 22 01:37:39 PM PST 23
Finished Nov 22 01:37:51 PM PST 23
Peak memory 217396 kb
Host smart-e8b1ad5d-35a3-45c6-b9a8-36418b6399d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25760859776117373242314476329829665572800260296406555309238816810386782525159 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.25760859776117373242314476329829665572800260296406555309238816810386782525159
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.88986537376503600956514212953537039145930415001368679274628656811635642587072
Short name T345
Test name
Test status
Simulation time 625328098 ps
CPU time 7.99 seconds
Started Nov 22 01:37:26 PM PST 23
Finished Nov 22 01:37:37 PM PST 23
Peak memory 217456 kb
Host smart-9622c60a-74ca-4e29-a088-92dd30589863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88986537376503600956514212953537039145930415001368679274628656811635642587072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.lc_ctrl_security_escalation.88986537376503600956514212953537039145930415001368679274628656811635642587072
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.81070915114209286204321176828915693860378931195857505221906930997505446234906
Short name T797
Test name
Test status
Simulation time 291295056 ps
CPU time 4.79 seconds
Started Nov 22 01:37:13 PM PST 23
Finished Nov 22 01:37:18 PM PST 23
Peak memory 213764 kb
Host smart-a1b75083-c338-495a-baf2-f0262a208205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81070915114209286204321176828915693860378931195857505221906930997505446234906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_smoke.81070915114209286204321176828915693860378931195857505221906930997505446234906
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.14333171910263566740974950438954892523928007044115406541530259285558478660152
Short name T715
Test name
Test status
Simulation time 487150632 ps
CPU time 20.83 seconds
Started Nov 22 01:37:13 PM PST 23
Finished Nov 22 01:37:35 PM PST 23
Peak memory 250368 kb
Host smart-39dc316d-edfd-4bd1-926b-dd980f906bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14333171910263566740974950438954892523928007044115406541530259285558478660152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_state_failure.14333171910263566740974950438954892523928007044115406541530259285558478660152
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.71546815494968222841067126303099820072542705047683786801466832972486919933788
Short name T709
Test name
Test status
Simulation time 217117078 ps
CPU time 7.18 seconds
Started Nov 22 01:37:17 PM PST 23
Finished Nov 22 01:37:29 PM PST 23
Peak memory 246340 kb
Host smart-d1787faa-b43d-4911-ae7a-bdf623a182b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71546815494968222841067126303099820072542705047683786801466832972486919933788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.lc_ctrl_state_post_trans.71546815494968222841067126303099820072542705047683786801466832972486919933788
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.12578798868671353999487077446249274599035606809194751883516358924808603307077
Short name T705
Test name
Test status
Simulation time 36820395678 ps
CPU time 285.05 seconds
Started Nov 22 01:37:28 PM PST 23
Finished Nov 22 01:42:15 PM PST 23
Peak memory 279608 kb
Host smart-da0175a3-1ee0-477c-b86d-8c18cedd8472
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125787988686713539994870774462492745990356068091947518835163589248
08603307077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.125787988686713539994870774462492745990356068091947518835
16358924808603307077
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.101930160918811415255118760645190433288016701777603305944080530921711772007919
Short name T609
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:37:25 PM PST 23
Finished Nov 22 01:37:29 PM PST 23
Peak memory 207580 kb
Host smart-ff0a49b2-5425-4a33-b97b-46fda9abca1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101930160918811415255118760645190433288016701777603305944080530921711772007919 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_volatile_unlock_smoke.10193016091881141525511876064519043328801670177760330
5944080530921711772007919
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.41234730402119489169431620134115756949376916985372037479339548385846339660504
Short name T340
Test name
Test status
Simulation time 42189906 ps
CPU time 0.97 seconds
Started Nov 22 01:39:34 PM PST 23
Finished Nov 22 01:39:40 PM PST 23
Peak memory 207700 kb
Host smart-2e1a8e09-4026-4461-81a9-81096c8d4ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41234730402119489169431620134115756949376916985372037479339548385846339660504 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.41234730402119489169431620134115756949376916985372037479339548385846339660504
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.60117469094505597750874434119509118684275246626380973195490497643914609397641
Short name T354
Test name
Test status
Simulation time 978628843 ps
CPU time 14.18 seconds
Started Nov 22 01:39:21 PM PST 23
Finished Nov 22 01:39:36 PM PST 23
Peak memory 217348 kb
Host smart-d7d9da24-9ff1-4625-b8b6-b7ab5a764ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60117469094505597750874434119509118684275246626380973195490497643914609397641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.lc_ctrl_errors.60117469094505597750874434119509118684275246626380973195490497643914609397641
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.340243062595911746475050883044849307675456221394643705240033769975312991297
Short name T812
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.4 seconds
Started Nov 22 01:39:29 PM PST 23
Finished Nov 22 01:39:39 PM PST 23
Peak memory 209008 kb
Host smart-a15877fd-f3a9-433d-b13b-c8ca62085a52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340243062595911746475050883044849307675456221394643705240033769975312991297 -assert n
opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.340243062595911746475050883044849307675456221394643705240033769975312991297
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.31586557998554671721066710543940276663235510900326823479883078987701491103824
Short name T267
Test name
Test status
Simulation time 159313969 ps
CPU time 3 seconds
Started Nov 22 01:39:29 PM PST 23
Finished Nov 22 01:39:33 PM PST 23
Peak memory 217496 kb
Host smart-d5c7cbdf-2dd2-4948-960f-d761e781d3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31586557998554671721066710543940276663235510900326823479883078987701491103824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.lc_ctrl_prog_failure.31586557998554671721066710543940276663235510900326823479883078987701491103824
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.25417149742410426513786992362138143003923231863120210293412252034486029482686
Short name T353
Test name
Test status
Simulation time 1010128591 ps
CPU time 15.22 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 218476 kb
Host smart-46bff4cd-1c40-4f61-a6ab-bae858d5625d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25417149742410426513786992362138143003923231863120210293412252034486029482686 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.25417149742410426513786992362138143003923231863120210293412252034486029482686
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.46251529111491933429361371505901157798858584622197219491918662797228293312794
Short name T693
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.81 seconds
Started Nov 22 01:39:43 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 217392 kb
Host smart-85e8edcc-b96b-452e-a3ae-cd14c4e9ceb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46251529111491933429361371505901157798858584622197219491918662797228293312794 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_digest.46251529111491933429361371505901157798858584622197219491918662797228293312794
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.78680526793794775833790073292844852670734993286152665638230749295571335944888
Short name T750
Test name
Test status
Simulation time 964986095 ps
CPU time 11.69 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 217380 kb
Host smart-35719be2-7cb9-43a9-9fc3-cee7b0efb1c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78680526793794775833790073292844852670734993286152665638230749295571335944888 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.78680526793794775833790073292844852670734993286152665638230749295571335944888
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.95242315316923639818101856600136771434997943163477408031332647586112337782584
Short name T324
Test name
Test status
Simulation time 625328098 ps
CPU time 9.32 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:06 PM PST 23
Peak memory 217312 kb
Host smart-bdc5c726-66a6-4759-b14a-2e7f5780775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95242315316923639818101856600136771434997943163477408031332647586112337782584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.lc_ctrl_security_escalation.95242315316923639818101856600136771434997943163477408031332647586112337782584
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.22065483889815820972435146536839100123676410788674320238352274845580079952590
Short name T88
Test name
Test status
Simulation time 291295056 ps
CPU time 4.54 seconds
Started Nov 22 01:39:30 PM PST 23
Finished Nov 22 01:39:35 PM PST 23
Peak memory 213800 kb
Host smart-7373e35f-8b7c-44da-a086-db194d6c1da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22065483889815820972435146536839100123676410788674320238352274845580079952590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.lc_ctrl_smoke.22065483889815820972435146536839100123676410788674320238352274845580079952590
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.9600609577643963474230944662125871976680595179989537702302871498759085027948
Short name T283
Test name
Test status
Simulation time 487150632 ps
CPU time 21.34 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:40 PM PST 23
Peak memory 250492 kb
Host smart-3a655ad5-1af4-4b78-a756-a9da5d35588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9600609577643963474230944662125871976680595179989537702302871498759085027948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.lc_ctrl_state_failure.9600609577643963474230944662125871976680595179989537702302871498759085027948
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.41299670193366613829455100510690799440310760254529808909763791144191754803448
Short name T894
Test name
Test status
Simulation time 217117078 ps
CPU time 7 seconds
Started Nov 22 01:39:28 PM PST 23
Finished Nov 22 01:39:36 PM PST 23
Peak memory 246380 kb
Host smart-75c1c37c-be98-4cc7-8c27-1cb4f41ce521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41299670193366613829455100510690799440310760254529808909763791144191754803448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.lc_ctrl_state_post_trans.41299670193366613829455100510690799440310760254529808909763791144191754803448
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.65523918020333954281332281024459265064361462218628479792453382982504245414945
Short name T341
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.07 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:44:30 PM PST 23
Peak memory 283272 kb
Host smart-50cdbc0c-e050-45cc-a39e-28d040217f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655239180203339542813322810244592650643614622186284797924533829825
04245414945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.65523918020333954281332281024459265064361462218628479792
453382982504245414945
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.9848046825891429327535798327319440331008152579505523476892238777740188263872
Short name T287
Test name
Test status
Simulation time 16404398 ps
CPU time 0.7 seconds
Started Nov 22 01:39:29 PM PST 23
Finished Nov 22 01:39:30 PM PST 23
Peak memory 207652 kb
Host smart-ed477047-538e-408c-b11a-386bb6a4a611
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9848046825891429327535798327319440331008152579505523476892238777740188263872 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_volatile_unlock_smoke.984804682589142932753579832731944033100815257950552347
6892238777740188263872
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.41109106162700280271892522607800988171111651143189714414270797154400138794978
Short name T415
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:39:42 PM PST 23
Finished Nov 22 01:39:46 PM PST 23
Peak memory 207708 kb
Host smart-9adaafb3-6a52-4ae4-a079-a5b8acafdb0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109106162700280271892522607800988171111651143189714414270797154400138794978 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.41109106162700280271892522607800988171111651143189714414270797154400138794978
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.24056767854578835362573781752529779906213075326025528263121216198354354944226
Short name T319
Test name
Test status
Simulation time 978628843 ps
CPU time 13.57 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:40:05 PM PST 23
Peak memory 217488 kb
Host smart-e4a9565a-2d4a-43c6-a39d-7aaf24f2185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24056767854578835362573781752529779906213075326025528263121216198354354944226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.lc_ctrl_errors.24056767854578835362573781752529779906213075326025528263121216198354354944226
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.103437868156749800561611057024835860713474015990542093523825297407623438305311
Short name T561
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.53 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 208988 kb
Host smart-b730aac6-ca14-403b-983e-7a7ef3b79460
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103437868156749800561611057024835860713474015990542093523825297407623438305311 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.103437868156749800561611057024835860713474015990542093523825297407623438305311
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.64490832466886349408895363142844744987165021502492881188323978866367430902225
Short name T599
Test name
Test status
Simulation time 159313969 ps
CPU time 3.07 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:40:09 PM PST 23
Peak memory 217492 kb
Host smart-4b99e73a-0034-451b-bbb0-f78a4bb46248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64490832466886349408895363142844744987165021502492881188323978866367430902225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.lc_ctrl_prog_failure.64490832466886349408895363142844744987165021502492881188323978866367430902225
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.73203540408662911320258030117839760693115145108203236202413119086885222934752
Short name T793
Test name
Test status
Simulation time 1010128591 ps
CPU time 15.04 seconds
Started Nov 22 01:39:42 PM PST 23
Finished Nov 22 01:40:00 PM PST 23
Peak memory 218500 kb
Host smart-8082ae10-0d4a-4658-b1b1-fd22a793c6fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73203540408662911320258030117839760693115145108203236202413119086885222934752 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.73203540408662911320258030117839760693115145108203236202413119086885222934752
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.99849816338767157889676749706280411519534087076264110019730913624918762665676
Short name T957
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.75 seconds
Started Nov 22 01:39:41 PM PST 23
Finished Nov 22 01:40:00 PM PST 23
Peak memory 217312 kb
Host smart-c560ab9d-e9b8-431f-855a-2aff122846c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99849816338767157889676749706280411519534087076264110019730913624918762665676 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_digest.99849816338767157889676749706280411519534087076264110019730913624918762665676
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.72483516987776309413054036149254757332978297708739349670255026190036831969434
Short name T313
Test name
Test status
Simulation time 964986095 ps
CPU time 10.91 seconds
Started Nov 22 01:39:28 PM PST 23
Finished Nov 22 01:39:40 PM PST 23
Peak memory 217468 kb
Host smart-f694771a-3c1e-42ef-bc09-d711eaf4ae9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72483516987776309413054036149254757332978297708739349670255026190036831969434 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.72483516987776309413054036149254757332978297708739349670255026190036831969434
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.22369283571462831508532694813114754965281260496683571393062132483549861138383
Short name T364
Test name
Test status
Simulation time 625328098 ps
CPU time 8.18 seconds
Started Nov 22 01:39:16 PM PST 23
Finished Nov 22 01:39:26 PM PST 23
Peak memory 217368 kb
Host smart-d9342f57-d53e-4baa-9575-714e847f7f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22369283571462831508532694813114754965281260496683571393062132483549861138383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.lc_ctrl_security_escalation.22369283571462831508532694813114754965281260496683571393062132483549861138383
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.111405323130987532406802480601064526928601625420903044314261930106722031997263
Short name T530
Test name
Test status
Simulation time 291295056 ps
CPU time 4.35 seconds
Started Nov 22 01:39:45 PM PST 23
Finished Nov 22 01:39:50 PM PST 23
Peak memory 213768 kb
Host smart-0cf0d1c4-bb71-4f27-8410-38659e2474cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111405323130987532406802480601064526928601625420903044314261930106722031997263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.lc_ctrl_smoke.111405323130987532406802480601064526928601625420903044314261930106722031997263
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2573731584567754187749887337361920479033858628441957756429651976544196487983
Short name T276
Test name
Test status
Simulation time 487150632 ps
CPU time 21.01 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:40:11 PM PST 23
Peak memory 250448 kb
Host smart-8035c3e7-a249-4d92-b373-ef9def40d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573731584567754187749887337361920479033858628441957756429651976544196487983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.lc_ctrl_state_failure.2573731584567754187749887337361920479033858628441957756429651976544196487983
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.55905998453562357629283256881517680671396342094414087658605082229791876552613
Short name T426
Test name
Test status
Simulation time 217117078 ps
CPU time 7.31 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 246200 kb
Host smart-6b703469-c7e8-4fd1-9132-33a98a122bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55905998453562357629283256881517680671396342094414087658605082229791876552613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.lc_ctrl_state_post_trans.55905998453562357629283256881517680671396342094414087658605082229791876552613
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.102785948646966929325654263588032723776574199503086723657757699768324322469774
Short name T328
Test name
Test status
Simulation time 36820395678 ps
CPU time 289.99 seconds
Started Nov 22 01:39:33 PM PST 23
Finished Nov 22 01:44:24 PM PST 23
Peak memory 283348 kb
Host smart-1968a705-5dfc-44bb-8d65-43725992d22e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102785948646966929325654263588032723776574199503086723657757699768
324322469774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.1027859486469669293256542635880327237765741995030867236
57757699768324322469774
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.104344327350690797097331181897900356968391485154556554068742599016167938739853
Short name T317
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:49 PM PST 23
Peak memory 207596 kb
Host smart-7a2522d7-aeb6-42b3-bbce-b4aa7a08cedf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104344327350690797097331181897900356968391485154556554068742599016167938739853 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_volatile_unlock_smoke.1043443273506907970973311818979003569683914851545565
54068742599016167938739853
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.32162571782314109613662511897907909110516905604292402089142264921111897074335
Short name T331
Test name
Test status
Simulation time 42189906 ps
CPU time 0.98 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:39:52 PM PST 23
Peak memory 207696 kb
Host smart-2107adc8-99a3-458c-b282-cefc0a37540e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32162571782314109613662511897907909110516905604292402089142264921111897074335 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.32162571782314109613662511897907909110516905604292402089142264921111897074335
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.114920877703404502224636506570599326163456258146926513926294289617735776388761
Short name T455
Test name
Test status
Simulation time 978628843 ps
CPU time 13.78 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:40:02 PM PST 23
Peak memory 217488 kb
Host smart-8c54a4cf-29fb-43dd-9a7f-34887bb9b1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114920877703404502224636506570599326163456258146926513926294289617735776388761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.lc_ctrl_errors.114920877703404502224636506570599326163456258146926513926294289617735776388761
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.103306160238602472042884546002353792838528404775582709131021231975345515014110
Short name T549
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.53 seconds
Started Nov 22 01:39:41 PM PST 23
Finished Nov 22 01:39:53 PM PST 23
Peak memory 208956 kb
Host smart-f4274dab-2266-4c1a-b02c-370b26397b5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103306160238602472042884546002353792838528404775582709131021231975345515014110 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.103306160238602472042884546002353792838528404775582709131021231975345515014110
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.22315038341943992434943687040869903124774897908324101578809287344504906204592
Short name T434
Test name
Test status
Simulation time 159313969 ps
CPU time 2.88 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:39:55 PM PST 23
Peak memory 217476 kb
Host smart-36bcbc32-10fb-4cec-9e37-e75b3e23cfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22315038341943992434943687040869903124774897908324101578809287344504906204592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.lc_ctrl_prog_failure.22315038341943992434943687040869903124774897908324101578809287344504906204592
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.74227622388163676648195147748834480098645471929718854007720878427828157009344
Short name T479
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.33 seconds
Started Nov 22 01:39:48 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 218480 kb
Host smart-b883bc6c-5394-4c2e-be9e-f41e26164259
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74227622388163676648195147748834480098645471929718854007720878427828157009344 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.74227622388163676648195147748834480098645471929718854007720878427828157009344
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.13058311741113221098267700457778408801986332767085965971250159489649353378177
Short name T787
Test name
Test status
Simulation time 1321911811 ps
CPU time 17.68 seconds
Started Nov 22 01:39:53 PM PST 23
Finished Nov 22 01:40:12 PM PST 23
Peak memory 217380 kb
Host smart-e29df1c1-2ebb-42eb-a43c-2c334d10d7e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13058311741113221098267700457778408801986332767085965971250159489649353378177 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_digest.13058311741113221098267700457778408801986332767085965971250159489649353378177
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1266119074280672381356205019352455624566513155360155089281752069734354153093
Short name T17
Test name
Test status
Simulation time 964986095 ps
CPU time 11.22 seconds
Started Nov 22 01:39:46 PM PST 23
Finished Nov 22 01:39:58 PM PST 23
Peak memory 217400 kb
Host smart-b360d9cf-eabc-477a-9105-aba66a8abe63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266119074280672381356205019352455624566513155360155089281752069734354153093 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.1266119074280672381356205019352455624566513155360155089281752069734354153093
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.57966051793318874150970505781204010101606395099495914808119885121974264679002
Short name T9
Test name
Test status
Simulation time 625328098 ps
CPU time 8.53 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:05 PM PST 23
Peak memory 217312 kb
Host smart-70116955-531e-44ee-b499-41aed3c4b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57966051793318874150970505781204010101606395099495914808119885121974264679002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.lc_ctrl_security_escalation.57966051793318874150970505781204010101606395099495914808119885121974264679002
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.102509265082091497911773106433559304772163193680433068691167961148138376515726
Short name T86
Test name
Test status
Simulation time 291295056 ps
CPU time 4.63 seconds
Started Nov 22 01:39:38 PM PST 23
Finished Nov 22 01:39:45 PM PST 23
Peak memory 213796 kb
Host smart-0b562257-c628-4c2f-8017-85637b275e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102509265082091497911773106433559304772163193680433068691167961148138376515726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.lc_ctrl_smoke.102509265082091497911773106433559304772163193680433068691167961148138376515726
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.65376862008942489564663137946434807948685200649078281842826990750614163909077
Short name T318
Test name
Test status
Simulation time 487150632 ps
CPU time 22.78 seconds
Started Nov 22 01:39:45 PM PST 23
Finished Nov 22 01:40:08 PM PST 23
Peak memory 250372 kb
Host smart-62cec14f-68d8-43f6-92d9-60076ff55e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65376862008942489564663137946434807948685200649078281842826990750614163909077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.lc_ctrl_state_failure.65376862008942489564663137946434807948685200649078281842826990750614163909077
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.72641190971120842704067295220255363918065824830691146653324627554635339002566
Short name T942
Test name
Test status
Simulation time 217117078 ps
CPU time 6.91 seconds
Started Nov 22 01:39:30 PM PST 23
Finished Nov 22 01:39:38 PM PST 23
Peak memory 246292 kb
Host smart-7ec42fab-5e7b-4575-a638-0328a48ec00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72641190971120842704067295220255363918065824830691146653324627554635339002566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.lc_ctrl_state_post_trans.72641190971120842704067295220255363918065824830691146653324627554635339002566
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.9963788919231530158582331429934637748651171874043237581199223573150055488780
Short name T940
Test name
Test status
Simulation time 36820395678 ps
CPU time 292.56 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:44:48 PM PST 23
Peak memory 279616 kb
Host smart-5558c900-39ca-4a05-96eb-ef1f3430807b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996378891923153015858233142993463774865117187404323758119922357315
0055488780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.996378891923153015858233142993463774865117187404323758119
9223573150055488780
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.104932236119463051190118822086050239597168475845331702596021896039884415700882
Short name T412
Test name
Test status
Simulation time 16404398 ps
CPU time 0.76 seconds
Started Nov 22 01:39:34 PM PST 23
Finished Nov 22 01:39:35 PM PST 23
Peak memory 207564 kb
Host smart-ef65dc38-8c6e-4f33-b2b9-e37667ed20c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104932236119463051190118822086050239597168475845331702596021896039884415700882 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_volatile_unlock_smoke.1049322361194630511901188220860502395971684758453317
02596021896039884415700882
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.98261910827386016618677560864980635791260053267841697104522536274002307842323
Short name T813
Test name
Test status
Simulation time 42189906 ps
CPU time 0.93 seconds
Started Nov 22 01:40:16 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 207660 kb
Host smart-f76fb9f6-09c8-41a9-b727-cce27539f98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98261910827386016618677560864980635791260053267841697104522536274002307842323 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.98261910827386016618677560864980635791260053267841697104522536274002307842323
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.105615968102397432415678305003360077793551089186255598101244024257905111335383
Short name T703
Test name
Test status
Simulation time 978628843 ps
CPU time 13.72 seconds
Started Nov 22 01:40:20 PM PST 23
Finished Nov 22 01:40:35 PM PST 23
Peak memory 217412 kb
Host smart-4f35bb38-4311-4fad-a99c-dd1739430fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105615968102397432415678305003360077793551089186255598101244024257905111335383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.lc_ctrl_errors.105615968102397432415678305003360077793551089186255598101244024257905111335383
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.7850914867831417881050196100138415548286170057345719652121220159898900105740
Short name T679
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.41 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 209012 kb
Host smart-780ed1ac-d377-422d-abed-bf2344eedc39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7850914867831417881050196100138415548286170057345719652121220159898900105740 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.7850914867831417881050196100138415548286170057345719652121220159898900105740
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.108714775086409161346412736010682220753651854653883514050670777140170801140810
Short name T695
Test name
Test status
Simulation time 159313969 ps
CPU time 2.98 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:40:09 PM PST 23
Peak memory 217492 kb
Host smart-8ea372e0-d40b-4174-950c-b4421ec98e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108714775086409161346412736010682220753651854653883514050670777140170801140810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.lc_ctrl_prog_failure.108714775086409161346412736010682220753651854653883514050670777140170801140810
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.12844597634306393165395889356436709491374141862505639808127831256987366285449
Short name T288
Test name
Test status
Simulation time 1010128591 ps
CPU time 13.98 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 218412 kb
Host smart-c62858fe-b316-46c7-a155-8e1093dde873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844597634306393165395889356436709491374141862505639808127831256987366285449 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.12844597634306393165395889356436709491374141862505639808127831256987366285449
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.37960312610923408275227591193337862117549745776348700346154194192641932417465
Short name T907
Test name
Test status
Simulation time 1321911811 ps
CPU time 17.17 seconds
Started Nov 22 01:39:53 PM PST 23
Finished Nov 22 01:40:11 PM PST 23
Peak memory 217412 kb
Host smart-65e09bbe-eda7-4ac7-9c50-23e9e6660c02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37960312610923408275227591193337862117549745776348700346154194192641932417465 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_digest.37960312610923408275227591193337862117549745776348700346154194192641932417465
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.35683876555885646161217052625984963814558963134068382906874752760449343083852
Short name T872
Test name
Test status
Simulation time 964986095 ps
CPU time 11.63 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 217444 kb
Host smart-3fa364c9-21b8-44b8-8228-2f800521514b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35683876555885646161217052625984963814558963134068382906874752760449343083852 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.35683876555885646161217052625984963814558963134068382906874752760449343083852
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.12306723514386284000261432454391742560438389470352703427556036185605734026003
Short name T913
Test name
Test status
Simulation time 625328098 ps
CPU time 8.24 seconds
Started Nov 22 01:39:58 PM PST 23
Finished Nov 22 01:40:07 PM PST 23
Peak memory 217296 kb
Host smart-8f7face1-2466-4d24-a65b-c27605988117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12306723514386284000261432454391742560438389470352703427556036185605734026003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.lc_ctrl_security_escalation.12306723514386284000261432454391742560438389470352703427556036185605734026003
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.114901119272076602674045809803632882882962685943831504056894718857589227338209
Short name T563
Test name
Test status
Simulation time 291295056 ps
CPU time 4.66 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:06 PM PST 23
Peak memory 213856 kb
Host smart-eab8847b-1d53-4910-97d2-73e8ed04c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114901119272076602674045809803632882882962685943831504056894718857589227338209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.lc_ctrl_smoke.114901119272076602674045809803632882882962685943831504056894718857589227338209
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.74388483883466314484907400555021691344889409466785690809555203361180518095919
Short name T378
Test name
Test status
Simulation time 487150632 ps
CPU time 21.75 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:22 PM PST 23
Peak memory 250452 kb
Host smart-9a635fe4-0b65-479a-bad6-23a293655bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74388483883466314484907400555021691344889409466785690809555203361180518095919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.lc_ctrl_state_failure.74388483883466314484907400555021691344889409466785690809555203361180518095919
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.51920689127855663052320683988535395715365757324037437084122528164141866544730
Short name T389
Test name
Test status
Simulation time 217117078 ps
CPU time 7.02 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 246276 kb
Host smart-c1ecfa35-29a3-4248-b427-507154b45bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51920689127855663052320683988535395715365757324037437084122528164141866544730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.lc_ctrl_state_post_trans.51920689127855663052320683988535395715365757324037437084122528164141866544730
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.64983313670622536856447853115575627471431160550847554376616527571509628793964
Short name T514
Test name
Test status
Simulation time 36820395678 ps
CPU time 292.12 seconds
Started Nov 22 01:40:29 PM PST 23
Finished Nov 22 01:45:24 PM PST 23
Peak memory 283564 kb
Host smart-1b699cbd-a40f-4aac-b0d5-c3f2a5d2e64f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649833136706225368564478531155756274714311605508475543766165275715
09628793964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.64983313670622536856447853115575627471431160550847554376
616527571509628793964
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.105869062799456539292909433751944606524760095548611504799844459626624936121130
Short name T828
Test name
Test status
Simulation time 16404398 ps
CPU time 0.74 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 207620 kb
Host smart-ca1f351c-1c7a-4072-9f0c-e06e25339010
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105869062799456539292909433751944606524760095548611504799844459626624936121130 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_volatile_unlock_smoke.1058690627994565392929094337519446065247600955486115
04799844459626624936121130
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.35558440935165455151553494892695087764737095147596125903717546082324928604869
Short name T299
Test name
Test status
Simulation time 42189906 ps
CPU time 0.95 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:39:58 PM PST 23
Peak memory 207608 kb
Host smart-42b3203b-f5ef-40ab-93e1-7795bc5714cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35558440935165455151553494892695087764737095147596125903717546082324928604869 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.35558440935165455151553494892695087764737095147596125903717546082324928604869
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.115593784933213562399928219884355558231716184947889504357943489245648945923298
Short name T385
Test name
Test status
Simulation time 978628843 ps
CPU time 14.13 seconds
Started Nov 22 01:39:48 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 217336 kb
Host smart-66bc6357-155b-43b0-bb97-3ea2bcd3719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115593784933213562399928219884355558231716184947889504357943489245648945923298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.lc_ctrl_errors.115593784933213562399928219884355558231716184947889504357943489245648945923298
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1575048576755408931844204715319169108509597258885866864935555296539356060630
Short name T966
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.91 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:58 PM PST 23
Peak memory 208876 kb
Host smart-7b96ef30-5d49-4258-942b-0718ceeda8b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575048576755408931844204715319169108509597258885866864935555296539356060630 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1575048576755408931844204715319169108509597258885866864935555296539356060630
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.13499403187829133956330885129092673650888146270088778009254045044023886562869
Short name T909
Test name
Test status
Simulation time 159313969 ps
CPU time 2.9 seconds
Started Nov 22 01:39:38 PM PST 23
Finished Nov 22 01:39:43 PM PST 23
Peak memory 217476 kb
Host smart-f95a1eb2-3d51-455f-a2aa-2fab31f83483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13499403187829133956330885129092673650888146270088778009254045044023886562869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.lc_ctrl_prog_failure.13499403187829133956330885129092673650888146270088778009254045044023886562869
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.114216058180370112652293199149436610391563194788685509846112435767196283529267
Short name T482
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.37 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:11 PM PST 23
Peak memory 218428 kb
Host smart-7bd91fcd-f596-482a-b79f-cfc6f55e0a4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114216058180370112652293199149436610391563194788685509846112435767196283529267 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.114216058180370112652293199149436610391563194788685509846112435767196283529267
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.11666425583715303750218286161244724079588313619811389076480763659806710955175
Short name T723
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.52 seconds
Started Nov 22 01:39:45 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 217360 kb
Host smart-357555be-298e-4313-bd51-9483d6714f3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11666425583715303750218286161244724079588313619811389076480763659806710955175 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_digest.11666425583715303750218286161244724079588313619811389076480763659806710955175
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4374055275538143029977337013783543612102765062136223800534195128817848583287
Short name T936
Test name
Test status
Simulation time 964986095 ps
CPU time 11.24 seconds
Started Nov 22 01:39:45 PM PST 23
Finished Nov 22 01:39:57 PM PST 23
Peak memory 217436 kb
Host smart-e27eb4d8-321a-45f1-919d-a8902aa00bcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4374055275538143029977337013783543612102765062136223800534195128817848583287 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.4374055275538143029977337013783543612102765062136223800534195128817848583287
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.77516485852439195338417209198153148902732497954308036160509660593619908118970
Short name T786
Test name
Test status
Simulation time 625328098 ps
CPU time 8.18 seconds
Started Nov 22 01:39:43 PM PST 23
Finished Nov 22 01:39:53 PM PST 23
Peak memory 217444 kb
Host smart-f56e74d2-468e-44e2-aed2-968884e552a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77516485852439195338417209198153148902732497954308036160509660593619908118970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.lc_ctrl_security_escalation.77516485852439195338417209198153148902732497954308036160509660593619908118970
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.7522820748858975004181114881513596691782571343707366468013769825620509528109
Short name T525
Test name
Test status
Simulation time 291295056 ps
CPU time 4.6 seconds
Started Nov 22 01:40:19 PM PST 23
Finished Nov 22 01:40:26 PM PST 23
Peak memory 213864 kb
Host smart-4e6a5b41-a613-4d77-8897-b8ac5e82ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7522820748858975004181114881513596691782571343707366468013769825620509528109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.lc_ctrl_smoke.7522820748858975004181114881513596691782571343707366468013769825620509528109
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.99645464912827102741271339631700140164903722006274446912943348175838695337229
Short name T384
Test name
Test status
Simulation time 487150632 ps
CPU time 20.35 seconds
Started Nov 22 01:40:09 PM PST 23
Finished Nov 22 01:40:31 PM PST 23
Peak memory 250400 kb
Host smart-a5dbfaac-9f25-4c09-893b-dc0f3d2992ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99645464912827102741271339631700140164903722006274446912943348175838695337229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.lc_ctrl_state_failure.99645464912827102741271339631700140164903722006274446912943348175838695337229
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.90126047493332770211222198383161725399362178538972948714961206431270650070907
Short name T394
Test name
Test status
Simulation time 217117078 ps
CPU time 7.1 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:39:59 PM PST 23
Peak memory 246308 kb
Host smart-a98d9388-d7f4-4717-8cab-ed4561ad3f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90126047493332770211222198383161725399362178538972948714961206431270650070907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.lc_ctrl_state_post_trans.90126047493332770211222198383161725399362178538972948714961206431270650070907
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2215008164497515866343631442555451137887806929327993728593942409245229479160
Short name T56
Test name
Test status
Simulation time 36820395678 ps
CPU time 289.33 seconds
Started Nov 22 01:39:42 PM PST 23
Finished Nov 22 01:44:34 PM PST 23
Peak memory 279652 kb
Host smart-87487043-8097-4f01-9273-c161dcd35f0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221500816449751586634363144255545113788780692932799372859394240924
5229479160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.221500816449751586634363144255545113788780692932799372859
3942409245229479160
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.8093150539783895045637665675159495133515270333237277645606509165417737973283
Short name T403
Test name
Test status
Simulation time 16404398 ps
CPU time 0.74 seconds
Started Nov 22 01:40:10 PM PST 23
Finished Nov 22 01:40:12 PM PST 23
Peak memory 207608 kb
Host smart-45816073-c19f-41db-9cac-0e97091d5715
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8093150539783895045637665675159495133515270333237277645606509165417737973283 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_volatile_unlock_smoke.809315053978389504563766567515949513351527033323727764
5606509165417737973283
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.8337736033756474052958553466521363071174686888148810313166402604363829256525
Short name T85
Test name
Test status
Simulation time 42189906 ps
CPU time 0.95 seconds
Started Nov 22 01:39:45 PM PST 23
Finished Nov 22 01:39:47 PM PST 23
Peak memory 207656 kb
Host smart-8a6a1f22-8198-4eb9-a7c8-e3d88c2f69ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8337736033756474052958553466521363071174686888148810313166402604363829256525 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.8337736033756474052958553466521363071174686888148810313166402604363829256525
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.6921014397670185525713330124740968546361505867273434172879787638196357405279
Short name T584
Test name
Test status
Simulation time 978628843 ps
CPU time 14.02 seconds
Started Nov 22 01:39:45 PM PST 23
Finished Nov 22 01:40:00 PM PST 23
Peak memory 217428 kb
Host smart-541f3e1d-3979-4973-a7e2-004f035fa5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6921014397670185525713330124740968546361505867273434172879787638196357405279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.lc_ctrl_errors.6921014397670185525713330124740968546361505867273434172879787638196357405279
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.80690982388656925675298341849333762827703249632512497128992385730413978202187
Short name T954
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.46 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:58 PM PST 23
Peak memory 208880 kb
Host smart-6011baf2-84b4-49dd-9c43-675d24d89ce5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80690982388656925675298341849333762827703249632512497128992385730413978202187 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.80690982388656925675298341849333762827703249632512497128992385730413978202187
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.76528129832590949004228121146553560897840518024181161573727039776782496679255
Short name T782
Test name
Test status
Simulation time 159313969 ps
CPU time 2.97 seconds
Started Nov 22 01:39:39 PM PST 23
Finished Nov 22 01:39:44 PM PST 23
Peak memory 217380 kb
Host smart-fae24837-d6e8-4888-8fc3-8e6ebb821c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76528129832590949004228121146553560897840518024181161573727039776782496679255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.lc_ctrl_prog_failure.76528129832590949004228121146553560897840518024181161573727039776782496679255
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.86990498039185859556896990845631089532701056410339405571813464210768659861952
Short name T311
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.06 seconds
Started Nov 22 01:39:43 PM PST 23
Finished Nov 22 01:39:59 PM PST 23
Peak memory 218500 kb
Host smart-a726290f-4369-489e-9f6c-b0a48bc6582d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86990498039185859556896990845631089532701056410339405571813464210768659861952 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.86990498039185859556896990845631089532701056410339405571813464210768659861952
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.25091509369401770376821231648209912910845136873230154323103410918791727927745
Short name T692
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.88 seconds
Started Nov 22 01:39:40 PM PST 23
Finished Nov 22 01:39:58 PM PST 23
Peak memory 217360 kb
Host smart-7bd3d28f-48b3-46e5-92bb-ab0afd095eb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25091509369401770376821231648209912910845136873230154323103410918791727927745 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_digest.25091509369401770376821231648209912910845136873230154323103410918791727927745
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.112256185311359781302345121176684187469796853732604605245212448234836860633229
Short name T870
Test name
Test status
Simulation time 964986095 ps
CPU time 11.33 seconds
Started Nov 22 01:39:54 PM PST 23
Finished Nov 22 01:40:06 PM PST 23
Peak memory 217380 kb
Host smart-4f6a97fc-ff6e-4a5c-865a-be5340bf6efd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112256185311359781302345121176684187469796853732604605245212448234836860633229 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.112256185311359781302345121176684187469796853732604605245212448234836860633229
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.99551098512261144719195206452341274161989244267784838641475350396626705335767
Short name T632
Test name
Test status
Simulation time 625328098 ps
CPU time 8.52 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:39:59 PM PST 23
Peak memory 217444 kb
Host smart-88c5649f-8418-4e50-847c-834e36f32a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99551098512261144719195206452341274161989244267784838641475350396626705335767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.lc_ctrl_security_escalation.99551098512261144719195206452341274161989244267784838641475350396626705335767
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.13377338561092170751859563853867507952243606467296710560040207056609436915835
Short name T958
Test name
Test status
Simulation time 291295056 ps
CPU time 4.57 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:39:57 PM PST 23
Peak memory 213852 kb
Host smart-d076ec37-5b36-4be7-912f-7139ee12c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13377338561092170751859563853867507952243606467296710560040207056609436915835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.lc_ctrl_smoke.13377338561092170751859563853867507952243606467296710560040207056609436915835
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.67888639560926873530516171672599778786112404925045894809645321155070631058050
Short name T854
Test name
Test status
Simulation time 487150632 ps
CPU time 22.01 seconds
Started Nov 22 01:39:48 PM PST 23
Finished Nov 22 01:40:10 PM PST 23
Peak memory 250340 kb
Host smart-97eb0eed-a063-421f-8f07-11ab25ae4177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67888639560926873530516171672599778786112404925045894809645321155070631058050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.lc_ctrl_state_failure.67888639560926873530516171672599778786112404925045894809645321155070631058050
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.54690971300849992368199811544563132779952504967933176646083575509744696384903
Short name T925
Test name
Test status
Simulation time 217117078 ps
CPU time 6.82 seconds
Started Nov 22 01:39:44 PM PST 23
Finished Nov 22 01:39:52 PM PST 23
Peak memory 246236 kb
Host smart-7d11b351-a191-4c27-9ca3-1e5cd04a2713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54690971300849992368199811544563132779952504967933176646083575509744696384903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.lc_ctrl_state_post_trans.54690971300849992368199811544563132779952504967933176646083575509744696384903
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.111743422303470033606178168150800456276105932694154060817666186269660038841905
Short name T38
Test name
Test status
Simulation time 36820395678 ps
CPU time 287.54 seconds
Started Nov 22 01:39:50 PM PST 23
Finished Nov 22 01:44:38 PM PST 23
Peak memory 283336 kb
Host smart-e4065197-0ea3-4d23-83e4-203c3fe09bc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111743422303470033606178168150800456276105932694154060817666186269
660038841905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.1117434223034700336061781681508004562761059326941540608
17666186269660038841905
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.112839527069035047115855590843866038255392575150174922227674318803463706134335
Short name T396
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:39:43 PM PST 23
Finished Nov 22 01:39:45 PM PST 23
Peak memory 207584 kb
Host smart-d3341269-e0e2-42aa-bb2d-33b5ebdd2502
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112839527069035047115855590843866038255392575150174922227674318803463706134335 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_volatile_unlock_smoke.1128395270690350471158555908438660382553925751501749
22227674318803463706134335
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.88607345257480066527695004742169909504759268596457266889101819066380965901861
Short name T882
Test name
Test status
Simulation time 42189906 ps
CPU time 0.92 seconds
Started Nov 22 01:39:46 PM PST 23
Finished Nov 22 01:39:48 PM PST 23
Peak memory 207752 kb
Host smart-04a0871c-3ada-4f58-8f12-ca06d032f996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88607345257480066527695004742169909504759268596457266889101819066380965901861 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.88607345257480066527695004742169909504759268596457266889101819066380965901861
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.13005328784405311918426369556844143120857230349231174955060167476911262339750
Short name T893
Test name
Test status
Simulation time 978628843 ps
CPU time 14.6 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:40:05 PM PST 23
Peak memory 217484 kb
Host smart-15f2b0ca-2141-4814-a6cc-3fba80d66e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13005328784405311918426369556844143120857230349231174955060167476911262339750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.lc_ctrl_errors.13005328784405311918426369556844143120857230349231174955060167476911262339750
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.73218647228643738926686310247297428414841857145103701506108040472615925544201
Short name T682
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.45 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:57 PM PST 23
Peak memory 209004 kb
Host smart-c69ec310-7e05-4463-a8d0-324986ace834
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73218647228643738926686310247297428414841857145103701506108040472615925544201 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.73218647228643738926686310247297428414841857145103701506108040472615925544201
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.21848085567026959639472206360545987796709973239694080919780317351674603645491
Short name T523
Test name
Test status
Simulation time 159313969 ps
CPU time 2.95 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:50 PM PST 23
Peak memory 217512 kb
Host smart-d4b4cc03-4067-4035-bca2-79869ba4b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21848085567026959639472206360545987796709973239694080919780317351674603645491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.lc_ctrl_prog_failure.21848085567026959639472206360545987796709973239694080919780317351674603645491
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.65568512258595795572816719238303677299472146577262434163611365556666573593429
Short name T699
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.31 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:40:10 PM PST 23
Peak memory 218496 kb
Host smart-33ee0266-075f-4adb-8016-aa2eafc12243
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65568512258595795572816719238303677299472146577262434163611365556666573593429 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.65568512258595795572816719238303677299472146577262434163611365556666573593429
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.115509718259977256687234999181217313206719445056268212926048721431856789434386
Short name T724
Test name
Test status
Simulation time 1321911811 ps
CPU time 14.95 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:40:07 PM PST 23
Peak memory 217412 kb
Host smart-3943fd09-ba8f-4345-a453-2463e2fefeca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115509718259977256687234999181217313206719445056268212926048721431856789434386 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_digest.115509718259977256687234999181217313206719445056268212926048721431856789434386
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.30098173781447066672916433616038557662804255329134806122768388931592589080809
Short name T903
Test name
Test status
Simulation time 964986095 ps
CPU time 11.08 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:59 PM PST 23
Peak memory 217456 kb
Host smart-026c155c-1c2d-47f9-9d65-7d5c1938e7df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30098173781447066672916433616038557662804255329134806122768388931592589080809 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.30098173781447066672916433616038557662804255329134806122768388931592589080809
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.49348473748325414534036108737792946595697765446590395570110883768359435247490
Short name T94
Test name
Test status
Simulation time 625328098 ps
CPU time 8.08 seconds
Started Nov 22 01:39:43 PM PST 23
Finished Nov 22 01:39:53 PM PST 23
Peak memory 217488 kb
Host smart-3d78726e-4f1c-4af3-a8bc-31994b952cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49348473748325414534036108737792946595697765446590395570110883768359435247490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.lc_ctrl_security_escalation.49348473748325414534036108737792946595697765446590395570110883768359435247490
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.82601031053878476765437919041551826583886257626840750287945510880421445374819
Short name T437
Test name
Test status
Simulation time 291295056 ps
CPU time 4.37 seconds
Started Nov 22 01:39:44 PM PST 23
Finished Nov 22 01:39:49 PM PST 23
Peak memory 213708 kb
Host smart-f54e96a6-98e6-47c2-923b-3faa011e65ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82601031053878476765437919041551826583886257626840750287945510880421445374819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.lc_ctrl_smoke.82601031053878476765437919041551826583886257626840750287945510880421445374819
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.48419933392439108687745984672421256936833787185535596795019065123858731816433
Short name T77
Test name
Test status
Simulation time 487150632 ps
CPU time 21.93 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 250416 kb
Host smart-276f01d1-60a7-4772-b987-944fac416d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48419933392439108687745984672421256936833787185535596795019065123858731816433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.lc_ctrl_state_failure.48419933392439108687745984672421256936833787185535596795019065123858731816433
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.20039125052325216839636188482594553246930992876343405446907710369482288500515
Short name T891
Test name
Test status
Simulation time 217117078 ps
CPU time 7.46 seconds
Started Nov 22 01:39:38 PM PST 23
Finished Nov 22 01:39:48 PM PST 23
Peak memory 246356 kb
Host smart-64ba025b-2025-41e0-bbba-1ced7dfd9f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20039125052325216839636188482594553246930992876343405446907710369482288500515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.lc_ctrl_state_post_trans.20039125052325216839636188482594553246930992876343405446907710369482288500515
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.54481654677327746951947388667229482552149208832440301956308347491093686605935
Short name T506
Test name
Test status
Simulation time 36820395678 ps
CPU time 284.42 seconds
Started Nov 22 01:39:58 PM PST 23
Finished Nov 22 01:44:43 PM PST 23
Peak memory 283476 kb
Host smart-76ab543b-b95f-47f5-85b5-bac25040f69e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544816546773277469519473886672294825521492088324403019563083474910
93686605935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.54481654677327746951947388667229482552149208832440301956
308347491093686605935
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.101081088780352339505127829050565613713499472452423151750971516147962014158019
Short name T391
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:39:34 PM PST 23
Finished Nov 22 01:39:40 PM PST 23
Peak memory 207588 kb
Host smart-1061eca2-b4bb-4071-b58a-b3dfdc32d4e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101081088780352339505127829050565613713499472452423151750971516147962014158019 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_volatile_unlock_smoke.1010810887803523395051278290505656137134994724524231
51750971516147962014158019
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.109309349638100035704569509689059667499010774453003222181842993226465541981118
Short name T906
Test name
Test status
Simulation time 42189906 ps
CPU time 0.95 seconds
Started Nov 22 01:39:54 PM PST 23
Finished Nov 22 01:39:55 PM PST 23
Peak memory 207716 kb
Host smart-c14be371-1442-46ab-b11d-342de3f914cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109309349638100035704569509689059667499010774453003222181842993226465541981118 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.109309349638100035704569509689059667499010774453003222181842993226465541981118
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2457106138912641490486026205864953589715398913233537990326277315956402434233
Short name T402
Test name
Test status
Simulation time 978628843 ps
CPU time 12.66 seconds
Started Nov 22 01:39:46 PM PST 23
Finished Nov 22 01:39:59 PM PST 23
Peak memory 217380 kb
Host smart-3c6c4db8-9637-4bdb-a0b4-127d43df6692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457106138912641490486026205864953589715398913233537990326277315956402434233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.lc_ctrl_errors.2457106138912641490486026205864953589715398913233537990326277315956402434233
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.68390959441619371516193569438667884786381183309394198887489410562198706176539
Short name T862
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.77 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 208976 kb
Host smart-8024d833-fd77-4888-aa70-48109c20d4c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68390959441619371516193569438667884786381183309394198887489410562198706176539 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.68390959441619371516193569438667884786381183309394198887489410562198706176539
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.16692064592509226658552031648483372769350408537152460446242429463649323290064
Short name T568
Test name
Test status
Simulation time 159313969 ps
CPU time 2.95 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:10 PM PST 23
Peak memory 217356 kb
Host smart-fa015520-5549-4beb-9b28-6b90e48b5331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16692064592509226658552031648483372769350408537152460446242429463649323290064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.lc_ctrl_prog_failure.16692064592509226658552031648483372769350408537152460446242429463649323290064
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.44880038476996115750277847656027326556562046063202784307591031381380067013917
Short name T968
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.58 seconds
Started Nov 22 01:39:48 PM PST 23
Finished Nov 22 01:40:03 PM PST 23
Peak memory 218520 kb
Host smart-8b77d95c-e4c3-41c9-a842-e5624f66d7d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44880038476996115750277847656027326556562046063202784307591031381380067013917 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.44880038476996115750277847656027326556562046063202784307591031381380067013917
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.6886981404279167174069736599919597060088089751845809953276532232271671699595
Short name T453
Test name
Test status
Simulation time 1321911811 ps
CPU time 18.04 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:20 PM PST 23
Peak memory 217520 kb
Host smart-56c7bdae-13d8-41bf-bbac-51c1d8e7a1e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6886981404279167174069736599919597060088089751845809953276532232271671699595 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_digest.6886981404279167174069736599919597060088089751845809953276532232271671699595
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.92903566901353396801509756906011702345476940735158003929700008198088421868639
Short name T781
Test name
Test status
Simulation time 964986095 ps
CPU time 11.17 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:12 PM PST 23
Peak memory 217400 kb
Host smart-2df66ded-2849-4020-8c5d-8f44d8113de6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92903566901353396801509756906011702345476940735158003929700008198088421868639 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.92903566901353396801509756906011702345476940735158003929700008198088421868639
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.8245911400181349640729334840731264617643028719524714063157579087660886476254
Short name T481
Test name
Test status
Simulation time 625328098 ps
CPU time 8.49 seconds
Started Nov 22 01:39:46 PM PST 23
Finished Nov 22 01:39:55 PM PST 23
Peak memory 217420 kb
Host smart-8b25c95f-781b-43ae-9834-ccbc97a71470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8245911400181349640729334840731264617643028719524714063157579087660886476254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.lc_ctrl_security_escalation.8245911400181349640729334840731264617643028719524714063157579087660886476254
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.23152228775576027106583706763015876245642681164667281109047025247189421007973
Short name T947
Test name
Test status
Simulation time 291295056 ps
CPU time 4.82 seconds
Started Nov 22 01:39:53 PM PST 23
Finished Nov 22 01:39:59 PM PST 23
Peak memory 213820 kb
Host smart-d61b0005-3e30-49d2-b677-605a7c6b41cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23152228775576027106583706763015876245642681164667281109047025247189421007973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.lc_ctrl_smoke.23152228775576027106583706763015876245642681164667281109047025247189421007973
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.109374025256334856917247616134156662777114204568991141794698300032021431874778
Short name T761
Test name
Test status
Simulation time 487150632 ps
CPU time 20.95 seconds
Started Nov 22 01:39:59 PM PST 23
Finished Nov 22 01:40:21 PM PST 23
Peak memory 250440 kb
Host smart-3f7e9370-0e5c-4447-aa29-4009e7be3574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109374025256334856917247616134156662777114204568991141794698300032021431874778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.lc_ctrl_state_failure.109374025256334856917247616134156662777114204568991141794698300032021431874778
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.53417268645778953435875482746237080846218872960605356769867120874832360321069
Short name T767
Test name
Test status
Simulation time 217117078 ps
CPU time 7.03 seconds
Started Nov 22 01:40:06 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 246308 kb
Host smart-fab0cc54-b605-42a4-93c8-017fd7249e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53417268645778953435875482746237080846218872960605356769867120874832360321069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.lc_ctrl_state_post_trans.53417268645778953435875482746237080846218872960605356769867120874832360321069
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.52467365745531874740807677946085106492857814550483573650853260198154412061719
Short name T58
Test name
Test status
Simulation time 36820395678 ps
CPU time 287.69 seconds
Started Nov 22 01:40:03 PM PST 23
Finished Nov 22 01:44:53 PM PST 23
Peak memory 283340 kb
Host smart-7e8fedc8-1973-4c00-acd7-bbb8888fb4eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524673657455318747408076779460851064928578145504835736508532601981
54412061719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.52467365745531874740807677946085106492857814550483573650
853260198154412061719
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.85146553671541258281393070488076366911709402599998267899344255068781956215956
Short name T10
Test name
Test status
Simulation time 16404398 ps
CPU time 0.71 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:39:53 PM PST 23
Peak memory 207556 kb
Host smart-a1dee1e5-6e50-4e30-a55a-8132a3a0d460
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85146553671541258281393070488076366911709402599998267899344255068781956215956 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_volatile_unlock_smoke.85146553671541258281393070488076366911709402599998267
899344255068781956215956
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.34175171818096829037819758132316474855854915381847251666785951755706706819890
Short name T373
Test name
Test status
Simulation time 42189906 ps
CPU time 0.95 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:39:53 PM PST 23
Peak memory 207708 kb
Host smart-16c19473-67c1-4021-83ba-8adfdc9255cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34175171818096829037819758132316474855854915381847251666785951755706706819890 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.34175171818096829037819758132316474855854915381847251666785951755706706819890
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.5489556627292135114872206402763959023294364608897408653516737247990189677580
Short name T871
Test name
Test status
Simulation time 978628843 ps
CPU time 13.7 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:40:06 PM PST 23
Peak memory 217468 kb
Host smart-5d8e25d8-609c-481a-a082-2894e5bc7200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5489556627292135114872206402763959023294364608897408653516737247990189677580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.lc_ctrl_errors.5489556627292135114872206402763959023294364608897408653516737247990189677580
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.25566388189691528949589170303402128560389243965757776083292137782274651955271
Short name T760
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.7 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:57 PM PST 23
Peak memory 208980 kb
Host smart-8cceccff-8a43-4a43-95cf-9b6b084f8e2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25566388189691528949589170303402128560389243965757776083292137782274651955271 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.25566388189691528949589170303402128560389243965757776083292137782274651955271
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.22536982130572006246051649229708586736575319057532391775890925641645548099331
Short name T668
Test name
Test status
Simulation time 159313969 ps
CPU time 2.96 seconds
Started Nov 22 01:39:50 PM PST 23
Finished Nov 22 01:39:54 PM PST 23
Peak memory 217508 kb
Host smart-319d351b-cad0-42c4-a622-5b120bac25b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22536982130572006246051649229708586736575319057532391775890925641645548099331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.lc_ctrl_prog_failure.22536982130572006246051649229708586736575319057532391775890925641645548099331
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.79471370431987348399978534568886242108910116158385323029623658963047775075221
Short name T536
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.48 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 218464 kb
Host smart-5c66defe-39c5-4584-bc2c-0f4670bb3332
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79471370431987348399978534568886242108910116158385323029623658963047775075221 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.79471370431987348399978534568886242108910116158385323029623658963047775075221
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.15378629127867758290204877371954478515137612741340112393627803379980213509865
Short name T500
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.72 seconds
Started Nov 22 01:39:44 PM PST 23
Finished Nov 22 01:40:02 PM PST 23
Peak memory 217276 kb
Host smart-7779dae1-d82e-4214-b2de-8005a8f02e22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15378629127867758290204877371954478515137612741340112393627803379980213509865 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_digest.15378629127867758290204877371954478515137612741340112393627803379980213509865
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.99566521246613147533879066013142387919799592585456507156453235449351126352199
Short name T666
Test name
Test status
Simulation time 964986095 ps
CPU time 11.23 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 217356 kb
Host smart-7ff4da86-e01c-4c79-bde6-070ebb550388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99566521246613147533879066013142387919799592585456507156453235449351126352199 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.99566521246613147533879066013142387919799592585456507156453235449351126352199
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.56422738422983799444069510756751286795149204946790932046830058180718582823574
Short name T650
Test name
Test status
Simulation time 625328098 ps
CPU time 8.7 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 217436 kb
Host smart-49ad50c9-8afb-492b-9a04-b2c22dd8759b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56422738422983799444069510756751286795149204946790932046830058180718582823574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.lc_ctrl_security_escalation.56422738422983799444069510756751286795149204946790932046830058180718582823574
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.50648359216324765974856796440027710561711443104324613106213223754457685737126
Short name T429
Test name
Test status
Simulation time 291295056 ps
CPU time 4.65 seconds
Started Nov 22 01:39:53 PM PST 23
Finished Nov 22 01:39:58 PM PST 23
Peak memory 213780 kb
Host smart-ad471b27-8ca2-4e2a-8443-cd59a2525105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50648359216324765974856796440027710561711443104324613106213223754457685737126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.lc_ctrl_smoke.50648359216324765974856796440027710561711443104324613106213223754457685737126
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.84921107130262010726106417040339092226287801626187573052323890797896619947824
Short name T87
Test name
Test status
Simulation time 487150632 ps
CPU time 20.93 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:40:08 PM PST 23
Peak memory 250448 kb
Host smart-55b48024-bb34-4fb3-a3c5-63763f0dee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84921107130262010726106417040339092226287801626187573052323890797896619947824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.lc_ctrl_state_failure.84921107130262010726106417040339092226287801626187573052323890797896619947824
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.86052834279038801937822187948397332133744490209037331339463033320118084613867
Short name T37
Test name
Test status
Simulation time 217117078 ps
CPU time 7.15 seconds
Started Nov 22 01:39:46 PM PST 23
Finished Nov 22 01:39:54 PM PST 23
Peak memory 246232 kb
Host smart-bdf49b52-2e2d-406a-adcc-bc8505d7bacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86052834279038801937822187948397332133744490209037331339463033320118084613867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.lc_ctrl_state_post_trans.86052834279038801937822187948397332133744490209037331339463033320118084613867
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.59983986989974883045638400350028575702427419475047772336077149693973411120068
Short name T625
Test name
Test status
Simulation time 36820395678 ps
CPU time 282.18 seconds
Started Nov 22 01:39:51 PM PST 23
Finished Nov 22 01:44:34 PM PST 23
Peak memory 283396 kb
Host smart-0f97ff71-191d-4fb3-a437-d5f45d80927b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599839869899748830456384003500285757024274194750477723360771496939
73411120068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.59983986989974883045638400350028575702427419475047772336
077149693973411120068
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.13707372503704269299204871664426862522293435684297045374645980966695038797190
Short name T779
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:39:59 PM PST 23
Finished Nov 22 01:40:01 PM PST 23
Peak memory 207556 kb
Host smart-557e842d-811c-4e0e-82f1-f1f65c86a9e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707372503704269299204871664426862522293435684297045374645980966695038797190 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_volatile_unlock_smoke.13707372503704269299204871664426862522293435684297045
374645980966695038797190
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.20210977682544955412108032984829528947938644872684315176085451687350944555776
Short name T302
Test name
Test status
Simulation time 42189906 ps
CPU time 1 seconds
Started Nov 22 01:40:01 PM PST 23
Finished Nov 22 01:40:04 PM PST 23
Peak memory 207752 kb
Host smart-496fef59-31c7-46bf-9bd5-3abcb174b0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20210977682544955412108032984829528947938644872684315176085451687350944555776 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.20210977682544955412108032984829528947938644872684315176085451687350944555776
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.21978697225356294840441598045418263739192184244476107333049202671680337551951
Short name T731
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.51 seconds
Started Nov 22 01:39:56 PM PST 23
Finished Nov 22 01:40:06 PM PST 23
Peak memory 208944 kb
Host smart-263afaad-f4cb-4f34-9d4c-3f7e2b56063c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978697225356294840441598045418263739192184244476107333049202671680337551951 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.21978697225356294840441598045418263739192184244476107333049202671680337551951
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.112179434144096705484712599039803671347135645904626870974528970050417577869360
Short name T937
Test name
Test status
Simulation time 159313969 ps
CPU time 2.98 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:39:55 PM PST 23
Peak memory 217440 kb
Host smart-4c764dc8-53bb-4007-ab35-35d911dfa0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112179434144096705484712599039803671347135645904626870974528970050417577869360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.lc_ctrl_prog_failure.112179434144096705484712599039803671347135645904626870974528970050417577869360
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.49994240432533735355494535867743222793112009103549041619521999158227439072775
Short name T439
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.32 seconds
Started Nov 22 01:40:02 PM PST 23
Finished Nov 22 01:40:18 PM PST 23
Peak memory 218500 kb
Host smart-c79ef0b3-9c05-42fd-aaf8-66fda235ce4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49994240432533735355494535867743222793112009103549041619521999158227439072775 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.49994240432533735355494535867743222793112009103549041619521999158227439072775
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.103075349820723159858300720493092372938719184327950427063891607597725807471646
Short name T520
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.88 seconds
Started Nov 22 01:40:00 PM PST 23
Finished Nov 22 01:40:18 PM PST 23
Peak memory 217440 kb
Host smart-c77b3167-2ade-4df6-8333-fa98a81c383c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103075349820723159858300720493092372938719184327950427063891607597725807471646 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_digest.103075349820723159858300720493092372938719184327950427063891607597725807471646
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.21068223223385225788636116362393934138196847092046764354075758048782211835048
Short name T18
Test name
Test status
Simulation time 964986095 ps
CPU time 10.88 seconds
Started Nov 22 01:39:55 PM PST 23
Finished Nov 22 01:40:07 PM PST 23
Peak memory 217344 kb
Host smart-a195f237-033d-4c33-a845-68392c1d4170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21068223223385225788636116362393934138196847092046764354075758048782211835048 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.21068223223385225788636116362393934138196847092046764354075758048782211835048
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.36355382681468901253417560779939579476900447426997003869812503186057820550400
Short name T511
Test name
Test status
Simulation time 625328098 ps
CPU time 8.26 seconds
Started Nov 22 01:40:08 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 217388 kb
Host smart-115d7572-5b08-499d-8d8a-d4b4eb7a8574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36355382681468901253417560779939579476900447426997003869812503186057820550400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.lc_ctrl_security_escalation.36355382681468901253417560779939579476900447426997003869812503186057820550400
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.45694058358449399311172198244239859239486373849085152267034618895138931679108
Short name T400
Test name
Test status
Simulation time 291295056 ps
CPU time 4.6 seconds
Started Nov 22 01:39:47 PM PST 23
Finished Nov 22 01:39:52 PM PST 23
Peak memory 213812 kb
Host smart-27426b86-cf66-485f-a279-812e31f66b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45694058358449399311172198244239859239486373849085152267034618895138931679108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.lc_ctrl_smoke.45694058358449399311172198244239859239486373849085152267034618895138931679108
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.52352209955524269864303609358444269596374661772108205239239365644296650828620
Short name T886
Test name
Test status
Simulation time 487150632 ps
CPU time 21.41 seconds
Started Nov 22 01:39:52 PM PST 23
Finished Nov 22 01:40:14 PM PST 23
Peak memory 250396 kb
Host smart-677c811a-8f99-4f99-9514-18a7c18ca048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52352209955524269864303609358444269596374661772108205239239365644296650828620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.lc_ctrl_state_failure.52352209955524269864303609358444269596374661772108205239239365644296650828620
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.74295625836399984333718807721333960774568658314964067262143128369516772972316
Short name T669
Test name
Test status
Simulation time 217117078 ps
CPU time 7.14 seconds
Started Nov 22 01:39:50 PM PST 23
Finished Nov 22 01:39:58 PM PST 23
Peak memory 246332 kb
Host smart-fc800894-8298-463b-a23b-4fb6aee87459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74295625836399984333718807721333960774568658314964067262143128369516772972316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.lc_ctrl_state_post_trans.74295625836399984333718807721333960774568658314964067262143128369516772972316
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.48656972022993452316207934565602020546039025446502457137979820823444838502063
Short name T363
Test name
Test status
Simulation time 36820395678 ps
CPU time 293.52 seconds
Started Nov 22 01:40:04 PM PST 23
Finished Nov 22 01:44:59 PM PST 23
Peak memory 283472 kb
Host smart-59040257-ca90-4b0d-ac49-5fdf3bc57f78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486569720229934523162079345656020205460390254465024571379798208234
44838502063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.48656972022993452316207934565602020546039025446502457137
979820823444838502063
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.67758207280132599383263496515461820904845605528069306238664050677013150550010
Short name T285
Test name
Test status
Simulation time 16404398 ps
CPU time 0.76 seconds
Started Nov 22 01:39:49 PM PST 23
Finished Nov 22 01:39:51 PM PST 23
Peak memory 207472 kb
Host smart-4a664dce-fc08-4ec5-9b3c-31566af686f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67758207280132599383263496515461820904845605528069306238664050677013150550010 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_volatile_unlock_smoke.67758207280132599383263496515461820904845605528069306
238664050677013150550010
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.108247923577346049875400041881018610939994022272527630174608680890268996886723
Short name T430
Test name
Test status
Simulation time 42189906 ps
CPU time 1 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:07 PM PST 23
Peak memory 207616 kb
Host smart-11779707-0232-4c7e-8954-6b5acb59b432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108247923577346049875400041881018610939994022272527630174608680890268996886723 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.108247923577346049875400041881018610939994022272527630174608680890268996886723
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1982885585595788973755795852189576702525266454263942859030889175555567338251
Short name T673
Test name
Test status
Simulation time 19636515 ps
CPU time 0.82 seconds
Started Nov 22 01:37:38 PM PST 23
Finished Nov 22 01:37:39 PM PST 23
Peak memory 207564 kb
Host smart-ca4ff4cc-ceea-4daa-a4f4-b279f6eafb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982885585595788973755795852189576702525266454263942859030889175555567338251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1982885585595788973755795852189576702525266454263942859030889175555567338251
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2657094477560013712182823401339675753130546523184225988966332647204989684861
Short name T799
Test name
Test status
Simulation time 978628843 ps
CPU time 13.57 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 217424 kb
Host smart-dc060d97-0a13-4769-be4b-048ee7289a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657094477560013712182823401339675753130546523184225988966332647204989684861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.lc_ctrl_errors.2657094477560013712182823401339675753130546523184225988966332647204989684861
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.6429509888165239359337582578624477717383671738227853466813387983617279900236
Short name T548
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.69 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 209012 kb
Host smart-49a4c827-c1c3-41c4-93ee-bbfade5d5927
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6429509888165239359337582578624477717383671738227853466813387983617279900236 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.6429509888165239359337582578624477717383671738227853466813387983617279900236
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.108590040920031162158138013803304970781715039649466653871778302897546287444789
Short name T309
Test name
Test status
Simulation time 5872518263 ps
CPU time 38.51 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:39 PM PST 23
Peak memory 217612 kb
Host smart-77104533-8fca-48c0-b3b3-41c4af705afe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108590040920031162158138013803304970781715039649466653871778302897546287444789 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_errors.108590040920031162158138013803304970781715039649466653871778302897546287444789
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.9547151992833389571678021015262853930583581003616028856286721678811246654812
Short name T772
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.82 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 217304 kb
Host smart-435e8e48-dbe9-4f95-b082-3bdc7decb225
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9547151992833389571678021015262853930583581003616028856286721678811246654812 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.9547151992833389571678021015262853930583581003616028856286721678811246654812
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.95973701363132015695090164535861682580641500449713610945940420527600882389783
Short name T911
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.3 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 217376 kb
Host smart-601463ac-e659-4727-aee9-ad132e93c3a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95973701363132015695090164535861682580641500449713610945940420527600882389783 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_prog_failure.95973701363132015695090164535861682580641500449713610945940420527600882389783
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.29477098017157012582090338788528808116431069259986499931438389275848410152062
Short name T827
Test name
Test status
Simulation time 1406053995 ps
CPU time 9.79 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 212320 kb
Host smart-c43703f5-5bea-4d14-8236-9457d4b073ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29477098017157012582090338788528808116431069259986499931438389275848410152062 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_regwen_during_op.294770980171570125820903387885288081164310692599864999314
38389275848410152062
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.93201469289511406246320871853897852402774941898960411076576294864765158086185
Short name T956
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.83 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 212912 kb
Host smart-2554de28-8574-4b09-85f6-971991e2551d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93201469289511406246320871853897852402774941898960411076576294864765158086185 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.93201469289511406246320871853897852402774941898960411076576294864765158086185
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.50571784430225270748271532651601647042442913058219319876834931165201716357751
Short name T510
Test name
Test status
Simulation time 5030489285 ps
CPU time 49.96 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:49 PM PST 23
Peak memory 269152 kb
Host smart-3ef07bce-8da5-4db4-96d3-637c61b5eadd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50571784430225270748271532651601647042442913058219319876834931165201716357751 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_state_failure.505717844302252707482715326516016470424429130582193198768349311
65201716357751
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.111689471948627355443477946761334076419470652758693562427591147200510775399091
Short name T475
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.48 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 246792 kb
Host smart-da8d45fc-ccb2-4932-ad5d-bcbf8b42c904
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111689471948627355443477946761334076419470652758693562427591147200510775399091 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_state_post_trans.11168947194862735544347794676133407641947065275869356242
7591147200510775399091
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.44558882444847573614437470448076414109111853588990415211874939080377050592645
Short name T450
Test name
Test status
Simulation time 159313969 ps
CPU time 2.94 seconds
Started Nov 22 01:37:53 PM PST 23
Finished Nov 22 01:38:02 PM PST 23
Peak memory 217472 kb
Host smart-13d92c37-1221-4652-b44c-8dda7e8b3cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44558882444847573614437470448076414109111853588990415211874939080377050592645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_prog_failure.44558882444847573614437470448076414109111853588990415211874939080377050592645
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.57046462270449563156254699318424104115620717961206106388816652478025024782138
Short name T268
Test name
Test status
Simulation time 420615450 ps
CPU time 5.75 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 213352 kb
Host smart-9d07a579-aea1-4baa-9d29-a62e23b97471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57046462270449563156254699318424104115620717961206106388816652478025024782138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.lc_ctrl_regwen_during_op.57046462270449563156254699318424104115620717961206106388816652478025024782138
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.11739148268715419356441035763796585835156810304525250991934049065032415089602
Short name T895
Test name
Test status
Simulation time 1010128591 ps
CPU time 15.72 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 218496 kb
Host smart-292291d0-9919-4e0a-a814-c84e1dfbd5c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11739148268715419356441035763796585835156810304525250991934049065032415089602 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.11739148268715419356441035763796585835156810304525250991934049065032415089602
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.19518923543918299887050113090820224821304807661029261172660491983900026123233
Short name T491
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.9 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 217436 kb
Host smart-53b05776-2dde-4d9e-8c33-00fc1ac660e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19518923543918299887050113090820224821304807661029261172660491983900026123233 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_digest.19518923543918299887050113090820224821304807661029261172660491983900026123233
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.35827270693167450308555331519250379926666795792644543877096467130040462933276
Short name T527
Test name
Test status
Simulation time 964986095 ps
CPU time 11.12 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 217368 kb
Host smart-359ffab8-bae2-42a8-afe1-0b407c03d5dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35827270693167450308555331519250379926666795792644543877096467130040462933276 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.35827270693167450308555331519250379926666795792644543877096467130040462933276
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.111209958078061123719783874233594120903285993959938565023508461121898200127765
Short name T325
Test name
Test status
Simulation time 625328098 ps
CPU time 8.15 seconds
Started Nov 22 01:37:41 PM PST 23
Finished Nov 22 01:37:51 PM PST 23
Peak memory 217456 kb
Host smart-47680949-b3e2-4a3d-9613-d664464aef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111209958078061123719783874233594120903285993959938565023508461121898200127765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.lc_ctrl_security_escalation.111209958078061123719783874233594120903285993959938565023508461121898200127765
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.58099951035266086896215811413303786496757044123032852393994093977891047249717
Short name T753
Test name
Test status
Simulation time 291295056 ps
CPU time 4.56 seconds
Started Nov 22 01:37:26 PM PST 23
Finished Nov 22 01:37:34 PM PST 23
Peak memory 213840 kb
Host smart-79666f2d-bdfa-46c5-97d9-af7667fbb69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58099951035266086896215811413303786496757044123032852393994093977891047249717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_smoke.58099951035266086896215811413303786496757044123032852393994093977891047249717
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.113413291785972189642035675342624898080544348842496328125100240713658485481815
Short name T342
Test name
Test status
Simulation time 487150632 ps
CPU time 20.8 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 250440 kb
Host smart-9b26ef99-1a53-4c8a-b816-e26b9ea2b7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113413291785972189642035675342624898080544348842496328125100240713658485481815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_state_failure.113413291785972189642035675342624898080544348842496328125100240713658485481815
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.87738050811419193950081816749365270745413407103775692585368193725129469838726
Short name T722
Test name
Test status
Simulation time 217117078 ps
CPU time 7.13 seconds
Started Nov 22 01:37:39 PM PST 23
Finished Nov 22 01:37:47 PM PST 23
Peak memory 246312 kb
Host smart-9af138e5-faab-4a06-8e1c-74736ec42bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87738050811419193950081816749365270745413407103775692585368193725129469838726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.lc_ctrl_state_post_trans.87738050811419193950081816749365270745413407103775692585368193725129469838726
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.37761357480970322400267931303064596443560441434933276658015704684381581774834
Short name T26
Test name
Test status
Simulation time 36820395678 ps
CPU time 295 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:42:58 PM PST 23
Peak memory 279652 kb
Host smart-70168021-51e8-45d6-950c-040c67c6f7ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377613574809703224002679313030645964435604414349332766580157046843
81581774834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.377613574809703224002679313030645964435604414349332766580
15704684381581774834
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.111857959113542614347777610891513159048556914583778769749013191571662946536914
Short name T785
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:37:27 PM PST 23
Finished Nov 22 01:37:30 PM PST 23
Peak memory 207628 kb
Host smart-2426c9ac-1721-419e-bcf0-2fd362faa2eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111857959113542614347777610891513159048556914583778769749013191571662946536914 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_volatile_unlock_smoke.11185795911354261434777761089151315904855691458377876
9749013191571662946536914
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.94808348076524211878773809525343305001815201452700223823780659921590038149934
Short name T834
Test name
Test status
Simulation time 42189906 ps
CPU time 0.95 seconds
Started Nov 22 01:37:34 PM PST 23
Finished Nov 22 01:37:36 PM PST 23
Peak memory 207748 kb
Host smart-79d8c196-2a94-4aee-8b11-887db8a4749e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94808348076524211878773809525343305001815201452700223823780659921590038149934 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.94808348076524211878773809525343305001815201452700223823780659921590038149934
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.12482368419001611986392713416199986638970348114848089224915194419352832482405
Short name T305
Test name
Test status
Simulation time 19636515 ps
CPU time 0.75 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 207572 kb
Host smart-7e4d7440-8a98-4feb-afc5-c1d5dda32bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12482368419001611986392713416199986638970348114848089224915194419352832482405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.12482368419001611986392713416199986638970348114848089224915194419352832482405
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.87803409733523723602494518336540843528208512022928172922516646208640638870969
Short name T676
Test name
Test status
Simulation time 978628843 ps
CPU time 13.84 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 217436 kb
Host smart-dd20206f-c8ac-46a7-b091-ec8b8d4f52bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87803409733523723602494518336540843528208512022928172922516646208640638870969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.lc_ctrl_errors.87803409733523723602494518336540843528208512022928172922516646208640638870969
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.64096445367128164556058618361049337719798288238524035568796633010253162385497
Short name T914
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.29 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 208888 kb
Host smart-02cc0e1b-30b3-4c4c-96b0-0f369114125b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64096445367128164556058618361049337719798288238524035568796633010253162385497 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.64096445367128164556058618361049337719798288238524035568796633010253162385497
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.100580891646223101185651749697186908646603177069688175425922933714992227525953
Short name T697
Test name
Test status
Simulation time 5872518263 ps
CPU time 39.8 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:53 PM PST 23
Peak memory 217744 kb
Host smart-4d948688-c6b0-4f33-b838-9a4bdff6996a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100580891646223101185651749697186908646603177069688175425922933714992227525953 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_errors.100580891646223101185651749697186908646603177069688175425922933714992227525953
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.8522822943247175727316821075709756726920909771942710232950880390307279713419
Short name T392
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.36 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 217324 kb
Host smart-aed36236-7248-46b1-bf4a-cef18fba651c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8522822943247175727316821075709756726920909771942710232950880390307279713419 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.8522822943247175727316821075709756726920909771942710232950880390307279713419
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.102123786593788262866699420009340337968560870010443685714696749578638471822733
Short name T138
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.38 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 217436 kb
Host smart-96824bf6-713e-4a54-9a6f-e0d8992e8d90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102123786593788262866699420009340337968560870010443685714696749578638471822733 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_prog_failure.1021237865937882628666994200093403379685608700104436857146967495
78638471822733
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.93520329334044389730285818801711318457563751752905326927914656071456426742389
Short name T890
Test name
Test status
Simulation time 1406053995 ps
CPU time 10.19 seconds
Started Nov 22 01:38:11 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 212320 kb
Host smart-841d8c49-8a44-4b80-ba40-7b084d4d073c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93520329334044389730285818801711318457563751752905326927914656071456426742389 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_regwen_during_op.935203293340443897302858188017113184575637517529053269279
14656071456426742389
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.49746522910698480869605425385795823963748289039119071075457274026323453522153
Short name T850
Test name
Test status
Simulation time 1348822310 ps
CPU time 9.41 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 212804 kb
Host smart-da8c1262-51dd-46cb-a8e6-4b28e5602b71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49746522910698480869605425385795823963748289039119071075457274026323453522153 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.49746522910698480869605425385795823963748289039119071075457274026323453522153
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.47589515697941140956285328964860349450036364018123787004600163246914750676205
Short name T635
Test name
Test status
Simulation time 5030489285 ps
CPU time 47.5 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:39:03 PM PST 23
Peak memory 268972 kb
Host smart-a9a899b7-6696-42ae-8fd9-ba0cd68bc09a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47589515697941140956285328964860349450036364018123787004600163246914750676205 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_state_failure.475895156979411409562853289648603494500363640181237870046001632
46914750676205
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.64317872666582941109304242928062424403435045198045840253742432912799295623183
Short name T641
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.77 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 246716 kb
Host smart-2b87ef44-9552-4172-87b9-a99f66a94073
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64317872666582941109304242928062424403435045198045840253742432912799295623183 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_state_post_trans.643178726665829411093042429280624244034350451980458402537
42432912799295623183
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.39508277957777129578877639651451964250316139377596072993380716480578234625683
Short name T411
Test name
Test status
Simulation time 159313969 ps
CPU time 2.99 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 217376 kb
Host smart-28dcfd48-b328-4c5f-8f5b-c33f43868438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39508277957777129578877639651451964250316139377596072993380716480578234625683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_prog_failure.39508277957777129578877639651451964250316139377596072993380716480578234625683
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.114814211363336113999328658240506424680130648497767615886951240587944477485072
Short name T480
Test name
Test status
Simulation time 420615450 ps
CPU time 5.58 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 213188 kb
Host smart-4b8aa76f-4a5b-41c0-9b74-94cdc1e530ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114814211363336113999328658240506424680130648497767615886951240587944477485072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.lc_ctrl_regwen_during_op.114814211363336113999328658240506424680130648497767615886951240587944477485072
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.57797735046713403301206118324631122680622970359700017596346740860191300626425
Short name T269
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.38 seconds
Started Nov 22 01:38:11 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 218496 kb
Host smart-9a5d1ed0-529d-4af0-9604-110fd86b5036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57797735046713403301206118324631122680622970359700017596346740860191300626425 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.57797735046713403301206118324631122680622970359700017596346740860191300626425
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.29126827583923299238797868648151439059446205632483588298661814880478737773866
Short name T21
Test name
Test status
Simulation time 1321911811 ps
CPU time 16.48 seconds
Started Nov 22 01:37:36 PM PST 23
Finished Nov 22 01:37:53 PM PST 23
Peak memory 217288 kb
Host smart-d00a4dfa-abf9-461c-a133-525947fd2d49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29126827583923299238797868648151439059446205632483588298661814880478737773866 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_digest.29126827583923299238797868648151439059446205632483588298661814880478737773866
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.83367512407889613982735966083532733366352664408557543837760065201429643065346
Short name T867
Test name
Test status
Simulation time 964986095 ps
CPU time 11.14 seconds
Started Nov 22 01:38:12 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 217260 kb
Host smart-cf8b121e-d996-4289-b6ff-c88d99ef2a41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83367512407889613982735966083532733366352664408557543837760065201429643065346 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.83367512407889613982735966083532733366352664408557543837760065201429643065346
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.30877156722427921600219727909313091880421269383946920977468731016310106717267
Short name T739
Test name
Test status
Simulation time 625328098 ps
CPU time 8.7 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 217484 kb
Host smart-eafc6bd6-61af-412e-81be-26bb9ff21cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30877156722427921600219727909313091880421269383946920977468731016310106717267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_security_escalation.30877156722427921600219727909313091880421269383946920977468731016310106717267
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.88901640517488787805686202007065295276335847204294675142234088643571255921875
Short name T796
Test name
Test status
Simulation time 291295056 ps
CPU time 4.73 seconds
Started Nov 22 01:37:59 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 213904 kb
Host smart-87e37fa8-19a9-4e52-be17-05479698eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88901640517488787805686202007065295276335847204294675142234088643571255921875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_smoke.88901640517488787805686202007065295276335847204294675142234088643571255921875
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.99542441694332533573964547178951305832440374592172607171325249565148526553422
Short name T773
Test name
Test status
Simulation time 487150632 ps
CPU time 21.35 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 250364 kb
Host smart-467f7ef3-6ec2-4149-bbd7-e121a6ad8fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99542441694332533573964547178951305832440374592172607171325249565148526553422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_state_failure.99542441694332533573964547178951305832440374592172607171325249565148526553422
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.8440238536346036755155725846219843146918631482385702423042238504456974576931
Short name T716
Test name
Test status
Simulation time 217117078 ps
CPU time 7.04 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 246440 kb
Host smart-d724241e-5e8e-4f36-a092-7ee6a5d9cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8440238536346036755155725846219843146918631482385702423042238504456974576931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.lc_ctrl_state_post_trans.8440238536346036755155725846219843146918631482385702423042238504456974576931
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.29061913527527398345825818640400384431161621090133039206199002913434662485574
Short name T842
Test name
Test status
Simulation time 36820395678 ps
CPU time 290.75 seconds
Started Nov 22 01:37:28 PM PST 23
Finished Nov 22 01:42:21 PM PST 23
Peak memory 279592 kb
Host smart-7ae4e507-bea2-4a15-ac6b-e5dbdbed28ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290619135275273983458258186404003844311616210901330392061990029134
34662485574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.290619135275273983458258186404003844311616210901330392061
99002913434662485574
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.55852425719668818307835855690181285725604028055186063162516844899066454617791
Short name T912
Test name
Test status
Simulation time 16404398 ps
CPU time 0.72 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 207624 kb
Host smart-0d84f798-0be9-4782-a1d1-cb5c8f5e8534
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55852425719668818307835855690181285725604028055186063162516844899066454617791 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_volatile_unlock_smoke.558524257196688183078358556901812857256040280551860631
62516844899066454617791
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.111023428622729493882935919413199241758209765735028321784554255906650553890644
Short name T835
Test name
Test status
Simulation time 42189906 ps
CPU time 0.94 seconds
Started Nov 22 01:37:56 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 207772 kb
Host smart-6be62568-f9ed-4e27-92e5-4c371684106c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111023428622729493882935919413199241758209765735028321784554255906650553890644 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.111023428622729493882935919413199241758209765735028321784554255906650553890644
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.108241148940140552972099377371848345637020988716518075592363356937837097015916
Short name T759
Test name
Test status
Simulation time 19636515 ps
CPU time 0.79 seconds
Started Nov 22 01:37:45 PM PST 23
Finished Nov 22 01:37:53 PM PST 23
Peak memory 207580 kb
Host smart-5649e05d-bbf4-4aa5-a892-171c17073e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108241148940140552972099377371848345637020988716518075592363356937837097015916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.108241148940140552972099377371848345637020988716518075592363356937837097015916
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.31677552346423813556064055294591769410875990909929024717411974417154679205103
Short name T418
Test name
Test status
Simulation time 978628843 ps
CPU time 13.63 seconds
Started Nov 22 01:37:39 PM PST 23
Finished Nov 22 01:37:54 PM PST 23
Peak memory 217468 kb
Host smart-f77e93f7-4c6d-4837-9859-53243c6426e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31677552346423813556064055294591769410875990909929024717411974417154679205103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.lc_ctrl_errors.31677552346423813556064055294591769410875990909929024717411974417154679205103
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.61421419213886593770220224654891039743985450961834181671604197190727181050736
Short name T774
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.54 seconds
Started Nov 22 01:37:42 PM PST 23
Finished Nov 22 01:37:54 PM PST 23
Peak memory 209008 kb
Host smart-1c368811-131b-4549-a312-15a87488fca8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61421419213886593770220224654891039743985450961834181671604197190727181050736 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.61421419213886593770220224654891039743985450961834181671604197190727181050736
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.45170277604133859663177575962634163693440153591016442834511295281500103809504
Short name T348
Test name
Test status
Simulation time 5872518263 ps
CPU time 42.45 seconds
Started Nov 22 01:37:40 PM PST 23
Finished Nov 22 01:38:24 PM PST 23
Peak memory 217764 kb
Host smart-e3f088f3-4c14-43f1-a821-6323d0b53b05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45170277604133859663177575962634163693440153591016442834511295281500103809504 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_errors.45170277604133859663177575962634163693440153591016442834511295281500103809504
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.111690149589678371169098426098853741922044315988436696823687781428906401298472
Short name T627
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.64 seconds
Started Nov 22 01:37:52 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 217260 kb
Host smart-bf2b29e8-d584-4c57-a275-baf914e431dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111690149589678371169098426098853741922044315988436696823687781428906401298472 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.111690149589678371169098426098853741922044315988436696823687781428906401298472
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.24837549071766550399718199438909176747375105246438807469264531889776851518659
Short name T137
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.19 seconds
Started Nov 22 01:37:39 PM PST 23
Finished Nov 22 01:37:50 PM PST 23
Peak memory 217320 kb
Host smart-e7ea3672-e30f-4851-b82c-0fef6d5935d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24837549071766550399718199438909176747375105246438807469264531889776851518659 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_prog_failure.24837549071766550399718199438909176747375105246438807469264531889776851518659
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.23228760157273914360252158706091760560828669273333603241390384544166869250981
Short name T312
Test name
Test status
Simulation time 1406053995 ps
CPU time 10.19 seconds
Started Nov 22 01:37:41 PM PST 23
Finished Nov 22 01:37:53 PM PST 23
Peak memory 212240 kb
Host smart-4774be01-0264-48f5-b5dd-36aedb116503
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228760157273914360252158706091760560828669273333603241390384544166869250981 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_regwen_during_op.232287601572739143602521587060917605608286692733336032413
90384544166869250981
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.92246440721768612044806112500246349186357263790338251855437832963652756851204
Short name T847
Test name
Test status
Simulation time 1348822310 ps
CPU time 9.17 seconds
Started Nov 22 01:37:53 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 212892 kb
Host smart-bf325164-0378-4627-8ae6-f4fbe1d0d154
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92246440721768612044806112500246349186357263790338251855437832963652756851204 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.92246440721768612044806112500246349186357263790338251855437832963652756851204
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.35679453688653231259428341725749796928124491736241366953628191602104012884729
Short name T454
Test name
Test status
Simulation time 5030489285 ps
CPU time 50.49 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:51 PM PST 23
Peak memory 269112 kb
Host smart-93f76279-71d2-4c69-8114-35e7c7c496b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35679453688653231259428341725749796928124491736241366953628191602104012884729 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_state_failure.356794536886532312594283417257497969281244917362413669536281916
02104012884729
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.48125510981971134990720142470975813942554592256744284177115699885062505427586
Short name T780
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.15 seconds
Started Nov 22 01:37:52 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 246772 kb
Host smart-df71db97-2f6c-454f-b5a5-964c7b383717
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48125510981971134990720142470975813942554592256744284177115699885062505427586 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_state_post_trans.481255109819711349907201424709758139425545922567442841771
15699885062505427586
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.77554313568491831056219729342173038802127655113727974456436693852250153947093
Short name T702
Test name
Test status
Simulation time 159313969 ps
CPU time 2.9 seconds
Started Nov 22 01:37:26 PM PST 23
Finished Nov 22 01:37:32 PM PST 23
Peak memory 217464 kb
Host smart-464a802c-56c1-4697-beab-e0972e9e2539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77554313568491831056219729342173038802127655113727974456436693852250153947093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_prog_failure.77554313568491831056219729342173038802127655113727974456436693852250153947093
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.7205654428794880979207454232600569913642554996373705636178231387792253298433
Short name T20
Test name
Test status
Simulation time 420615450 ps
CPU time 5.95 seconds
Started Nov 22 01:37:41 PM PST 23
Finished Nov 22 01:37:48 PM PST 23
Peak memory 213292 kb
Host smart-97cb88c2-2242-431b-98e3-667f80150860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7205654428794880979207454232600569913642554996373705636178231387792253298433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.lc_ctrl_regwen_during_op.7205654428794880979207454232600569913642554996373705636178231387792253298433
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.31978743178853947439880081932366602195403230384707570114412678492848905181948
Short name T593
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.34 seconds
Started Nov 22 01:37:38 PM PST 23
Finished Nov 22 01:37:53 PM PST 23
Peak memory 218404 kb
Host smart-369effa9-d6ca-4bf8-b7c9-fc58b680d4b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31978743178853947439880081932366602195403230384707570114412678492848905181948 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.31978743178853947439880081932366602195403230384707570114412678492848905181948
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.67573599275510939643780991950051287833816078328515653319133665053668580986257
Short name T825
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.46 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 217380 kb
Host smart-0b0cdf87-7e0f-45e7-a87e-8a4299aff050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67573599275510939643780991950051287833816078328515653319133665053668580986257 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_digest.67573599275510939643780991950051287833816078328515653319133665053668580986257
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.95467486008896515755368879272765356866807225100719979150281077873710951462788
Short name T587
Test name
Test status
Simulation time 964986095 ps
CPU time 10.94 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 217420 kb
Host smart-c383d5a9-339f-43ed-9622-6b88d4915087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95467486008896515755368879272765356866807225100719979150281077873710951462788 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.95467486008896515755368879272765356866807225100719979150281077873710951462788
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.22533781704320134321506409056798230457735734298810068885065221939072314603678
Short name T960
Test name
Test status
Simulation time 625328098 ps
CPU time 7.98 seconds
Started Nov 22 01:37:25 PM PST 23
Finished Nov 22 01:37:37 PM PST 23
Peak memory 217512 kb
Host smart-bc699c92-82e7-4e4e-af36-a0dacd0e7fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22533781704320134321506409056798230457735734298810068885065221939072314603678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_security_escalation.22533781704320134321506409056798230457735734298810068885065221939072314603678
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.67504501854669588675933603388888153566441083142552375430303137336070627954658
Short name T547
Test name
Test status
Simulation time 291295056 ps
CPU time 4.61 seconds
Started Nov 22 01:37:34 PM PST 23
Finished Nov 22 01:37:40 PM PST 23
Peak memory 213768 kb
Host smart-8e5a56f7-4870-4073-b9c4-376f984e73a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67504501854669588675933603388888153566441083142552375430303137336070627954658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_smoke.67504501854669588675933603388888153566441083142552375430303137336070627954658
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.75323460742848779972661664689144830381137570039537586122560689480226335147480
Short name T579
Test name
Test status
Simulation time 487150632 ps
CPU time 20.76 seconds
Started Nov 22 01:37:25 PM PST 23
Finished Nov 22 01:37:50 PM PST 23
Peak memory 250392 kb
Host smart-49fa22a2-9da3-4e35-9797-79f4fa323de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75323460742848779972661664689144830381137570039537586122560689480226335147480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_state_failure.75323460742848779972661664689144830381137570039537586122560689480226335147480
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.74007659593653336493988648030762625445443590362712755940198734627384532709324
Short name T821
Test name
Test status
Simulation time 217117078 ps
CPU time 7.1 seconds
Started Nov 22 01:37:36 PM PST 23
Finished Nov 22 01:37:44 PM PST 23
Peak memory 246340 kb
Host smart-0458ce5a-3fb2-45d5-864a-1254de59f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74007659593653336493988648030762625445443590362712755940198734627384532709324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.lc_ctrl_state_post_trans.74007659593653336493988648030762625445443590362712755940198734627384532709324
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.69058235203586447153377087734362020610401276121935947510864566859674596266872
Short name T746
Test name
Test status
Simulation time 36820395678 ps
CPU time 290.67 seconds
Started Nov 22 01:37:43 PM PST 23
Finished Nov 22 01:42:36 PM PST 23
Peak memory 279616 kb
Host smart-564f50c2-3cc8-48a0-a9cb-d44cd62233e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690582352035864471533770877343620206104012761219359475108645668596
74596266872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.690582352035864471533770877343620206104012761219359475108
64566859674596266872
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.52202437055552894937017937305584025163828303910301298557972746341678427221779
Short name T756
Test name
Test status
Simulation time 16404398 ps
CPU time 0.71 seconds
Started Nov 22 01:37:25 PM PST 23
Finished Nov 22 01:37:29 PM PST 23
Peak memory 207628 kb
Host smart-22a76d9a-8bc4-4662-874e-7251050c2e9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52202437055552894937017937305584025163828303910301298557972746341678427221779 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_volatile_unlock_smoke.522024370555528949370179373055840251638283039103012985
57972746341678427221779
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.87712643738569851294558895457988710057396280506665392307254826302024102836403
Short name T465
Test name
Test status
Simulation time 42189906 ps
CPU time 0.94 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 207716 kb
Host smart-64297e13-a9b3-43d7-86c7-31fa9293d132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87712643738569851294558895457988710057396280506665392307254826302024102836403 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.87712643738569851294558895457988710057396280506665392307254826302024102836403
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.31452005829867437119246412452812946974836742337079771540679285548052015141260
Short name T560
Test name
Test status
Simulation time 19636515 ps
CPU time 0.75 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:01 PM PST 23
Peak memory 207472 kb
Host smart-de1cb676-5d6c-4636-94a0-525e52f55092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31452005829867437119246412452812946974836742337079771540679285548052015141260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.31452005829867437119246412452812946974836742337079771540679285548052015141260
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.7584150133464431122150311201322905960798131944042029973983516149995684584638
Short name T945
Test name
Test status
Simulation time 978628843 ps
CPU time 14.34 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:38:06 PM PST 23
Peak memory 217460 kb
Host smart-7eb48e9e-b34f-432e-960b-3400562bdb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7584150133464431122150311201322905960798131944042029973983516149995684584638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.lc_ctrl_errors.7584150133464431122150311201322905960798131944042029973983516149995684584638
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.39192250458961859531002999878430912193215133144407414344383082501446630201950
Short name T35
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.43 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:10 PM PST 23
Peak memory 209020 kb
Host smart-773480c7-babf-4868-be56-259470a66c8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39192250458961859531002999878430912193215133144407414344383082501446630201950 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.39192250458961859531002999878430912193215133144407414344383082501446630201950
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.57615171241151167847124173681191963617505159423789206104402684229110108664644
Short name T614
Test name
Test status
Simulation time 5872518263 ps
CPU time 42.3 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:43 PM PST 23
Peak memory 217776 kb
Host smart-94e33e63-4a08-4e7d-9e1c-5cc7656920b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57615171241151167847124173681191963617505159423789206104402684229110108664644 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_errors.57615171241151167847124173681191963617505159423789206104402684229110108664644
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.49706210125373160367907751889481627500357300793848059523648486840751938200846
Short name T815
Test name
Test status
Simulation time 2797596434 ps
CPU time 14.11 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 217372 kb
Host smart-5612f6d6-b4ca-4d9f-820b-a4bd976ccb10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49706210125373160367907751889481627500357300793848059523648486840751938200846 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.49706210125373160367907751889481627500357300793848059523648486840751938200846
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.34788465832830688061066569254170576571639907694515011098521420147252913696596
Short name T417
Test name
Test status
Simulation time 1480535542 ps
CPU time 11.22 seconds
Started Nov 22 01:37:58 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 217412 kb
Host smart-ed535275-a784-4409-9fe0-70f8f49eb76d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34788465832830688061066569254170576571639907694515011098521420147252913696596 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_prog_failure.34788465832830688061066569254170576571639907694515011098521420147252913696596
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.22836280940575663131512256221918359890248414152527736720409954086432976421542
Short name T818
Test name
Test status
Simulation time 1406053995 ps
CPU time 9.93 seconds
Started Nov 22 01:38:01 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 211712 kb
Host smart-45dc1621-0f67-40f9-a07a-d36c189b9e72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836280940575663131512256221918359890248414152527736720409954086432976421542 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_regwen_during_op.228362809405756631315122562219183598902484141525277367204
09954086432976421542
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.90611462478964071847476304912334784914199468745877570909507026685594209712776
Short name T410
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.58 seconds
Started Nov 22 01:38:00 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 212892 kb
Host smart-3bd9fc2a-a96f-4549-abd2-18a7c2cc266d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90611462478964071847476304912334784914199468745877570909507026685594209712776 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.90611462478964071847476304912334784914199468745877570909507026685594209712776
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.11193012411831837031023593744621074539945702355195548815154190336667383120486
Short name T745
Test name
Test status
Simulation time 5030489285 ps
CPU time 49.41 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:56 PM PST 23
Peak memory 269156 kb
Host smart-8b078097-056e-4231-8fd5-4e6e935895b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11193012411831837031023593744621074539945702355195548815154190336667383120486 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_state_failure.111930124118318370310235937446210745399457023551955488151541903
36667383120486
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.45194748066714770922182774367916679645581777514753166505909627958973727709457
Short name T141
Test name
Test status
Simulation time 1491321170 ps
CPU time 14.98 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 246656 kb
Host smart-5da2ab55-9c68-4c5f-96a3-ca949db843ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45194748066714770922182774367916679645581777514753166505909627958973727709457 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_state_post_trans.451947480667147709221827743679166796455817775147531665059
09627958973727709457
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.74163199038778425015938954638993145049690471917796355912616839007023695044455
Short name T919
Test name
Test status
Simulation time 159313969 ps
CPU time 2.97 seconds
Started Nov 22 01:37:46 PM PST 23
Finished Nov 22 01:37:57 PM PST 23
Peak memory 217492 kb
Host smart-2600b958-b1e9-46e0-ac9f-84bf1cd3c8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74163199038778425015938954638993145049690471917796355912616839007023695044455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_prog_failure.74163199038778425015938954638993145049690471917796355912616839007023695044455
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.84325843027670139742930552340326192455169100826932354648588365712890767273657
Short name T949
Test name
Test status
Simulation time 420615450 ps
CPU time 6.17 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:07 PM PST 23
Peak memory 213436 kb
Host smart-90ee58d3-7a72-40c6-b6a5-5b8dd9ce2686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84325843027670139742930552340326192455169100826932354648588365712890767273657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.lc_ctrl_regwen_during_op.84325843027670139742930552340326192455169100826932354648588365712890767273657
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.6897086576328070200392205775806679748902916695685928901412730662964539565220
Short name T451
Test name
Test status
Simulation time 1010128591 ps
CPU time 16 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 218364 kb
Host smart-6415ba33-06fd-4283-a7bc-ff91378ac4fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6897086576328070200392205775806679748902916695685928901412730662964539565220 -assert nopostproc
+UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.6897086576328070200392205775806679748902916695685928901412730662964539565220
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.53999927820840631333931934230869229933111254976735455777004604351010232936218
Short name T961
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.54 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:21 PM PST 23
Peak memory 217420 kb
Host smart-76f512e2-dd2e-4ff6-b705-d5bd22d6e4b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53999927820840631333931934230869229933111254976735455777004604351010232936218 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_digest.53999927820840631333931934230869229933111254976735455777004604351010232936218
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.88496179713334533448762513411148812678271351708340134374673633655399754290089
Short name T851
Test name
Test status
Simulation time 964986095 ps
CPU time 11.22 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:17 PM PST 23
Peak memory 217456 kb
Host smart-f4ac34ff-1d52-4108-a11c-72352a176f46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88496179713334533448762513411148812678271351708340134374673633655399754290089 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.88496179713334533448762513411148812678271351708340134374673633655399754290089
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.37163321358312626940304723086691748341611769379020883997630581720671587640140
Short name T768
Test name
Test status
Simulation time 625328098 ps
CPU time 8.48 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:09 PM PST 23
Peak memory 217480 kb
Host smart-89986395-6a89-4ddc-8f61-021c651dcfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37163321358312626940304723086691748341611769379020883997630581720671587640140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_security_escalation.37163321358312626940304723086691748341611769379020883997630581720671587640140
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.93754813433804959269115020281081418236097908104918552383844675318233001316399
Short name T737
Test name
Test status
Simulation time 291295056 ps
CPU time 4.56 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:05 PM PST 23
Peak memory 213808 kb
Host smart-c87bf89f-882c-4c89-8b72-329e99fbe8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93754813433804959269115020281081418236097908104918552383844675318233001316399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_smoke.93754813433804959269115020281081418236097908104918552383844675318233001316399
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.14671329932343713830811587623793971900502511673996721635042243666703749667468
Short name T969
Test name
Test status
Simulation time 487150632 ps
CPU time 20.34 seconds
Started Nov 22 01:37:55 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 250320 kb
Host smart-abd15f55-f31f-402e-be97-b49c7730b86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14671329932343713830811587623793971900502511673996721635042243666703749667468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_state_failure.14671329932343713830811587623793971900502511673996721635042243666703749667468
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.15991278634276406742073357446234235165949830746895187175325239832822059495849
Short name T959
Test name
Test status
Simulation time 217117078 ps
CPU time 6.91 seconds
Started Nov 22 01:37:57 PM PST 23
Finished Nov 22 01:38:07 PM PST 23
Peak memory 246296 kb
Host smart-08123f46-478f-4376-9bb8-0b6a92ae055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15991278634276406742073357446234235165949830746895187175325239832822059495849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.lc_ctrl_state_post_trans.15991278634276406742073357446234235165949830746895187175325239832822059495849
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.39694494512834240737335767529788393107173451172711953156322709753628310691860
Short name T15
Test name
Test status
Simulation time 36820395678 ps
CPU time 290.89 seconds
Started Nov 22 01:38:03 PM PST 23
Finished Nov 22 01:42:58 PM PST 23
Peak memory 279536 kb
Host smart-c234ee0f-1aa1-46a6-8a4a-f45ca747f14e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396944945128342407373357675297883931071734511727119531563227097536
28310691860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.396944945128342407373357675297883931071734511727119531563
22709753628310691860
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.54440104432235315165137012922714962720473666618353254198295133215959307802897
Short name T820
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:37:44 PM PST 23
Finished Nov 22 01:37:52 PM PST 23
Peak memory 207612 kb
Host smart-6ea81e31-f862-4f4c-aec7-52843b584c02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54440104432235315165137012922714962720473666618353254198295133215959307802897 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_volatile_unlock_smoke.544401044322353151651370129227149627204736666183532541
98295133215959307802897
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.17989952046250893678794206751330762416466483447304458429437154788795959712969
Short name T84
Test name
Test status
Simulation time 42189906 ps
CPU time 0.99 seconds
Started Nov 22 01:37:42 PM PST 23
Finished Nov 22 01:37:45 PM PST 23
Peak memory 207708 kb
Host smart-1f46eee4-541c-4694-9075-bc2b246fdda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17989952046250893678794206751330762416466483447304458429437154788795959712969 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.17989952046250893678794206751330762416466483447304458429437154788795959712969
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.11569375661720384244828269152731472562755499498770084070923377264692899794210
Short name T562
Test name
Test status
Simulation time 19636515 ps
CPU time 0.77 seconds
Started Nov 22 01:38:05 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 207404 kb
Host smart-cd689f4c-d1a5-4049-8791-465a8fc6a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11569375661720384244828269152731472562755499498770084070923377264692899794210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.11569375661720384244828269152731472562755499498770084070923377264692899794210
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.76896682093584077323617412684549424427898418237820578137942225173160698141737
Short name T44
Test name
Test status
Simulation time 978628843 ps
CPU time 14.03 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:30 PM PST 23
Peak memory 217392 kb
Host smart-a98b2d36-9a01-4696-a674-3db71798c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76896682093584077323617412684549424427898418237820578137942225173160698141737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.lc_ctrl_errors.76896682093584077323617412684549424427898418237820578137942225173160698141737
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.37092741536730545213378335373449570033873985264389541585294592187477487639267
Short name T800
Test name
Test status
Simulation time 1895300081 ps
CPU time 9.57 seconds
Started Nov 22 01:38:11 PM PST 23
Finished Nov 22 01:38:28 PM PST 23
Peak memory 208836 kb
Host smart-aac33048-5fc3-4b09-86aa-6a7148b1c767
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37092741536730545213378335373449570033873985264389541585294592187477487639267 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.37092741536730545213378335373449570033873985264389541585294592187477487639267
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.36561390060880745527013734552423363425847692802749853265564569960864248280181
Short name T916
Test name
Test status
Simulation time 5872518263 ps
CPU time 40.6 seconds
Started Nov 22 01:38:07 PM PST 23
Finished Nov 22 01:38:53 PM PST 23
Peak memory 217788 kb
Host smart-6b09394f-020d-40d2-b6ac-405dd5a1f5de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36561390060880745527013734552423363425847692802749853265564569960864248280181 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_errors.36561390060880745527013734552423363425847692802749853265564569960864248280181
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.95679727006136115953785380475308329404245259259255895509809843005687739872477
Short name T347
Test name
Test status
Simulation time 2797596434 ps
CPU time 13.8 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 217336 kb
Host smart-6a411a2e-1024-41c7-bc23-0700da3db4ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95679727006136115953785380475308329404245259259255895509809843005687739872477 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.95679727006136115953785380475308329404245259259255895509809843005687739872477
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.17662170372752283926344423822845517067769672657541050317664228999901264924322
Short name T840
Test name
Test status
Simulation time 1480535542 ps
CPU time 10.45 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:27 PM PST 23
Peak memory 217468 kb
Host smart-70898a62-1e7c-4afc-9917-d98532729b16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17662170372752283926344423822845517067769672657541050317664228999901264924322 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_prog_failure.17662170372752283926344423822845517067769672657541050317664228999901264924322
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.31558836949843218774384554350813273134052665795304924533539738457907551631681
Short name T770
Test name
Test status
Simulation time 1406053995 ps
CPU time 10.1 seconds
Started Nov 22 01:37:39 PM PST 23
Finished Nov 22 01:37:50 PM PST 23
Peak memory 212300 kb
Host smart-5cbd6cb1-beae-4020-a6f5-b1a5d033f037
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31558836949843218774384554350813273134052665795304924533539738457907551631681 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_regwen_during_op.315588369498432187743845543508132731340526657953049245335
39738457907551631681
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2961302032519156856925165675018671363938028238252029615995209946275789713033
Short name T25
Test name
Test status
Simulation time 1348822310 ps
CPU time 8.7 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:38:23 PM PST 23
Peak memory 212776 kb
Host smart-90080cdb-01fb-4275-95e7-5ceab9426893
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961302032519156856925165675018671363938028238252029615995209946275789713033 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.2961302032519156856925165675018671363938028238252029615995209946275789713033
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.81258866321714708631057165777139948926595958282503667049594670932585377140626
Short name T602
Test name
Test status
Simulation time 5030489285 ps
CPU time 50.82 seconds
Started Nov 22 01:38:08 PM PST 23
Finished Nov 22 01:39:04 PM PST 23
Peak memory 269156 kb
Host smart-25faf23d-203f-42a0-aa23-8196a6ae657f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81258866321714708631057165777139948926595958282503667049594670932585377140626 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_state_failure.812588663217147086310571657771399489265959582825036670495946709
32585377140626
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.8849757332394683216505106870541031581915139121290312139248863390609375121019
Short name T502
Test name
Test status
Simulation time 1491321170 ps
CPU time 15.25 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:31 PM PST 23
Peak memory 246812 kb
Host smart-0abe214b-59b0-41ed-851b-ae8e1492d6c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8849757332394683216505106870541031581915139121290312139248863390609375121019 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_state_post_trans.8849757332394683216505106870541031581915139121290312139248
863390609375121019
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.79270460389829724793326581219686058746659959239335511207006408148037644181199
Short name T663
Test name
Test status
Simulation time 159313969 ps
CPU time 2.95 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:18 PM PST 23
Peak memory 217400 kb
Host smart-76fe7fb1-3d0d-4918-8759-e934b8219ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79270460389829724793326581219686058746659959239335511207006408148037644181199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_prog_failure.79270460389829724793326581219686058746659959239335511207006408148037644181199
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.84722287341607288817750449682550859019189437680466068406610424316233165617193
Short name T952
Test name
Test status
Simulation time 420615450 ps
CPU time 5.82 seconds
Started Nov 22 01:38:09 PM PST 23
Finished Nov 22 01:38:20 PM PST 23
Peak memory 213232 kb
Host smart-09f16358-db16-4b37-86cf-05789be58558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84722287341607288817750449682550859019189437680466068406610424316233165617193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.lc_ctrl_regwen_during_op.84722287341607288817750449682550859019189437680466068406610424316233165617193
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.89086582747031849756703145753566753944727352344895332672438790347252283937023
Short name T284
Test name
Test status
Simulation time 1010128591 ps
CPU time 14.09 seconds
Started Nov 22 01:37:52 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 218528 kb
Host smart-64077257-4a12-44ed-8dc1-72a66b35c497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89086582747031849756703145753566753944727352344895332672438790347252283937023 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.89086582747031849756703145753566753944727352344895332672438790347252283937023
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.80569793762412680511455037928832028833794622346674937304107869430394259875753
Short name T714
Test name
Test status
Simulation time 1321911811 ps
CPU time 15.47 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:38:15 PM PST 23
Peak memory 217440 kb
Host smart-f8aafda6-8d0a-470c-9065-726538c41f58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80569793762412680511455037928832028833794622346674937304107869430394259875753 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_digest.80569793762412680511455037928832028833794622346674937304107869430394259875753
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.81403964407072180274878912240598332462104464622562176326201922270004258846936
Short name T899
Test name
Test status
Simulation time 964986095 ps
CPU time 11.38 seconds
Started Nov 22 01:37:41 PM PST 23
Finished Nov 22 01:37:55 PM PST 23
Peak memory 217348 kb
Host smart-6d1a4acb-e45c-475b-8687-633e3b446916
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81403964407072180274878912240598332462104464622562176326201922270004258846936 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.81403964407072180274878912240598332462104464622562176326201922270004258846936
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.59867929422190894094173985985287347159554685319736323721767664917302493510461
Short name T920
Test name
Test status
Simulation time 625328098 ps
CPU time 8.52 seconds
Started Nov 22 01:38:10 PM PST 23
Finished Nov 22 01:38:25 PM PST 23
Peak memory 217404 kb
Host smart-d7445f88-b647-4fd6-971c-e26830dc5e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59867929422190894094173985985287347159554685319736323721767664917302493510461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_security_escalation.59867929422190894094173985985287347159554685319736323721767664917302493510461
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.22194183408414526120506759332170160004789342916473744080654794244820133697650
Short name T498
Test name
Test status
Simulation time 291295056 ps
CPU time 4.43 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:11 PM PST 23
Peak memory 213696 kb
Host smart-4537023a-6593-4c88-8a20-ebc6e65d3e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22194183408414526120506759332170160004789342916473744080654794244820133697650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_smoke.22194183408414526120506759332170160004789342916473744080654794244820133697650
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.102419706066157282914047228292189395578867664029560737224779904348266498004729
Short name T729
Test name
Test status
Simulation time 487150632 ps
CPU time 21.04 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:32 PM PST 23
Peak memory 250476 kb
Host smart-af57bbb1-85a0-4597-99df-5eaf126ed95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102419706066157282914047228292189395578867664029560737224779904348266498004729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_state_failure.102419706066157282914047228292189395578867664029560737224779904348266498004729
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.101737609604347059516671374430680503756982032219217413590045275932415204980840
Short name T967
Test name
Test status
Simulation time 217117078 ps
CPU time 6.9 seconds
Started Nov 22 01:38:02 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 246348 kb
Host smart-19ffc78f-46d2-4647-ab84-dda8954912c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101737609604347059516671374430680503756982032219217413590045275932415204980840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.lc_ctrl_state_post_trans.101737609604347059516671374430680503756982032219217413590045275932415204980840
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.69314583507548616979006071348127616441754785649932325824094942615920830727749
Short name T727
Test name
Test status
Simulation time 36820395678 ps
CPU time 291.38 seconds
Started Nov 22 01:37:54 PM PST 23
Finished Nov 22 01:42:51 PM PST 23
Peak memory 279656 kb
Host smart-c2948a11-d0ec-4d5d-825e-9b38b33d35c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693145835075486169790060713481276164417547856499323258240949426159
20830727749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.693145835075486169790060713481276164417547856499323258240
94942615920830727749
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.77289527867870337267355795577718867148430291052796867091785362618070812141344
Short name T469
Test name
Test status
Simulation time 16404398 ps
CPU time 0.75 seconds
Started Nov 22 01:38:06 PM PST 23
Finished Nov 22 01:38:12 PM PST 23
Peak memory 207532 kb
Host smart-8d455af1-cf0e-4417-97e0-ddc9f0a335e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77289527867870337267355795577718867148430291052796867091785362618070812141344 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_volatile_unlock_smoke.772895278678703372673557955777188671484302910527968670
91785362618070812141344
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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