Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	972669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1167171

1

T1

1617

T2

733

T10

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1839425	1			T1	1985		T2	382		T103	88
values[0x0]	149723	1			T1	377		T2	315		T10	32
values[0x1]	150692	1			T1	351		T2	341		T10	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	770923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1368917

1

T1

1866

T2

824

T10

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6633	1			T1	7		T113	2		T140	2
valid_sources[0x01]	6555	1			T1	16		T103	2		T166	1
valid_sources[0x02]	6808	1			T1	16		T165	4		T113	2
valid_sources[0x03]	7644	1			T1	13		T10	5		T166	3
valid_sources[0x04]	6979	1			T1	14		T10	2		T166	2
valid_sources[0x05]	8344	1			T1	5		T103	2		T108	6
valid_sources[0x06]	8737	1			T1	11		T113	4		T140	1
valid_sources[0x07]	7897	1			T1	5		T166	2		T113	3
valid_sources[0x08]	7981	1			T1	8		T108	2		T113	8
valid_sources[0x09]	7802	1			T1	13		T10	1		T113	2
valid_sources[0x0a]	7183	1			T1	11		T103	9		T108	4
valid_sources[0x0b]	9980	1			T1	11		T166	2		T113	1
valid_sources[0x0c]	7243	1			T1	10		T166	1		T113	4
valid_sources[0x0d]	7054	1			T1	6		T103	1		T166	1
valid_sources[0x0e]	7292	1			T1	13		T108	6		T166	1
valid_sources[0x0f]	9221	1			T1	7		T103	3		T166	1
valid_sources[0x10]	7136	1			T1	4		T106	1		T113	1
valid_sources[0x11]	8234	1			T1	15		T166	1		T113	3
valid_sources[0x12]	7130	1			T1	15		T103	10		T113	1
valid_sources[0x13]	7307	1			T1	15		T140	3		T136	1
valid_sources[0x14]	7126	1			T1	7		T165	3		T113	7
valid_sources[0x15]	8106	1			T1	10		T113	2		T140	1
valid_sources[0x16]	8779	1			T1	6		T113	1		T114	10
valid_sources[0x17]	7107	1			T1	5		T113	2		T114	4
valid_sources[0x18]	6825	1			T1	13		T103	1		T165	5
valid_sources[0x19]	23192	1			T1	9		T108	13		T166	1
valid_sources[0x1a]	14938	1			T1	9		T10	3		T103	4
valid_sources[0x1b]	7546	1			T1	15		T166	1		T113	5
valid_sources[0x1c]	8012	1			T1	10		T103	7		T165	1
valid_sources[0x1d]	6611	1			T1	14		T10	2		T103	3
valid_sources[0x1e]	7377	1			T1	13		T103	7		T165	1
valid_sources[0x1f]	7305	1			T1	11		T166	1		T113	7
valid_sources[0x20]	6356	1			T1	6		T103	1		T108	1
valid_sources[0x21]	7095	1			T1	11		T103	1		T166	1
valid_sources[0x22]	7430	1			T1	22		T103	5		T166	1
valid_sources[0x23]	7618	1			T1	7		T113	5		T140	3
valid_sources[0x24]	6822	1			T1	15		T105	1		T113	1
valid_sources[0x25]	6532	1			T1	4		T166	3		T113	2
valid_sources[0x26]	8267	1			T1	6		T2	1038		T103	2
valid_sources[0x27]	10781	1			T1	13		T106	9		T113	1
valid_sources[0x28]	6844	1			T1	5		T166	1		T113	7
valid_sources[0x29]	10968	1			T1	5		T113	4		T140	1
valid_sources[0x2a]	8864	1			T1	8		T113	4		T114	8
valid_sources[0x2b]	9455	1			T1	12		T103	2		T108	9
valid_sources[0x2c]	10883	1			T1	6		T103	6		T113	1
valid_sources[0x2d]	9455	1			T1	3		T166	1		T140	2
valid_sources[0x2e]	8353	1			T1	18		T113	1		T114	4
valid_sources[0x2f]	8385	1			T1	4		T166	1		T113	5
valid_sources[0x30]	6725	1			T1	8		T103	2		T113	1
valid_sources[0x31]	7050	1			T1	14		T166	2		T140	2
valid_sources[0x32]	7374	1			T1	10		T113	3		T140	6
valid_sources[0x33]	7286	1			T1	7		T113	3		T140	5
valid_sources[0x34]	6779	1			T1	14		T113	3		T140	1
valid_sources[0x35]	6849	1			T1	9		T165	1		T166	2
valid_sources[0x36]	6777	1			T1	10		T103	3		T106	2
valid_sources[0x37]	7161	1			T1	14		T103	6		T140	1
valid_sources[0x38]	7340	1			T1	8		T166	3		T113	3
valid_sources[0x39]	10735	1			T1	7		T103	1		T105	2
valid_sources[0x3a]	6821	1			T1	8		T103	4		T106	4
valid_sources[0x3b]	7137	1			T1	18		T103	2		T166	2
valid_sources[0x3c]	9947	1			T1	9		T166	2		T113	3
valid_sources[0x3d]	6954	1			T1	6		T103	5		T113	1
valid_sources[0x3e]	8202	1			T1	11		T113	1		T140	3
valid_sources[0x3f]	8020	1			T1	2		T166	1		T113	2
valid_sources[0x40]	6858	1			T1	16		T10	1		T103	3
valid_sources[0x41]	6564	1			T1	10		T10	3		T103	6
valid_sources[0x42]	7256	1			T1	17		T113	1		T140	7
valid_sources[0x43]	6992	1			T1	22		T103	8		T105	1
valid_sources[0x44]	9060	1			T1	12		T10	1		T166	4
valid_sources[0x45]	9019	1			T1	10		T108	11		T113	6
valid_sources[0x46]	7592	1			T1	12		T113	4		T140	2
valid_sources[0x47]	7223	1			T1	9		T103	1		T108	3
valid_sources[0x48]	11420	1			T1	10		T166	1		T114	3
valid_sources[0x49]	11405	1			T1	19		T103	1		T113	4
valid_sources[0x4a]	7117	1			T1	5		T105	1		T114	1
valid_sources[0x4b]	7388	1			T1	13		T10	2		T105	1
valid_sources[0x4c]	7591	1			T1	12		T114	11		T187	1
valid_sources[0x4d]	7149	1			T1	14		T105	1		T108	14
valid_sources[0x4e]	40894	1			T1	16		T105	2		T166	2
valid_sources[0x4f]	7494	1			T1	10		T172	1		T182	4
valid_sources[0x50]	7176	1			T1	12		T108	8		T165	1
valid_sources[0x51]	7344	1			T1	10		T113	1		T114	5
valid_sources[0x52]	7007	1			T1	7		T103	1		T105	2
valid_sources[0x53]	6896	1			T1	5		T113	3		T140	1
valid_sources[0x54]	7400	1			T1	13		T166	2		T113	1
valid_sources[0x55]	8541	1			T1	2		T103	1		T166	2
valid_sources[0x56]	6916	1			T1	12		T113	2		T140	3
valid_sources[0x57]	7511	1			T1	13		T103	2		T108	3
valid_sources[0x58]	6623	1			T1	14		T103	4		T166	2
valid_sources[0x59]	7722	1			T1	16		T103	2		T108	10
valid_sources[0x5a]	13438	1			T1	9		T106	7		T166	2
valid_sources[0x5b]	7272	1			T1	8		T113	8		T187	2
valid_sources[0x5c]	7322	1			T1	6		T166	1		T113	1
valid_sources[0x5d]	7053	1			T1	17		T166	2		T113	9
valid_sources[0x5e]	6918	1			T1	9		T165	11		T113	3
valid_sources[0x5f]	6998	1			T1	9		T106	7		T113	6
valid_sources[0x60]	9545	1			T1	9		T113	4		T173	10
valid_sources[0x61]	7771	1			T1	11		T113	1		T173	1
valid_sources[0x62]	6893	1			T1	8		T103	3		T166	1
valid_sources[0x63]	7380	1			T1	10		T103	1		T106	7
valid_sources[0x64]	7919	1			T1	12		T166	1		T113	3
valid_sources[0x65]	9495	1			T1	9		T10	1		T103	5
valid_sources[0x66]	7236	1			T1	8		T10	5		T103	4
valid_sources[0x67]	8129	1			T1	9		T10	4		T103	1
valid_sources[0x68]	7158	1			T1	11		T113	3		T140	4
valid_sources[0x69]	6891	1			T1	12		T103	1		T113	1
valid_sources[0x6a]	7154	1			T1	10		T108	12		T113	3
valid_sources[0x6b]	6934	1			T1	9		T108	5		T166	2
valid_sources[0x6c]	7124	1			T1	10		T165	1		T113	5
valid_sources[0x6d]	7238	1			T1	10		T166	1		T113	1
valid_sources[0x6e]	6885	1			T1	9		T113	4		T140	4
valid_sources[0x6f]	7272	1			T1	13		T103	2		T166	1
valid_sources[0x70]	12050	1			T1	3		T113	2		T140	2
valid_sources[0x71]	9210	1			T1	25		T10	7		T103	1
valid_sources[0x72]	8654	1			T1	16		T103	1		T166	1
valid_sources[0x73]	7038	1			T1	14		T113	2		T140	2
valid_sources[0x74]	11163	1			T1	8		T166	3		T113	5
valid_sources[0x75]	6898	1			T1	12		T113	5		T140	2
valid_sources[0x76]	6905	1			T1	15		T166	4		T113	2
valid_sources[0x77]	7063	1			T1	14		T103	1		T165	4
valid_sources[0x78]	8339	1			T1	16		T103	1		T166	2
valid_sources[0x79]	7143	1			T1	5		T106	14		T113	1
valid_sources[0x7a]	7753	1			T1	11		T166	1		T113	2
valid_sources[0x7b]	7067	1			T1	17		T103	4		T106	11
valid_sources[0x7c]	8578	1			T1	13		T113	2		T140	1
valid_sources[0x7d]	6589	1			T1	7		T103	4		T113	9
valid_sources[0x7e]	8358	1			T1	18		T103	4		T108	1
valid_sources[0x7f]	7761	1			T1	10		T103	2		T113	4
valid_sources[0x80]	7219	1			T1	3		T166	1		T113	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

908370

1

T1

985

T2

161

T103

79

values[0x0]

all_enables

biggest_size

129882

1

T1

330

T2

282

T10

8

values[0x1]

all_enables

biggest_size

128919

1

T1

302

T2

290

T10

2