Unified Coverage Report :: Module :: lc_ctrl_reg_top

Module : lc_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.54	100.00	98.16			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_tap	99.53	99.56	98.57			100.00	100.00
tb.dut.u_reg	99.54	100.00	98.16			100.00	100.00

---

Module Instance : tb.dut.u_reg_tap

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.53	99.56	98.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.09	95.78	98.26	50.24		91.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.75	100.00	83.10	98.16		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	82.14	100.00		46.43			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	66.67	66.67
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	88.34	84.29	96.36			72.73	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.54	100.00	98.16			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.21	97.79	98.28	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.75	100.00	83.10	98.16		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	66.67	66.67
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00

Line Coverage for Module : lc_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	595	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
ALWAYS	1143	36	36	100.00
CONT_ASSIGN	1181	1	1	100.00
ALWAYS	1185	1	1	100.00
CONT_ASSIGN	1224	1	1	100.00
CONT_ASSIGN	1226	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1230	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1234	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1260	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
ALWAYS	1298	36	36	100.00
ALWAYS	1338	53	53	100.00
CONT_ASSIGN	1507	0	0
CONT_ASSIGN	1515	1	1	100.00
CONT_ASSIGN	1516	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
236	1	1
251	1	1
267	1	1
283	1	1
499	1	1
502	1	1
516	1	1
538	1	1
541	1	1
555	1	1
561	1	1
564	1	1
579	1	1
595	1	1
602	1	1
605	1	1
619	1	1
626	1	1
629	1	1
643	1	1
650	1	1
653	1	1
667	1	1
674	1	1
677	1	1
691	1	1
697	1	1
700	1	1
714	1	1
720	1	1
723	1	1
737	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1151	1	1
1152	1	1
1153	1	1
1154	1	1
1155	1	1
1156	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
1170	1	1
1171	1	1
1172	1	1
1173	1	1
1174	1	1
1175	1	1
1176	1	1
1177	1	1
1178	1	1
1181	1	1
1185	1	1
1224	1	1
1226	1	1
1228	1	1
1230	1	1
1231	1	1
1232	1	1
1234	1	1
1235	1	1
1236	1	1
1238	1	1
1239	1	1
1240	1	1
1242	1	1
1243	1	1
1244	1	1
1246	1	1
1248	1	1
1249	1	1
1250	1	1
1252	1	1
1253	1	1
1254	1	1
1256	1	1
1257	1	1
1258	1	1
1260	1	1
1261	1	1
1262	1	1
1264	1	1
1265	1	1
1266	1	1
1268	1	1
1269	1	1
1270	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1277	1	1
1278	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1285	1	1
1286	1	1
1287	1	1
1288	1	1
1289	1	1
1290	1	1
1291	1	1
1292	1	1
1293	1	1
1294	1	1
1298	1	1
1299	1	1
1300	1	1
1301	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1338	1	1
1339	1	1
1341	1	1
1342	1	1
1343	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1362	1	1
1366	1	1
1370	1	1
1374	1	1
1378	1	1
1379	1	1
1383	1	1
1387	1	1
1391	1	1
1395	1	1
1399	1	1
1403	1	1
1407	1	1
1411	1	1
1415	1	1
1419	1	1
1423	1	1
1424	1	1
1428	1	1
1429	1	1
1433	1	1
1437	1	1
1441	1	1
1445	1	1
1449	1	1
1453	1	1
1457	1	1
1461	1	1
1465	1	1
1469	1	1
1473	1	1
1477	1	1
1481	1	1
1485	1	1
1489	1	1
1493	1	1
1507		unreachable
1515	1	1
1516	1	1

---

Cond Coverage for Module : lc_ctrl_reg_top

	Total	Covered	Percent
Conditions	434	426	98.16
Logical	434	426	98.16
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
61-1292	98.12
1293-1294	100.00

---

Branch Coverage for Module : lc_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1181	2	2	100.00
IF	71	3	3	100.00
CASE	1339	36	36	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1181	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T113,T114,T138
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1339	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	135809138	2377822	0	0
reAfterRv	135809138	2377821	0	0
rePulse	135809138	1994145	0	0
wePulse	135809138	383676	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	135809138	2377822	0	0
T1	50673	2713	0	0
T2	28844	1038	0	0
T3	199884	776	0	0
T10	4904	51	0	0
T103	10473	28	0	0
T104	6601	45	0	0
T105	2919	16	0	0
T106	1202	74	0	0
T107	5085	36	0	0
T108	2205	184	0	0
T113	11428	722	0	0
T136	5201	18	0	0
T140	0	408	0	0
T165	1358	73	0	0
T166	2068	170	0	0
T167	5107	38	0	0
T168	12335	90	0	0
T169	3411	36	0	0
T170	0	36	0	0
T171	0	22	0	0
T172	9309	0	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	135809138	2377821	0	0
T1	50673	2713	0	0
T2	28844	1038	0	0
T3	199884	776	0	0
T10	4904	51	0	0
T103	10473	28	0	0
T104	6601	45	0	0
T105	2919	16	0	0
T106	1202	74	0	0
T107	5085	36	0	0
T108	2205	184	0	0
T113	11428	722	0	0
T136	5201	18	0	0
T140	0	408	0	0
T165	1358	73	0	0
T166	2068	170	0	0
T167	5107	38	0	0
T168	12335	90	0	0
T169	3411	36	0	0
T170	0	36	0	0
T171	0	22	0	0
T172	9309	0	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	135809138	1994145	0	0
T1	50673	1985	0	0
T2	28844	382	0	0
T3	199884	424	0	0
T10	4904	0	0	0
T103	10473	9	0	0
T104	6601	12	0	0
T105	2919	12	0	0
T106	1202	8	0	0
T107	5085	3	0	0
T108	2205	18	0	0
T113	11428	76	0	0
T136	5201	12	0	0
T140	0	40	0	0
T165	1358	7	0	0
T166	2068	15	0	0
T168	12335	24	0	0
T169	3411	3	0	0
T170	0	3	0	0
T172	9309	0	0	0
T173	0	50	0	0
T174	0	132	0	0
T175	0	192	0	0
T176	955	0	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	135809138	383676	0	0
T1	50673	728	0	0
T2	28844	656	0	0
T3	199884	352	0	0
T10	4904	51	0	0
T103	10473	19	0	0
T104	6601	33	0	0
T105	2919	4	0	0
T106	1202	66	0	0
T107	5085	33	0	0
T108	2205	166	0	0
T113	11428	646	0	0
T136	5201	6	0	0
T140	0	368	0	0
T165	1358	66	0	0
T166	2068	155	0	0
T167	5107	38	0	0
T168	12335	66	0	0
T169	3411	33	0	0
T170	0	33	0	0
T171	0	22	0	0
T172	9309	0	0	0

Line Coverage for Instance : tb.dut.u_reg_tap

	Line No.	Total	Covered	Percent
TOTAL		227	226	99.56
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	595	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
ALWAYS	1143	36	36	100.00
CONT_ASSIGN	1181	1	1	100.00
ALWAYS	1185	1	1	100.00
CONT_ASSIGN	1224	1	1	100.00
CONT_ASSIGN	1226	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1230	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1234	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1260	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
ALWAYS	1298	36	36	100.00
ALWAYS	1338	53	53	100.00
CONT_ASSIGN	1507	0	0
CONT_ASSIGN	1515	1	1	100.00
CONT_ASSIGN	1516	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	0	1
236	1	1
251	1	1
267	1	1
283	1	1
499	1	1
502	1	1
516	1	1
538	1	1
541	1	1
555	1	1
561	1	1
564	1	1
579	1	1
595	1	1
602	1	1
605	1	1
619	1	1
626	1	1
629	1	1
643	1	1
650	1	1
653	1	1
667	1	1
674	1	1
677	1	1
691	1	1
697	1	1
700	1	1
714	1	1
720	1	1
723	1	1
737	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1151	1	1
1152	1	1
1153	1	1
1154	1	1
1155	1	1
1156	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
1170	1	1
1171	1	1
1172	1	1
1173	1	1
1174	1	1
1175	1	1
1176	1	1
1177	1	1
1178	1	1
1181	1	1
1185	1	1
1224	1	1
1226	1	1
1228	1	1
1230	1	1
1231	1	1
1232	1	1
1234	1	1
1235	1	1
1236	1	1
1238	1	1
1239	1	1
1240	1	1
1242	1	1
1243	1	1
1244	1	1
1246	1	1
1248	1	1
1249	1	1
1250	1	1
1252	1	1
1253	1	1
1254	1	1
1256	1	1
1257	1	1
1258	1	1
1260	1	1
1261	1	1
1262	1	1
1264	1	1
1265	1	1
1266	1	1
1268	1	1
1269	1	1
1270	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1277	1	1
1278	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1285	1	1
1286	1	1
1287	1	1
1288	1	1
1289	1	1
1290	1	1
1291	1	1
1292	1	1
1293	1	1
1294	1	1
1298	1	1
1299	1	1
1300	1	1
1301	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1338	1	1
1339	1	1
1341	1	1
1342	1	1
1343	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1362	1	1
1366	1	1
1370	1	1
1374	1	1
1378	1	1
1379	1	1
1383	1	1
1387	1	1
1391	1	1
1395	1	1
1399	1	1
1403	1	1
1407	1	1
1411	1	1
1415	1	1
1419	1	1
1423	1	1
1424	1	1
1428	1	1
1429	1	1
1433	1	1
1437	1	1
1441	1	1
1445	1	1
1449	1	1
1453	1	1
1457	1	1
1461	1	1
1465	1	1
1469	1	1
1473	1	1
1477	1	1
1481	1	1
1485	1	1
1489	1	1
1493	1	1
1507		unreachable
1515	1	1
1516	1	1

---

Cond Coverage for Instance : tb.dut.u_reg_tap

	Total	Covered	Percent
Conditions	280	276	98.57
Logical	280	276	98.57
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T104,T105

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T110,T63,T64
1	0	Excluded		VC_COV_UNR

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T110,T63,T64
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T110,T63,T64

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Excluded		VC_COV_UNR
1	0	0	Not Covered

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       502
 EXPRESSION (claim_transition_if_we & claim_transition_if_regwen_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T177,T178
1	1	Covered	T3,T104,T107

 LINE       541
 EXPRESSION (transition_cmd_we & transition_regwen_qs)
             --------1--------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T3,T4,T18
1	1	Covered	T4,T17,T20

 LINE       564
 EXPRESSION (transition_ctrl_we & transition_regwen_qs)
             ---------1--------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T20,T21
1	1	Covered	T4,T5,T20

 LINE       605
 EXPRESSION (transition_token_0_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T3,T104,T107
1	1	Covered	T4,T5,T17

 LINE       629
 EXPRESSION (transition_token_1_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T3,T104,T107
1	1	Covered	T4,T5,T17

 LINE       653
 EXPRESSION (transition_token_2_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T3,T104,T107
1	1	Covered	T4,T5,T17

 LINE       677
 EXPRESSION (transition_token_3_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T3,T104,T105
1	1	Covered	T4,T5,T17

 LINE       700
 EXPRESSION (transition_target_we & transition_regwen_qs)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T3,T104,T107
1	1	Covered	T4,T5,T17

 LINE       723
 EXPRESSION (otp_vendor_test_ctrl_we & transition_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T3,T104,T107
1	1	Covered	T4,T5,T17

 LINE       1144
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_ALERT_TEST_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T104,T105,T107

 LINE       1145
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_STATUS_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1146
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_CLAIM_TRANSITION_IF_REGWEN_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T104,T105,T107

 LINE       1147
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_CLAIM_TRANSITION_IF_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1148
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T104,T105,T107

 LINE       1149
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_CMD_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1150
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_CTRL_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T4,T5,T20

 LINE       1151
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1152
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1153
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1154
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1155
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TARGET_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1156
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_OTP_VENDOR_TEST_CTRL_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1157
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_OTP_VENDOR_TEST_STATUS_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1158
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1159
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_TRANSITION_CNT_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1160
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_ID_STATE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T104,T105,T107

 LINE       1161
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_HW_REVISION0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1162
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_HW_REVISION1_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1163
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_0_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1164
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_1_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1165
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_2_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1166
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_3_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1167
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_4_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1168
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_5_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1169
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_6_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1170
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_7_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1171
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_0_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1172
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_1_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1173
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_2_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1174
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_3_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1175
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_4_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1176
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_5_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T105

 LINE       1177
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_6_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1178
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_7_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T3,T104,T105
1	Covered	T3,T104,T107

 LINE       1181
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T104,T105

 LINE       1181
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T104,T105
1	0	Covered	T3,T104,T105

 LINE       1185
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests	Exclude Annotation
ALL ZEROS	Covered	T3,T104,T105
35 (addr_hit[34] & ((|(4'...	Excluded		VC_COV_UNR
34 (addr_hit[33] & ((|(4'...	Excluded		VC_COV_UNR
33 (addr_hit[32] & ((|(4'...	Excluded		VC_COV_UNR
32 (addr_hit[31] & ((|(4'...	Excluded		VC_COV_UNR
31 (addr_hit[30] & ((|(4'...	Excluded		VC_COV_UNR
30 (addr_hit[29] & ((|(4'...	Excluded		VC_COV_UNR
29 (addr_hit[28] & ((|(4'...	Excluded		VC_COV_UNR
28 (addr_hit[27] & ((|(4'...	Excluded		VC_COV_UNR
27 (addr_hit[26] & ((|(4'...	Excluded		VC_COV_UNR
26 (addr_hit[25] & ((|(4'...	Excluded		VC_COV_UNR
25 (addr_hit[24] & ((|(4'...	Excluded		VC_COV_UNR
24 (addr_hit[23] & ((|(4'...	Excluded		VC_COV_UNR
23 (addr_hit[22] & ((|(4'...	Excluded		VC_COV_UNR
22 (addr_hit[21] & ((|(4'...	Excluded		VC_COV_UNR
21 (addr_hit[20] & ((|(4'...	Excluded		VC_COV_UNR
20 (addr_hit[19] & ((|(4'...	Excluded		VC_COV_UNR
19 (addr_hit[18] & ((|(4'...	Excluded		VC_COV_UNR
18 (addr_hit[17] & ((|(4'...	Excluded		VC_COV_UNR
17 (addr_hit[16] & ((|(4'...	Excluded		VC_COV_UNR
16 (addr_hit[15] & ((|(4'...	Excluded		VC_COV_UNR
15 (addr_hit[14] & ((|(4'...	Excluded		VC_COV_UNR
14 (addr_hit[13] & ((|(4'...	Excluded		VC_COV_UNR
13 (addr_hit[12] & ((|(4'...	Excluded		VC_COV_UNR
12 (addr_hit[11] & ((|(4'...	Excluded		VC_COV_UNR
11 (addr_hit[10] & ((|(4'...	Excluded		VC_COV_UNR
10 (addr_hit[9] & ((|(4'b...	Excluded		VC_COV_UNR
9 (addr_hit[8] & ((|(4'b...	Excluded		VC_COV_UNR
8 (addr_hit[7] & ((|(4'b...	Excluded		VC_COV_UNR
7 (addr_hit[6] & ((|(4'b...	Excluded		VC_COV_UNR
6 (addr_hit[5] & ((|(4'b...	Excluded		VC_COV_UNR
5 (addr_hit[4] & ((|(4'b...	Excluded		VC_COV_UNR
4 (addr_hit[3] & ((|(4'b...	Excluded		VC_COV_UNR
3 (addr_hit[2] & ((|(4'b...	Excluded		VC_COV_UNR
2 (addr_hit[1] & ((|(4'b...	Excluded		VC_COV_UNR
1 (addr_hit[0] & ((|(4'b...	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T104,T105,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T104,T105,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T104,T105,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T20
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T104,T105,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T105
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1185
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T3,T104,T107
1	1	Excluded		VC_COV_UNR

 LINE       1224
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T104,T105,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T107,T167

 LINE       1231
 EXPRESSION (addr_hit[1] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1232
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T104,T105,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T107,T168

 LINE       1235
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T105

 LINE       1236
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T107

 LINE       1239
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T104,T105,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T105,T136

 LINE       1240
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1243
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T4,T5,T20
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T20

 LINE       1244
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T4,T5,T20
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T20

 LINE       1249
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T105,T136

 LINE       1250
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T107

 LINE       1253
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T105,T136

 LINE       1254
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T107

 LINE       1257
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T105,T136

 LINE       1258
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T107

 LINE       1261
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T105,T136

 LINE       1262
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T105

 LINE       1265
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T105,T107

 LINE       1266
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T107

 LINE       1269
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T104,T105,T136

 LINE       1270
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T107

 LINE       1273
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T104,T105

 LINE       1274
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1275
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1276
 EXPRESSION (addr_hit[16] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T104,T105,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Not Covered

 LINE       1277
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1278
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1279
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1280
 EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1281
 EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1282
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1283
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1284
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1285
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1286
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1287
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1288
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1289
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1290
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1291
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1292
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T105
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

 LINE       1294
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T104,T105
1	0	1	Covered	T3,T104,T107
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T3,T4,T17

---

Branch Coverage for Instance : tb.dut.u_reg_tap

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1181	2	2	100.00
IF	71	3	3	100.00
CASE	1339	36	36	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1181	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T104,T105
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T110,T63,T64
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1339	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_tap

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	67904569	246963	0	0
reAfterRv	67904569	246963	0	0
rePulse	67904569	156974	0	0
wePulse	67904569	89989	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	246963	0	0
T3	99942	776	0	0
T10	2452	0	0	0
T104	6601	45	0	0
T105	2919	16	0	0
T107	5085	36	0	0
T136	5201	18	0	0
T167	5107	38	0	0
T168	12335	90	0	0
T169	3411	36	0	0
T170	0	36	0	0
T171	0	22	0	0
T172	9309	0	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	246963	0	0
T3	99942	776	0	0
T10	2452	0	0	0
T104	6601	45	0	0
T105	2919	16	0	0
T107	5085	36	0	0
T136	5201	18	0	0
T167	5107	38	0	0
T168	12335	90	0	0
T169	3411	36	0	0
T170	0	36	0	0
T171	0	22	0	0
T172	9309	0	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	156974	0	0
T3	99942	424	0	0
T10	2452	0	0	0
T104	6601	12	0	0
T105	2919	12	0	0
T107	5085	3	0	0
T136	5201	12	0	0
T168	12335	24	0	0
T169	3411	3	0	0
T170	0	3	0	0
T172	9309	0	0	0
T174	0	132	0	0
T175	0	192	0	0
T176	955	0	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	89989	0	0
T3	99942	352	0	0
T10	2452	0	0	0
T104	6601	33	0	0
T105	2919	4	0	0
T107	5085	33	0	0
T136	5201	6	0	0
T167	5107	38	0	0
T168	12335	66	0	0
T169	3411	33	0	0
T170	0	33	0	0
T171	0	22	0	0
T172	9309	0	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	595	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
ALWAYS	1143	36	36	100.00
CONT_ASSIGN	1181	1	1	100.00
ALWAYS	1185	1	1	100.00
CONT_ASSIGN	1224	1	1	100.00
CONT_ASSIGN	1226	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1230	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1234	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1260	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
ALWAYS	1298	36	36	100.00
ALWAYS	1338	53	53	100.00
CONT_ASSIGN	1507	0	0
CONT_ASSIGN	1515	1	1	100.00
CONT_ASSIGN	1516	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
236	1	1
251	1	1
267	1	1
283	1	1
499	1	1
502	1	1
516	1	1
538	1	1
541	1	1
555	1	1
561	1	1
564	1	1
579	1	1
595	1	1
602	1	1
605	1	1
619	1	1
626	1	1
629	1	1
643	1	1
650	1	1
653	1	1
667	1	1
674	1	1
677	1	1
691	1	1
697	1	1
700	1	1
714	1	1
720	1	1
723	1	1
737	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1151	1	1
1152	1	1
1153	1	1
1154	1	1
1155	1	1
1156	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
1170	1	1
1171	1	1
1172	1	1
1173	1	1
1174	1	1
1175	1	1
1176	1	1
1177	1	1
1178	1	1
1181	1	1
1185	1	1
1224	1	1
1226	1	1
1228	1	1
1230	1	1
1231	1	1
1232	1	1
1234	1	1
1235	1	1
1236	1	1
1238	1	1
1239	1	1
1240	1	1
1242	1	1
1243	1	1
1244	1	1
1246	1	1
1248	1	1
1249	1	1
1250	1	1
1252	1	1
1253	1	1
1254	1	1
1256	1	1
1257	1	1
1258	1	1
1260	1	1
1261	1	1
1262	1	1
1264	1	1
1265	1	1
1266	1	1
1268	1	1
1269	1	1
1270	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1277	1	1
1278	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1285	1	1
1286	1	1
1287	1	1
1288	1	1
1289	1	1
1290	1	1
1291	1	1
1292	1	1
1293	1	1
1294	1	1
1298	1	1
1299	1	1
1300	1	1
1301	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1338	1	1
1339	1	1
1341	1	1
1342	1	1
1343	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1362	1	1
1366	1	1
1370	1	1
1374	1	1
1378	1	1
1379	1	1
1383	1	1
1387	1	1
1391	1	1
1395	1	1
1399	1	1
1403	1	1
1407	1	1
1411	1	1
1415	1	1
1419	1	1
1423	1	1
1424	1	1
1428	1	1
1429	1	1
1433	1	1
1437	1	1
1441	1	1
1445	1	1
1449	1	1
1453	1	1
1457	1	1
1461	1	1
1465	1	1
1469	1	1
1473	1	1
1477	1	1
1481	1	1
1485	1	1
1489	1	1
1493	1	1
1507		unreachable
1515	1	1
1516	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	434	426	98.16
Logical	434	426	98.16
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
61-1293	98.14
1294	100.00

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1181	2	2	100.00
IF	71	3	3	100.00
CASE	1339	36	36	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1181	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T113,T114,T138
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1339	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T10
addr_hit[2]	Covered	T1,T2,T10
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T10
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T10
addr_hit[8]	Covered	T1,T2,T10
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T10
addr_hit[13]	Covered	T1,T2,T10
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T10
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T10
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T10
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T10
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T10
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	67904569	2130859	0	0
reAfterRv	67904569	2130858	0	0
rePulse	67904569	1837171	0	0
wePulse	67904569	293687	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	2130859	0	0
T1	50673	2713	0	0
T2	28844	1038	0	0
T3	99942	0	0	0
T10	2452	51	0	0
T103	10473	28	0	0
T106	1202	74	0	0
T108	2205	184	0	0
T113	11428	722	0	0
T140	0	408	0	0
T165	1358	73	0	0
T166	2068	170	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	2130858	0	0
T1	50673	2713	0	0
T2	28844	1038	0	0
T3	99942	0	0	0
T10	2452	51	0	0
T103	10473	28	0	0
T106	1202	74	0	0
T108	2205	184	0	0
T113	11428	722	0	0
T140	0	408	0	0
T165	1358	73	0	0
T166	2068	170	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	1837171	0	0
T1	50673	1985	0	0
T2	28844	382	0	0
T3	99942	0	0	0
T10	2452	0	0	0
T103	10473	9	0	0
T106	1202	8	0	0
T108	2205	18	0	0
T113	11428	76	0	0
T140	0	40	0	0
T165	1358	7	0	0
T166	2068	15	0	0
T173	0	50	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	293687	0	0
T1	50673	728	0	0
T2	28844	656	0	0
T3	99942	0	0	0
T10	2452	51	0	0
T103	10473	19	0	0
T106	1202	66	0	0
T108	2205	166	0	0
T113	11428	646	0	0
T140	0	368	0	0
T165	1358	66	0	0
T166	2068	155	0	0