Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.75	100.00	83.10	98.16		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	67904569	14113	0	0
claim_transition_if_regwen_rd_A	67904569	1582	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	14113	0	0
T103	10473	765	0	0
T105	2919	14	0	0
T113	11428	8	0	0
T114	9618	12	0	0
T136	5201	42	0	0
T138	5473	2	0	0
T139	0	138	0	0
T168	12335	0	0	0
T169	3411	0	0	0
T172	9309	0	0	0
T176	955	4	0	0
T179	0	36	0	0
T180	0	31	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67904569	1582	0	0
T103	10473	11	0	0
T108	2205	1	0	0
T113	11428	72	0	0
T139	1405	0	0	0
T142	0	18	0	0
T170	4144	0	0	0
T172	9309	440	0	0
T176	955	0	0	0
T179	1586	0	0	0
T180	0	2	0	0
T181	2749	22	0	0
T182	1283	3	0	0
T183	0	8	0	0
T184	0	11	0	0