Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	881116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1071497

1

T1

1015

T2

28337

T90

624

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1663692	1			T1	880		T2	51230		T90	81
values[0x0]	144301	1			T1	366		T2	1882		T90	329
values[0x1]	144620	1			T1	314		T2	1911		T90	341

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	698493	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1254120

1

T1

1136

T2

33841

T90

649

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6198	1			T90	3		T92	3		T111	2
valid_sources[0x01]	6137	1			T90	3		T93	4		T151	4
valid_sources[0x02]	6396	1			T111	1		T114	2		T115	3
valid_sources[0x03]	6225	1			T90	5		T111	1		T119	9
valid_sources[0x04]	6359	1			T90	12		T92	10		T93	1
valid_sources[0x05]	7918	1			T90	8		T139	2		T112	1
valid_sources[0x06]	8862	1			T90	2		T92	7		T93	1
valid_sources[0x07]	6634	1			T91	8		T92	2		T93	1
valid_sources[0x08]	6238	1			T90	2		T92	2		T93	1
valid_sources[0x09]	6841	1			T90	1		T92	3		T93	3
valid_sources[0x0a]	8102	1			T93	1		T111	1		T139	1
valid_sources[0x0b]	7462	1			T90	3		T92	1		T111	3
valid_sources[0x0c]	6861	1			T90	2		T93	3		T111	7
valid_sources[0x0d]	6267	1			T90	9		T92	1		T139	1
valid_sources[0x0e]	6630	1			T90	4		T93	1		T111	3
valid_sources[0x0f]	7362	1			T92	5		T93	3		T112	1
valid_sources[0x10]	6157	1			T90	3		T118	1		T117	2
valid_sources[0x11]	9469	1			T90	7		T94	19		T111	5
valid_sources[0x12]	6236	1			T90	2		T91	5		T112	3
valid_sources[0x13]	7640	1			T90	1		T91	2		T93	3
valid_sources[0x14]	7965	1			T90	3		T111	1		T117	5
valid_sources[0x15]	6110	1			T90	3		T91	1		T92	1
valid_sources[0x16]	6044	1			T93	1		T111	2		T112	2
valid_sources[0x17]	5888	1			T90	1		T112	1		T114	6
valid_sources[0x18]	32124	1			T90	3		T111	2		T117	1
valid_sources[0x19]	7917	1			T90	2		T92	10		T93	1
valid_sources[0x1a]	6173	1			T90	8		T93	2		T111	1
valid_sources[0x1b]	7815	1			T90	1		T92	5		T93	1
valid_sources[0x1c]	12820	1			T90	1		T93	2		T114	1
valid_sources[0x1d]	16858	1			T90	3		T93	3		T112	2
valid_sources[0x1e]	6684	1			T90	4		T92	5		T111	3
valid_sources[0x1f]	6312	1			T90	2		T92	4		T93	1
valid_sources[0x20]	5901	1			T90	2		T93	2		T139	1
valid_sources[0x21]	6324	1			T90	1		T93	2		T119	23
valid_sources[0x22]	7688	1			T90	4		T92	10		T111	3
valid_sources[0x23]	6290	1			T90	5		T111	2		T112	1
valid_sources[0x24]	6220	1			T90	2		T93	1		T111	2
valid_sources[0x25]	6493	1			T90	2		T93	2		T111	2
valid_sources[0x26]	6429	1			T90	3		T111	1		T112	1
valid_sources[0x27]	6680	1			T90	2		T111	7		T114	4
valid_sources[0x28]	6500	1			T90	3		T91	2		T139	1
valid_sources[0x29]	29043	1			T2	22366		T90	7		T92	2
valid_sources[0x2a]	6048	1			T90	1		T114	2		T144	1
valid_sources[0x2b]	7237	1			T90	2		T92	5		T111	1
valid_sources[0x2c]	6332	1			T90	5		T111	2		T112	5
valid_sources[0x2d]	8079	1			T90	5		T111	2		T112	1
valid_sources[0x2e]	8500	1			T90	1		T92	9		T93	2
valid_sources[0x2f]	6607	1			T90	8		T93	2		T111	6
valid_sources[0x30]	7053	1			T93	1		T111	3		T114	3
valid_sources[0x31]	7589	1			T111	6		T139	2		T114	3
valid_sources[0x32]	6559	1			T90	3		T93	1		T112	1
valid_sources[0x33]	7411	1			T90	6		T93	1		T111	3
valid_sources[0x34]	6396	1			T90	13		T91	3		T93	6
valid_sources[0x35]	6293	1			T92	1		T112	2		T114	6
valid_sources[0x36]	6645	1			T90	1		T92	3		T111	2
valid_sources[0x37]	6190	1			T90	5		T93	5		T111	1
valid_sources[0x38]	7738	1			T90	5		T91	2		T139	3
valid_sources[0x39]	39212	1			T2	32281		T90	5		T93	2
valid_sources[0x3a]	6066	1			T90	8		T93	2		T112	1
valid_sources[0x3b]	5845	1			T90	8		T93	2		T112	2
valid_sources[0x3c]	6185	1			T2	17		T90	4		T93	4
valid_sources[0x3d]	7938	1			T90	6		T93	4		T111	5
valid_sources[0x3e]	7615	1			T90	1		T93	3		T112	1
valid_sources[0x3f]	6027	1			T111	2		T112	1		T114	7
valid_sources[0x40]	5676	1			T111	1		T117	1		T114	6
valid_sources[0x41]	7793	1			T90	4		T139	2		T114	2
valid_sources[0x42]	7293	1			T90	2		T93	3		T111	1
valid_sources[0x43]	6228	1			T90	3		T92	4		T93	3
valid_sources[0x44]	6270	1			T90	2		T93	4		T111	2
valid_sources[0x45]	6314	1			T92	3		T93	2		T111	1
valid_sources[0x46]	6508	1			T2	17		T90	3		T93	5
valid_sources[0x47]	6213	1			T90	2		T112	1		T117	1
valid_sources[0x48]	9568	1			T2	17		T90	1		T93	6
valid_sources[0x49]	7393	1			T90	3		T93	3		T111	2
valid_sources[0x4a]	5974	1			T90	2		T91	4		T111	4
valid_sources[0x4b]	6270	1			T90	10		T111	4		T139	1
valid_sources[0x4c]	6396	1			T90	5		T93	4		T112	4
valid_sources[0x4d]	6227	1			T90	4		T93	1		T111	7
valid_sources[0x4e]	8317	1			T90	1		T93	3		T111	1
valid_sources[0x4f]	6967	1			T90	11		T111	3		T114	4
valid_sources[0x50]	6781	1			T90	4		T92	5		T111	3
valid_sources[0x51]	6287	1			T90	3		T91	3		T92	3
valid_sources[0x52]	7642	1			T90	13		T139	1		T114	3
valid_sources[0x53]	6507	1			T90	5		T93	1		T111	3
valid_sources[0x54]	7379	1			T92	3		T111	1		T112	2
valid_sources[0x55]	6276	1			T90	6		T118	9		T117	2
valid_sources[0x56]	6665	1			T90	3		T111	1		T114	3
valid_sources[0x57]	6208	1			T90	2		T92	1		T93	2
valid_sources[0x58]	6067	1			T112	1		T117	4		T114	3
valid_sources[0x59]	6299	1			T90	1		T93	2		T118	4
valid_sources[0x5a]	14700	1			T90	4		T92	2		T139	3
valid_sources[0x5b]	6092	1			T90	8		T93	1		T111	4
valid_sources[0x5c]	17521	1			T115	3		T187	1		T188	1
valid_sources[0x5d]	7267	1			T90	1		T92	1		T93	1
valid_sources[0x5e]	6600	1			T90	2		T111	2		T112	2
valid_sources[0x5f]	7864	1			T90	7		T111	1		T112	1
valid_sources[0x60]	6453	1			T90	2		T118	6		T114	2
valid_sources[0x61]	6836	1			T90	8		T93	4		T111	2
valid_sources[0x62]	6509	1			T90	1		T93	3		T111	1
valid_sources[0x63]	6369	1			T90	3		T111	4		T114	6
valid_sources[0x64]	6568	1			T92	3		T93	3		T111	7
valid_sources[0x65]	6333	1			T93	9		T111	1		T112	3
valid_sources[0x66]	6373	1			T93	2		T112	2		T114	7
valid_sources[0x67]	6328	1			T2	9		T90	2		T92	4
valid_sources[0x68]	5729	1			T90	4		T93	1		T112	3
valid_sources[0x69]	6137	1			T90	3		T92	2		T93	4
valid_sources[0x6a]	6254	1			T90	6		T93	3		T112	2
valid_sources[0x6b]	9592	1			T111	1		T112	1		T114	3
valid_sources[0x6c]	6723	1			T90	3		T111	3		T114	1
valid_sources[0x6d]	6383	1			T93	1		T111	2		T117	3
valid_sources[0x6e]	6887	1			T90	2		T93	1		T114	4
valid_sources[0x6f]	6471	1			T2	17		T90	1		T92	1
valid_sources[0x70]	7627	1			T90	2		T93	2		T114	3
valid_sources[0x71]	6129	1			T90	2		T111	1		T139	3
valid_sources[0x72]	6020	1			T92	2		T117	1		T114	2
valid_sources[0x73]	6256	1			T2	2		T90	1		T93	1
valid_sources[0x74]	6415	1			T90	8		T93	2		T118	18
valid_sources[0x75]	8907	1			T139	1		T112	1		T117	2
valid_sources[0x76]	6541	1			T93	1		T139	1		T114	3
valid_sources[0x77]	8365	1			T90	6		T93	5		T111	3
valid_sources[0x78]	8915	1			T90	4		T92	4		T93	3
valid_sources[0x79]	6514	1			T90	4		T93	4		T117	3
valid_sources[0x7a]	7583	1			T90	1		T91	6		T93	1
valid_sources[0x7b]	7532	1			T90	4		T111	1		T151	2
valid_sources[0x7c]	6403	1			T90	1		T93	1		T114	4
valid_sources[0x7d]	7574	1			T90	1		T93	1		T111	1
valid_sources[0x7e]	6731	1			T90	3		T93	1		T111	3
valid_sources[0x7f]	6077	1			T91	1		T111	3		T112	2
valid_sources[0x80]	8622	1			T90	2		T91	5		T92	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

823436

1

T1

420

T2

25058

T90

26

values[0x0]

all_enables

biggest_size

124940

1

T1

321

T2

1628

T90

295

values[0x1]

all_enables

biggest_size

123121

1

T1

274

T2

1651

T90

303