Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	70637425	13426	0	0
claim_transition_if_regwen_rd_A	70637425	1371	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70637425	13426	0	0
T2	116338	6	0	0
T90	10028	13	0	0
T91	2007	22	0	0
T93	6267	6	0	0
T112	3170	669	0	0
T114	7337	6	0	0
T115	6263	479	0	0
T116	2053	287	0	0
T127	0	7	0	0
T143	53766	0	0	0
T146	1157	13	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70637425	1371	0	0
T91	2007	18	0	0
T93	6267	31	0	0
T111	4712	35	0	0
T117	2222	74	0	0
T119	1959	6	0	0
T127	5831	47	0	0
T139	1583	7	0	0
T145	15876	0	0	0
T147	2902	6	0	0
T148	0	11	0	0
T149	0	30	0	0
T150	8694	0	0	0