Unified Coverage Report :: Module :: dmi_jtag

Module : dmi_jtag

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.56			95.56

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag	95.56			95.56

---

Module Instance : tb.dut.u_dmi_jtag

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.56			95.56

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.82			95.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_dmi_cdc	96.65			96.65
i_dmi_jtag_tap	83.87			83.87

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : dmi_jtag

	Total	Covered	Percent
Totals	20	17	85.00
Total Bits	180	172	95.56
Total Bits 0->1	90	86	95.56
Total Bits 1->0	90	86	95.56

Ports	20	17	85.00
Port Bits	180	172	95.56
Port Bits 0->1	90	86	95.56
Port Bits 1->0	90	86	95.56

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
testmode_i	No	No		No		INPUT
test_rst_ni	Yes	Yes	T3,T6,T7	Yes	T3,T6,T7	INPUT
dmi_rst_no	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
dmi_req_o.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
dmi_req_o.op[1:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
dmi_req_o.addr[5:0]	Yes	Yes	*T3,T5,*T6	Yes	T3,T5,T6	OUTPUT
dmi_req_o.addr[6]	No	No		No		OUTPUT
dmi_req_valid_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
dmi_req_ready_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
dmi_resp_i.resp[1:0]	No	No		No		INPUT
dmi_resp_i.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
dmi_resp_ready_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
dmi_resp_valid_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
tck_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
tms_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
trst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
td_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
td_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
tdo_oe_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT

*Tests covering at least one bit in the range