Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41667 |
1 |
|
|
T1 |
8 |
|
T2 |
57 |
|
T3 |
17 |
auto[1] |
1260 |
1 |
|
|
T2 |
11 |
|
T36 |
8 |
|
T20 |
23 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42198 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
729 |
1 |
|
|
T49 |
16 |
|
T50 |
11 |
|
T51 |
16 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41483 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1444 |
1 |
|
|
T5 |
6 |
|
T13 |
7 |
|
T29 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41450 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1477 |
1 |
|
|
T5 |
9 |
|
T13 |
17 |
|
T28 |
3 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41503 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1424 |
1 |
|
|
T5 |
13 |
|
T13 |
10 |
|
T68 |
9 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
39793 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T10 |
83 |
no_err_inj |
3134 |
1 |
|
|
T3 |
17 |
|
T9 |
2 |
|
T14 |
2 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41628 |
1 |
|
|
T1 |
8 |
|
T2 |
61 |
|
T3 |
17 |
auto[1] |
1299 |
1 |
|
|
T2 |
7 |
|
T36 |
15 |
|
T20 |
20 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42184 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
743 |
1 |
|
|
T49 |
20 |
|
T50 |
9 |
|
T51 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31419 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[1] |
11508 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41478 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1449 |
1 |
|
|
T5 |
7 |
|
T13 |
6 |
|
T28 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41527 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1400 |
1 |
|
|
T5 |
12 |
|
T13 |
14 |
|
T68 |
12 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41505 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1422 |
1 |
|
|
T5 |
11 |
|
T13 |
8 |
|
T29 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41649 |
1 |
|
|
T1 |
8 |
|
T2 |
59 |
|
T3 |
17 |
auto[1] |
1278 |
1 |
|
|
T2 |
9 |
|
T36 |
8 |
|
T20 |
22 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41468 |
1 |
|
|
T2 |
68 |
|
T3 |
17 |
|
T9 |
2 |
auto[1] |
1459 |
1 |
|
|
T1 |
8 |
|
T66 |
18 |
|
T19 |
13 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42195 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
732 |
1 |
|
|
T49 |
15 |
|
T50 |
20 |
|
T51 |
23 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42179 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
748 |
1 |
|
|
T49 |
30 |
|
T50 |
21 |
|
T51 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42209 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
718 |
1 |
|
|
T49 |
19 |
|
T50 |
25 |
|
T51 |
18 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41157 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1770 |
1 |
|
|
T28 |
15 |
|
T29 |
11 |
|
T89 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39124 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
3803 |
1 |
|
|
T10 |
83 |
|
T12 |
77 |
|
T40 |
71 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41479 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1448 |
1 |
|
|
T5 |
6 |
|
T13 |
9 |
|
T28 |
2 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41459 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1468 |
1 |
|
|
T5 |
9 |
|
T13 |
9 |
|
T28 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41462 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
1465 |
1 |
|
|
T5 |
7 |
|
T13 |
6 |
|
T28 |
2 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41622 |
1 |
|
|
T1 |
8 |
|
T2 |
56 |
|
T3 |
17 |
auto[1] |
1305 |
1 |
|
|
T2 |
12 |
|
T36 |
8 |
|
T20 |
21 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37944 |
1 |
|
|
T1 |
8 |
|
T2 |
58 |
|
T3 |
17 |
auto[1] |
4983 |
1 |
|
|
T2 |
10 |
|
T185 |
100 |
|
T36 |
10 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39119 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[1] |
3808 |
1 |
|
|
T42 |
64 |
|
T44 |
87 |
|
T67 |
64 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42927 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41612 |
1 |
|
|
T1 |
8 |
|
T2 |
63 |
|
T3 |
17 |
auto[1] |
1315 |
1 |
|
|
T2 |
5 |
|
T36 |
3 |
|
T20 |
16 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41615 |
1 |
|
|
T1 |
8 |
|
T2 |
62 |
|
T3 |
17 |
auto[1] |
1312 |
1 |
|
|
T2 |
6 |
|
T36 |
10 |
|
T20 |
26 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41623 |
1 |
|
|
T1 |
8 |
|
T2 |
60 |
|
T3 |
17 |
auto[1] |
1304 |
1 |
|
|
T2 |
8 |
|
T36 |
7 |
|
T20 |
22 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
38919 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T10 |
83 |
auto[0] |
no_err_inj |
2238 |
1 |
|
|
T3 |
17 |
|
T9 |
2 |
|
T14 |
2 |
auto[1] |
err_inj |
874 |
1 |
|
|
T28 |
9 |
|
T29 |
7 |
|
T89 |
5 |
auto[1] |
no_err_inj |
896 |
1 |
|
|
T28 |
6 |
|
T29 |
4 |
|
T89 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39803 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[0] |
auto[1] |
1354 |
1 |
|
|
T5 |
9 |
|
T13 |
9 |
|
T68 |
12 |
auto[1] |
auto[0] |
1656 |
1 |
|
|
T28 |
14 |
|
T29 |
10 |
|
T89 |
12 |
auto[1] |
auto[1] |
114 |
1 |
|
|
T28 |
1 |
|
T29 |
1 |
|
T186 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39856 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[0] |
auto[1] |
1301 |
1 |
|
|
T5 |
12 |
|
T13 |
14 |
|
T68 |
12 |
auto[1] |
auto[0] |
1671 |
1 |
|
|
T28 |
15 |
|
T29 |
11 |
|
T89 |
10 |
auto[1] |
auto[1] |
99 |
1 |
|
|
T89 |
2 |
|
T48 |
2 |
|
T187 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39788 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[0] |
auto[1] |
1369 |
1 |
|
|
T5 |
7 |
|
T13 |
6 |
|
T68 |
10 |
auto[1] |
auto[0] |
1674 |
1 |
|
|
T28 |
13 |
|
T29 |
10 |
|
T89 |
9 |
auto[1] |
auto[1] |
96 |
1 |
|
|
T28 |
2 |
|
T29 |
1 |
|
T89 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39794 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[0] |
auto[1] |
1363 |
1 |
|
|
T5 |
9 |
|
T13 |
17 |
|
T68 |
8 |
auto[1] |
auto[0] |
1656 |
1 |
|
|
T28 |
12 |
|
T29 |
9 |
|
T89 |
12 |
auto[1] |
auto[1] |
114 |
1 |
|
|
T28 |
3 |
|
T29 |
2 |
|
T20 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39816 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[0] |
auto[1] |
1341 |
1 |
|
|
T5 |
13 |
|
T13 |
10 |
|
T68 |
9 |
auto[1] |
auto[0] |
1687 |
1 |
|
|
T28 |
15 |
|
T29 |
11 |
|
T89 |
12 |
auto[1] |
auto[1] |
83 |
1 |
|
|
T20 |
2 |
|
T186 |
1 |
|
T48 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39791 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T3 |
17 |
auto[0] |
auto[1] |
1366 |
1 |
|
|
T5 |
6 |
|
T13 |
7 |
|
T68 |
7 |
auto[1] |
auto[0] |
1692 |
1 |
|
|
T28 |
15 |
|
T29 |
10 |
|
T89 |
12 |
auto[1] |
auto[1] |
78 |
1 |
|
|
T29 |
1 |
|
T186 |
1 |
|
T188 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30706 |
1 |
|
|
T1 |
8 |
|
T2 |
57 |
|
T9 |
2 |
auto[0] |
auto[1] |
713 |
1 |
|
|
T2 |
11 |
|
T36 |
8 |
|
T47 |
10 |
auto[1] |
auto[0] |
10961 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
547 |
1 |
|
|
T20 |
23 |
|
T48 |
10 |
|
T99 |
12 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30636 |
1 |
|
|
T1 |
8 |
|
T2 |
61 |
|
T9 |
2 |
auto[0] |
auto[1] |
783 |
1 |
|
|
T2 |
7 |
|
T36 |
15 |
|
T47 |
8 |
auto[1] |
auto[0] |
10992 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
516 |
1 |
|
|
T20 |
20 |
|
T48 |
6 |
|
T99 |
8 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30616 |
1 |
|
|
T2 |
68 |
|
T9 |
2 |
|
T10 |
83 |
auto[0] |
auto[1] |
803 |
1 |
|
|
T1 |
8 |
|
T66 |
18 |
|
T189 |
9 |
auto[1] |
auto[0] |
10852 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
656 |
1 |
|
|
T19 |
13 |
|
T48 |
10 |
|
T190 |
19 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30716 |
1 |
|
|
T1 |
8 |
|
T2 |
59 |
|
T9 |
2 |
auto[0] |
auto[1] |
703 |
1 |
|
|
T2 |
9 |
|
T36 |
8 |
|
T47 |
6 |
auto[1] |
auto[0] |
10933 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
575 |
1 |
|
|
T20 |
22 |
|
T48 |
5 |
|
T99 |
13 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
26985 |
1 |
|
|
T1 |
8 |
|
T2 |
58 |
|
T9 |
2 |
auto[0] |
auto[1] |
4434 |
1 |
|
|
T2 |
10 |
|
T185 |
100 |
|
T36 |
10 |
auto[1] |
auto[0] |
10959 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
549 |
1 |
|
|
T20 |
30 |
|
T48 |
5 |
|
T99 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30502 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[0] |
auto[1] |
917 |
1 |
|
|
T13 |
9 |
|
T28 |
1 |
|
T29 |
1 |
auto[1] |
auto[0] |
10957 |
1 |
|
|
T3 |
17 |
|
T5 |
71 |
|
T15 |
20 |
auto[1] |
auto[1] |
551 |
1 |
|
|
T5 |
9 |
|
T17 |
13 |
|
T186 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30562 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[0] |
auto[1] |
857 |
1 |
|
|
T13 |
9 |
|
T28 |
2 |
|
T68 |
12 |
auto[1] |
auto[0] |
10917 |
1 |
|
|
T3 |
17 |
|
T5 |
74 |
|
T15 |
20 |
auto[1] |
auto[1] |
591 |
1 |
|
|
T5 |
6 |
|
T17 |
14 |
|
T186 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30526 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[0] |
auto[1] |
893 |
1 |
|
|
T13 |
14 |
|
T68 |
12 |
|
T87 |
9 |
auto[1] |
auto[0] |
11001 |
1 |
|
|
T3 |
17 |
|
T5 |
68 |
|
T15 |
20 |
auto[1] |
auto[1] |
507 |
1 |
|
|
T5 |
12 |
|
T17 |
6 |
|
T191 |
6 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30521 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[0] |
auto[1] |
898 |
1 |
|
|
T13 |
6 |
|
T28 |
1 |
|
T29 |
1 |
auto[1] |
auto[0] |
10957 |
1 |
|
|
T3 |
17 |
|
T5 |
73 |
|
T15 |
20 |
auto[1] |
auto[1] |
551 |
1 |
|
|
T5 |
7 |
|
T17 |
13 |
|
T191 |
11 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30489 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[0] |
auto[1] |
930 |
1 |
|
|
T13 |
17 |
|
T28 |
3 |
|
T29 |
2 |
auto[1] |
auto[0] |
10961 |
1 |
|
|
T3 |
17 |
|
T5 |
71 |
|
T15 |
20 |
auto[1] |
auto[1] |
547 |
1 |
|
|
T5 |
9 |
|
T17 |
11 |
|
T20 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30531 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[0] |
auto[1] |
888 |
1 |
|
|
T13 |
7 |
|
T29 |
1 |
|
T68 |
7 |
auto[1] |
auto[0] |
10952 |
1 |
|
|
T3 |
17 |
|
T5 |
74 |
|
T15 |
20 |
auto[1] |
auto[1] |
556 |
1 |
|
|
T5 |
6 |
|
T17 |
6 |
|
T186 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30711 |
1 |
|
|
T1 |
8 |
|
T2 |
60 |
|
T9 |
2 |
auto[0] |
auto[1] |
708 |
1 |
|
|
T2 |
8 |
|
T36 |
7 |
|
T47 |
11 |
auto[1] |
auto[0] |
10912 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
596 |
1 |
|
|
T20 |
22 |
|
T48 |
8 |
|
T99 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30703 |
1 |
|
|
T1 |
8 |
|
T2 |
62 |
|
T9 |
2 |
auto[0] |
auto[1] |
716 |
1 |
|
|
T2 |
6 |
|
T36 |
10 |
|
T47 |
4 |
auto[1] |
auto[0] |
10912 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
596 |
1 |
|
|
T20 |
26 |
|
T48 |
7 |
|
T99 |
16 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30446 |
1 |
|
|
T1 |
8 |
|
T2 |
68 |
|
T9 |
2 |
auto[0] |
auto[1] |
973 |
1 |
|
|
T28 |
15 |
|
T29 |
11 |
|
T89 |
12 |
auto[1] |
auto[0] |
10711 |
1 |
|
|
T3 |
17 |
|
T5 |
80 |
|
T15 |
20 |
auto[1] |
auto[1] |
797 |
1 |
|
|
T20 |
12 |
|
T186 |
11 |
|
T48 |
12 |