Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	896843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1082729

1

T45

129

T76

349

T77

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1695412	1			T45	40		T76	83		T77	36
values[0x0]	141456	1			T45	52		T76	144		T77	48
values[0x1]	142704	1			T45	59		T76	202		T77	71

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	710860	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1268712

1

T45

135

T76

399

T77

143

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6451	1			T78	1		T80	2		T84	6
valid_sources[0x01]	6064	1			T76	2		T77	1		T78	1
valid_sources[0x02]	7262	1			T45	22		T76	1		T80	3
valid_sources[0x03]	7093	1			T76	1		T77	1		T78	1
valid_sources[0x04]	6173	1			T77	1		T145	1		T150	1
valid_sources[0x05]	6121	1			T76	2		T77	1		T80	3
valid_sources[0x06]	25575	1			T76	2		T80	1		T145	3
valid_sources[0x07]	6301	1			T76	2		T80	2		T81	1
valid_sources[0x08]	6279	1			T76	1		T78	3		T80	5
valid_sources[0x09]	15716	1			T76	1		T81	1		T83	13
valid_sources[0x0a]	6096	1			T76	1		T78	1		T79	2
valid_sources[0x0b]	7880	1			T76	1		T77	1		T78	1
valid_sources[0x0c]	6614	1			T76	2		T77	2		T78	1
valid_sources[0x0d]	6367	1			T76	4		T77	2		T80	3
valid_sources[0x0e]	7489	1			T76	1		T77	2		T78	1
valid_sources[0x0f]	6977	1			T76	1		T77	1		T80	2
valid_sources[0x10]	6618	1			T77	1		T81	1		T142	1
valid_sources[0x11]	6583	1			T76	2		T80	3		T145	3
valid_sources[0x12]	6805	1			T76	2		T77	1		T78	3
valid_sources[0x13]	10221	1			T76	1		T77	1		T79	1
valid_sources[0x14]	6416	1			T97	1		T142	1		T148	1
valid_sources[0x15]	6235	1			T76	2		T77	1		T78	1
valid_sources[0x16]	6447	1			T76	2		T78	1		T80	1
valid_sources[0x17]	6506	1			T80	1		T83	1		T142	1
valid_sources[0x18]	7922	1			T76	2		T151	2		T144	1
valid_sources[0x19]	6310	1			T76	4		T77	1		T149	1
valid_sources[0x1a]	6854	1			T76	3		T77	1		T78	1
valid_sources[0x1b]	6657	1			T76	1		T77	1		T78	2
valid_sources[0x1c]	6081	1			T81	1		T97	1		T92	1
valid_sources[0x1d]	11093	1			T76	2		T77	1		T78	1
valid_sources[0x1e]	6324	1			T76	3		T77	3		T97	4
valid_sources[0x1f]	6740	1			T76	1		T78	1		T79	5
valid_sources[0x20]	7460	1			T76	1		T97	1		T145	2
valid_sources[0x21]	6591	1			T78	1		T79	1		T80	7
valid_sources[0x22]	6361	1			T76	2		T77	1		T78	2
valid_sources[0x23]	6395	1			T76	2		T81	1		T145	2
valid_sources[0x24]	6581	1			T76	2		T78	1		T79	7
valid_sources[0x25]	6999	1			T76	1		T77	1		T80	2
valid_sources[0x26]	6555	1			T76	1		T77	3		T78	1
valid_sources[0x27]	6053	1			T76	4		T77	1		T81	1
valid_sources[0x28]	6065	1			T76	2		T77	1		T80	6
valid_sources[0x29]	6419	1			T76	1		T80	5		T142	1
valid_sources[0x2a]	8050	1			T76	2		T80	5		T81	1
valid_sources[0x2b]	6107	1			T76	1		T77	1		T78	2
valid_sources[0x2c]	12729	1			T76	3		T77	1		T78	2
valid_sources[0x2d]	8606	1			T77	1		T78	2		T149	1
valid_sources[0x2e]	7575	1			T76	2		T77	1		T81	1
valid_sources[0x2f]	6444	1			T76	2		T79	19		T81	1
valid_sources[0x30]	6487	1			T76	1		T78	1		T80	2
valid_sources[0x31]	6265	1			T76	2		T78	3		T80	1
valid_sources[0x32]	6229	1			T76	2		T77	2		T78	1
valid_sources[0x33]	6579	1			T78	1		T80	1		T151	3
valid_sources[0x34]	9095	1			T45	27		T76	4		T77	1
valid_sources[0x35]	6132	1			T76	3		T77	3		T78	1
valid_sources[0x36]	6248	1			T76	1		T77	1		T78	1
valid_sources[0x37]	6060	1			T76	2		T78	2		T80	2
valid_sources[0x38]	6730	1			T76	1		T77	1		T79	2
valid_sources[0x39]	6198	1			T76	2		T78	1		T80	4
valid_sources[0x3a]	6219	1			T76	2		T77	1		T78	1
valid_sources[0x3b]	6525	1			T76	2		T79	2		T80	4
valid_sources[0x3c]	12631	1			T76	2		T77	1		T78	3
valid_sources[0x3d]	6941	1			T76	3		T77	1		T78	1
valid_sources[0x3e]	8841	1			T81	1		T144	1		T149	2
valid_sources[0x3f]	6909	1			T76	3		T78	1		T80	1
valid_sources[0x40]	6405	1			T76	1		T80	2		T142	1
valid_sources[0x41]	6048	1			T76	2		T78	1		T79	19
valid_sources[0x42]	6641	1			T76	3		T77	1		T78	3
valid_sources[0x43]	6329	1			T76	3		T77	2		T78	2
valid_sources[0x44]	31508	1			T76	4		T78	1		T80	1
valid_sources[0x45]	6178	1			T79	9		T80	2		T81	2
valid_sources[0x46]	6125	1			T76	3		T80	2		T81	1
valid_sources[0x47]	6519	1			T76	1		T78	1		T80	2
valid_sources[0x48]	7528	1			T76	2		T77	4		T81	4
valid_sources[0x49]	6342	1			T76	1		T77	1		T80	3
valid_sources[0x4a]	6046	1			T80	2		T97	2		T145	1
valid_sources[0x4b]	6067	1			T76	2		T77	1		T78	2
valid_sources[0x4c]	6810	1			T76	1		T80	3		T143	6
valid_sources[0x4d]	6288	1			T76	1		T77	1		T80	2
valid_sources[0x4e]	6629	1			T78	1		T80	2		T145	1
valid_sources[0x4f]	6433	1			T76	1		T80	1		T81	1
valid_sources[0x50]	6099	1			T76	4		T78	2		T80	6
valid_sources[0x51]	88882	1			T76	2		T77	2		T78	1
valid_sources[0x52]	7498	1			T77	1		T78	2		T80	4
valid_sources[0x53]	7849	1			T76	1		T80	1		T81	1
valid_sources[0x54]	5930	1			T76	2		T77	1		T80	1
valid_sources[0x55]	8014	1			T76	3		T80	5		T151	2
valid_sources[0x56]	6423	1			T76	2		T77	1		T78	3
valid_sources[0x57]	6304	1			T77	1		T80	3		T151	3
valid_sources[0x58]	6552	1			T76	2		T78	1		T80	4
valid_sources[0x59]	6574	1			T76	2		T77	2		T78	1
valid_sources[0x5a]	6401	1			T76	1		T80	4		T97	5
valid_sources[0x5b]	6142	1			T78	2		T81	2		T97	7
valid_sources[0x5c]	7506	1			T45	18		T76	3		T77	1
valid_sources[0x5d]	7464	1			T78	1		T80	1		T81	1
valid_sources[0x5e]	8019	1			T45	60		T76	2		T78	1
valid_sources[0x5f]	6429	1			T45	4		T76	2		T77	1
valid_sources[0x60]	6384	1			T76	3		T78	1		T80	1
valid_sources[0x61]	6399	1			T76	2		T77	4		T78	1
valid_sources[0x62]	6777	1			T76	1		T77	1		T78	3
valid_sources[0x63]	14449	1			T76	1		T77	1		T78	2
valid_sources[0x64]	6418	1			T76	4		T77	1		T80	1
valid_sources[0x65]	6197	1			T76	1		T80	1		T142	2
valid_sources[0x66]	6570	1			T76	2		T80	5		T81	2
valid_sources[0x67]	6337	1			T76	1		T78	2		T79	33
valid_sources[0x68]	6740	1			T76	1		T77	2		T81	1
valid_sources[0x69]	6137	1			T76	2		T77	1		T80	1
valid_sources[0x6a]	6228	1			T76	2		T77	1		T78	1
valid_sources[0x6b]	6199	1			T76	3		T80	1		T142	1
valid_sources[0x6c]	6861	1			T76	4		T77	1		T78	1
valid_sources[0x6d]	6399	1			T76	5		T78	1		T80	4
valid_sources[0x6e]	6458	1			T76	2		T77	1		T80	2
valid_sources[0x6f]	6194	1			T76	4		T79	4		T80	3
valid_sources[0x70]	8894	1			T76	3		T78	4		T80	2
valid_sources[0x71]	48186	1			T76	3		T78	3		T80	7
valid_sources[0x72]	13590	1			T76	1		T77	1		T78	1
valid_sources[0x73]	12313	1			T78	1		T80	11		T81	2
valid_sources[0x74]	6067	1			T76	4		T78	2		T80	5
valid_sources[0x75]	6294	1			T76	2		T77	1		T78	1
valid_sources[0x76]	6259	1			T78	4		T145	5		T152	1
valid_sources[0x77]	6333	1			T76	1		T77	1		T80	3
valid_sources[0x78]	7514	1			T76	2		T80	2		T81	4
valid_sources[0x79]	7961	1			T76	1		T78	1		T80	1
valid_sources[0x7a]	6731	1			T76	1		T77	1		T79	61
valid_sources[0x7b]	6623	1			T76	3		T77	1		T78	1
valid_sources[0x7c]	9716	1			T78	1		T80	2		T81	1
valid_sources[0x7d]	6850	1			T76	1		T77	1		T78	3
valid_sources[0x7e]	6234	1			T76	1		T80	1		T81	2
valid_sources[0x7f]	6443	1			T77	2		T78	1		T80	1
valid_sources[0x80]	6283	1			T76	4		T77	1		T78	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

837852

1

T45

26

T76

79

T77

34

values[0x0]

all_enables

biggest_size

122718

1

T45

49

T76

136

T77

46

values[0x1]

all_enables

biggest_size

122159

1

T45

54

T76

134

T77

48