Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.75	100.00	83.10	98.16		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	62650977	13558	0	0
claim_transition_if_regwen_rd_A	62650977	1425	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62650977	13558	0	0
T45	2684	33	0	0
T76	3350	487	0	0
T77	8337	450	0	0
T78	4397	194	0	0
T79	7107	12	0	0
T80	13428	592	0	0
T81	2052	150	0	0
T82	3949	0	0	0
T83	10577	8	0	0
T84	4853	167	0	0
T127	0	782	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62650977	1425	0	0
T45	2684	21	0	0
T76	3350	0	0	0
T77	8337	0	0	0
T78	4397	0	0	0
T79	7107	0	0	0
T80	13428	6	0	0
T81	2052	0	0	0
T82	3949	0	0	0
T83	10577	0	0	0
T84	4853	4	0	0
T136	0	2	0	0
T138	0	4	0	0
T143	0	9	0	0
T144	0	6	0	0
T145	0	41	0	0
T146	0	1	0	0
T147	0	5	0	0