Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	713593	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

893950

1

T60

190

T88

218

T89

310

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1332367	1			T60	262		T88	31		T89	93
values[0x0]	136980	1			T60	26		T88	92		T89	105
values[0x1]	138196	1			T60	40		T88	95		T89	164

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	564820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1042723

1

T60

216

T88

218

T89

345

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4596	1			T60	1		T88	1		T89	1
valid_sources[0x01]	4644	1			T89	1		T92	20		T93	1
valid_sources[0x02]	5897	1			T60	2		T93	2		T94	1
valid_sources[0x03]	7975	1			T60	2		T88	4		T89	1
valid_sources[0x04]	5019	1			T60	4		T89	2		T93	1
valid_sources[0x05]	5359	1			T88	1		T93	1		T94	2
valid_sources[0x06]	7329	1			T60	2		T89	4		T93	2
valid_sources[0x07]	5148	1			T89	1		T93	2		T94	2
valid_sources[0x08]	5234	1			T60	1		T88	2		T93	2
valid_sources[0x09]	5056	1			T60	2		T88	2		T89	1
valid_sources[0x0a]	4822	1			T60	1		T88	2		T89	1
valid_sources[0x0b]	5296	1			T60	1		T89	3		T92	12
valid_sources[0x0c]	5216	1			T88	1		T89	1		T93	1
valid_sources[0x0d]	6029	1			T60	3		T89	1		T101	4
valid_sources[0x0e]	5183	1			T60	4		T88	4		T89	2
valid_sources[0x0f]	5304	1			T93	3		T112	3		T101	2
valid_sources[0x10]	5186	1			T60	3		T88	1		T89	5
valid_sources[0x11]	6195	1			T60	2		T89	4		T93	3
valid_sources[0x12]	4566	1			T89	4		T93	2		T107	4
valid_sources[0x13]	8594	1			T60	2		T89	3		T93	1
valid_sources[0x14]	4668	1			T60	5		T88	1		T89	2
valid_sources[0x15]	4847	1			T89	1		T107	2		T101	3
valid_sources[0x16]	4816	1			T60	3		T88	1		T89	1
valid_sources[0x17]	5039	1			T94	1		T104	2		T103	4
valid_sources[0x18]	5130	1			T60	1		T89	1		T93	3
valid_sources[0x19]	5142	1			T60	1		T89	3		T92	17
valid_sources[0x1a]	7751	1			T60	1		T89	1		T93	1
valid_sources[0x1b]	6617	1			T60	1		T93	1		T107	3
valid_sources[0x1c]	5043	1			T60	1		T88	1		T89	1
valid_sources[0x1d]	4983	1			T60	1		T93	3		T101	3
valid_sources[0x1e]	5107	1			T60	1		T89	1		T107	2
valid_sources[0x1f]	5272	1			T60	2		T88	1		T89	1
valid_sources[0x20]	5111	1			T89	4		T93	1		T94	3
valid_sources[0x21]	4890	1			T60	1		T88	1		T93	2
valid_sources[0x22]	5148	1			T60	1		T107	5		T158	2
valid_sources[0x23]	5033	1			T60	1		T88	3		T139	4
valid_sources[0x24]	5142	1			T60	2		T88	1		T89	2
valid_sources[0x25]	6628	1			T60	2		T107	2		T99	2
valid_sources[0x26]	5101	1			T60	1		T88	2		T93	1
valid_sources[0x27]	4907	1			T89	7		T94	2		T159	1
valid_sources[0x28]	4969	1			T60	1		T88	2		T92	18
valid_sources[0x29]	5557	1			T60	2		T88	6		T93	1
valid_sources[0x2a]	5678	1			T60	1		T88	2		T89	1
valid_sources[0x2b]	8527	1			T60	1		T89	3		T104	5
valid_sources[0x2c]	5168	1			T88	3		T89	1		T94	1
valid_sources[0x2d]	7113	1			T88	2		T93	2		T107	10
valid_sources[0x2e]	4820	1			T60	1		T89	1		T93	1
valid_sources[0x2f]	12110	1			T60	2		T89	2		T93	1
valid_sources[0x30]	4959	1			T60	1		T88	1		T89	2
valid_sources[0x31]	7564	1			T60	2		T93	1		T112	7
valid_sources[0x32]	5305	1			T60	1		T88	3		T89	2
valid_sources[0x33]	8091	1			T60	1		T89	1		T93	1
valid_sources[0x34]	4768	1			T60	2		T89	2		T93	1
valid_sources[0x35]	5048	1			T88	2		T89	1		T107	1
valid_sources[0x36]	5036	1			T88	3		T101	2		T139	1
valid_sources[0x37]	4861	1			T89	3		T101	5		T159	3
valid_sources[0x38]	5854	1			T60	2		T89	4		T99	10
valid_sources[0x39]	5141	1			T89	2		T93	2		T107	2
valid_sources[0x3a]	4952	1			T60	2		T89	1		T93	1
valid_sources[0x3b]	5133	1			T89	1		T93	1		T159	7
valid_sources[0x3c]	10240	1			T60	1		T88	1		T89	1
valid_sources[0x3d]	6499	1			T60	1		T89	2		T93	1
valid_sources[0x3e]	7251	1			T60	1		T88	1		T89	1
valid_sources[0x3f]	4833	1			T88	1		T107	6		T112	13
valid_sources[0x40]	18057	1			T60	1		T89	1		T107	7
valid_sources[0x41]	4918	1			T60	1		T88	3		T89	7
valid_sources[0x42]	5019	1			T60	1		T88	3		T93	1
valid_sources[0x43]	4843	1			T101	2		T159	3		T102	2
valid_sources[0x44]	4669	1			T89	1		T93	3		T107	2
valid_sources[0x45]	5072	1			T60	1		T89	3		T159	1
valid_sources[0x46]	4845	1			T60	2		T88	2		T89	2
valid_sources[0x47]	21959	1			T89	3		T93	1		T107	12
valid_sources[0x48]	5139	1			T60	1		T88	2		T89	1
valid_sources[0x49]	5042	1			T60	1		T88	3		T93	1
valid_sources[0x4a]	4797	1			T60	1		T93	3		T94	7
valid_sources[0x4b]	5073	1			T88	1		T89	2		T93	1
valid_sources[0x4c]	5168	1			T60	6		T88	2		T89	1
valid_sources[0x4d]	4923	1			T60	2		T89	2		T93	2
valid_sources[0x4e]	4883	1			T60	3		T89	2		T92	19
valid_sources[0x4f]	5174	1			T60	1		T88	1		T89	3
valid_sources[0x50]	5012	1			T60	1		T94	1		T103	10
valid_sources[0x51]	5189	1			T60	1		T88	2		T89	1
valid_sources[0x52]	9533	1			T60	1		T94	2		T159	1
valid_sources[0x53]	4699	1			T60	2		T89	3		T159	2
valid_sources[0x54]	4602	1			T89	2		T93	2		T94	2
valid_sources[0x55]	4636	1			T60	1		T88	1		T93	5
valid_sources[0x56]	7825	1			T60	1		T89	1		T93	1
valid_sources[0x57]	6528	1			T88	2		T89	4		T107	2
valid_sources[0x58]	4771	1			T89	3		T107	1		T101	1
valid_sources[0x59]	4890	1			T60	2		T88	1		T89	3
valid_sources[0x5a]	6053	1			T60	1		T93	1		T101	2
valid_sources[0x5b]	4865	1			T60	1		T88	1		T89	2
valid_sources[0x5c]	5998	1			T60	1		T89	2		T93	2
valid_sources[0x5d]	6259	1			T60	1		T89	6		T93	1
valid_sources[0x5e]	4998	1			T60	1		T89	2		T102	2
valid_sources[0x5f]	26360	1			T60	2		T88	2		T89	2
valid_sources[0x60]	6899	1			T60	1		T89	1		T93	1
valid_sources[0x61]	4773	1			T89	1		T93	4		T107	1
valid_sources[0x62]	19856	1			T60	2		T94	1		T107	3
valid_sources[0x63]	5214	1			T60	6		T88	3		T89	1
valid_sources[0x64]	5100	1			T60	2		T112	19		T159	1
valid_sources[0x65]	4989	1			T60	1		T88	1		T93	2
valid_sources[0x66]	8639	1			T89	2		T93	2		T94	6
valid_sources[0x67]	5197	1			T89	1		T93	1		T94	3
valid_sources[0x68]	5138	1			T94	2		T107	2		T102	4
valid_sources[0x69]	6484	1			T88	2		T89	1		T93	2
valid_sources[0x6a]	4930	1			T89	1		T93	1		T94	1
valid_sources[0x6b]	5848	1			T60	2		T93	5		T107	2
valid_sources[0x6c]	5241	1			T60	1		T89	3		T107	15
valid_sources[0x6d]	15509	1			T60	1		T107	3		T101	5
valid_sources[0x6e]	5945	1			T60	1		T88	1		T94	2
valid_sources[0x6f]	7626	1			T60	3		T89	2		T94	5
valid_sources[0x70]	4874	1			T60	2		T88	2		T89	1
valid_sources[0x71]	5444	1			T60	3		T94	2		T159	1
valid_sources[0x72]	5027	1			T60	4		T88	5		T93	1
valid_sources[0x73]	5190	1			T60	3		T107	1		T112	3
valid_sources[0x74]	5957	1			T60	1		T89	1		T107	4
valid_sources[0x75]	5017	1			T60	3		T93	1		T107	2
valid_sources[0x76]	4830	1			T88	2		T89	2		T93	3
valid_sources[0x77]	5203	1			T60	3		T88	2		T89	4
valid_sources[0x78]	5535	1			T60	1		T88	2		T89	3
valid_sources[0x79]	6565	1			T60	2		T88	9		T89	2
valid_sources[0x7a]	5378	1			T89	3		T93	3		T112	9
valid_sources[0x7b]	5098	1			T93	3		T107	22		T101	3
valid_sources[0x7c]	4858	1			T89	1		T93	2		T94	2
valid_sources[0x7d]	17615	1			T89	1		T107	2		T112	10
valid_sources[0x7e]	4778	1			T60	1		T89	1		T107	3
valid_sources[0x7f]	5009	1			T89	2		T93	1		T112	1
valid_sources[0x80]	5121	1			T93	2		T104	1		T101	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

656964

1

T60

131

T88

31

T89

85

values[0x0]

all_enables

biggest_size

118848

1

T60

21

T88

92

T89

104

values[0x1]

all_enables

biggest_size

118138

1

T60

38

T88

95

T89

121