Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
4.08			4.08

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_esc_receiver0.u_prim_count	4.08			4.08
tb.dut.u_prim_esc_receiver1.u_prim_count	4.08			4.08

---

Module Instance : tb.dut.u_prim_esc_receiver0.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
4.08			4.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
4.08			4.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				u_prim_esc_receiver0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_esc_receiver1.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
4.08			4.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
4.08			4.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00			100.00				u_prim_esc_receiver1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count

	Total	Covered	Percent
Totals	7	2	28.57
Total Bits	98	4	4.08
Total Bits 0->1	49	2	4.08
Total Bits 1->0	49	2	4.08

Ports	7	2	28.57
Port Bits	98	4	4.08
Port Bits 0->1	49	2	4.08
Port Bits 1->0	49	2	4.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	No	No		No		INPUT
set_cnt_i[21:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[21:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[21:0]	No	No		No		OUTPUT
cnt_after_commit_o[21:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_prim_esc_receiver0.u_prim_count

	Total	Covered	Percent
Totals	7	2	28.57
Total Bits	98	4	4.08
Total Bits 0->1	49	2	4.08
Total Bits 1->0	49	2	4.08

Ports	7	2	28.57
Port Bits	98	4	4.08
Port Bits 0->1	49	2	4.08
Port Bits 1->0	49	2	4.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	No	No		No		INPUT
set_cnt_i[21:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[21:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[21:0]	No	No		No		OUTPUT
cnt_after_commit_o[21:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_prim_esc_receiver1.u_prim_count

	Total	Covered	Percent
Totals	7	2	28.57
Total Bits	98	4	4.08
Total Bits 0->1	49	2	4.08
Total Bits 1->0	49	2	4.08

Ports	7	2	28.57
Port Bits	98	4	4.08
Port Bits 0->1	49	2	4.08
Port Bits 1->0	49	2	4.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	No	No		No		INPUT
set_cnt_i[21:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[21:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[21:0]	No	No		No		OUTPUT
cnt_after_commit_o[21:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT