Unified Coverage Report :: Module :: tlul_err

Module : tlul_err

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_tap.u_reg_if.u_err	73.56	69.23	100.00			25.00	100.00
tb.dut.u_reg.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_tap.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.56	69.23	100.00			25.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.56	69.23	100.00			25.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.91	97.37	94.29			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.44	100.00	97.78			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Module : tlul_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T87

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T88

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T87

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T60,T86,T87
0	0	1	Covered	T89,T92,T93
0	1	0	Covered	T89,T93,T94
1	0	0	Covered	T60,T86,T87

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T89,T93,T94
1	0	Covered	T86,T87,T89
1	1	Covered	T60,T86,T87

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T89,T92,T93
0	0	1	Covered	T60,T86,T87
0	1	0	Covered	T60,T86,T88
1	0	0	Covered	T60,T86,T87

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T87

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T88

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T87

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T60,T89,T92
1	Covered	T60,T89,T92

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T60,T89,T92
1	Covered	T60,T89,T92

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T93,T94
1	0	1	Covered	T89,T93,T94
1	1	0	Covered	T89,T92,T93
1	1	1	Covered	T60,T86,T87

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T86,T87,T89
0	0	1	Covered	T60,T86,T87
0	1	0	Covered	T60,T86,T89
1	0	0	Covered	T60,T86,T87

---

Branch Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T60,T89,T92
1	'h1	1	-	Covered	T60,T89,T92
1	'h1	0	-	Covered	T60,T89,T92
1	'h1	-	1	Covered	T60,T89,T92
1	'h1	-	0	Covered	T60,T89,T92
1	'h00000002	-	-	Covered	T60,T86,T87
1	default	-	-	Covered	T89,T93,T94
0	-	-	-	Covered	T60,T86,T87

---

Assert Coverage for Module : tlul_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1964	1964	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1964	1964	0	0
T60	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0
T89	2	2	0	0
T90	2	2	0	0
T91	2	2	0	0
T92	2	2	0	0
T93	2	2	0	0
T94	2	2	0	0

Line Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	18	69.23
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	0	0.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	0	0.00
ALWAYS	56	17	11	64.71
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	0	1
39	1	1
42	1	1
53	0	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	0	1
64	0	1
65	0	1
69	0	1
71	0	1
73	0	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T86,T87,T90

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T60,T86,T87
1	Excluded		VC_COV_UNR

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T86,T87,T90

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T86,T87,T90
0	0	1	Excluded		VC_COV_UNR
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T60,T86,T87

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T86,T87,T90
1	1	Covered	T86,T87,T90

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Excluded		VC_COV_UNR
0	0	1	Covered	T86,T87,T90
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T86,T87,T90

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T86,T87,T90

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T60,T86,T87
1	Excluded		VC_COV_UNR

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T86,T87,T90

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T86,T87,T90

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T86,T87,T90
0	0	1	Covered	T86,T87,T90
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T86,T87,T90

---

Branch Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	2	25.00
IF	60	8	2	25.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Not Covered
1	'h1	1	-	Not Covered
1	'h1	0	-	Not Covered
1	'h1	-	1	Not Covered
1	'h1	-	0	Not Covered
1	'h00000002	-	-	Covered	T86,T87,T90
1	default	-	-	Not Covered
0	-	-	-	Covered	T86,T87,T90

---

Assert Coverage for Instance : tb.dut.u_reg_tap.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	982	982	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T87,T88

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T88

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T87

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T60,T88,T89
0	0	1	Covered	T89,T92,T93
0	1	0	Covered	T89,T93,T94
1	0	0	Covered	T86,T87,T89

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T89,T93,T94
1	0	Covered	T86,T87,T89
1	1	Covered	T60,T88,T89

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T89,T92,T93
0	0	1	Covered	T60,T86,T87
0	1	0	Covered	T60,T86,T88
1	0	0	Covered	T60,T87,T88

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T87,T88

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T88

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T60,T86,T87
1	Covered	T60,T86,T87

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T60,T89,T92
1	Covered	T60,T89,T92

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T60,T89,T92
1	Covered	T60,T89,T92

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T93,T94
1	0	1	Covered	T89,T93,T94
1	1	0	Covered	T89,T92,T93
1	1	1	Covered	T60,T88,T89

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T87,T89,T92
0	0	1	Covered	T60,T88,T89
0	1	0	Covered	T60,T86,T89
1	0	0	Covered	T60,T86,T87

---

Branch Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T60,T89,T92
1	'h1	1	-	Covered	T60,T89,T92
1	'h1	0	-	Covered	T60,T89,T92
1	'h1	-	1	Covered	T60,T89,T92
1	'h1	-	0	Covered	T60,T89,T92
1	'h00000002	-	-	Covered	T60,T88,T89
1	default	-	-	Covered	T89,T93,T94
0	-	-	-	Covered	T60,T86,T87

---

Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	982	982	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0