Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1437228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1643528

1

T1

5

T2

842

T3

814

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2757979	1			T1	1		T2	491		T3	477
values[0x0]	161278	1			T1	3		T2	319		T3	330
values[0x1]	161499	1			T1	5		T2	385		T3	358

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1142451	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1938305

1

T1

7

T2

947

T3

904

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10742	1			T3	4		T13	4		T91	3
valid_sources[0x01]	10894	1			T2	4		T3	2		T13	5
valid_sources[0x02]	11709	1			T3	3		T13	7		T90	1
valid_sources[0x03]	10802	1			T3	4		T13	1		T91	7
valid_sources[0x04]	10625	1			T3	7		T13	8		T114	1
valid_sources[0x05]	10321	1			T3	4		T13	10		T91	2
valid_sources[0x06]	10787	1			T2	8		T3	3		T13	9
valid_sources[0x07]	12214	1			T3	6		T13	3		T90	1
valid_sources[0x08]	10210	1			T2	47		T3	4		T13	5
valid_sources[0x09]	11932	1			T2	11		T3	3		T13	4
valid_sources[0x0a]	10366	1			T2	26		T3	8		T13	14
valid_sources[0x0b]	10318	1			T3	1		T13	3		T91	1
valid_sources[0x0c]	10539	1			T3	7		T13	3		T92	1
valid_sources[0x0d]	12761	1			T2	3		T3	2		T13	3
valid_sources[0x0e]	12307	1			T3	4		T13	6		T91	1
valid_sources[0x0f]	11148	1			T2	27		T3	5		T5	17
valid_sources[0x10]	11771	1			T3	6		T13	4		T90	2
valid_sources[0x11]	11218	1			T3	8		T13	5		T92	2
valid_sources[0x12]	10423	1			T3	5		T13	9		T91	4
valid_sources[0x13]	10716	1			T3	3		T13	6		T92	3
valid_sources[0x14]	10864	1			T3	5		T13	4		T92	5
valid_sources[0x15]	10860	1			T3	1		T13	2		T90	1
valid_sources[0x16]	10696	1			T3	5		T13	4		T91	1
valid_sources[0x17]	12227	1			T2	26		T3	3		T13	4
valid_sources[0x18]	10657	1			T3	4		T90	1		T92	1
valid_sources[0x19]	10652	1			T2	16		T3	5		T13	6
valid_sources[0x1a]	10755	1			T2	16		T3	7		T13	5
valid_sources[0x1b]	11509	1			T3	4		T13	6		T92	3
valid_sources[0x1c]	16004	1			T3	4		T13	4		T90	1
valid_sources[0x1d]	12420	1			T3	5		T13	6		T90	1
valid_sources[0x1e]	11344	1			T3	8		T13	10		T96	3
valid_sources[0x1f]	10996	1			T3	3		T13	9		T91	3
valid_sources[0x20]	11247	1			T2	3		T3	7		T13	3
valid_sources[0x21]	10732	1			T3	3		T13	4		T92	2
valid_sources[0x22]	10412	1			T3	8		T13	9		T114	4
valid_sources[0x23]	10544	1			T3	6		T13	2		T90	1
valid_sources[0x24]	10522	1			T3	4		T13	2		T91	2
valid_sources[0x25]	10885	1			T3	6		T13	9		T90	1
valid_sources[0x26]	10278	1			T3	8		T13	4		T92	1
valid_sources[0x27]	10812	1			T2	1		T3	7		T13	4
valid_sources[0x28]	10024	1			T2	5		T3	3		T13	5
valid_sources[0x29]	11106	1			T3	7		T13	6		T91	1
valid_sources[0x2a]	11459	1			T3	5		T13	6		T90	4
valid_sources[0x2b]	10445	1			T2	3		T3	6		T13	4
valid_sources[0x2c]	10375	1			T3	4		T13	9		T92	1
valid_sources[0x2d]	11015	1			T3	4		T13	11		T96	4
valid_sources[0x2e]	15518	1			T3	5		T13	5		T91	2
valid_sources[0x2f]	15474	1			T3	1		T13	4		T91	3
valid_sources[0x30]	10776	1			T3	4		T13	8		T90	2
valid_sources[0x31]	19844	1			T2	9		T3	7		T13	6
valid_sources[0x32]	12167	1			T3	3		T13	8		T90	2
valid_sources[0x33]	60981	1			T3	3		T13	3		T90	1
valid_sources[0x34]	10943	1			T2	2		T3	5		T13	6
valid_sources[0x35]	10594	1			T3	3		T13	8		T90	1
valid_sources[0x36]	10181	1			T3	5		T13	4		T116	4
valid_sources[0x37]	10564	1			T3	1		T13	7		T92	5
valid_sources[0x38]	11607	1			T3	6		T90	1		T92	1
valid_sources[0x39]	10531	1			T3	4		T13	8		T92	4
valid_sources[0x3a]	12010	1			T3	5		T13	5		T90	1
valid_sources[0x3b]	11204	1			T3	7		T13	3		T92	6
valid_sources[0x3c]	11246	1			T2	1		T3	6		T13	8
valid_sources[0x3d]	10326	1			T3	7		T13	7		T92	1
valid_sources[0x3e]	11185	1			T2	11		T3	5		T13	2
valid_sources[0x3f]	10710	1			T3	4		T13	2		T90	2
valid_sources[0x40]	11205	1			T3	3		T13	12		T90	2
valid_sources[0x41]	10848	1			T2	3		T3	3		T13	10
valid_sources[0x42]	10214	1			T2	5		T3	2		T13	3
valid_sources[0x43]	30410	1			T3	3		T13	3		T91	1
valid_sources[0x44]	12113	1			T2	44		T3	4		T13	8
valid_sources[0x45]	10202	1			T3	2		T13	6		T91	1
valid_sources[0x46]	14437	1			T3	2		T13	4		T91	1
valid_sources[0x47]	10178	1			T3	3		T13	4		T90	1
valid_sources[0x48]	13201	1			T2	9		T3	5		T13	3
valid_sources[0x49]	12127	1			T2	4		T3	6		T13	7
valid_sources[0x4a]	10665	1			T2	3		T3	1		T13	2
valid_sources[0x4b]	10583	1			T3	4		T13	6		T90	1
valid_sources[0x4c]	11685	1			T3	1		T13	1		T90	3
valid_sources[0x4d]	10570	1			T2	22		T3	6		T13	7
valid_sources[0x4e]	10540	1			T2	5		T3	4		T13	5
valid_sources[0x4f]	10461	1			T13	4		T90	1		T91	1
valid_sources[0x50]	10357	1			T3	4		T13	11		T90	2
valid_sources[0x51]	10581	1			T3	6		T13	6		T91	4
valid_sources[0x52]	10338	1			T3	2		T13	8		T90	2
valid_sources[0x53]	11987	1			T2	1		T3	2		T13	3
valid_sources[0x54]	14503	1			T3	4		T13	7		T91	1
valid_sources[0x55]	10847	1			T1	9		T3	3		T13	4
valid_sources[0x56]	11842	1			T3	7		T13	6		T91	3
valid_sources[0x57]	10972	1			T2	7		T3	6		T13	3
valid_sources[0x58]	10611	1			T3	3		T13	6		T91	1
valid_sources[0x59]	10863	1			T3	11		T13	1		T91	2
valid_sources[0x5a]	10824	1			T3	6		T13	6		T90	1
valid_sources[0x5b]	11286	1			T2	8		T3	5		T13	5
valid_sources[0x5c]	12271	1			T3	3		T13	5		T92	1
valid_sources[0x5d]	11102	1			T2	6		T3	4		T13	2
valid_sources[0x5e]	10426	1			T3	8		T13	1		T92	1
valid_sources[0x5f]	12488	1			T3	5		T13	4		T90	1
valid_sources[0x60]	10723	1			T2	7		T3	5		T13	4
valid_sources[0x61]	13258	1			T3	1		T13	3		T91	2
valid_sources[0x62]	10943	1			T3	5		T13	6		T159	1
valid_sources[0x63]	10801	1			T3	4		T90	1		T91	1
valid_sources[0x64]	11752	1			T3	5		T13	4		T90	2
valid_sources[0x65]	10856	1			T3	2		T13	7		T90	1
valid_sources[0x66]	10617	1			T3	4		T13	8		T91	2
valid_sources[0x67]	10778	1			T3	6		T13	6		T90	4
valid_sources[0x68]	10607	1			T3	8		T13	5		T90	1
valid_sources[0x69]	11532	1			T2	43		T3	7		T4	991
valid_sources[0x6a]	10605	1			T2	66		T3	6		T13	17
valid_sources[0x6b]	11214	1			T3	7		T13	3		T92	2
valid_sources[0x6c]	12356	1			T3	2		T13	3		T96	2
valid_sources[0x6d]	13853	1			T3	3		T13	3		T91	2
valid_sources[0x6e]	15277	1			T3	6		T13	5		T92	1
valid_sources[0x6f]	10488	1			T3	5		T13	6		T92	1
valid_sources[0x70]	12527	1			T3	9		T13	7		T91	1
valid_sources[0x71]	10221	1			T3	7		T13	3		T91	4
valid_sources[0x72]	10807	1			T2	9		T3	6		T13	6
valid_sources[0x73]	10811	1			T2	2		T3	7		T13	7
valid_sources[0x74]	10155	1			T3	2		T13	6		T90	1
valid_sources[0x75]	12315	1			T3	7		T13	6		T114	2
valid_sources[0x76]	10450	1			T3	5		T13	5		T90	2
valid_sources[0x77]	16941	1			T2	37		T3	7		T5	6255
valid_sources[0x78]	10888	1			T2	27		T3	2		T13	3
valid_sources[0x79]	10553	1			T3	5		T13	4		T91	1
valid_sources[0x7a]	15492	1			T2	26		T3	3		T13	7
valid_sources[0x7b]	10637	1			T2	2		T3	4		T13	5
valid_sources[0x7c]	10720	1			T3	3		T13	4		T92	2
valid_sources[0x7d]	11193	1			T3	4		T13	8		T90	1
valid_sources[0x7e]	10174	1			T13	2		T90	2		T91	1
valid_sources[0x7f]	14273	1			T3	2		T13	5		T91	3
valid_sources[0x80]	10494	1			T3	9		T13	5		T90	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1365301

1

T2

225

T3

215

T4

250

values[0x0]

all_enables

biggest_size

140018

1

T1

3

T2

284

T3

287

values[0x1]

all_enables

biggest_size

138209

1

T1

2

T2

333

T3

312