Module Definition
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Module : lc_ctrl_kmac_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_ctrl_kmac_if 100.00 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_lc_ctrl_kmac_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.75 98.21 100.00 100.00 95.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.13 100.00 83.10 98.16 100.00 84.38 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_flop_2sync 100.00 100.00 100.00
u_prim_sync_reqack_data_in 96.93 96.43 100.00 91.30 100.00
u_state_regs 100.00 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : lc_ctrl_kmac_if
Line No.TotalCoveredPercent
TOTAL4141100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN8111100.00
ALWAYS8888100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10711100.00
ALWAYS1592121100.00
ALWAYS20333100.00
ALWAYS20633100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
81 1 1
88 1 1
89 1 1
90 1 1
91 1 1
93 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
102 1 1
103 1 1
104 1 1
107 1 1
159 1 1
160 1 1
161 1 1
162 1 1
164 1 1
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
MISSING_ELSE
MISSING_ELSE
179 1 1
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
MISSING_ELSE
189 1 1
190 1 1
191 1 1
MISSING_ELSE
196 1 1
203 3 3
206 1 1
207 1 1
209 1 1

Cond Coverage for Module : lc_ctrl_kmac_if
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       95
 EXPRESSION (token_hash_req_i && token_hash_ack_d)
             --------1-------    --------2-------
-1--2-StatusTests
01CoveredT16,T47,T33
10CoveredT2,T3,T4
11CoveredT2,T3,T4 

 LINE       107
 EXPRESSION (token_hash_req_i & ((~token_hash_ack_q)))
             --------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4
FSM Coverage for Module : lc_ctrl_kmac_if
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DoneSt 191 Covered T2,T3,T4
FirstSt 203 Covered T1,T2,T3
SecondSt 173 Covered T2,T3,T4
WaitSt 184 Covered T2,T3,T4


transitionsLine No.CoveredTests
DoneSt->FirstSt 203 Covered T2,T3,T4
FirstSt->SecondSt 173 Covered T2,T3,T4
SecondSt->FirstSt 203 Covered T156
SecondSt->WaitSt 184 Covered T2,T3,T4
WaitSt->DoneSt 191 Covered T2,T3,T4
WaitSt->FirstSt 203 Covered T52,T157,T158


Branch Coverage for Module : lc_ctrl_kmac_if
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 3 3 100.00
CASE 164 9 9 100.00
IF 203 2 2 100.00
IF 206 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	95	if ((token_hash_req_i && token_hash_ack_d))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	164	case (state_q)
-2-:	168	if (kmac_req)
-3-:	172	if (kmac_data_i.ready)
-4-:	183	if (kmac_data_i.ready)
-5-:	189	if (kmac_data_i.done)

Branches:
-1--2--3--4--5-StatusTests
FirstSt 1 1 - - Covered T2,T3,T4
FirstSt 1 0 - - Covered T2,T13,T15
FirstSt 0 - - - Covered T1,T2,T3
SecondSt - - 1 - Covered T2,T3,T4
SecondSt - - 0 - Covered T2,T13,T15
WaitSt - - - 1 Covered T2,T3,T4
WaitSt - - - 0 Covered T2,T3,T4
DoneSt - - - - Covered T2,T3,T4
default - - - - Covered T5,T17,T18 



	LineNo.	Expression
-1-:	203	if ((!rst_kmac_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	206	if ((!rst_kmac_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : lc_ctrl_kmac_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataStable_A 81489714 31586214 0 0
u_state_regs_A 79501365 75834940 0 0


DataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 81489714 31586214 0 0
T2 32290 1558 0 0
T3 25578 849 0 0
T4 24914 361 0 0
T5 352795 30545 0 0
T6 57621 1561 0 0
T7 55690 284 0 0
T12 1069 0 0 0
T13 29268 7238 0 0
T14 1933 115 0 0
T15 2966 278 0 0
T16 0 598 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 79501365 75834940 0 0
T1 1164 1076 0 0
T2 32290 25778 0 0
T3 25578 19058 0 0
T4 24914 20295 0 0
T5 326160 307591 0 0
T6 57621 56193 0 0
T12 1069 976 0 0
T13 29268 24808 0 0
T14 1933 1452 0 0
T15 2966 2144 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%