Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	83590146	13404	0	0
claim_transition_if_regwen_rd_A	83590146	1745	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83590146	13404	0	0
T90	7509	399	0	0
T92	5827	4	0	0
T96	2004	188	0	0
T97	1622	114	0	0
T114	2742	484	0	0
T115	9717	555	0	0
T116	10349	9	0	0
T117	0	4	0	0
T124	11556	680	0	0
T141	3768	29	0	0
T154	5992	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83590146	1745	0	0
T90	7509	12	0	0
T91	3642	297	0	0
T92	5827	27	0	0
T115	9717	21	0	0
T116	10349	0	0	0
T118	1328	2	0	0
T119	4016	4	0	0
T124	11556	15	0	0
T130	0	48	0	0
T142	2346	0	0	0
T148	0	6	0	0
T154	5992	0	0	0
T155	0	28	0	0