Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3872482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4347352

1

T2

7

T3

59

T4

79958

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7490553	1			T3	57		T4	152949		T8	808
values[0x0]	362294	1			T2	14		T3	18		T4	2123
values[0x1]	366987	1			T2	8		T3	22		T4	2111

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3077094	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5142740

1

T2

8

T3

68

T4

95568

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31774	1			T4	588		T8	6		T11	14
valid_sources[0x01]	33883	1			T4	605		T8	3		T11	9
valid_sources[0x02]	23290	1			T4	603		T8	3		T11	7
valid_sources[0x03]	24089	1			T4	576		T8	4		T11	2
valid_sources[0x04]	44192	1			T4	667		T8	3		T9	4
valid_sources[0x05]	45631	1			T4	584		T8	4		T9	23
valid_sources[0x06]	25836	1			T3	13		T4	678		T8	4
valid_sources[0x07]	23987	1			T4	640		T8	2		T11	8
valid_sources[0x08]	25878	1			T4	601		T8	5		T9	14
valid_sources[0x09]	27390	1			T4	664		T8	2		T9	13
valid_sources[0x0a]	23947	1			T4	556		T8	6		T11	15
valid_sources[0x0b]	27704	1			T4	677		T8	4		T9	23
valid_sources[0x0c]	23716	1			T4	613		T8	7		T11	13
valid_sources[0x0d]	24173	1			T4	567		T8	4		T9	4
valid_sources[0x0e]	68455	1			T4	600		T8	3		T11	5
valid_sources[0x0f]	28621	1			T4	600		T8	5		T11	8
valid_sources[0x10]	55645	1			T4	583		T8	5		T11	19
valid_sources[0x11]	23517	1			T4	624		T8	8		T9	3
valid_sources[0x12]	23554	1			T4	533		T8	4		T11	8
valid_sources[0x13]	23664	1			T3	1		T4	575		T8	4
valid_sources[0x14]	30986	1			T4	655		T8	8		T9	13
valid_sources[0x15]	25682	1			T4	671		T8	9		T9	5
valid_sources[0x16]	24879	1			T4	621		T8	5		T11	7
valid_sources[0x17]	97891	1			T4	582		T8	5		T11	8
valid_sources[0x18]	24388	1			T4	519		T8	6		T11	22
valid_sources[0x19]	24524	1			T3	7		T4	640		T8	5
valid_sources[0x1a]	26682	1			T3	28		T4	612		T8	1
valid_sources[0x1b]	24916	1			T4	666		T8	4		T11	31
valid_sources[0x1c]	24621	1			T4	707		T8	2		T9	33
valid_sources[0x1d]	26398	1			T4	553		T8	6		T11	30
valid_sources[0x1e]	27338	1			T4	599		T8	6		T11	8
valid_sources[0x1f]	42911	1			T4	650		T8	2		T9	22
valid_sources[0x20]	24129	1			T4	621		T8	6		T11	11
valid_sources[0x21]	25915	1			T4	644		T8	6		T9	3
valid_sources[0x22]	25231	1			T4	657		T8	7		T9	11
valid_sources[0x23]	28051	1			T4	604		T8	4		T9	19
valid_sources[0x24]	23254	1			T4	553		T8	7		T11	4
valid_sources[0x25]	24519	1			T4	601		T8	6		T9	11
valid_sources[0x26]	26196	1			T4	669		T8	1		T9	16
valid_sources[0x27]	23370	1			T4	648		T8	5		T11	17
valid_sources[0x28]	29988	1			T4	700		T8	4		T11	3
valid_sources[0x29]	34820	1			T4	572		T8	4		T9	19
valid_sources[0x2a]	25942	1			T4	605		T8	8		T9	1
valid_sources[0x2b]	26168	1			T4	605		T8	4		T11	6
valid_sources[0x2c]	22971	1			T4	655		T8	3		T11	7
valid_sources[0x2d]	23727	1			T4	648		T8	8		T11	15
valid_sources[0x2e]	48822	1			T4	606		T8	5		T11	14
valid_sources[0x2f]	33273	1			T4	580		T8	8		T9	14
valid_sources[0x30]	23817	1			T4	557		T8	4		T11	7
valid_sources[0x31]	24742	1			T4	625		T8	4		T11	5
valid_sources[0x32]	23150	1			T4	658		T8	4		T11	7
valid_sources[0x33]	26011	1			T4	677		T8	3		T11	2
valid_sources[0x34]	42748	1			T4	611		T8	2		T9	4
valid_sources[0x35]	23795	1			T4	570		T8	3		T9	4
valid_sources[0x36]	26248	1			T4	661		T8	7		T11	8
valid_sources[0x37]	23729	1			T4	601		T8	14		T9	14
valid_sources[0x38]	27753	1			T4	610		T8	3		T11	17
valid_sources[0x39]	39982	1			T4	601		T8	6		T11	3
valid_sources[0x3a]	26076	1			T4	630		T8	5		T9	11
valid_sources[0x3b]	28133	1			T4	585		T8	7		T11	6
valid_sources[0x3c]	30030	1			T4	518		T8	6		T11	5
valid_sources[0x3d]	40300	1			T4	671		T8	9		T11	13
valid_sources[0x3e]	25255	1			T4	627		T8	5		T11	15
valid_sources[0x3f]	25108	1			T4	646		T8	5		T11	14
valid_sources[0x40]	24216	1			T4	670		T8	5		T11	10
valid_sources[0x41]	45264	1			T4	629		T8	6		T9	10
valid_sources[0x42]	32884	1			T4	602		T8	11		T11	4
valid_sources[0x43]	27681	1			T4	590		T8	6		T11	14
valid_sources[0x44]	25105	1			T4	604		T8	3		T9	25
valid_sources[0x45]	24444	1			T4	646		T8	2		T9	7
valid_sources[0x46]	42094	1			T4	616		T8	3		T11	7
valid_sources[0x47]	27634	1			T3	5		T4	627		T8	11
valid_sources[0x48]	23170	1			T4	602		T8	6		T11	17
valid_sources[0x49]	24795	1			T4	653		T8	7		T11	2
valid_sources[0x4a]	38411	1			T4	574		T8	3		T9	3
valid_sources[0x4b]	26509	1			T4	545		T8	10		T11	11
valid_sources[0x4c]	23624	1			T4	538		T8	10		T9	13
valid_sources[0x4d]	24824	1			T4	567		T8	5		T11	18
valid_sources[0x4e]	23377	1			T4	692		T8	5		T9	36
valid_sources[0x4f]	24239	1			T4	674		T8	2		T11	15
valid_sources[0x50]	35142	1			T4	617		T8	3		T9	18
valid_sources[0x51]	24249	1			T4	635		T8	6		T11	4
valid_sources[0x52]	27158	1			T4	657		T8	5		T11	2
valid_sources[0x53]	35956	1			T4	701		T8	6		T11	10
valid_sources[0x54]	25101	1			T4	651		T8	2		T9	25
valid_sources[0x55]	24511	1			T4	626		T8	9		T11	12
valid_sources[0x56]	86950	1			T4	593		T8	6		T11	7
valid_sources[0x57]	24721	1			T4	605		T8	2		T11	20
valid_sources[0x58]	24033	1			T4	588		T8	5		T11	7
valid_sources[0x59]	24716	1			T4	527		T8	2		T9	1
valid_sources[0x5a]	27968	1			T4	564		T8	6		T9	4
valid_sources[0x5b]	26787	1			T4	528		T8	6		T11	11
valid_sources[0x5c]	27562	1			T4	625		T8	2		T11	19
valid_sources[0x5d]	175612	1			T4	625		T8	4		T9	4
valid_sources[0x5e]	24785	1			T4	585		T8	6		T11	6
valid_sources[0x5f]	24266	1			T4	633		T8	4		T11	18
valid_sources[0x60]	23752	1			T4	599		T8	12		T11	14
valid_sources[0x61]	26697	1			T4	559		T8	6		T11	14
valid_sources[0x62]	24690	1			T4	646		T8	2		T9	9
valid_sources[0x63]	26708	1			T4	626		T8	3		T11	3
valid_sources[0x64]	26544	1			T4	603		T8	4		T11	8
valid_sources[0x65]	23126	1			T4	655		T8	2		T11	11
valid_sources[0x66]	27449	1			T4	568		T8	5		T11	5
valid_sources[0x67]	140182	1			T4	589		T8	6		T9	10
valid_sources[0x68]	24011	1			T4	563		T8	5		T9	5
valid_sources[0x69]	35412	1			T4	609		T8	4		T11	24
valid_sources[0x6a]	23400	1			T4	627		T8	1		T11	11
valid_sources[0x6b]	25021	1			T4	604		T8	5		T9	4
valid_sources[0x6c]	24442	1			T4	573		T8	6		T11	9
valid_sources[0x6d]	39186	1			T4	626		T8	8		T9	12
valid_sources[0x6e]	24256	1			T4	604		T8	4		T11	6
valid_sources[0x6f]	25671	1			T4	562		T8	7		T9	2
valid_sources[0x70]	25732	1			T4	608		T8	10		T9	25
valid_sources[0x71]	24755	1			T4	626		T8	3		T11	10
valid_sources[0x72]	30254	1			T4	602		T8	7		T9	6
valid_sources[0x73]	39621	1			T3	1		T4	587		T8	1
valid_sources[0x74]	28433	1			T4	608		T8	3		T11	12
valid_sources[0x75]	25040	1			T4	624		T8	4		T11	6
valid_sources[0x76]	25885	1			T4	675		T8	4		T11	7
valid_sources[0x77]	24207	1			T4	618		T8	1		T11	18
valid_sources[0x78]	25613	1			T4	594		T11	23		T6	2
valid_sources[0x79]	23379	1			T4	635		T8	3		T11	9
valid_sources[0x7a]	28487	1			T4	670		T8	2		T11	1
valid_sources[0x7b]	26728	1			T4	548		T8	2		T9	15
valid_sources[0x7c]	25920	1			T4	604		T8	1		T9	21
valid_sources[0x7d]	24086	1			T4	565		T8	9		T10	15
valid_sources[0x7e]	25885	1			T4	598		T8	6		T11	14
valid_sources[0x7f]	24471	1			T4	655		T8	4		T11	11
valid_sources[0x80]	24200	1			T4	638		T8	4		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3719245

1

T3

23

T4

76248

T8

383

values[0x0]

all_enables

biggest_size

314516

1

T2

6

T3

18

T4

1860

values[0x1]

all_enables

biggest_size

313591

1

T2

1

T3

18

T4

1850