Unified Coverage Report :: Module :: tlul_rsp_intg_chk

Module : tlul_rsp_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00	40.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_rsp_chk	80.00	100.00	40.00				100.00

---

Module Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00	40.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.72	100.00	40.00	6.90			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.51	91.30	68.75			90.00	100.00	u_tap_tlul_host

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	6.90			6.90

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_rsp_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	23	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	50	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1
47	1	1
50	1	1

---

Cond Coverage for Module : tlul_rsp_intg_chk

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Not Covered

---

Assert Coverage for Module : tlul_rsp_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	1617	1617	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617	1617	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0