Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2998680	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3432392

1

T1

198

T2

115

T3

911

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5759626	1			T1	151		T2	100		T3	666
values[0x0]	335312	1			T1	78		T2	42		T3	340
values[0x1]	336134	1			T1	66		T2	44		T3	332

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2380490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4050582

1

T1

220

T2

134

T3

1017

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19798	1			T15	3		T16	2		T17	4
valid_sources[0x01]	19084	1			T1	6		T9	4		T11	1
valid_sources[0x02]	20927	1			T1	7		T9	1		T14	1
valid_sources[0x03]	24186	1			T9	2		T14	14		T15	5
valid_sources[0x04]	18897	1			T2	6		T9	3		T14	25
valid_sources[0x05]	19668	1			T1	1		T9	1		T14	7
valid_sources[0x06]	23171	1			T9	3		T14	1		T17	9
valid_sources[0x07]	19830	1			T1	1		T9	3		T14	10
valid_sources[0x08]	19743	1			T9	1		T14	7		T15	2
valid_sources[0x09]	20253	1			T1	3		T9	1		T15	3
valid_sources[0x0a]	18694	1			T1	3		T9	4		T14	4
valid_sources[0x0b]	19184	1			T9	1		T14	16		T15	2
valid_sources[0x0c]	22127	1			T11	1		T12	1		T14	13
valid_sources[0x0d]	18837	1			T9	1		T14	6		T15	2
valid_sources[0x0e]	54809	1			T9	1		T11	2		T14	5
valid_sources[0x0f]	19034	1			T1	5		T9	6		T15	9
valid_sources[0x10]	19052	1			T9	4		T15	3		T17	7
valid_sources[0x11]	19071	1			T2	11		T14	20		T15	6
valid_sources[0x12]	18878	1			T1	9		T9	4		T14	8
valid_sources[0x13]	18871	1			T1	1		T9	1		T14	6
valid_sources[0x14]	19603	1			T2	2		T9	6		T4	17
valid_sources[0x15]	23658	1			T2	5		T9	2		T14	2
valid_sources[0x16]	18818	1			T15	4		T17	2		T25	4
valid_sources[0x17]	19460	1			T9	1		T14	7		T15	2
valid_sources[0x18]	19676	1			T1	1		T9	1		T13	1
valid_sources[0x19]	18913	1			T9	2		T14	1		T15	2
valid_sources[0x1a]	33494	1			T1	12		T9	3		T11	1
valid_sources[0x1b]	39226	1			T9	1		T11	1		T14	2
valid_sources[0x1c]	21988	1			T9	4		T12	1		T4	17
valid_sources[0x1d]	20979	1			T1	1		T9	1		T11	1
valid_sources[0x1e]	22752	1			T1	5		T9	1		T13	1
valid_sources[0x1f]	20674	1			T9	2		T15	10		T17	3
valid_sources[0x20]	20745	1			T9	1		T14	7		T15	3
valid_sources[0x21]	25106	1			T9	1		T12	1		T4	17
valid_sources[0x22]	18959	1			T9	1		T14	2		T15	4
valid_sources[0x23]	32037	1			T9	3		T14	6		T15	2
valid_sources[0x24]	20045	1			T2	1		T9	2		T14	2
valid_sources[0x25]	22632	1			T9	1		T14	6		T15	3
valid_sources[0x26]	19383	1			T9	3		T11	1		T14	12
valid_sources[0x27]	35279	1			T13	1		T14	4		T15	6
valid_sources[0x28]	19358	1			T9	4		T14	7		T15	5
valid_sources[0x29]	19047	1			T2	7		T9	2		T12	1
valid_sources[0x2a]	19533	1			T9	6		T14	4		T15	6
valid_sources[0x2b]	20169	1			T14	7		T15	4		T25	6
valid_sources[0x2c]	19218	1			T1	2		T9	2		T12	1
valid_sources[0x2d]	20345	1			T1	5		T9	4		T14	3
valid_sources[0x2e]	50257	1			T2	1		T9	3		T4	30585
valid_sources[0x2f]	21209	1			T1	3		T2	5		T14	2
valid_sources[0x30]	20599	1			T12	1		T14	3		T15	4
valid_sources[0x31]	19491	1			T2	2		T9	2		T11	1
valid_sources[0x32]	18813	1			T9	2		T14	19		T15	2
valid_sources[0x33]	19007	1			T9	2		T14	4		T15	2
valid_sources[0x34]	19079	1			T9	1		T14	8		T15	2
valid_sources[0x35]	19437	1			T2	3		T9	2		T13	1
valid_sources[0x36]	18955	1			T9	4		T14	5		T15	1
valid_sources[0x37]	156288	1			T9	6		T4	67468		T14	1
valid_sources[0x38]	79691	1			T1	8		T14	1		T16	3
valid_sources[0x39]	19534	1			T14	1		T15	1		T17	3
valid_sources[0x3a]	24315	1			T2	15		T9	2		T14	19
valid_sources[0x3b]	23147	1			T9	2		T14	6		T15	3
valid_sources[0x3c]	20767	1			T9	3		T12	1		T15	5
valid_sources[0x3d]	18427	1			T2	2		T9	1		T14	5
valid_sources[0x3e]	23440	1			T1	7		T9	1		T11	1
valid_sources[0x3f]	19175	1			T9	1		T14	3		T15	5
valid_sources[0x40]	18815	1			T1	3		T9	3		T15	5
valid_sources[0x41]	18885	1			T9	1		T4	1		T14	5
valid_sources[0x42]	19860	1			T2	4		T9	3		T11	1
valid_sources[0x43]	19999	1			T9	1		T13	1		T14	11
valid_sources[0x44]	18870	1			T9	4		T14	12		T15	5
valid_sources[0x45]	19466	1			T9	2		T11	1		T13	2
valid_sources[0x46]	39475	1			T9	2		T13	1		T15	4
valid_sources[0x47]	21094	1			T2	2		T9	1		T14	12
valid_sources[0x48]	23505	1			T14	7		T15	3		T17	3
valid_sources[0x49]	20760	1			T9	1		T14	4		T15	5
valid_sources[0x4a]	22287	1			T9	4		T11	1		T12	1
valid_sources[0x4b]	22045	1			T3	1338		T9	2		T14	1
valid_sources[0x4c]	20168	1			T1	6		T2	1		T4	6
valid_sources[0x4d]	20398	1			T2	5		T9	1		T12	1
valid_sources[0x4e]	25993	1			T9	2		T14	1		T15	5
valid_sources[0x4f]	19770	1			T13	2		T14	15		T15	5
valid_sources[0x50]	19120	1			T2	5		T9	2		T4	1
valid_sources[0x51]	18577	1			T9	2		T14	3		T15	5
valid_sources[0x52]	19160	1			T9	3		T14	3		T15	1
valid_sources[0x53]	20571	1			T1	1		T9	2		T11	1
valid_sources[0x54]	19214	1			T1	5		T2	1		T9	5
valid_sources[0x55]	19482	1			T2	5		T9	2		T4	17
valid_sources[0x56]	20898	1			T9	1		T14	5		T15	6
valid_sources[0x57]	23687	1			T13	1		T14	5		T15	3
valid_sources[0x58]	21984	1			T9	4		T11	1		T14	5
valid_sources[0x59]	18904	1			T1	2		T2	1		T9	1
valid_sources[0x5a]	19214	1			T9	2		T14	12		T15	3
valid_sources[0x5b]	56899	1			T9	2		T4	17		T15	6
valid_sources[0x5c]	19136	1			T1	11		T2	1		T9	2
valid_sources[0x5d]	19144	1			T9	2		T14	1		T15	2
valid_sources[0x5e]	19027	1			T1	1		T2	2		T9	4
valid_sources[0x5f]	23353	1			T1	5		T9	1		T14	13
valid_sources[0x60]	19347	1			T9	2		T14	4		T15	5
valid_sources[0x61]	20457	1			T12	1		T13	1		T15	4
valid_sources[0x62]	22571	1			T9	3		T13	1		T14	7
valid_sources[0x63]	18958	1			T9	3		T15	2		T17	1
valid_sources[0x64]	21151	1			T1	3		T9	3		T14	8
valid_sources[0x65]	18945	1			T9	3		T14	6		T15	3
valid_sources[0x66]	167655	1			T1	1		T12	1		T4	17
valid_sources[0x67]	19250	1			T9	2		T4	17		T14	4
valid_sources[0x68]	21941	1			T1	5		T9	1		T15	5
valid_sources[0x69]	20385	1			T1	9		T9	3		T12	1
valid_sources[0x6a]	19335	1			T9	3		T14	4		T15	3
valid_sources[0x6b]	42902	1			T9	2		T11	1		T12	1
valid_sources[0x6c]	19054	1			T9	3		T4	17		T14	11
valid_sources[0x6d]	20002	1			T1	1		T13	1		T14	7
valid_sources[0x6e]	18871	1			T1	1		T2	9		T9	1
valid_sources[0x6f]	19450	1			T12	1		T13	1		T14	2
valid_sources[0x70]	23052	1			T1	2		T9	4		T12	2
valid_sources[0x71]	19316	1			T9	3		T14	8		T15	4
valid_sources[0x72]	20496	1			T9	3		T14	1		T15	4
valid_sources[0x73]	19159	1			T9	3		T14	20		T15	5
valid_sources[0x74]	20078	1			T2	3		T9	4		T14	5
valid_sources[0x75]	18869	1			T11	1		T15	9		T17	7
valid_sources[0x76]	44949	1			T9	4		T12	1		T14	7
valid_sources[0x77]	18757	1			T9	3		T14	5		T15	6
valid_sources[0x78]	20376	1			T2	3		T15	9		T17	4
valid_sources[0x79]	19015	1			T2	1		T9	2		T14	7
valid_sources[0x7a]	23439	1			T2	1		T9	1		T14	7
valid_sources[0x7b]	19173	1			T14	5		T15	6		T16	1
valid_sources[0x7c]	18946	1			T14	3		T15	3		T16	2
valid_sources[0x7d]	19727	1			T9	4		T12	1		T15	3
valid_sources[0x7e]	24737	1			T9	1		T14	5		T15	1
valid_sources[0x7f]	18881	1			T9	2		T14	6		T15	7
valid_sources[0x80]	22086	1			T2	2		T9	1		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2854052

1

T1

73

T2

49

T3

338

values[0x0]

all_enables

biggest_size

290660

1

T1

67

T2

31

T3

293

values[0x1]

all_enables

biggest_size

287680

1

T1

58

T2

35

T3

280