Unified Coverage Report :: Module :: prim_clock_mux2

Module : prim_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_clock_mux2_0/prim_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux	75.00			75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux	75.00			75.00
tb.dut.u_prim_clock_mux2
tb.dut.u_prim_rst_n_mux2

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67			66.67				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	75.00			75.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36			96.36				i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	75.00			75.00

---

Module Instance : tb.dut.u_prim_clock_mux2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.14	100.00	81.94	98.16		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_prim_rst_n_mux2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.14	100.00	81.94	98.16		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

Toggle Coverage for Module : prim_clock_mux2

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk1_i	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT