Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.14	100.00	81.94	98.16		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	190470325	30657	0	0
claim_transition_if_regwen_rd_A	190470325	2291	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190470325	30657	0	0
T4	417773	4	0	0
T5	33809	0	0	0
T13	1370	0	0	0
T14	35555	0	0	0
T15	22617	0	0	0
T16	4404	0	0	0
T17	21370	0	0	0
T19	0	7	0	0
T24	39065	0	0	0
T25	36543	0	0	0
T26	4200	0	0	0
T130	0	3	0	0
T180	0	10	0	0
T185	0	9	0	0
T186	0	3	0	0
T187	0	7	0	0
T188	0	1	0	0
T189	0	2	0	0
T190	0	3	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190470325	2291	0	0
T55	0	17	0	0
T107	0	8	0	0
T186	306377	7	0	0
T188	0	5	0	0
T190	0	9	0	0
T191	0	8	0	0
T192	0	9	0	0
T193	0	2	0	0
T194	0	13	0	0
T195	0	7	0	0
T196	2373	0	0	0
T197	519880	0	0	0
T198	27788	0	0	0
T199	375460	0	0	0
T200	1969	0	0	0
T201	18363	0	0	0
T202	30777	0	0	0
T203	2380	0	0	0
T204	1868	0	0	0