Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_fifo_async_simple
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.78 96.78

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp 95.95 95.95
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req 98.89 98.89



Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.95 95.95


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 97.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.95 96.95 i_dmi_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 100.00 100.00



Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.89 98.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.32 99.32


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.95 96.95 i_dmi_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 100.00 100.00

Toggle Coverage for Module : prim_fifo_async_simple ( parameter Width=41,EnRstChks=0,EnRzHs=1 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
98.89 98.89
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

TotalCoveredPercent
Totals 10 9 90.00
Total Bits 180 178 98.89
Total Bits 0->1 90 89 98.89
Total Bits 1->0 90 89 98.89

Ports 10 9 90.00
Port Bits 180 178 98.89
Port Bits 0->1 90 89 98.89
Port Bits 1->0 90 89 98.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_wr_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rst_wr_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
wvalid_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
wready_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
wdata_i[40:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk_rd_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_rd_ni Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rvalid_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
rready_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rdata_o[39:0] Yes Yes *T5,*T6,*T7 Yes T5,T6,T7 OUTPUT
rdata_o[40] No No No OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Module : prim_fifo_async_simple ( parameter Width=34,EnRstChks=0,EnRzHs=1 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
95.95 95.95
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp

TotalCoveredPercent
Totals 9 7 77.78
Total Bits 150 142 94.67
Total Bits 0->1 75 71 94.67
Total Bits 1->0 75 71 94.67

Ports 9 7 77.78
Port Bits 150 142 94.67
Port Bits 0->1 75 71 94.67
Port Bits 1->0 75 71 94.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_wr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_wr_ni Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
wvalid_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
wready_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
wdata_i[1:0] No No No INPUT
wdata_i[33:2] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk_rd_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rst_rd_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
rvalid_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
rready_i Unreachable Unreachable Unreachable INPUT
rdata_o[1:0] No No No OUTPUT
rdata_o[33:2] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp
TotalCoveredPercent
Totals 9 7 77.78
Total Bits 148 142 95.95
Total Bits 0->1 73 71 97.26
Total Bits 1->0 75 71 94.67

Ports 9 7 77.78
Port Bits 148 142 95.95
Port Bits 0->1 73 71 97.26
Port Bits 1->0 75 71 94.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_wr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_wr_ni Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
wvalid_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
wready_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
wdata_i[1:0] No No No INPUT
wdata_i[33:2] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk_rd_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rst_rd_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
rvalid_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
rready_i Unreachable Unreachable Unreachable INPUT
rdata_o[1:0] No No Excluded OUTPUT 0->1:VC_COV_UNR
rdata_o[33:2] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req
TotalCoveredPercent
Totals 10 9 90.00
Total Bits 180 178 98.89
Total Bits 0->1 90 89 98.89
Total Bits 1->0 90 89 98.89

Ports 10 9 90.00
Port Bits 180 178 98.89
Port Bits 0->1 90 89 98.89
Port Bits 1->0 90 89 98.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_wr_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rst_wr_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
wvalid_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
wready_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
wdata_i[40:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
clk_rd_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_rd_ni Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rvalid_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
rready_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rdata_o[39:0] Yes Yes *T5,*T6,*T7 Yes T5,T6,T7 OUTPUT
rdata_o[40] No No No OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%