Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1706934	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1955724

1

T1

5

T2

525

T3

94

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3282317	1			T1	64		T2	495		T3	100
values[0x0]	189123	1			T1	3		T2	193		T3	26
values[0x1]	191218	1			T1	5		T2	215		T3	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1355628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2307030

1

T1

24

T2

632

T3

109

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9471	1			T12	5		T14	4		T32	4
valid_sources[0x01]	9907	1			T12	1		T14	3		T32	2
valid_sources[0x02]	9477	1			T2	6		T12	2		T14	1
valid_sources[0x03]	9039	1			T2	9		T14	1		T32	5
valid_sources[0x04]	9419	1			T3	2		T12	2		T14	4
valid_sources[0x05]	62952	1			T32	8		T22	1		T23	3
valid_sources[0x06]	8980	1			T12	1		T14	4		T32	3
valid_sources[0x07]	8870	1			T14	2		T32	4		T22	1
valid_sources[0x08]	9215	1			T12	2		T14	2		T32	5
valid_sources[0x09]	9037	1			T12	1		T14	3		T32	3
valid_sources[0x0a]	9012	1			T12	2		T32	5		T22	3
valid_sources[0x0b]	11767	1			T3	1		T12	5		T14	3
valid_sources[0x0c]	9205	1			T3	2		T12	3		T14	7
valid_sources[0x0d]	11651	1			T12	3		T14	1		T32	5
valid_sources[0x0e]	19282	1			T12	1		T14	2		T32	5
valid_sources[0x0f]	9918	1			T14	1		T32	5		T23	2
valid_sources[0x10]	33351	1			T2	20		T12	1		T14	5
valid_sources[0x11]	9954	1			T12	1		T32	2		T22	3
valid_sources[0x12]	9879	1			T14	1		T15	1		T32	15
valid_sources[0x13]	10937	1			T12	1		T32	8		T22	2
valid_sources[0x14]	9278	1			T12	1		T14	7		T32	5
valid_sources[0x15]	10038	1			T3	1		T12	2		T14	6
valid_sources[0x16]	9185	1			T3	1		T12	1		T14	3
valid_sources[0x17]	11485	1			T2	2		T14	3		T32	3
valid_sources[0x18]	9155	1			T12	1		T14	10		T32	2
valid_sources[0x19]	9061	1			T2	16		T14	3		T32	6
valid_sources[0x1a]	9066	1			T12	2		T14	4		T32	2
valid_sources[0x1b]	13329	1			T2	2		T3	5		T12	1
valid_sources[0x1c]	8906	1			T15	1		T32	6		T22	1
valid_sources[0x1d]	9412	1			T12	1		T32	3		T22	3
valid_sources[0x1e]	9990	1			T2	15		T12	1		T14	1
valid_sources[0x1f]	8899	1			T3	2		T12	1		T32	6
valid_sources[0x20]	11793	1			T12	1		T14	2		T32	1
valid_sources[0x21]	9440	1			T3	2		T12	1		T14	2
valid_sources[0x22]	9310	1			T12	2		T32	2		T6	1
valid_sources[0x23]	9900	1			T3	8		T14	5		T32	5
valid_sources[0x24]	9192	1			T32	3		T23	7		T25	8
valid_sources[0x25]	10413	1			T12	3		T14	1		T32	7
valid_sources[0x26]	10539	1			T14	12		T32	10		T22	1
valid_sources[0x27]	9803	1			T2	11		T3	4		T12	1
valid_sources[0x28]	9833	1			T14	3		T32	9		T23	2
valid_sources[0x29]	16800	1			T2	9		T3	1		T14	10
valid_sources[0x2a]	12694	1			T3	3		T12	2		T15	1
valid_sources[0x2b]	10385	1			T14	3		T15	1		T32	6
valid_sources[0x2c]	9604	1			T14	2		T32	5		T22	2
valid_sources[0x2d]	9207	1			T3	2		T12	1		T14	3
valid_sources[0x2e]	10735	1			T12	1		T32	5		T22	1
valid_sources[0x2f]	9240	1			T32	8		T23	5		T6	1
valid_sources[0x30]	9291	1			T2	3		T12	2		T32	11
valid_sources[0x31]	33012	1			T2	1		T12	2		T32	2
valid_sources[0x32]	9676	1			T12	3		T14	7		T32	14
valid_sources[0x33]	11240	1			T14	4		T32	10		T22	2
valid_sources[0x34]	9051	1			T2	10		T32	1		T23	5
valid_sources[0x35]	9112	1			T12	2		T14	2		T15	1
valid_sources[0x36]	8940	1			T32	3		T22	1		T23	3
valid_sources[0x37]	19271	1			T2	2		T12	1		T14	1
valid_sources[0x38]	9131	1			T2	9		T3	5		T14	8
valid_sources[0x39]	9091	1			T2	13		T12	4		T14	4
valid_sources[0x3a]	9780	1			T12	1		T14	1		T32	6
valid_sources[0x3b]	9163	1			T2	47		T3	1		T12	1
valid_sources[0x3c]	9137	1			T14	1		T15	1		T32	3
valid_sources[0x3d]	10987	1			T32	2		T23	4		T25	13
valid_sources[0x3e]	9780	1			T12	1		T32	4		T23	3
valid_sources[0x3f]	10538	1			T12	5		T23	5		T25	9
valid_sources[0x40]	9610	1			T2	1		T14	12		T32	3
valid_sources[0x41]	10648	1			T14	3		T32	3		T22	2
valid_sources[0x42]	9752	1			T2	23		T3	4		T14	8
valid_sources[0x43]	9210	1			T2	9		T32	2		T22	3
valid_sources[0x44]	9765	1			T14	2		T32	4		T23	3
valid_sources[0x45]	9142	1			T12	1		T14	2		T32	4
valid_sources[0x46]	8887	1			T14	1		T32	6		T23	3
valid_sources[0x47]	9560	1			T3	7		T14	5		T32	2
valid_sources[0x48]	9523	1			T3	1		T12	1		T32	7
valid_sources[0x49]	9220	1			T2	27		T3	2		T14	5
valid_sources[0x4a]	11967	1			T12	1		T14	2		T22	1
valid_sources[0x4b]	9171	1			T12	1		T14	6		T32	3
valid_sources[0x4c]	9042	1			T12	3		T32	4		T22	2
valid_sources[0x4d]	10311	1			T2	18		T12	2		T14	2
valid_sources[0x4e]	9556	1			T12	3		T13	9		T14	5
valid_sources[0x4f]	9955	1			T12	2		T14	4		T32	7
valid_sources[0x50]	9658	1			T2	9		T3	6		T12	2
valid_sources[0x51]	9612	1			T12	2		T14	4		T32	8
valid_sources[0x52]	97055	1			T2	4		T14	5		T32	1
valid_sources[0x53]	10989	1			T12	1		T13	226		T14	4
valid_sources[0x54]	9474	1			T3	2		T12	1		T14	7
valid_sources[0x55]	9628	1			T32	2		T22	1		T23	4
valid_sources[0x56]	8850	1			T12	2		T14	6		T32	2
valid_sources[0x57]	16499	1			T12	1		T14	1		T32	4
valid_sources[0x58]	10413	1			T14	6		T15	1		T32	3
valid_sources[0x59]	9600	1			T12	3		T32	1		T5	2
valid_sources[0x5a]	140506	1			T14	1		T32	4		T22	1
valid_sources[0x5b]	9789	1			T2	20		T12	2		T14	3
valid_sources[0x5c]	9457	1			T12	1		T14	6		T32	1
valid_sources[0x5d]	10966	1			T12	4		T32	2		T22	3
valid_sources[0x5e]	9162	1			T12	2		T14	16		T32	1
valid_sources[0x5f]	8742	1			T32	6		T23	5		T6	1
valid_sources[0x60]	10321	1			T12	2		T14	3		T32	1
valid_sources[0x61]	9223	1			T12	4		T14	2		T32	2
valid_sources[0x62]	11344	1			T12	1		T14	5		T32	3
valid_sources[0x63]	9145	1			T12	8		T32	5		T22	1
valid_sources[0x64]	9581	1			T12	2		T14	6		T32	2
valid_sources[0x65]	9489	1			T12	3		T13	40		T14	17
valid_sources[0x66]	8762	1			T14	1		T32	1		T5	4
valid_sources[0x67]	9380	1			T3	4		T12	1		T14	2
valid_sources[0x68]	9101	1			T2	10		T14	3		T32	1
valid_sources[0x69]	10617	1			T12	1		T32	8		T22	1
valid_sources[0x6a]	9621	1			T12	1		T14	1		T15	1
valid_sources[0x6b]	10302	1			T1	72		T12	1		T14	1
valid_sources[0x6c]	9183	1			T3	1		T13	7		T14	1
valid_sources[0x6d]	49656	1			T13	108		T14	1		T15	1
valid_sources[0x6e]	9393	1			T3	1		T12	2		T14	12
valid_sources[0x6f]	9238	1			T12	1		T14	2		T32	5
valid_sources[0x70]	9446	1			T12	4		T22	1		T23	4
valid_sources[0x71]	9225	1			T12	2		T14	10		T32	5
valid_sources[0x72]	9799	1			T2	4		T12	2		T14	10
valid_sources[0x73]	10087	1			T12	2		T32	6		T22	2
valid_sources[0x74]	85363	1			T14	7		T32	4		T22	1
valid_sources[0x75]	100546	1			T3	3		T12	2		T14	1
valid_sources[0x76]	11939	1			T3	13		T12	3		T14	13
valid_sources[0x77]	9373	1			T14	6		T32	5		T23	5
valid_sources[0x78]	9122	1			T12	2		T14	9		T32	3
valid_sources[0x79]	9207	1			T3	1		T12	1		T14	9
valid_sources[0x7a]	9269	1			T12	2		T14	2		T32	9
valid_sources[0x7b]	9266	1			T12	1		T22	1		T23	3
valid_sources[0x7c]	9420	1			T12	4		T14	2		T32	5
valid_sources[0x7d]	138884	1			T12	3		T14	3		T32	4
valid_sources[0x7e]	9006	1			T2	54		T22	2		T5	1
valid_sources[0x7f]	9811	1			T3	8		T32	4		T23	6
valid_sources[0x80]	9566	1			T12	4		T14	3		T32	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1627085

1

T2

170

T3

47

T4

59

values[0x0]

all_enables

biggest_size

164764

1

T1

2

T2

173

T3

22

values[0x1]

all_enables

biggest_size

163875

1

T1

3

T2

182

T3

25