Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112340659	29198	0	0
claim_transition_if_regwen_rd_A	112340659	1919	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112340659	29198	0	0
T9	63093	0	0	0
T20	23109	0	0	0
T21	739668	0	0	0
T30	238427	5	0	0
T40	21959	0	0	0
T41	46150	0	0	0
T50	0	2	0	0
T55	0	4	0	0
T56	15069	0	0	0
T83	3982	0	0	0
T92	1410	0	0	0
T123	0	7	0	0
T125	0	2	0	0
T129	0	17	0	0
T174	0	9	0	0
T175	0	1	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	7310	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112340659	1919	0	0
T89	106040	0	0	0
T104	0	12	0	0
T132	0	36	0	0
T133	0	3	0	0
T135	0	30	0	0
T142	0	61	0	0
T179	335221	3	0	0
T180	0	3	0	0
T181	0	14	0	0
T182	0	7	0	0
T183	0	18	0	0
T184	19427	0	0	0
T185	4545	0	0	0
T186	36471	0	0	0
T187	10804	0	0	0
T188	298484	0	0	0
T189	332949	0	0	0
T190	17243	0	0	0
T191	27150	0	0	0